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[BINUTILS, AArch64] Enable Transactional Memory Extension
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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CommitLineData
12019-05-01 Sudakshina Das <sudi.das@arm.com>
2
3 * aarch64-asm-2.c: Regenerated.
4 * aarch64-dis-2.c: Regenerated.
5 * aarch64-opc-2.c: Regenerated.
6 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
7 AARCH64_OPND_TME_UIMM16.
8 (aarch64_print_operand): Likewise.
9 * aarch64-tbl.h (QL_IMM_NIL): New.
10 (TME): New.
11 (_TME_INSN): New.
12 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
13
142019-04-29 John Darrington <john@darrington.wattle.id.au>
15
16 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
17
182019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
19 Faraz Shahbazker <fshahbazker@wavecomp.com>
20
21 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
22
232019-04-24 John Darrington <john@darrington.wattle.id.au>
24
25 * s12z-opc.h: Add extern "C" bracketing to help
26 users who wish to use this interface in c++ code.
27
282019-04-24 John Darrington <john@darrington.wattle.id.au>
29
30 * s12z-opc.c (bm_decode): Handle bit map operations with the
31 "reserved0" mode.
32
332019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
34
35 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
36 specifier. Add entries for VLDR and VSTR of system registers.
37 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
38 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
39 of %J and %K format specifier.
40
412019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
42
43 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
44 Add new entries for VSCCLRM instruction.
45 (print_insn_coprocessor): Handle new %C format control code.
46
472019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
48
49 * arm-dis.c (enum isa): New enum.
50 (struct sopcode32): New structure.
51 (coprocessor_opcodes): change type of entries to struct sopcode32 and
52 set isa field of all current entries to ANY.
53 (print_insn_coprocessor): Change type of insn to struct sopcode32.
54 Only match an entry if its isa field allows the current mode.
55
562019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
57
58 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
59 CLRM.
60 (print_insn_thumb32): Add logic to print %n CLRM register list.
61
622019-04-15 Sudakshina Das <sudi.das@arm.com>
63
64 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
65 and %Q patterns.
66
672019-04-15 Sudakshina Das <sudi.das@arm.com>
68
69 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
70 (print_insn_thumb32): Edit the switch case for %Z.
71
722019-04-15 Sudakshina Das <sudi.das@arm.com>
73
74 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
75
762019-04-15 Sudakshina Das <sudi.das@arm.com>
77
78 * arm-dis.c (thumb32_opcodes): New instruction bfl.
79
802019-04-15 Sudakshina Das <sudi.das@arm.com>
81
82 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
83
842019-04-15 Sudakshina Das <sudi.das@arm.com>
85
86 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
87 Arm register with r13 and r15 unpredictable.
88 (thumb32_opcodes): New instructions for bfx and bflx.
89
902019-04-15 Sudakshina Das <sudi.das@arm.com>
91
92 * arm-dis.c (thumb32_opcodes): New instructions for bf.
93
942019-04-15 Sudakshina Das <sudi.das@arm.com>
95
96 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
97
982019-04-15 Sudakshina Das <sudi.das@arm.com>
99
100 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
101
1022019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
103
104 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
105
1062019-04-12 John Darrington <john@darrington.wattle.id.au>
107
108 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
109 "optr". ("operator" is a reserved word in c++).
110
1112019-04-11 Sudakshina Das <sudi.das@arm.com>
112
113 * aarch64-opc.c (aarch64_print_operand): Add case for
114 AARCH64_OPND_Rt_SP.
115 (verify_constraints): Likewise.
116 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
117 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
118 to accept Rt|SP as first operand.
119 (AARCH64_OPERANDS): Add new Rt_SP.
120 * aarch64-asm-2.c: Regenerated.
121 * aarch64-dis-2.c: Regenerated.
122 * aarch64-opc-2.c: Regenerated.
123
1242019-04-11 Sudakshina Das <sudi.das@arm.com>
125
126 * aarch64-asm-2.c: Regenerated.
127 * aarch64-dis-2.c: Likewise.
128 * aarch64-opc-2.c: Likewise.
129 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
130
1312019-04-09 Robert Suchanek <robert.suchanek@mips.com>
132
133 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
134
1352019-04-08 H.J. Lu <hongjiu.lu@intel.com>
136
137 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
138 * i386-init.h: Regenerated.
139
1402019-04-07 Alan Modra <amodra@gmail.com>
141
142 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
143 op_separator to control printing of spaces, comma and parens
144 rather than need_comma, need_paren and spaces vars.
145
1462019-04-07 Alan Modra <amodra@gmail.com>
147
148 PR 24421
149 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
150 (print_insn_neon, print_insn_arm): Likewise.
151
1522019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
153
154 * i386-dis-evex.h (evex_table): Updated to support BF16
155 instructions.
156 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
157 and EVEX_W_0F3872_P_3.
158 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
159 (cpu_flags): Add bitfield for CpuAVX512_BF16.
160 * i386-opc.h (enum): Add CpuAVX512_BF16.
161 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
162 * i386-opc.tbl: Add AVX512 BF16 instructions.
163 * i386-init.h: Regenerated.
164 * i386-tbl.h: Likewise.
165
1662019-04-05 Alan Modra <amodra@gmail.com>
167
168 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
169 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
170 to favour printing of "-" branch hint when using the "y" bit.
171 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
172
1732019-04-05 Alan Modra <amodra@gmail.com>
174
175 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
176 opcode until first operand is output.
177
1782019-04-04 Peter Bergner <bergner@linux.ibm.com>
179
180 PR gas/24349
181 * ppc-opc.c (valid_bo_pre_v2): Add comments.
182 (valid_bo_post_v2): Add support for 'at' branch hints.
183 (insert_bo): Only error on branch on ctr.
184 (get_bo_hint_mask): New function.
185 (insert_boe): Add new 'branch_taken' formal argument. Add support
186 for inserting 'at' branch hints.
187 (extract_boe): Add new 'branch_taken' formal argument. Add support
188 for extracting 'at' branch hints.
189 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
190 (BOE): Delete operand.
191 (BOM, BOP): New operands.
192 (RM): Update value.
193 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
194 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
195 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
196 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
197 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
198 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
199 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
200 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
201 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
202 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
203 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
204 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
205 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
206 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
207 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
208 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
209 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
210 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
211 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
212 bttarl+>: New extended mnemonics.
213
2142019-03-28 Alan Modra <amodra@gmail.com>
215
216 PR 24390
217 * ppc-opc.c (BTF): Define.
218 (powerpc_opcodes): Use for mtfsb*.
219 * ppc-dis.c (print_insn_powerpc): Print fields with both
220 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
221
2222019-03-25 Tamar Christina <tamar.christina@arm.com>
223
224 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
225 (mapping_symbol_for_insn): Implement new algorithm.
226 (print_insn): Remove duplicate code.
227
2282019-03-25 Tamar Christina <tamar.christina@arm.com>
229
230 * aarch64-dis.c (print_insn_aarch64):
231 Implement override.
232
2332019-03-25 Tamar Christina <tamar.christina@arm.com>
234
235 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
236 order.
237
2382019-03-25 Tamar Christina <tamar.christina@arm.com>
239
240 * aarch64-dis.c (last_stop_offset): New.
241 (print_insn_aarch64): Use stop_offset.
242
2432019-03-19 H.J. Lu <hongjiu.lu@intel.com>
244
245 PR gas/24359
246 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
247 CPU_ANY_AVX2_FLAGS.
248 * i386-init.h: Regenerated.
249
2502019-03-18 H.J. Lu <hongjiu.lu@intel.com>
251
252 PR gas/24348
253 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
254 vmovdqu16, vmovdqu32 and vmovdqu64.
255 * i386-tbl.h: Regenerated.
256
2572019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
258
259 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
260 from vstrszb, vstrszh, and vstrszf.
261
2622019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
263
264 * s390-opc.txt: Add instruction descriptions.
265
2662019-02-08 Jim Wilson <jimw@sifive.com>
267
268 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
269 <bne>: Likewise.
270
2712019-02-07 Tamar Christina <tamar.christina@arm.com>
272
273 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
274
2752019-02-07 Tamar Christina <tamar.christina@arm.com>
276
277 PR binutils/23212
278 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
279 * aarch64-opc.c (verify_elem_sd): New.
280 (fields): Add FLD_sz entr.
281 * aarch64-tbl.h (_SIMD_INSN): New.
282 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
283 fmulx scalar and vector by element isns.
284
2852019-02-07 Nick Clifton <nickc@redhat.com>
286
287 * po/sv.po: Updated Swedish translation.
288
2892019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
290
291 * s390-mkopc.c (main): Accept arch13 as cpu string.
292 * s390-opc.c: Add new instruction formats and instruction opcode
293 masks.
294 * s390-opc.txt: Add new arch13 instructions.
295
2962019-01-25 Sudakshina Das <sudi.das@arm.com>
297
298 * aarch64-tbl.h (QL_LDST_AT): Update macro.
299 (aarch64_opcode): Change encoding for stg, stzg
300 st2g and st2zg.
301 * aarch64-asm-2.c: Regenerated.
302 * aarch64-dis-2.c: Regenerated.
303 * aarch64-opc-2.c: Regenerated.
304
3052019-01-25 Sudakshina Das <sudi.das@arm.com>
306
307 * aarch64-asm-2.c: Regenerated.
308 * aarch64-dis-2.c: Likewise.
309 * aarch64-opc-2.c: Likewise.
310 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
311
3122019-01-25 Sudakshina Das <sudi.das@arm.com>
313 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
314
315 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
316 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
317 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
318 * aarch64-dis.h (ext_addr_simple_2): Likewise.
319 * aarch64-opc.c (operand_general_constraint_met_p): Remove
320 case for ldstgv_indexed.
321 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
322 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
323 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
324 * aarch64-asm-2.c: Regenerated.
325 * aarch64-dis-2.c: Regenerated.
326 * aarch64-opc-2.c: Regenerated.
327
3282019-01-23 Nick Clifton <nickc@redhat.com>
329
330 * po/pt_BR.po: Updated Brazilian Portuguese translation.
331
3322019-01-21 Nick Clifton <nickc@redhat.com>
333
334 * po/de.po: Updated German translation.
335 * po/uk.po: Updated Ukranian translation.
336
3372019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
338 * mips-dis.c (mips_arch_choices): Fix typo in
339 gs464, gs464e and gs264e descriptors.
340
3412019-01-19 Nick Clifton <nickc@redhat.com>
342
343 * configure: Regenerate.
344 * po/opcodes.pot: Regenerate.
345
3462018-06-24 Nick Clifton <nickc@redhat.com>
347
348 2.32 branch created.
349
3502019-01-09 John Darrington <john@darrington.wattle.id.au>
351
352 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
353 if it is null.
354 -dis.c (opr_emit_disassembly): Do not omit an index if it is
355 zero.
356
3572019-01-09 Andrew Paprocki <andrew@ishiboo.com>
358
359 * configure: Regenerate.
360
3612019-01-07 Alan Modra <amodra@gmail.com>
362
363 * configure: Regenerate.
364 * po/POTFILES.in: Regenerate.
365
3662019-01-03 John Darrington <john@darrington.wattle.id.au>
367
368 * s12z-opc.c: New file.
369 * s12z-opc.h: New file.
370 * s12z-dis.c: Removed all code not directly related to display
371 of instructions. Used the interface provided by the new files
372 instead.
373 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
374 * Makefile.in: Regenerate.
375 * configure.ac (bfd_s12z_arch): Correct the dependencies.
376 * configure: Regenerate.
377
3782019-01-01 Alan Modra <amodra@gmail.com>
379
380 Update year range in copyright notice of all files.
381
382For older changes see ChangeLog-2018
383\f
384Copyright (C) 2019 Free Software Foundation, Inc.
385
386Copying and distribution of this file, with or without modification,
387are permitted in any medium without royalty provided the copyright
388notice and this notice are preserved.
389
390Local Variables:
391mode: change-log
392left-margin: 8
393fill-column: 74
394version-control: never
395End:
GDB Binutils - Deliverables
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