[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2012-05-11  Nick Clifton  <nickc@redhat.com>

	PR binutils/14006
	* arm-dis.c (print_insn): Fix detection of instruction mode in
	files containing multiple executable sections.

2012-05-03  Sean Keys  <skeys@ipdatasys.com>

	* Makefile.in, configure: regenerate
	* disassemble.c (disassembler): Recognize ARCH_XGATE.
	* xgate-dis.c (read_memory, print_insn, print_insn_xgate):
	New functions.
	* configure.in: Recognize xgate.
	* xgate-dis.c, xgate-opc.c: New files for support of xgate
	* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
	and opcode generation for xgate.

2012-04-30  DJ Delorie  <dj@redhat.com>

	* rx-decode.opc (MOV): Do not sign-extend immediates which are
	already the maximum bit size.
	* rx-decode.c: Regenerate.

2012-04-27  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
	* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.

	* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
	* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.

	* sparc-opc.c (CBCOND): New define.
	(CBCOND_XCC): Likewise.
	(cbcond): New helper macro.
	(sparc_opcodes): Add compare-and-branch instructions.

	* sparc-dis.c (print_insn_sparc): Handle ')'.
	* sparc-opc.c (sparc_opcodes): Add crypto instructions.

	* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
	into new struct sparc_opcode 'hwcaps' field instead of 'flags'.

2012-04-12  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (X_DISP10): Define.
	(print_insn_sparc): Handle '='.

2012-04-01  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (fmtconst): Replace decimal handling with a single
	sprintf call and the '*' field width.

2012-03-23  Maxim Kuvyrkov  <maxim@codesourcery.com>

	* mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.

2012-03-16  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
	(powerpc_opcd_indices): Bump array size.
	(disassemble_init_powerpc): Set powerpc_opcd_indices entries
	corresponding to unused opcodes to following entry.
	(lookup_powerpc): New function, extracted and optimised from..
	(print_insn_powerpc): ..here.

2012-03-15  Alan Modra  <amodra@gmail.com>
	    James Lemke  <jwlemke@codesourcery.com>

	* disassemble.c (disassemble_init_for_target): Handle ppc init.
	* ppc-dis.c (private): New var.
	(powerpc_init_dialect): Don't return calloc failure, instead use
	private.
	(PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
	(powerpc_opcd_indices): New array.
	(disassemble_init_powerpc): New function.
	(print_insn_big_powerpc): Don't init dialect here.
	(print_insn_little_powerpc): Likewise.
	(print_insn_powerpc): Start search using powerpc_opcd_indices.

2012-03-10  Edmar Wienskoski  <edmar@freescale.com>

	* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
	* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
	(PPCVEC2, PPCTMR, E6500): New short names.
	(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
	mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
	lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
	lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
	lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
	optional operands on sync instruction for E6500 target.

2012-03-08  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.txt: Set instruction type of pku to SS_L2RDRD.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* mt-dis.c: Regenerate.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* v850-opc.c (extract_v8): Rearrange to make it obvious this
	is the inverse of corresponding insert function.
	(extract_d22, extract_u9, extract_r4): Likewise.
	(extract_d9): Correct sign extension.
	(extract_d16_15): Don't assume "long" is 32 bits, and don't
	rely on implementation defined behaviour for shift right of
	signed types.
	(extract_d16_16, extract_d17_16, extract_i9): Likewise.
	(extract_d23): Likewise, and correct mask.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (print_arg): Mask constant to 32 bits.
	* crx-opc.c (cst4_map): Use int array.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* arc-dis.c (BITS): Don't use shifts to mask off bits.
	(FIELDD): Sign extend with xor,sub.

2012-02-25  Walter Lee  <walt@tilera.com>

	* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
	* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
	TILEPRO_OPC_LW_TLS_SN.

2012-02-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (HLEPrefixNone): New.
	(HLEPrefixLock): Likewise.
	(HLEPrefixAny): Likewise.
	(HLEPrefixRelease): Likewise.

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (HLE_Fixup1): New.
	(HLE_Fixup2): Likewise.
	(HLE_Fixup3): Likewise.
	(Ebh1): Likewise.
	(Evh1): Likewise.
	(Ebh2): Likewise.
	(Evh2): Likewise.
	(Ebh3): Likewise.
	(Evh3): Likewise.
	(MOD_C6_REG_7): Likewise.
	(MOD_C7_REG_7): Likewise.
	(RM_C6_REG_7): Likewise.
	(RM_C7_REG_7): Likewise.
	(XACQUIRE_PREFIX): Likewise.
	(XRELEASE_PREFIX): Likewise.
	(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
	cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
	Ebh2/Evh2 on xchg.  Use Ebh3/Evh3 on mov.
	(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
	not, or, sbb, sub and xor.  Use Ebh3/Evh3 on mov.  Use
	MOD_C6_REG_7 and MOD_C7_REG_7.
	(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
	(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7.  Add xend and
	xtest.
	(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
	(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.

	* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
	CPU_RTM_FLAGS.
	(cpu_flags): Add CpuHLE and CpuRTM.
	(opcode_modifiers): Add HLEPrefixOk.

	* i386-opc.h (CpuHLE): New.
	(CpuRTM): Likewise.
	(HLEPrefixOk): Likewise.
	(i386_cpu_flags): Add cpuhle and cpurtm.
	(i386_opcode_modifier): Add hleprefixok.

	* i386-opc.tbl: Add HLEPrefixOk=3 to mov.  Add HLEPrefixOk to
	add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
	sbb, sub, xor and xadd.  Add HLEPrefixOk=2 to xchg with memory
	operand.  Add xacquire, xrelease, xabort, xbegin, xend and
	xtest.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2012-01-24  DJ Delorie  <dj@redhat.com>

	* rl78-decode.opc (rl78_decode_opcode): Add NOT1.
	* rl78-decode.c: Regenerate.

2012-01-17  James Murray  <jsm@jsm-net.demon.co.uk>

	PR binutils/10173
	* cr16-dis.c (print_arg): Test symtab_size not num_symbols.

2012-01-17  Andreas Schwab  <schwab@linux-m68k.org>

	* m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
	register and move them after pmove with PSR/PCSR register.

2012-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (mod_table): Add vmfunc.

	* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
	(cpu_flags): CpuVMFUNC.

	* i386-opc.h (CpuVMFUNC): New.
	(i386_cpu_flags): Add cpuvmfunc.

	* i386-opc.tbl: Add vmfunc.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

For older changes see ChangeLog-2011
\f
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mode: change-log
left-margin: 8
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Commit	Line	Data
	1	2012-05-11 Nick Clifton <nickc@redhat.com>
	2
	3	PR binutils/14006
	4	* arm-dis.c (print_insn): Fix detection of instruction mode in
	5	files containing multiple executable sections.
	6
	7	2012-05-03 Sean Keys <skeys@ipdatasys.com>
	8
	9	* Makefile.in, configure: regenerate
	10	* disassemble.c (disassembler): Recognize ARCH_XGATE.
	11	* xgate-dis.c (read_memory, print_insn, print_insn_xgate):
	12	New functions.
	13	* configure.in: Recognize xgate.
	14	* xgate-dis.c, xgate-opc.c: New files for support of xgate
	15	* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
	16	and opcode generation for xgate.
	17
	18	2012-04-30 DJ Delorie <dj@redhat.com>
	19
	20	* rx-decode.opc (MOV): Do not sign-extend immediates which are
	21	already the maximum bit size.
	22	* rx-decode.c: Regenerate.
	23
	24	2012-04-27 David S. Miller <davem@davemloft.net>
	25
	26	* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
	27	* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
	28
	29	* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
	30	* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
	31
	32	* sparc-opc.c (CBCOND): New define.
	33	(CBCOND_XCC): Likewise.
	34	(cbcond): New helper macro.
	35	(sparc_opcodes): Add compare-and-branch instructions.
	36
	37	* sparc-dis.c (print_insn_sparc): Handle ')'.
	38	* sparc-opc.c (sparc_opcodes): Add crypto instructions.
	39
	40	* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
	41	into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
	42
	43	2012-04-12 David S. Miller <davem@davemloft.net>
	44
	45	* sparc-dis.c (X_DISP10): Define.
	46	(print_insn_sparc): Handle '='.
	47
	48	2012-04-01 Mike Frysinger <vapier@gentoo.org>
	49
	50	* bfin-dis.c (fmtconst): Replace decimal handling with a single
	51	sprintf call and the '*' field width.
	52
	53	2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
	54
	55	* mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
	56
	57	2012-03-16 Alan Modra <amodra@gmail.com>
	58
	59	* ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
	60	(powerpc_opcd_indices): Bump array size.
	61	(disassemble_init_powerpc): Set powerpc_opcd_indices entries
	62	corresponding to unused opcodes to following entry.
	63	(lookup_powerpc): New function, extracted and optimised from..
	64	(print_insn_powerpc): ..here.
	65
	66	2012-03-15 Alan Modra <amodra@gmail.com>
	67	James Lemke <jwlemke@codesourcery.com>
	68
	69	* disassemble.c (disassemble_init_for_target): Handle ppc init.
	70	* ppc-dis.c (private): New var.
	71	(powerpc_init_dialect): Don't return calloc failure, instead use
	72	private.
	73	(PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
	74	(powerpc_opcd_indices): New array.
	75	(disassemble_init_powerpc): New function.
	76	(print_insn_big_powerpc): Don't init dialect here.
	77	(print_insn_little_powerpc): Likewise.
	78	(print_insn_powerpc): Start search using powerpc_opcd_indices.
	79
	80	2012-03-10 Edmar Wienskoski <edmar@freescale.com>
	81
	82	* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
	83	* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
	84	(PPCVEC2, PPCTMR, E6500): New short names.
	85	(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
	86	mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
	87	lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
	88	lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
	89	lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
	90	optional operands on sync instruction for E6500 target.
	91
	92	2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	93
	94	* s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
	95
	96	2012-02-27 Alan Modra <amodra@gmail.com>
	97
	98	* mt-dis.c: Regenerate.
	99
	100	2012-02-27 Alan Modra <amodra@gmail.com>
	101
	102	* v850-opc.c (extract_v8): Rearrange to make it obvious this
	103	is the inverse of corresponding insert function.
	104	(extract_d22, extract_u9, extract_r4): Likewise.
	105	(extract_d9): Correct sign extension.
	106	(extract_d16_15): Don't assume "long" is 32 bits, and don't
	107	rely on implementation defined behaviour for shift right of
	108	signed types.
	109	(extract_d16_16, extract_d17_16, extract_i9): Likewise.
	110	(extract_d23): Likewise, and correct mask.
	111
	112	2012-02-27 Alan Modra <amodra@gmail.com>
	113
	114	* crx-dis.c (print_arg): Mask constant to 32 bits.
	115	* crx-opc.c (cst4_map): Use int array.
	116
	117	2012-02-27 Alan Modra <amodra@gmail.com>
	118
	119	* arc-dis.c (BITS): Don't use shifts to mask off bits.
	120	(FIELDD): Sign extend with xor,sub.
	121
	122	2012-02-25 Walter Lee <walt@tilera.com>
	123
	124	* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
	125	* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
	126	TILEPRO_OPC_LW_TLS_SN.
	127
	128	2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
	129
	130	* i386-opc.h (HLEPrefixNone): New.
	131	(HLEPrefixLock): Likewise.
	132	(HLEPrefixAny): Likewise.
	133	(HLEPrefixRelease): Likewise.
	134
	135	2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
	136
	137	* i386-dis.c (HLE_Fixup1): New.
	138	(HLE_Fixup2): Likewise.
	139	(HLE_Fixup3): Likewise.
	140	(Ebh1): Likewise.
	141	(Evh1): Likewise.
	142	(Ebh2): Likewise.
	143	(Evh2): Likewise.
	144	(Ebh3): Likewise.
	145	(Evh3): Likewise.
	146	(MOD_C6_REG_7): Likewise.
	147	(MOD_C7_REG_7): Likewise.
	148	(RM_C6_REG_7): Likewise.
	149	(RM_C7_REG_7): Likewise.
	150	(XACQUIRE_PREFIX): Likewise.
	151	(XRELEASE_PREFIX): Likewise.
	152	(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
	153	cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
	154	Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
	155	(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
	156	not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
	157	MOD_C6_REG_7 and MOD_C7_REG_7.
	158	(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
	159	(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
	160	xtest.
	161	(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
	162	(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
	163
	164	* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
	165	CPU_RTM_FLAGS.
	166	(cpu_flags): Add CpuHLE and CpuRTM.
	167	(opcode_modifiers): Add HLEPrefixOk.
	168
	169	* i386-opc.h (CpuHLE): New.
	170	(CpuRTM): Likewise.
	171	(HLEPrefixOk): Likewise.
	172	(i386_cpu_flags): Add cpuhle and cpurtm.
	173	(i386_opcode_modifier): Add hleprefixok.
	174
	175	* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
	176	add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
	177	sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
	178	operand. Add xacquire, xrelease, xabort, xbegin, xend and
	179	xtest.
	180	* i386-init.h: Regenerated.
	181	* i386-tbl.h: Likewise.
	182
	183	2012-01-24 DJ Delorie <dj@redhat.com>
	184
	185	* rl78-decode.opc (rl78_decode_opcode): Add NOT1.
	186	* rl78-decode.c: Regenerate.
	187
	188	2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
	189
	190	PR binutils/10173
	191	* cr16-dis.c (print_arg): Test symtab_size not num_symbols.
	192
	193	2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
	194
	195	* m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
	196	register and move them after pmove with PSR/PCSR register.
	197
	198	2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
	199
	200	* i386-dis.c (mod_table): Add vmfunc.
	201
	202	* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
	203	(cpu_flags): CpuVMFUNC.
	204
	205	* i386-opc.h (CpuVMFUNC): New.
	206	(i386_cpu_flags): Add cpuvmfunc.
	207
	208	* i386-opc.tbl: Add vmfunc.
	209	* i386-init.h: Regenerated.
	210	* i386-tbl.h: Likewise.
	211
	212	For older changes see ChangeLog-2011
	213	\f
	214	Local Variables:
	215	mode: change-log
	216	left-margin: 8
	217	fill-column: 74
	218	version-control: never
	219	End: