projects / deliverable / binutils-gdb.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
New Year - binutils ChangeLog rotation
[deliverable/binutils-gdb.git] / opcodes / ChangeLog-2013
... / ...
CommitLineData
12013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com>
2
3 * nds32-dis.c (sr_map): Add system register table for disassembling.
4 (usr_map): Fix typo.
5 * nds32-asm.c (keyword_sr): Add embedded debug registers.
6
72013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
8
9 * i386-dis.c (MOD_FF_REG_3): New.
10 (MOD_FF_REG_5): Likewise.
11 (mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
12 (reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.
13
142013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
15
16 * mips-dis.c: Add mips_cp1_names pointer.
17 (mips_cp1_names_numeric): New array.
18 (mips_cp1_names_mips3264): New array.
19 (mips_arch_choice): Add cp1_names.
20 (mips_arch_choices): Add relevant cp1 register name array to each of
21 the elements.
22 (set_default_mips_dis_options): Add support for setting up the
23 mips_cp1_names pointer.
24 (parse_mips_dis_option): Add support for the cp1-names command line
25 variable. Also setup the mips_cp1_names pointer.
26 (print_reg): Print out name of the cp1 register.
27
282013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
29
30 * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
31 +v and +w.
32 (micromips_opcodes): Reduced element index range for sldi, splati,
33 copy_s, copy_u, insert and insve instructions.
34 * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
35 +v and +w.
36 (mips_builtin_opcodes): Reduced element index range for sldi, splati,
37 copy_s, copy_u, insert and insve instructions.
38
392013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
40
41 * nds32-dis.c (mnemonic_96): Fix typo.
42
432013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
44 Wei-Cheng Wang <cole945@gmail.com>
45
46 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
47 and nds32-dis.c.
48 * Makefile.in: Regenerate.
49 * configure.in: Add case for bfd_nds32_arch.
50 * configure: Regenerate.
51 * disassemble.c (ARCH_nds32): Define.
52 * nds32-asm.c: New file for nds32.
53 * nds32-asm.h: New file for nds32.
54 * nds32-dis.c: New file for nds32.
55 * nds32-opc.h: New file for nds32.
56
572013-12-05 Nick Clifton <nickc@redhat.com>
58
59 * s390-mkopc.c (dumpTable): Provide a format string to printf so
60 that compiling with -Werror=format-security does not produce an
61 error.
62
632013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
64
65 * aarch64-opc.c (aarch64_pstatefields): Update.
66
672013-11-19 Catherine Moore <clm@codesourcery.com>
68
69 * micromips-opc.c (LM): Define.
70 (micromips_opcodes): Add LM to load instructions.
71 * mips-opc.c (prefe): Add LM attribute.
72
732013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
74
75 Revert
76
77 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
78
79 * aarch64-opc.c (CPENT): New define.
80 (F_READONLY, F_WRITEONLY): Likewise.
81 (aarch64_sys_regs): Add trace unit registers.
82 (aarch64_sys_reg_readonly_p): New function.
83 (aarch64_sys_reg_writeonly_p): Ditto.
84
852013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
86
87 * aarch64-opc.c (CPENT): New define.
88 (F_READONLY, F_WRITEONLY): Likewise.
89 (aarch64_sys_regs): Add trace unit registers.
90 (aarch64_sys_reg_readonly_p): New function.
91 (aarch64_sys_reg_writeonly_p): Ditto.
92
932013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
94
95 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
96 "mtcr".
97
982013-11-11 Catherine Moore <clm@codesourcery.com>
99
100 * mips-dis.c (print_insn_mips): Use
101 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
102 (print_insn_micromips): Likewise.
103 * mips-opc.c (LDD): Remove.
104 (CLD): Include INSN_LOAD_MEMORY.
105 (LM): New.
106 (mips_builtin_opcodes): Use LM instead of LDD.
107 Add LM to load instructions.
108
1092013-11-08 H.J. Lu <hongjiu.lu@intel.com>
110
111 PR gas/16140
112 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
113 * i386-init.h: Regenerated.
114
1152013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
116
117 * aarch64-opc.c (F_DEPRECATED): New macro.
118 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
119 F_DEPRECATED.
120 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
121 AARCH64_OPND_SYSREG.
122
1232013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
124
125 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
126 (convert_from_csel): Likewise.
127 * aarch64-opc.c (operand_general_constraint_met_p): Handle
128 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
129 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
130 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
131 COND for cinc, cset, cinv, csetm and cneg.
132 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
133 * aarch64-asm-2.c: Re-generated.
134 * aarch64-dis-2.c: Ditto.
135 * aarch64-opc-2.c: Ditto.
136
1372013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
138
139 * aarch64-opc.c (set_syntax_error): New function.
140 (operand_general_constraint_met_p): Replace set_other_error
141 with set_syntax_error.
142
1432013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
144
145 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
146 availability even for 31-bit programs.
147
1482013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
149
150 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
151
1522013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
153
154 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
155 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
156 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
157 (MSA): New define.
158 (MSA64): New define.
159 (micromips_opcodes): Add MSA instructions.
160 * mips-dis.c (msa_control_names): New array.
161 (mips_abi_choice): Add ASE_MSA to mips32r2.
162 Remove ASE_MDMX from mips64r2.
163 Add ASE_MSA and ASE_MSA64 to mips64r2.
164 (parse_mips_dis_option): Handle -Mmsa.
165 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
166 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
167 (print_mips_disassembler_options): Print -Mmsa.
168 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
169 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
170 (MSA): New define.
171 (MSA64): New define.
172 (mips_builtin_op): Add MSA instructions.
173
1742013-10-13 Sandra Loosemore <sandra@codesourcery.com>
175
176 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
177 as the primary name of r30.
178
1792013-10-12 Jan Beulich <jbeulich@suse.com>
180
181 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
182 default case.
183 (OP_E_register): Move v_bnd_mode alongside m_mode.
184 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
185 Drop Reg16 and Disp16. Add NoRex64.
186 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
187 * i386-tbl.h: Re-generate.
188
1892013-10-10 Sean Keys <skeys@ipdatasys.com>
190
191 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
192 table.
193 * xgate-dis.c (print_insn): Refactor to work with table change.
194
1952013-10-10 Roland McGrath <mcgrathr@google.com>
196
197 * i386-dis.c (oappend_maybe_intel): New function.
198 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
199 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
200 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
201
202 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
203 possible compiler warnings when the union's initializer is
204 actually meant for the 'preg' enum typed member.
205 * crx-opc.c (REG): Likewise.
206
207 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
208 Remove duplicate const qualifier.
209
2102013-10-08 Jan Beulich <jbeulich@suse.com>
211
212 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
213 (clflush): Use Anysize instead of Byte|Unspecified.
214 (prefetch*): Likewise.
215 * i386-tbl.h: Re-generate.
216
2172013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
218
219 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
220
2212013-09-30 H.J. Lu <hongjiu.lu@intel.com>
222
223 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
224 * i386-init.h: Regenerated.
225
2262013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
227
228 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
229 * i386-init.h: Regenerated.
230
2312013-09-20 Alan Modra <amodra@gmail.com>
232
233 * configure: Regenerate.
234
2352013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
236
237 * s390-opc.txt (clih): Make the immediate unsigned.
238
2392013-09-04 Roland McGrath <mcgrathr@google.com>
240
241 PR gas/15914
242 * arm-dis.c (arm_opcodes): Add udf.
243 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
244 (thumb32_opcodes): Add udf.w.
245 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
246
2472013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
248
249 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
250 For the load fp integer instructions only the suppression flag was
251 new with z196 version.
252
2532013-08-28 Nick Clifton <nickc@redhat.com>
254
255 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
256 immediate is not suitable for the 32-bit ABI.
257
2582013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
259
260 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
261 replacing NODS.
262
2632013-08-23 Yuri Chornoivan <yurchor@ukr.net>
264
265 PR binutils/15834
266 * aarch64-asm.c: Fix typos.
267 * aarch64-dis.c: Likewise.
268 * msp430-dis.c: Likewise.
269
2702013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
271
272 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
273 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
274 Use +H rather than +C for the real "dext".
275 * mips-opc.c (mips_builtin_opcodes): Likewise.
276
2772013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
278
279 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
280 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
281 and OPTIONAL_MAPPED_REG.
282 * mips-opc.c (decode_mips_operand): Likewise.
283 * mips16-opc.c (decode_mips16_operand): Likewise.
284 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
285
2862013-08-19 H.J. Lu <hongjiu.lu@intel.com>
287
288 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
289 (PREFIX_EVEX_0F3A3F): Likewise.
290 * i386-dis-evex.h (evex_table): Updated.
291
2922013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
293
294 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
295 VCLIPW.
296
2972013-08-05 Eric Botcazou <ebotcazou@adacore.com>
298 Konrad Eisele <konrad@gaisler.com>
299
300 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
301 bfd_mach_sparc.
302 * sparc-opc.c (MASK_LEON): Define.
303 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
304 (letandleon): New macro.
305 (v9andleon): Likewise.
306 (sparc_opc): Add leon.
307 (umac): Enable for letandleon.
308 (smac): Likewise.
309 (casa): Enable for v9andleon.
310 (cas): Likewise.
311 (casl): Likewise.
312
3132013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
314 Richard Sandiford <rdsandiford@googlemail.com>
315
316 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
317 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
318 (print_vu0_channel): New function.
319 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
320 (print_insn_args): Handle '#'.
321 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
322 * mips-opc.c (mips_vu0_channel_mask): New constant.
323 (decode_mips_operand): Handle new VU0 operand types.
324 (VU0, VU0CH): New macros.
325 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
326 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
327 Use "+6" rather than "G" for QMFC2 and QMTC2.
328
3292013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
330
331 * mips-formats.h (PCREL): Reorder parameters and update the definition
332 to match new mips_pcrel_operand layout.
333 (JUMP, JALX, BRANCH): Update accordingly.
334 * mips16-opc.c (decode_mips16_operand): Likewise.
335
3362013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
337
338 * micromips-opc.c (WR_s): Delete.
339
3402013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
341
342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
343 New macros.
344 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
345 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
346 (mips_builtin_opcodes): Use the new position-based read-write flags
347 instead of field-based ones. Use UDI for "udi..." instructions.
348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
349 New macros.
350 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
351 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
352 (WR_SP, RD_16): New macros.
353 (RD_SP): Redefine as an INSN2_* flag.
354 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
355 (mips16_opcodes): Use the new position-based read-write flags
356 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
357 pinfo2 field.
358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
359 New macros.
360 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
361 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
362 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
363 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
364 (micromips_opcodes): Use the new position-based read-write flags
365 instead of field-based ones.
366 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
367 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
368 of field-based flags.
369
3702013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
371
372 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
373 (WR_SP): Replace with...
374 (MOD_SP): ...this.
375 (mips16_opcodes): Update accordingly.
376 * mips-dis.c (print_insn_mips16): Likewise.
377
3782013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
379
380 * mips16-opc.c (mips16_opcodes): Reformat.
381
3822013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
383
384 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
385 for operands that are hard-coded to $0.
386 * micromips-opc.c (micromips_opcodes): Likewise.
387
3882013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
389
390 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
391 for the single-operand forms of JALR and JALR.HB.
392 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
393 and JALRS.HB.
394
3952013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
396
397 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
398 instructions. Fix them to use WR_MACC instead of WR_CC and
399 add missing RD_MACCs.
400
4012013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
404
4052013-07-29 Peter Bergner <bergner@vnet.ibm.com>
406
407 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
408
4092013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
410 Alexander Ivchenko <alexander.ivchenko@intel.com>
411 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
412 Sergey Lega <sergey.s.lega@intel.com>
413 Anna Tikhonova <anna.tikhonova@intel.com>
414 Ilya Tocar <ilya.tocar@intel.com>
415 Andrey Turetskiy <andrey.turetskiy@intel.com>
416 Ilya Verbin <ilya.verbin@intel.com>
417 Kirill Yukhin <kirill.yukhin@intel.com>
418 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
419
420 * i386-dis-evex.h: New.
421 * i386-dis.c (OP_Rounding): New.
422 (VPCMP_Fixup): New.
423 (OP_Mask): New.
424 (Rdq): New.
425 (XMxmmq): New.
426 (EXdScalarS): New.
427 (EXymm): New.
428 (EXEvexHalfBcstXmmq): New.
429 (EXxmm_mdq): New.
430 (EXEvexXGscat): New.
431 (EXEvexXNoBcst): New.
432 (VPCMP): New.
433 (EXxEVexR): New.
434 (EXxEVexS): New.
435 (XMask): New.
436 (MaskG): New.
437 (MaskE): New.
438 (MaskR): New.
439 (MaskVex): New.
440 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
441 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
442 evex_rounding_mode, evex_sae_mode, mask_mode.
443 (USE_EVEX_TABLE): New.
444 (EVEX_TABLE): New.
445 (EVEX enum): New.
446 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
447 REG_EVEX_0F38C7.
448 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
449 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
450 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
451 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
452 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
453 MOD_EVEX_0F38C7_REG_6.
454 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
455 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
456 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
457 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
458 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
459 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
460 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
461 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
462 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
463 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
464 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
465 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
466 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
467 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
468 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
469 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
470 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
471 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
472 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
473 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
474 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
475 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
476 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
477 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
478 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
479 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
480 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
481 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
482 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
483 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
484 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
485 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
486 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
487 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
488 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
489 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
490 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
491 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
492 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
493 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
494 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
495 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
496 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
497 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
498 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
499 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
500 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
501 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
502 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
503 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
504 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
505 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
506 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
507 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
508 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
509 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
510 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
511 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
512 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
513 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
514 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
515 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
516 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
517 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
518 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
519 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
520 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
521 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
522 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
523 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
524 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
525 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
526 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
527 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
528 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
529 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
530 PREFIX_EVEX_0F3A55.
531 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
532 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
533 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
534 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
535 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
536 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
537 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
538 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
539 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
540 VEX_W_0F3A32_P_2_LEN_0.
541 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
542 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
543 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
544 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
545 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
546 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
547 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
548 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
549 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
550 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
551 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
552 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
553 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
554 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
555 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
556 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
557 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
558 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
559 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
560 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
561 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
562 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
563 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
564 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
565 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
566 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
567 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
568 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
569 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
570 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
571 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
572 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
573 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
574 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
575 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
576 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
577 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
578 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
579 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
580 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
581 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
582 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
583 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
584 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
585 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
586 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
587 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
588 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
589 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
590 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
591 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
592 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
593 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
594 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
595 (struct vex): Add fields evex, r, v, mask_register_specifier,
596 zeroing, ll, b.
597 (intel_names_xmm): Add upper 16 registers.
598 (att_names_xmm): Ditto.
599 (intel_names_ymm): Ditto.
600 (att_names_ymm): Ditto.
601 (names_zmm): New.
602 (intel_names_zmm): Ditto.
603 (att_names_zmm): Ditto.
604 (names_mask): Ditto.
605 (intel_names_mask): Ditto.
606 (att_names_mask): Ditto.
607 (names_rounding): Ditto.
608 (names_broadcast): Ditto.
609 (x86_64_table): Add escape to evex-table.
610 (reg_table): Include reg_table evex-entries from
611 i386-dis-evex.h. Fix prefetchwt1 instruction.
612 (prefix_table): Add entries for new instructions.
613 (vex_table): Ditto.
614 (vex_len_table): Ditto.
615 (vex_w_table): Ditto.
616 (mod_table): Ditto.
617 (get_valid_dis386): Properly handle new instructions.
618 (print_insn): Handle zmm and mask registers, print mask operand.
619 (intel_operand_size): Support EVEX, new modes and sizes.
620 (OP_E_register): Handle new modes.
621 (OP_E_memory): Ditto.
622 (OP_G): Ditto.
623 (OP_XMM): Ditto.
624 (OP_EX): Ditto.
625 (OP_VEX): Ditto.
626 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
627 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
628 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
629 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
630 CpuAVX512PF and CpuVREX.
631 (operand_type_init): Add OPERAND_TYPE_REGZMM,
632 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
633 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
634 StaticRounding, SAE, Disp8MemShift, NoDefMask.
635 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
636 * i386-init.h: Regenerate.
637 * i386-opc.h (CpuAVX512F): New.
638 (CpuAVX512CD): New.
639 (CpuAVX512ER): New.
640 (CpuAVX512PF): New.
641 (CpuVREX): New.
642 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
643 cpuavx512pf and cpuvrex fields.
644 (VecSIB): Add VecSIB512.
645 (EVex): New.
646 (Masking): New.
647 (VecESize): New.
648 (Broadcast): New.
649 (StaticRounding): New.
650 (SAE): New.
651 (Disp8MemShift): New.
652 (NoDefMask): New.
653 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
654 staticrounding, sae, disp8memshift and nodefmask.
655 (RegZMM): New.
656 (Zmmword): Ditto.
657 (Vec_Disp8): Ditto.
658 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
659 fields.
660 (RegVRex): New.
661 * i386-opc.tbl: Add AVX512 instructions.
662 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
663 registers, mask registers.
664 * i386-tbl.h: Regenerate.
665
6662013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
667
668 PR gas/15220
669 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
670 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
671
6722013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
673
674 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
675 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
676 PREFIX_0F3ACC.
677 (prefix_table): Updated.
678 (three_byte_table): Likewise.
679 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
680 (cpu_flags): Add CpuSHA.
681 (i386_cpu_flags): Add cpusha.
682 * i386-init.h: Regenerate.
683 * i386-opc.h (CpuSHA): New.
684 (CpuUnused): Restored.
685 (i386_cpu_flags): Add cpusha.
686 * i386-opc.tbl: Add SHA instructions.
687 * i386-tbl.h: Regenerate.
688
6892013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
690 Kirill Yukhin <kirill.yukhin@intel.com>
691 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
692
693 * i386-dis.c (BND_Fixup): New.
694 (Ebnd): New.
695 (Ev_bnd): New.
696 (Gbnd): New.
697 (BND): New.
698 (v_bnd_mode): New.
699 (bnd_mode): New.
700 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
701 MOD_0F1B_PREFIX_1.
702 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
703 (dis tables): Replace XX with BND for near branch and call
704 instructions.
705 (prefix_table): Add new entries.
706 (mod_table): Likewise.
707 (names_bnd): New.
708 (intel_names_bnd): New.
709 (att_names_bnd): New.
710 (BND_PREFIX): New.
711 (prefix_name): Handle BND_PREFIX.
712 (print_insn): Initialize names_bnd.
713 (intel_operand_size): Handle new modes.
714 (OP_E_register): Likewise.
715 (OP_E_memory): Likewise.
716 (OP_G): Likewise.
717 * i386-gen.c (cpu_flag_init): Add CpuMPX.
718 (cpu_flags): Add CpuMPX.
719 (operand_type_init): Add RegBND.
720 (opcode_modifiers): Add BNDPrefixOk.
721 (operand_types): Add RegBND.
722 * i386-init.h: Regenerate.
723 * i386-opc.h (CpuMPX): New.
724 (CpuUnused): Comment out.
725 (i386_cpu_flags): Add cpumpx.
726 (BNDPrefixOk): New.
727 (i386_opcode_modifier): Add bndprefixok.
728 (RegBND): New.
729 (i386_operand_type): Add regbnd.
730 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
731 Add MPX instructions and bnd prefix.
732 * i386-reg.tbl: Add bnd0-bnd3 registers.
733 * i386-tbl.h: Regenerate.
734
7352013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
736
737 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
738 ATTRIBUTE_UNUSED.
739
7402013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
741
742 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
743 special rules.
744 * Makefile.in: Regenerate.
745 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
746 all fields. Reformat.
747
7482013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
749
750 * mips16-opc.c: Include mips-formats.h.
751 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
752 static arrays.
753 (decode_mips16_operand): New function.
754 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
755 (print_insn_arg): Handle OP_ENTRY_EXIT list.
756 Abort for OP_SAVE_RESTORE_LIST.
757 (print_mips16_insn_arg): Change interface. Use mips_operand
758 structures. Delete GET_OP_S. Move GET_OP definition to...
759 (print_insn_mips16): ...here. Call init_print_arg_state.
760 Update the call to print_mips16_insn_arg.
761
7622013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
763
764 * mips-formats.h: New file.
765 * mips-opc.c: Include mips-formats.h.
766 (reg_0_map): New static array.
767 (decode_mips_operand): New function.
768 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
769 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
770 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
771 (int_c_map): New static arrays.
772 (decode_micromips_operand): New function.
773 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
774 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
775 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
776 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
777 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
778 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
779 (micromips_imm_b_map, micromips_imm_c_map): Delete.
780 (print_reg): New function.
781 (mips_print_arg_state): New structure.
782 (init_print_arg_state, print_insn_arg): New functions.
783 (print_insn_args): Change interface and use mips_operand structures.
784 Delete GET_OP_S. Move GET_OP definition to...
785 (print_insn_mips): ...here. Update the call to print_insn_args.
786 (print_insn_micromips): Use print_insn_args.
787
7882013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
789
790 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
791 in macros.
792
7932013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
794
795 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
796 ADDA.S, MULA.S and SUBA.S.
797
7982013-07-08 H.J. Lu <hongjiu.lu@intel.com>
799
800 PR gas/13572
801 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
802 * i386-tbl.h: Regenerated.
803
8042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
805
806 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
807 and SD A(B) macros up.
808 * micromips-opc.c (micromips_opcodes): Likewise.
809
8102013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
811
812 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
813 instructions.
814
8152013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
816
817 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
818 MDMX-like instructions.
819 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
820 printing "Q" operands for INSN_5400 instructions.
821
8222013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
823
824 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
825 "+S" for "cins".
826 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
827 Combine cases.
828
8292013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
830
831 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
832 "jalx".
833 * mips16-opc.c (mips16_opcodes): Likewise.
834 * micromips-opc.c (micromips_opcodes): Likewise.
835 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
836 (print_insn_mips16): Handle "+i".
837 (print_insn_micromips): Likewise. Conditionally preserve the
838 ISA bit for "a" but not for "+i".
839
8402013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
841
842 * micromips-opc.c (WR_mhi): Rename to..
843 (WR_mh): ...this.
844 (micromips_opcodes): Update "movep" entry accordingly. Replace
845 "mh,mi" with "mh".
846 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
847 (micromips_to_32_reg_h_map1): ...this.
848 (micromips_to_32_reg_i_map): Rename to...
849 (micromips_to_32_reg_h_map2): ...this.
850 (print_micromips_insn): Remove "mi" case. Print both registers
851 in the pair for "mh".
852
8532013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
854
855 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
856 * micromips-opc.c (micromips_opcodes): Likewise.
857 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
858 and "+T" handling. Check for a "0" suffix when deciding whether to
859 use coprocessor 0 names. In that case, also check for ",H" selectors.
860
8612013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
862
863 * s390-opc.c (J12_12, J24_24): New macros.
864 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
865 (MASK_MII_UPI): Rename to MASK_MII_UPP.
866 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
867
8682013-07-04 Alan Modra <amodra@gmail.com>
869
870 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
871
8722013-06-26 Nick Clifton <nickc@redhat.com>
873
874 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
875 field when checking for type 2 nop.
876 * rx-decode.c: Regenerate.
877
8782013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
879
880 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
881 and "movep" macros.
882
8832013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
884
885 * mips-dis.c (is_mips16_plt_tail): New function.
886 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
887 word.
888 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
889
8902013-06-21 DJ Delorie <dj@redhat.com>
891
892 * msp430-decode.opc: New.
893 * msp430-decode.c: New/generated.
894 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
895 (MAINTAINER_CLEANFILES): Likewise.
896 Add rule to build msp430-decode.c frommsp430decode.opc
897 using the opc2c program.
898 * Makefile.in: Regenerate.
899 * configure.in: Add msp430-decode.lo to msp430 architecture files.
900 * configure: Regenerate.
901
9022013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
903
904 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
905 (SYMTAB_AVAILABLE): Removed.
906 (#include "elf/aarch64.h): Ditto.
907
9082013-06-17 Catherine Moore <clm@codesourcery.com>
909 Maciej W. Rozycki <macro@codesourcery.com>
910 Chao-Ying Fu <fu@mips.com>
911
912 * micromips-opc.c (EVA): Define.
913 (TLBINV): Define.
914 (micromips_opcodes): Add EVA opcodes.
915 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
916 (print_insn_args): Handle EVA offsets.
917 (print_insn_micromips): Likewise.
918 * mips-opc.c (EVA): Define.
919 (TLBINV): Define.
920 (mips_builtin_opcodes): Add EVA opcodes.
921
9222013-06-17 Alan Modra <amodra@gmail.com>
923
924 * Makefile.am (mips-opc.lo): Add rules to create automatic
925 dependency files. Pass archdefs.
926 (micromips-opc.lo, mips16-opc.lo): Likewise.
927 * Makefile.in: Regenerate.
928
9292013-06-14 DJ Delorie <dj@redhat.com>
930
931 * rx-decode.opc (rx_decode_opcode): Bit operations on
932 registers are 32-bit operations, not 8-bit operations.
933 * rx-decode.c: Regenerate.
934
9352013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
936
937 * micromips-opc.c (IVIRT): New define.
938 (IVIRT64): New define.
939 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
940 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
941
942 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
943 dmtgc0 to print cp0 names.
944
9452013-06-09 Sandra Loosemore <sandra@codesourcery.com>
946
947 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
948 argument.
949
9502013-06-08 Catherine Moore <clm@codesourcery.com>
951 Richard Sandiford <rdsandiford@googlemail.com>
952
953 * micromips-opc.c (D32, D33, MC): Update definitions.
954 (micromips_opcodes): Initialize ase field.
955 * mips-dis.c (mips_arch_choice): Add ase field.
956 (mips_arch_choices): Initialize ase field.
957 (set_default_mips_dis_options): Declare and setup mips_ase.
958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
959 MT32, MC): Update definitions.
960 (mips_builtin_opcodes): Initialize ase field.
961
9622013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
963
964 * s390-opc.txt (flogr): Require a register pair destination.
965
9662013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
967
968 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
969 instruction format.
970
9712013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
972
973 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
974
9752013-05-20 Peter Bergner <bergner@vnet.ibm.com>
976
977 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
978 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
979 XLS_MASK, PPCVSX2): New defines.
980 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
981 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
982 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
983 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
984 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
985 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
986 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
987 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
988 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
989 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
990 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
991 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
992 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
993 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
994 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
995 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
996 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
997 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
998 <lxvx, stxvx>: New extended mnemonics.
999
10002013-05-17 Alan Modra <amodra@gmail.com>
1001
1002 * ia64-raw.tbl: Replace non-ASCII char.
1003 * ia64-waw.tbl: Likewise.
1004 * ia64-asmtab.c: Regenerate.
1005
10062013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
1007
1008 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
1009 * i386-init.h: Regenerated.
1010
10112013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
1012
1013 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
1014 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
1015 check from [0, 255] to [-128, 255].
1016
10172013-05-09 Andrew Pinski <apinski@cavium.com>
1018
1019 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
1020 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
1021 (parse_mips_dis_option): Handle the virt option.
1022 (print_insn_args): Handle "+J".
1023 (print_mips_disassembler_options): Print out message about virt64.
1024 * mips-opc.c (IVIRT): New define.
1025 (IVIRT64): New define.
1026 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
1027 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
1028 Move rfe to the bottom as it conflicts with tlbgp.
1029
10302013-05-09 Alan Modra <amodra@gmail.com>
1031
1032 * ppc-opc.c (extract_vlesi): Properly sign extend.
1033 (extract_vlensi): Likewise. Comment reason for setting invalid.
1034
10352013-05-02 Nick Clifton <nickc@redhat.com>
1036
1037 * msp430-dis.c: Add support for MSP430X instructions.
1038
10392013-04-24 Sandra Loosemore <sandra@codesourcery.com>
1040
1041 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1042 to "eccinj".
1043
10442013-04-17 Wei-chen Wang <cole945@gmail.com>
1045
1046 PR binutils/15369
1047 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1048 of CGEN_CPU_ENDIAN.
1049 (hash_insns_list): Likewise.
1050
10512013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
1052
1053 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1054 warning workaround.
1055
10562013-04-08 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1059 * i386-tbl.h: Re-generate.
1060
10612013-04-06 David S. Miller <davem@davemloft.net>
1062
1063 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1064 of an opcode, prefer the one with F_PREFERRED set.
1065 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1066 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1067 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
1068 mark existing mnenomics as aliases. Add "cc" suffix to edge
1069 instructions generating condition codes, mark existing mnenomics
1070 as aliases. Add "fp" prefix to VIS compare instructions, mark
1071 existing mnenomics as aliases.
1072
10732013-04-03 Nick Clifton <nickc@redhat.com>
1074
1075 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1076 destination address by subtracting the operand from the current
1077 address.
1078 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1079 a positive value in the insn.
1080 (extract_u16_loop): Do not negate the returned value.
1081 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1082
1083 (ceilf.sw): Remove duplicate entry.
1084 (cvtf.hs): New entry.
1085 (cvtf.sh): Likewise.
1086 (fmaf.s): Likewise.
1087 (fmsf.s): Likewise.
1088 (fnmaf.s): Likewise.
1089 (fnmsf.s): Likewise.
1090 (maddf.s): Restrict to E3V5 architectures.
1091 (msubf.s): Likewise.
1092 (nmaddf.s): Likewise.
1093 (nmsubf.s): Likewise.
1094
10952013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1096
1097 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1098 check address mode.
1099 (print_insn): Pass sizeflag to get_sib.
1100
11012013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1102
1103 PR binutils/15068
1104 * tic6x-dis.c: Add support for displaying 16-bit insns.
1105
11062013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1107
1108 PR gas/15095
1109 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1110 individual msb and lsb halves in src1 & src2 fields. Discard the
1111 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1112 follow what Ti SDK does in that case as any value in the src1
1113 field yields the same output with SDK disassembler.
1114
11152013-03-12 Michael Eager <eager@eagercon.com>
1116
1117 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1118
11192013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1120
1121 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1122
11232013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1124
1125 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1126
11272013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1128
1129 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1130
11312013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1132
1133 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1134 (thumb32_opcodes): Likewise.
1135 (print_insn_thumb32): Handle 'S' control char.
1136
11372013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1138
1139 * lm32-desc.c: Regenerate.
1140
11412013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1142
1143 * i386-reg.tbl (riz): Add RegRex64.
1144 * i386-tbl.h: Regenerated.
1145
11462013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1147
1148 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1149 (aarch64_feature_crc): New static.
1150 (CRC): New macro.
1151 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1152 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1153 * aarch64-asm-2.c: Re-generate.
1154 * aarch64-dis-2.c: Ditto.
1155 * aarch64-opc-2.c: Ditto.
1156
11572013-02-27 Alan Modra <amodra@gmail.com>
1158
1159 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1160 * rl78-decode.c: Regenerate.
1161
11622013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1163
1164 * rl78-decode.opc: Fix encoding of DIVWU insn.
1165 * rl78-decode.c: Regenerate.
1166
11672013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1168
1169 PR gas/15159
1170 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1171
1172 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1173 (cpu_flags): Add CpuSMAP.
1174
1175 * i386-opc.h (CpuSMAP): New.
1176 (i386_cpu_flags): Add cpusmap.
1177
1178 * i386-opc.tbl: Add clac and stac.
1179
1180 * i386-init.h: Regenerated.
1181 * i386-tbl.h: Likewise.
1182
11832013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1184
1185 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1186 which also makes the disassembler output be in little
1187 endian like it should be.
1188
11892013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1190
1191 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1192 fields to NULL.
1193 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1194
11952013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
1196
1197 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1198 section disassembled.
1199
12002013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1201
1202 * arm-dis.c: Update strht pattern.
1203
12042013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1205
1206 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1207 single-float. Disable ll, lld, sc and scd for EE. Disable the
1208 trunc.w.s macro for EE.
1209
12102013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1211 Andrew Jenner <andrew@codesourcery.com>
1212
1213 Based on patches from Altera Corporation.
1214
1215 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1216 nios2-opc.c.
1217 * Makefile.in: Regenerated.
1218 * configure.in: Add case for bfd_nios2_arch.
1219 * configure: Regenerated.
1220 * disassemble.c (ARCH_nios2): Define.
1221 (disassembler): Add case for bfd_arch_nios2.
1222 * nios2-dis.c: New file.
1223 * nios2-opc.c: New file.
1224
12252013-02-04 Alan Modra <amodra@gmail.com>
1226
1227 * po/POTFILES.in: Regenerate.
1228 * rl78-decode.c: Regenerate.
1229 * rx-decode.c: Regenerate.
1230
12312013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1232
1233 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1234 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1235 * aarch64-asm.c (convert_xtl_to_shll): New function.
1236 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1237 calling convert_xtl_to_shll.
1238 * aarch64-dis.c (convert_shll_to_xtl): New function.
1239 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1240 calling convert_shll_to_xtl.
1241 * aarch64-gen.c: Update copyright year.
1242 * aarch64-asm-2.c: Re-generate.
1243 * aarch64-dis-2.c: Re-generate.
1244 * aarch64-opc-2.c: Re-generate.
1245
12462013-01-24 Nick Clifton <nickc@redhat.com>
1247
1248 * v850-dis.c: Add support for e3v5 architecture.
1249 * v850-opc.c: Likewise.
1250
12512013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1252
1253 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1254 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1255 * aarch64-opc.c (operand_general_constraint_met_p): For
1256 AARCH64_MOD_LSL, move the range check on the shift amount before the
1257 alignment check; change to call set_sft_amount_out_of_range_error
1258 instead of set_imm_out_of_range_error.
1259 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1260 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1261 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1262 SIMD_IMM_SFT.
1263
12642013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1265
1266 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1267
1268 * i386-init.h: Regenerated.
1269 * i386-tbl.h: Likewise.
1270
12712013-01-15 Nick Clifton <nickc@redhat.com>
1272
1273 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1274 values.
1275 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1276
12772013-01-14 Will Newton <will.newton@imgtec.com>
1278
1279 * metag-dis.c (REG_WIDTH): Increase to 64.
1280
12812013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1282
1283 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1284 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1285 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1286 (SH6): Update.
1287 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1288 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1289 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1290 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1291
12922013-01-10 Will Newton <will.newton@imgtec.com>
1293
1294 * Makefile.am: Add Meta.
1295 * configure.in: Add Meta.
1296 * disassemble.c: Add Meta support.
1297 * metag-dis.c: New file.
1298 * Makefile.in: Regenerate.
1299 * configure: Regenerate.
1300
13012013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1302
1303 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1304 (match_opcode): Rename to cr16_match_opcode.
1305
13062013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1307
1308 * mips-dis.c: Add names for CP0 registers of r5900.
1309 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1310 instructions sq and lq.
1311 Add support for MIPS r5900 CPU.
1312 Add support for 128 bit MMI (Multimedia Instructions).
1313 Add support for EE instructions (Emotion Engine).
1314 Disable unsupported floating point instructions (64 bit and
1315 undefined compare operations).
1316 Enable instructions of MIPS ISA IV which are supported by r5900.
1317 Disable 64 bit co processor instructions.
1318 Disable 64 bit multiplication and division instructions.
1319 Disable instructions for co-processor 2 and 3, because these are
1320 not supported (preparation for later VU0 support (Vector Unit)).
1321 Disable cvt.w.s because this behaves like trunc.w.s and the
1322 correct execution can't be ensured on r5900.
1323 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1324 will confuse less developers and compilers.
1325
13262013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1327
1328 * aarch64-opc.c (aarch64_print_operand): Change to print
1329 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1330 in comment.
1331 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1332 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1333 OP_MOV_IMM_WIDE.
1334
13352013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1336
1337 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1338 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1339
13402013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1341
1342 * i386-gen.c (process_copyright): Update copyright year to 2013.
1343
13442013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1345
1346 * cr16-dis.c (match_opcode,make_instruction): Remove static
1347 declaration.
1348 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1349 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1350
1351For older changes see ChangeLog-2012
1352\f
1353Copyright (C) 2013 Free Software Foundation, Inc.
1354
1355Copying and distribution of this file, with or without modification,
1356are permitted in any medium without royalty provided the copyright
1357notice and this notice are preserved.
1358
1359Local Variables:
1360mode: change-log
1361left-margin: 8
1362fill-column: 74
1363version-control: never
1364End:
GDB Binutils - Deliverables
This page took 0.026613 seconds and 4 git commands to generate.