| 1 | 2018-12-28 Alan Modra <amodra@gmail.com> |
| 2 | |
| 3 | PR 24028 |
| 4 | * ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with |
| 5 | PRId64/PRIx64. |
| 6 | |
| 7 | 2018-12-18 Alan Modra <amodra@gmail.com> |
| 8 | |
| 9 | * arm-dis.c: Include bfd.h. |
| 10 | * aarch64-opc.c: Include bfd_stdint.h rather than stdint.h. |
| 11 | * csky-dis.c: Likewise. |
| 12 | * nds32-asm.c: Likewise. |
| 13 | * riscv-dis.c: Likewise. |
| 14 | * s12z-dis.c: Likewise. |
| 15 | * wasm32-dis.c: Likewise. |
| 16 | |
| 17 | 2018-12-07 Jim Wilson <jimw@sifive.com> |
| 18 | |
| 19 | PR gas/23956 |
| 20 | * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg. |
| 21 | |
| 22 | 2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com> |
| 23 | |
| 24 | * configure.ac (enable-cgen-maint): Support passing path to cgen |
| 25 | source tree. |
| 26 | * configure: Regenerate. |
| 27 | |
| 28 | 2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com> |
| 29 | |
| 30 | * disassembler.c (disassemble_init_for_target): Add RISC-V |
| 31 | initialisation. |
| 32 | * riscv-dis.c (riscv_symbol_is_valid): New function. |
| 33 | |
| 34 | 2018-12-03 Kito Cheng <kito@andestech.com> |
| 35 | |
| 36 | * riscv-opc.c: Change the type of xlen, because type of |
| 37 | xlen_requirement changed. |
| 38 | |
| 39 | 2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com> |
| 40 | |
| 41 | PR 23193 |
| 42 | PR 19721 |
| 43 | * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR |
| 44 | encoding as MOV if the shift operation is a left shift of zero. |
| 45 | |
| 46 | 2018-11-29 Jim Wilson <jimw@sifive.com> |
| 47 | |
| 48 | * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS. |
| 49 | (c.unimp): New. |
| 50 | |
| 51 | 2018-11-27 Jim Wilson <jimw@sifive.com> |
| 52 | |
| 53 | * riscv-opc.c (ciw): Fix whitespace to align columns. |
| 54 | (ca): New. |
| 55 | |
| 56 | 2018-11-21 John Darrington <john@darrington.wattle.id.au> |
| 57 | |
| 58 | * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case |
| 59 | if the postbyte matches the appropriate pattern. |
| 60 | |
| 61 | 2018-11-13 Francois H. Theron <francois.theron@netronome.com> |
| 62 | |
| 63 | * nfp-dis.c: Fix crc[] disassembly if operands are swapped. |
| 64 | |
| 65 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 66 | |
| 67 | * aarch64-opc.c (aarch64_sys_regs_dc): New entries for |
| 68 | IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, |
| 69 | IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, |
| 70 | CIGDVAC and GZVA. |
| 71 | (aarch64_sys_ins_reg_supported_p): New check for above. |
| 72 | |
| 73 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 74 | |
| 75 | * aarch64-opc.c (aarch64_sys_regs): New entries for TCO, |
| 76 | TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, |
| 77 | RGSR_EL1 and GCR_EL1. |
| 78 | (aarch64_sys_reg_supported_p): New check for above. |
| 79 | (aarch64_pstatefields): New entry for TCO. |
| 80 | (aarch64_pstatefield_supported_p): New check for above. |
| 81 | |
| 82 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 83 | |
| 84 | * aarch64-asm.c (aarch64_ins_addr_simple_2): New. |
| 85 | * aarch64-asm.h (ins_addr_simple_2): Declare the above. |
| 86 | * aarch64-dis.c (aarch64_ext_addr_simple_2): New. |
| 87 | * aarch64-dis.h (ext_addr_simple_2): Declare the above. |
| 88 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for |
| 89 | AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. |
| 90 | (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. |
| 91 | * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. |
| 92 | (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. |
| 93 | * aarch64-asm-2.c: Regenerated. |
| 94 | * aarch64-dis-2.c: Regenerated. |
| 95 | * aarch64-opc-2.c: Regenerated. |
| 96 | |
| 97 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 98 | |
| 99 | * aarch64-tbl.h (QL_LDG): New. |
| 100 | (aarch64_opcode_table): Add ldg. |
| 101 | * aarch64-asm-2.c: Regenerated. |
| 102 | * aarch64-dis-2.c: Regenerated. |
| 103 | * aarch64-opc-2.c: Regenerated. |
| 104 | |
| 105 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 106 | |
| 107 | * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data |
| 108 | for AARCH64_OPND_QLF_imm_tag. |
| 109 | (operand_general_constraint_met_p): Add case for |
| 110 | AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. |
| 111 | (aarch64_print_operand): Likewise. |
| 112 | * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. |
| 113 | (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp |
| 114 | for both offset and pre/post indexed versions. |
| 115 | (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. |
| 116 | * aarch64-asm-2.c: Regenerated. |
| 117 | * aarch64-dis-2.c: Regenerated. |
| 118 | * aarch64-opc-2.c: Regenerated. |
| 119 | |
| 120 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 121 | |
| 122 | * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp. |
| 123 | * aarch64-asm-2.c: Regenerated. |
| 124 | * aarch64-dis-2.c: Regenerated. |
| 125 | * aarch64-opc-2.c: Regenerated. |
| 126 | |
| 127 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 128 | |
| 129 | * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. |
| 130 | (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. |
| 131 | * aarch64-opc.c (fields): Add entry for imm4_3. |
| 132 | (operand_general_constraint_met_p): Add cases for |
| 133 | AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. |
| 134 | (aarch64_print_operand): Likewise. |
| 135 | * aarch64-tbl.h (QL_ADDG): New. |
| 136 | (aarch64_opcode_table): Add addg, subg, irg and gmi. |
| 137 | (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. |
| 138 | * aarch64-asm.c (aarch64_ins_imm): Add case for |
| 139 | operand_need_shift_by_four. |
| 140 | * aarch64-asm-2.c: Regenerated. |
| 141 | * aarch64-dis-2.c: Regenerated. |
| 142 | * aarch64-opc-2.c: Regenerated. |
| 143 | |
| 144 | 2018-11-12 Sudakshina Das <sudi.das@arm.com> |
| 145 | |
| 146 | * aarch64-tbl.h (aarch64_feature_memtag): New. |
| 147 | (MEMTAG, MEMTAG_INSN): New. |
| 148 | |
| 149 | 2018-11-06 Sudakshina Das <sudi.das@arm.com> |
| 150 | |
| 151 | * arm-dis.c (select_arm_features): Update bfd_mach_arm_8 |
| 152 | with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML. |
| 153 | |
| 154 | 2018-11-06 Alan Modra <amodra@gmail.com> |
| 155 | |
| 156 | * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls), |
| 157 | (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0), |
| 158 | (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16), |
| 159 | (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd): |
| 160 | Don't return zero on error, insert mask bits instead. |
| 161 | (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete. |
| 162 | (insert_sh6, extract_sh6): Delete dead code. |
| 163 | (insert_sprbat, insert_sprg): Use unsigned comparisions. |
| 164 | (powerpc_operands <OIMM>): Set shift count rather than using |
| 165 | PPC_OPSHIFT_INV. |
| 166 | <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions. |
| 167 | |
| 168 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 169 | |
| 170 | * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for |
| 171 | vpbroadcast{d,q} with GPR operand. |
| 172 | |
| 173 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 174 | |
| 175 | * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete. |
| 176 | * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand |
| 177 | cases up one level in the hierarchy. |
| 178 | |
| 179 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 180 | |
| 181 | * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0, |
| 182 | MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0. |
| 183 | (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold |
| 184 | into MOD_VEX_0F93_P_3_LEN_0. |
| 185 | (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR |
| 186 | operand cases up one level in the hierarchy. |
| 187 | |
| 188 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 189 | |
| 190 | * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2, |
| 191 | VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2, |
| 192 | EVEX_W_0F3A22_P_2): Delete. |
| 193 | (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w} |
| 194 | entries up one level in the hierarchy. |
| 195 | (OP_E_memory): Handle dq_mode when determining Disp8 shift |
| 196 | value. |
| 197 | * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q} |
| 198 | entries up one level in the hierarchy. |
| 199 | * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to |
| 200 | VexWIG for AVX flavors. |
| 201 | * i386-tbl.h: Re-generate. |
| 202 | |
| 203 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 204 | |
| 205 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri, |
| 206 | vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd, |
| 207 | vcvtusi2ss, kmovd): Drop VexW=1. |
| 208 | * i386-tbl.h: Re-generate. |
| 209 | |
| 210 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 211 | |
| 212 | * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256, |
| 213 | EVex512, EVexLIG, EVexDYN): New. |
| 214 | (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM |
| 215 | insns): Use Vex128 instead of Vex=3 (aka VexLIG). |
| 216 | (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead |
| 217 | of EVex=4 (aka EVexLIG). |
| 218 | * i386-tbl.h: Re-generate. |
| 219 | |
| 220 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 221 | |
| 222 | * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms. |
| 223 | (vpmaxub): Re-order attributes on AVX512BW flavor. |
| 224 | * i386-tbl.h: Re-generate. |
| 225 | |
| 226 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 227 | |
| 228 | * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*, |
| 229 | vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of |
| 230 | Vex=1 on AVX / AVX2 flavors. |
| 231 | (vpmaxub): Re-order attributes on AVX512BW flavor. |
| 232 | * i386-tbl.h: Re-generate. |
| 233 | |
| 234 | 2018-11-06 Jan Beulich <jbeulich@suse.com> |
| 235 | |
| 236 | * i386-opc.tbl (VexW0, VexW1): New. |
| 237 | (vphadd*, vphsub*): Use VexW0 on XOP variants. |
| 238 | * i386-tbl.h: Re-generate. |
| 239 | |
| 240 | 2018-10-22 John Darrington <john@darrington.wattle.id.au> |
| 241 | |
| 242 | * s12z-dis.c (decode_possible_symbol): Add fallback case. |
| 243 | (rel_15_7): Likewise. |
| 244 | |
| 245 | 2018-10-19 Tamar Christina <tamar.christina@arm.com> |
| 246 | |
| 247 | * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode. |
| 248 | (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode. |
| 249 | (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them. |
| 250 | |
| 251 | 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com> |
| 252 | |
| 253 | * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data |
| 254 | corresponding to AARCH64_OPND_QLF_S_4B qualifier. |
| 255 | |
| 256 | 2018-10-10 Jan Beulich <jbeulich@suse.com> |
| 257 | |
| 258 | * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and |
| 259 | Size64. Add Size. |
| 260 | * i386-opc.h (Size16, Size32, Size64): Delete. |
| 261 | (Size): New. |
| 262 | (SIZE16, SIZE32, SIZE64): Define. |
| 263 | (struct i386_opcode_modifier): Drop size16, size32, and size64. |
| 264 | Add size. |
| 265 | * i386-opc.tbl (Size16, Size32, Size64): Define. |
| 266 | * i386-tbl.h: Re-generate. |
| 267 | |
| 268 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 269 | |
| 270 | * aarch64-opc.c (operand_general_constraint_met_p): Add |
| 271 | SSBS in the check for one-bit immediate. |
| 272 | (aarch64_sys_regs): New entry for SSBS. |
| 273 | (aarch64_sys_reg_supported_p): New check for above. |
| 274 | (aarch64_pstatefields): New entry for SSBS. |
| 275 | (aarch64_pstatefield_supported_p): New check for above. |
| 276 | |
| 277 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 278 | |
| 279 | * aarch64-opc.c (aarch64_sys_regs): New entries for |
| 280 | scxtnum_el[0,1,2,3,12] and id_pfr2_el1. |
| 281 | (aarch64_sys_reg_supported_p): New checks for above. |
| 282 | |
| 283 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 284 | |
| 285 | * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. |
| 286 | (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag |
| 287 | with the hint immediate. |
| 288 | * aarch64-opc.c (aarch64_hint_options): New entries for |
| 289 | c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. |
| 290 | (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET |
| 291 | while checking for HINT_OPD_F_NOPRINT flag. |
| 292 | * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to |
| 293 | extract value. |
| 294 | * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. |
| 295 | (aarch64_opcode_table): Add entry for BTI. |
| 296 | (AARCH64_OPERANDS): Add new description for BTI targets. |
| 297 | * aarch64-asm-2.c: Regenerate. |
| 298 | * aarch64-dis-2.c: Regenerate. |
| 299 | * aarch64-opc-2.c: Regenerate. |
| 300 | |
| 301 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 302 | |
| 303 | * aarch64-opc.c (aarch64_sys_regs): New entries for |
| 304 | rndr and rndrrs. |
| 305 | (aarch64_sys_reg_supported_p): New check for above. |
| 306 | |
| 307 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 308 | |
| 309 | * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. |
| 310 | (aarch64_sys_ins_reg_supported_p): New check for above. |
| 311 | |
| 312 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 313 | |
| 314 | * aarch64-dis.c (aarch64_ext_sysins_op): Add case for |
| 315 | AARCH64_OPND_SYSREG_SR. |
| 316 | * aarch64-opc.c (aarch64_print_operand): Likewise. |
| 317 | (aarch64_sys_regs_sr): Define table. |
| 318 | (aarch64_sys_ins_reg_supported_p): Check for RCTX with |
| 319 | AARCH64_FEATURE_PREDRES. |
| 320 | * aarch64-tbl.h (aarch64_feature_predres): New. |
| 321 | (PREDRES, PREDRES_INSN): New. |
| 322 | (aarch64_opcode_table): Add entries for cfp, dvp and cpp. |
| 323 | (AARCH64_OPERANDS): Add new description for SYSREG_SR. |
| 324 | * aarch64-asm-2.c: Regenerate. |
| 325 | * aarch64-dis-2.c: Regenerate. |
| 326 | * aarch64-opc-2.c: Regenerate. |
| 327 | |
| 328 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 329 | |
| 330 | * aarch64-tbl.h (aarch64_feature_sb): New. |
| 331 | (SB, SB_INSN): New. |
| 332 | (aarch64_opcode_table): Add entry for sb. |
| 333 | * aarch64-asm-2.c: Regenerate. |
| 334 | * aarch64-dis-2.c: Regenerate. |
| 335 | * aarch64-opc-2.c: Regenerate. |
| 336 | |
| 337 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 338 | |
| 339 | * aarch64-tbl.h (aarch64_feature_flagmanip): New. |
| 340 | (aarch64_feature_frintts): New. |
| 341 | (FLAGMANIP, FRINTTS): New. |
| 342 | (aarch64_opcode_table): Add entries for xaflag, axflag |
| 343 | and frint[32,64][x,z] instructions. |
| 344 | * aarch64-asm-2.c: Regenerate. |
| 345 | * aarch64-dis-2.c: Regenerate. |
| 346 | * aarch64-opc-2.c: Regenerate. |
| 347 | |
| 348 | 2018-10-09 Sudakshina Das <sudi.das@arm.com> |
| 349 | |
| 350 | * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New. |
| 351 | (ARMV8_5, V8_5_INSN): New. |
| 352 | |
| 353 | 2018-10-08 Tamar Christina <tamar.christina@arm.com> |
| 354 | |
| 355 | * aarch64-opc.c (verify_constraints): Use memset instead of {0}. |
| 356 | |
| 357 | 2018-10-05 H.J. Lu <hongjiu.lu@intel.com> |
| 358 | |
| 359 | * i386-dis.c (rm_table): Add enclv. |
| 360 | * i386-opc.tbl: Add enclv. |
| 361 | * i386-tbl.h: Regenerated. |
| 362 | |
| 363 | 2018-10-05 Sudakshina Das <sudi.das@arm.com> |
| 364 | |
| 365 | * arm-dis.c (arm_opcodes): Add sb. |
| 366 | (thumb32_opcodes): Likewise. |
| 367 | |
| 368 | 2018-10-05 Richard Henderson <rth@twiddle.net> |
| 369 | Stafford Horne <shorne@gmail.com> |
| 370 | |
| 371 | * or1k-desc.c: Regenerate. |
| 372 | * or1k-desc.h: Regenerate. |
| 373 | * or1k-opc.c: Regenerate. |
| 374 | * or1k-opc.h: Regenerate. |
| 375 | * or1k-opinst.c: Regenerate. |
| 376 | |
| 377 | 2018-10-05 Richard Henderson <rth@twiddle.net> |
| 378 | |
| 379 | * or1k-asm.c: Regenerated. |
| 380 | * or1k-desc.c: Regenerated. |
| 381 | * or1k-desc.h: Regenerated. |
| 382 | * or1k-dis.c: Regenerated. |
| 383 | * or1k-ibld.c: Regenerated. |
| 384 | * or1k-opc.c: Regenerated. |
| 385 | * or1k-opc.h: Regenerated. |
| 386 | * or1k-opinst.c: Regenerated. |
| 387 | |
| 388 | 2018-10-05 Richard Henderson <rth@twiddle.net> |
| 389 | |
| 390 | * or1k-asm.c: Regenerate. |
| 391 | |
| 392 | 2018-10-03 Tamar Christina <tamar.christina@arm.com> |
| 393 | |
| 394 | * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier. |
| 395 | * aarch64-dis.c (print_operands): Refactor to take notes. |
| 396 | (print_verifier_notes): New. |
| 397 | (print_aarch64_insn): Apply constraint verifier. |
| 398 | (print_insn_aarch64_word): Update call to print_aarch64_insn. |
| 399 | * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format. |
| 400 | |
| 401 | 2018-10-03 Tamar Christina <tamar.christina@arm.com> |
| 402 | |
| 403 | * aarch64-opc.c (init_insn_block): New. |
| 404 | (verify_constraints, aarch64_is_destructive_by_operands): New. |
| 405 | * aarch64-opc.h (verify_constraints): New. |
| 406 | |
| 407 | 2018-10-03 Tamar Christina <tamar.christina@arm.com> |
| 408 | |
| 409 | * aarch64-dis.c (aarch64_opcode_decode): Update verifier call. |
| 410 | * aarch64-opc.c (verify_ldpsw): Update arguments. |
| 411 | |
| 412 | 2018-10-03 Tamar Christina <tamar.christina@arm.com> |
| 413 | |
| 414 | * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove. |
| 415 | (aarch64_decode_insn, print_insn_aarch64_word): Use err_type. |
| 416 | |
| 417 | 2018-10-03 Tamar Christina <tamar.christina@arm.com> |
| 418 | |
| 419 | * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. |
| 420 | * aarch64-dis.c (insn_sequence): New. |
| 421 | |
| 422 | 2018-10-03 Tamar Christina <tamar.christina@arm.com> |
| 423 | |
| 424 | * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN, |
| 425 | _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN, |
| 426 | _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN, |
| 427 | V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize |
| 428 | constraints. |
| 429 | (_SVE_INSNC): New. |
| 430 | (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize |
| 431 | constraints. |
| 432 | (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and |
| 433 | F_SCAN flags. |
| 434 | (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf, |
| 435 | sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech, |
| 436 | sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb, |
| 437 | sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd, |
| 438 | uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub, |
| 439 | uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add |
| 440 | C_SCAN_MOVPRFX and C_MAX_ELEM constraints. |
| 441 | |
| 442 | 2018-10-02 Palmer Dabbelt <palmer@sifive.com> |
| 443 | |
| 444 | * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode. |
| 445 | |
| 446 | 2018-09-23 Sandra Loosemore <sandra@codesourcery.com> |
| 447 | |
| 448 | * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions |
| 449 | are used when extracting signed fields and converting them to |
| 450 | potentially 64-bit types. |
| 451 | |
| 452 | 2018-09-21 Simon Marchi <simon.marchi@ericsson.com> |
| 453 | |
| 454 | * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS. |
| 455 | * Makefile.in: Re-generate. |
| 456 | * aclocal.m4: Re-generate. |
| 457 | * configure: Re-generate. |
| 458 | * configure.ac: Remove check for -Wno-missing-field-initializers. |
| 459 | * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element. |
| 460 | (csky_v2_opcodes): Likewise. |
| 461 | |
| 462 | 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org> |
| 463 | |
| 464 | * arc-nps400-tbl.h: Append `ull' to large constants throughout. |
| 465 | |
| 466 | 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com> |
| 467 | |
| 468 | * nds32-asm.c (operand_fields): Remove the unused fields. |
| 469 | (nds32_opcodes): Remove the unused instructions. |
| 470 | * nds32-dis.c (nds32_ex9_info): Removed. |
| 471 | (nds32_parse_opcode): Updated. |
| 472 | (print_insn_nds32): Likewise. |
| 473 | * nds32-asm.c (config.h, stdlib.h, string.h): New includes. |
| 474 | (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. |
| 475 | (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, |
| 476 | build_opcode_hash_table): New functions. |
| 477 | (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, |
| 478 | nds32_opcode_table): New. |
| 479 | (hw_ktabs): Declare it to a pointer rather than an array. |
| 480 | (build_hash_table): Removed. |
| 481 | * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, |
| 482 | SYN_ROPT and upadte HW_GPR and HW_INT. |
| 483 | * nds32-dis.c (keywords): Remove const. |
| 484 | (match_field): New function. |
| 485 | (nds32_parse_opcode): Updated. |
| 486 | * disassemble.c (disassemble_init_for_target): |
| 487 | Add disassemble_init_nds32. |
| 488 | * nds32-dis.c (eum map_type): New. |
| 489 | (nds32_private_data): Likewise. |
| 490 | (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, |
| 491 | nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. |
| 492 | (print_insn_nds32): Updated. |
| 493 | * nds32-asm.c (parse_aext_reg): Add new parameter. |
| 494 | (parse_re, parse_re2, parse_aext_reg): Only reduced registers |
| 495 | are allowed to use. |
| 496 | All callers changed. |
| 497 | * nds32-asm.c (keyword_usr, keyword_sr): Updated. |
| 498 | (operand_fields): Add new fields. |
| 499 | (nds32_opcodes): Add new instructions. |
| 500 | (keyword_aridxi_mx): New keyword. |
| 501 | * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX |
| 502 | and NASM_ATTR_ZOL. |
| 503 | (ALU2_1, ALU2_2, ALU2_3): New macros. |
| 504 | * nds32-dis.c (nds32_filter_unknown_insn): Updated. |
| 505 | |
| 506 | 2018-09-17 Kito Cheng <kito@andestech.com> |
| 507 | |
| 508 | * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu. |
| 509 | |
| 510 | 2018-09-17 H.J. Lu <hongjiu.lu@intel.com> |
| 511 | |
| 512 | PR gas/23670 |
| 513 | * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, |
| 514 | EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. |
| 515 | (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. |
| 516 | (EVEX_LEN_0F7E_P_1): Likewise. |
| 517 | (EVEX_LEN_0F7E_P_2): Likewise. |
| 518 | (EVEX_LEN_0FD6_P_2): Likewise. |
| 519 | * i386-dis.c (USE_EVEX_LEN_TABLE): New. |
| 520 | (EVEX_LEN_TABLE): Likewise. |
| 521 | (EVEX_LEN_0F6E_P_2): New enum. |
| 522 | (EVEX_LEN_0F7E_P_1): Likewise. |
| 523 | (EVEX_LEN_0F7E_P_2): Likewise. |
| 524 | (EVEX_LEN_0FD6_P_2): Likewise. |
| 525 | (evex_len_table): New. |
| 526 | (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. |
| 527 | * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. |
| 528 | * i386-tbl.h: Regenerated. |
| 529 | |
| 530 | 2018-09-17 H.J. Lu <hongjiu.lu@intel.com> |
| 531 | |
| 532 | PR gas/23665 |
| 533 | * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and |
| 534 | VEX_LEN_0F7E_P_2 entries. |
| 535 | * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. |
| 536 | * i386-tbl.h: Regenerated. |
| 537 | |
| 538 | 2018-09-17 H.J. Lu <hongjiu.lu@intel.com> |
| 539 | |
| 540 | * i386-dis.c (VZERO_Fixup): Removed. |
| 541 | (VZERO): Likewise. |
| 542 | (VEX_LEN_0F10_P_1): Likewise. |
| 543 | (VEX_LEN_0F10_P_3): Likewise. |
| 544 | (VEX_LEN_0F11_P_1): Likewise. |
| 545 | (VEX_LEN_0F11_P_3): Likewise. |
| 546 | (VEX_LEN_0F2E_P_0): Likewise. |
| 547 | (VEX_LEN_0F2E_P_2): Likewise. |
| 548 | (VEX_LEN_0F2F_P_0): Likewise. |
| 549 | (VEX_LEN_0F2F_P_2): Likewise. |
| 550 | (VEX_LEN_0F51_P_1): Likewise. |
| 551 | (VEX_LEN_0F51_P_3): Likewise. |
| 552 | (VEX_LEN_0F52_P_1): Likewise. |
| 553 | (VEX_LEN_0F53_P_1): Likewise. |
| 554 | (VEX_LEN_0F58_P_1): Likewise. |
| 555 | (VEX_LEN_0F58_P_3): Likewise. |
| 556 | (VEX_LEN_0F59_P_1): Likewise. |
| 557 | (VEX_LEN_0F59_P_3): Likewise. |
| 558 | (VEX_LEN_0F5A_P_1): Likewise. |
| 559 | (VEX_LEN_0F5A_P_3): Likewise. |
| 560 | (VEX_LEN_0F5C_P_1): Likewise. |
| 561 | (VEX_LEN_0F5C_P_3): Likewise. |
| 562 | (VEX_LEN_0F5D_P_1): Likewise. |
| 563 | (VEX_LEN_0F5D_P_3): Likewise. |
| 564 | (VEX_LEN_0F5E_P_1): Likewise. |
| 565 | (VEX_LEN_0F5E_P_3): Likewise. |
| 566 | (VEX_LEN_0F5F_P_1): Likewise. |
| 567 | (VEX_LEN_0F5F_P_3): Likewise. |
| 568 | (VEX_LEN_0FC2_P_1): Likewise. |
| 569 | (VEX_LEN_0FC2_P_3): Likewise. |
| 570 | (VEX_LEN_0F3A0A_P_2): Likewise. |
| 571 | (VEX_LEN_0F3A0B_P_2): Likewise. |
| 572 | (VEX_W_0F10_P_0): Likewise. |
| 573 | (VEX_W_0F10_P_1): Likewise. |
| 574 | (VEX_W_0F10_P_2): Likewise. |
| 575 | (VEX_W_0F10_P_3): Likewise. |
| 576 | (VEX_W_0F11_P_0): Likewise. |
| 577 | (VEX_W_0F11_P_1): Likewise. |
| 578 | (VEX_W_0F11_P_2): Likewise. |
| 579 | (VEX_W_0F11_P_3): Likewise. |
| 580 | (VEX_W_0F12_P_0_M_0): Likewise. |
| 581 | (VEX_W_0F12_P_0_M_1): Likewise. |
| 582 | (VEX_W_0F12_P_1): Likewise. |
| 583 | (VEX_W_0F12_P_2): Likewise. |
| 584 | (VEX_W_0F12_P_3): Likewise. |
| 585 | (VEX_W_0F13_M_0): Likewise. |
| 586 | (VEX_W_0F14): Likewise. |
| 587 | (VEX_W_0F15): Likewise. |
| 588 | (VEX_W_0F16_P_0_M_0): Likewise. |
| 589 | (VEX_W_0F16_P_0_M_1): Likewise. |
| 590 | (VEX_W_0F16_P_1): Likewise. |
| 591 | (VEX_W_0F16_P_2): Likewise. |
| 592 | (VEX_W_0F17_M_0): Likewise. |
| 593 | (VEX_W_0F28): Likewise. |
| 594 | (VEX_W_0F29): Likewise. |
| 595 | (VEX_W_0F2B_M_0): Likewise. |
| 596 | (VEX_W_0F2E_P_0): Likewise. |
| 597 | (VEX_W_0F2E_P_2): Likewise. |
| 598 | (VEX_W_0F2F_P_0): Likewise. |
| 599 | (VEX_W_0F2F_P_2): Likewise. |
| 600 | (VEX_W_0F50_M_0): Likewise. |
| 601 | (VEX_W_0F51_P_0): Likewise. |
| 602 | (VEX_W_0F51_P_1): Likewise. |
| 603 | (VEX_W_0F51_P_2): Likewise. |
| 604 | (VEX_W_0F51_P_3): Likewise. |
| 605 | (VEX_W_0F52_P_0): Likewise. |
| 606 | (VEX_W_0F52_P_1): Likewise. |
| 607 | (VEX_W_0F53_P_0): Likewise. |
| 608 | (VEX_W_0F53_P_1): Likewise. |
| 609 | (VEX_W_0F58_P_0): Likewise. |
| 610 | (VEX_W_0F58_P_1): Likewise. |
| 611 | (VEX_W_0F58_P_2): Likewise. |
| 612 | (VEX_W_0F58_P_3): Likewise. |
| 613 | (VEX_W_0F59_P_0): Likewise. |
| 614 | (VEX_W_0F59_P_1): Likewise. |
| 615 | (VEX_W_0F59_P_2): Likewise. |
| 616 | (VEX_W_0F59_P_3): Likewise. |
| 617 | (VEX_W_0F5A_P_0): Likewise. |
| 618 | (VEX_W_0F5A_P_1): Likewise. |
| 619 | (VEX_W_0F5A_P_3): Likewise. |
| 620 | (VEX_W_0F5B_P_0): Likewise. |
| 621 | (VEX_W_0F5B_P_1): Likewise. |
| 622 | (VEX_W_0F5B_P_2): Likewise. |
| 623 | (VEX_W_0F5C_P_0): Likewise. |
| 624 | (VEX_W_0F5C_P_1): Likewise. |
| 625 | (VEX_W_0F5C_P_2): Likewise. |
| 626 | (VEX_W_0F5C_P_3): Likewise. |
| 627 | (VEX_W_0F5D_P_0): Likewise. |
| 628 | (VEX_W_0F5D_P_1): Likewise. |
| 629 | (VEX_W_0F5D_P_2): Likewise. |
| 630 | (VEX_W_0F5D_P_3): Likewise. |
| 631 | (VEX_W_0F5E_P_0): Likewise. |
| 632 | (VEX_W_0F5E_P_1): Likewise. |
| 633 | (VEX_W_0F5E_P_2): Likewise. |
| 634 | (VEX_W_0F5E_P_3): Likewise. |
| 635 | (VEX_W_0F5F_P_0): Likewise. |
| 636 | (VEX_W_0F5F_P_1): Likewise. |
| 637 | (VEX_W_0F5F_P_2): Likewise. |
| 638 | (VEX_W_0F5F_P_3): Likewise. |
| 639 | (VEX_W_0F60_P_2): Likewise. |
| 640 | (VEX_W_0F61_P_2): Likewise. |
| 641 | (VEX_W_0F62_P_2): Likewise. |
| 642 | (VEX_W_0F63_P_2): Likewise. |
| 643 | (VEX_W_0F64_P_2): Likewise. |
| 644 | (VEX_W_0F65_P_2): Likewise. |
| 645 | (VEX_W_0F66_P_2): Likewise. |
| 646 | (VEX_W_0F67_P_2): Likewise. |
| 647 | (VEX_W_0F68_P_2): Likewise. |
| 648 | (VEX_W_0F69_P_2): Likewise. |
| 649 | (VEX_W_0F6A_P_2): Likewise. |
| 650 | (VEX_W_0F6B_P_2): Likewise. |
| 651 | (VEX_W_0F6C_P_2): Likewise. |
| 652 | (VEX_W_0F6D_P_2): Likewise. |
| 653 | (VEX_W_0F6F_P_1): Likewise. |
| 654 | (VEX_W_0F6F_P_2): Likewise. |
| 655 | (VEX_W_0F70_P_1): Likewise. |
| 656 | (VEX_W_0F70_P_2): Likewise. |
| 657 | (VEX_W_0F70_P_3): Likewise. |
| 658 | (VEX_W_0F71_R_2_P_2): Likewise. |
| 659 | (VEX_W_0F71_R_4_P_2): Likewise. |
| 660 | (VEX_W_0F71_R_6_P_2): Likewise. |
| 661 | (VEX_W_0F72_R_2_P_2): Likewise. |
| 662 | (VEX_W_0F72_R_4_P_2): Likewise. |
| 663 | (VEX_W_0F72_R_6_P_2): Likewise. |
| 664 | (VEX_W_0F73_R_2_P_2): Likewise. |
| 665 | (VEX_W_0F73_R_3_P_2): Likewise. |
| 666 | (VEX_W_0F73_R_6_P_2): Likewise. |
| 667 | (VEX_W_0F73_R_7_P_2): Likewise. |
| 668 | (VEX_W_0F74_P_2): Likewise. |
| 669 | (VEX_W_0F75_P_2): Likewise. |
| 670 | (VEX_W_0F76_P_2): Likewise. |
| 671 | (VEX_W_0F77_P_0): Likewise. |
| 672 | (VEX_W_0F7C_P_2): Likewise. |
| 673 | (VEX_W_0F7C_P_3): Likewise. |
| 674 | (VEX_W_0F7D_P_2): Likewise. |
| 675 | (VEX_W_0F7D_P_3): Likewise. |
| 676 | (VEX_W_0F7E_P_1): Likewise. |
| 677 | (VEX_W_0F7F_P_1): Likewise. |
| 678 | (VEX_W_0F7F_P_2): Likewise. |
| 679 | (VEX_W_0FAE_R_2_M_0): Likewise. |
| 680 | (VEX_W_0FAE_R_3_M_0): Likewise. |
| 681 | (VEX_W_0FC2_P_0): Likewise. |
| 682 | (VEX_W_0FC2_P_1): Likewise. |
| 683 | (VEX_W_0FC2_P_2): Likewise. |
| 684 | (VEX_W_0FC2_P_3): Likewise. |
| 685 | (VEX_W_0FD0_P_2): Likewise. |
| 686 | (VEX_W_0FD0_P_3): Likewise. |
| 687 | (VEX_W_0FD1_P_2): Likewise. |
| 688 | (VEX_W_0FD2_P_2): Likewise. |
| 689 | (VEX_W_0FD3_P_2): Likewise. |
| 690 | (VEX_W_0FD4_P_2): Likewise. |
| 691 | (VEX_W_0FD5_P_2): Likewise. |
| 692 | (VEX_W_0FD6_P_2): Likewise. |
| 693 | (VEX_W_0FD7_P_2_M_1): Likewise. |
| 694 | (VEX_W_0FD8_P_2): Likewise. |
| 695 | (VEX_W_0FD9_P_2): Likewise. |
| 696 | (VEX_W_0FDA_P_2): Likewise. |
| 697 | (VEX_W_0FDB_P_2): Likewise. |
| 698 | (VEX_W_0FDC_P_2): Likewise. |
| 699 | (VEX_W_0FDD_P_2): Likewise. |
| 700 | (VEX_W_0FDE_P_2): Likewise. |
| 701 | (VEX_W_0FDF_P_2): Likewise. |
| 702 | (VEX_W_0FE0_P_2): Likewise. |
| 703 | (VEX_W_0FE1_P_2): Likewise. |
| 704 | (VEX_W_0FE2_P_2): Likewise. |
| 705 | (VEX_W_0FE3_P_2): Likewise. |
| 706 | (VEX_W_0FE4_P_2): Likewise. |
| 707 | (VEX_W_0FE5_P_2): Likewise. |
| 708 | (VEX_W_0FE6_P_1): Likewise. |
| 709 | (VEX_W_0FE6_P_2): Likewise. |
| 710 | (VEX_W_0FE6_P_3): Likewise. |
| 711 | (VEX_W_0FE7_P_2_M_0): Likewise. |
| 712 | (VEX_W_0FE8_P_2): Likewise. |
| 713 | (VEX_W_0FE9_P_2): Likewise. |
| 714 | (VEX_W_0FEA_P_2): Likewise. |
| 715 | (VEX_W_0FEB_P_2): Likewise. |
| 716 | (VEX_W_0FEC_P_2): Likewise. |
| 717 | (VEX_W_0FED_P_2): Likewise. |
| 718 | (VEX_W_0FEE_P_2): Likewise. |
| 719 | (VEX_W_0FEF_P_2): Likewise. |
| 720 | (VEX_W_0FF0_P_3_M_0): Likewise. |
| 721 | (VEX_W_0FF1_P_2): Likewise. |
| 722 | (VEX_W_0FF2_P_2): Likewise. |
| 723 | (VEX_W_0FF3_P_2): Likewise. |
| 724 | (VEX_W_0FF4_P_2): Likewise. |
| 725 | (VEX_W_0FF5_P_2): Likewise. |
| 726 | (VEX_W_0FF6_P_2): Likewise. |
| 727 | (VEX_W_0FF7_P_2): Likewise. |
| 728 | (VEX_W_0FF8_P_2): Likewise. |
| 729 | (VEX_W_0FF9_P_2): Likewise. |
| 730 | (VEX_W_0FFA_P_2): Likewise. |
| 731 | (VEX_W_0FFB_P_2): Likewise. |
| 732 | (VEX_W_0FFC_P_2): Likewise. |
| 733 | (VEX_W_0FFD_P_2): Likewise. |
| 734 | (VEX_W_0FFE_P_2): Likewise. |
| 735 | (VEX_W_0F3800_P_2): Likewise. |
| 736 | (VEX_W_0F3801_P_2): Likewise. |
| 737 | (VEX_W_0F3802_P_2): Likewise. |
| 738 | (VEX_W_0F3803_P_2): Likewise. |
| 739 | (VEX_W_0F3804_P_2): Likewise. |
| 740 | (VEX_W_0F3805_P_2): Likewise. |
| 741 | (VEX_W_0F3806_P_2): Likewise. |
| 742 | (VEX_W_0F3807_P_2): Likewise. |
| 743 | (VEX_W_0F3808_P_2): Likewise. |
| 744 | (VEX_W_0F3809_P_2): Likewise. |
| 745 | (VEX_W_0F380A_P_2): Likewise. |
| 746 | (VEX_W_0F380B_P_2): Likewise. |
| 747 | (VEX_W_0F3817_P_2): Likewise. |
| 748 | (VEX_W_0F381C_P_2): Likewise. |
| 749 | (VEX_W_0F381D_P_2): Likewise. |
| 750 | (VEX_W_0F381E_P_2): Likewise. |
| 751 | (VEX_W_0F3820_P_2): Likewise. |
| 752 | (VEX_W_0F3821_P_2): Likewise. |
| 753 | (VEX_W_0F3822_P_2): Likewise. |
| 754 | (VEX_W_0F3823_P_2): Likewise. |
| 755 | (VEX_W_0F3824_P_2): Likewise. |
| 756 | (VEX_W_0F3825_P_2): Likewise. |
| 757 | (VEX_W_0F3828_P_2): Likewise. |
| 758 | (VEX_W_0F3829_P_2): Likewise. |
| 759 | (VEX_W_0F382A_P_2_M_0): Likewise. |
| 760 | (VEX_W_0F382B_P_2): Likewise. |
| 761 | (VEX_W_0F3830_P_2): Likewise. |
| 762 | (VEX_W_0F3831_P_2): Likewise. |
| 763 | (VEX_W_0F3832_P_2): Likewise. |
| 764 | (VEX_W_0F3833_P_2): Likewise. |
| 765 | (VEX_W_0F3834_P_2): Likewise. |
| 766 | (VEX_W_0F3835_P_2): Likewise. |
| 767 | (VEX_W_0F3837_P_2): Likewise. |
| 768 | (VEX_W_0F3838_P_2): Likewise. |
| 769 | (VEX_W_0F3839_P_2): Likewise. |
| 770 | (VEX_W_0F383A_P_2): Likewise. |
| 771 | (VEX_W_0F383B_P_2): Likewise. |
| 772 | (VEX_W_0F383C_P_2): Likewise. |
| 773 | (VEX_W_0F383D_P_2): Likewise. |
| 774 | (VEX_W_0F383E_P_2): Likewise. |
| 775 | (VEX_W_0F383F_P_2): Likewise. |
| 776 | (VEX_W_0F3840_P_2): Likewise. |
| 777 | (VEX_W_0F3841_P_2): Likewise. |
| 778 | (VEX_W_0F38DB_P_2): Likewise. |
| 779 | (VEX_W_0F3A08_P_2): Likewise. |
| 780 | (VEX_W_0F3A09_P_2): Likewise. |
| 781 | (VEX_W_0F3A0A_P_2): Likewise. |
| 782 | (VEX_W_0F3A0B_P_2): Likewise. |
| 783 | (VEX_W_0F3A0C_P_2): Likewise. |
| 784 | (VEX_W_0F3A0D_P_2): Likewise. |
| 785 | (VEX_W_0F3A0E_P_2): Likewise. |
| 786 | (VEX_W_0F3A0F_P_2): Likewise. |
| 787 | (VEX_W_0F3A21_P_2): Likewise. |
| 788 | (VEX_W_0F3A40_P_2): Likewise. |
| 789 | (VEX_W_0F3A41_P_2): Likewise. |
| 790 | (VEX_W_0F3A42_P_2): Likewise. |
| 791 | (VEX_W_0F3A62_P_2): Likewise. |
| 792 | (VEX_W_0F3A63_P_2): Likewise. |
| 793 | (VEX_W_0F3ADF_P_2): Likewise. |
| 794 | (VEX_LEN_0F77_P_0): New. |
| 795 | (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11, |
| 796 | PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E, |
| 797 | PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52, |
| 798 | PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59, |
| 799 | PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C, |
| 800 | PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F, |
| 801 | PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62, |
| 802 | PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65, |
| 803 | PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68, |
| 804 | PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, |
| 805 | PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F, |
| 806 | PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4, |
| 807 | PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4, |
| 808 | PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2, |
| 809 | PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6, |
| 810 | PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75, |
| 811 | PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C, |
| 812 | PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2, |
| 813 | PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2, |
| 814 | PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5, |
| 815 | PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, |
| 816 | PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE, |
| 817 | PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1, |
| 818 | PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4, |
| 819 | PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8, |
| 820 | PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB, |
| 821 | PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE, |
| 822 | PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2, |
| 823 | PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5, |
| 824 | PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9, |
| 825 | PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC, |
| 826 | PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800, |
| 827 | PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803, |
| 828 | PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806, |
| 829 | PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809, |
| 830 | PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817, |
| 831 | PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E, |
| 832 | PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822, |
| 833 | PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825, |
| 834 | PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B, |
| 835 | PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832, |
| 836 | PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835, |
| 837 | PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839, |
| 838 | PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C, |
| 839 | PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F, |
| 840 | PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09, |
| 841 | PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C, |
| 842 | PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F, |
| 843 | PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries. |
| 844 | (vex_table): Update VEX 0F28 and 0F29 entries. |
| 845 | (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3, |
| 846 | VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0, |
| 847 | VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2, |
| 848 | VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1, |
| 849 | VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3, |
| 850 | VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1, |
| 851 | VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3, |
| 852 | VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1, |
| 853 | VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3, |
| 854 | VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and |
| 855 | VEX_LEN_0F3A0B_P_2 entries. |
| 856 | (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1, |
| 857 | VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1, |
| 858 | VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0, |
| 859 | VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2, |
| 860 | VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15, |
| 861 | VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1, |
| 862 | VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29, |
| 863 | VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0, |
| 864 | VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1, |
| 865 | VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1, |
| 866 | VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1, |
| 867 | VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1, |
| 868 | VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1, |
| 869 | VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2, |
| 870 | VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3, |
| 871 | VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3, |
| 872 | VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3, |
| 873 | VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3, |
| 874 | VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2, |
| 875 | VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2, |
| 876 | VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2, |
| 877 | VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2, |
| 878 | VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3, |
| 879 | VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2, |
| 880 | VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2, |
| 881 | VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2, |
| 882 | VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2, |
| 883 | VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3, |
| 884 | VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1, |
| 885 | VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0, |
| 886 | VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3, |
| 887 | VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2, |
| 888 | VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2, |
| 889 | VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2, |
| 890 | VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2, |
| 891 | VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2, |
| 892 | VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2, |
| 893 | VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3, |
| 894 | VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2, |
| 895 | VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2, |
| 896 | VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0, |
| 897 | VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2, |
| 898 | VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2, |
| 899 | VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2, |
| 900 | VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2, |
| 901 | VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2, |
| 902 | VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2, |
| 903 | VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2, |
| 904 | VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2, |
| 905 | VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2, |
| 906 | VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2, |
| 907 | VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2, |
| 908 | VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0, |
| 909 | VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2, |
| 910 | VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2, |
| 911 | VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2, |
| 912 | VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2, |
| 913 | VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2, |
| 914 | VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2, |
| 915 | VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2, |
| 916 | VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2, |
| 917 | VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2, |
| 918 | VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2, |
| 919 | VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and |
| 920 | VEX_W_0F3ADF_P_2 entries. |
| 921 | (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50, |
| 922 | MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2, |
| 923 | MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries. |
| 924 | |
| 925 | 2018-09-17 H.J. Lu <hongjiu.lu@intel.com> |
| 926 | |
| 927 | * i386-opc.tbl (VexWIG): New. |
| 928 | Replace VexW=3 with VexWIG. |
| 929 | |
| 930 | 2018-09-15 H.J. Lu <hongjiu.lu@intel.com> |
| 931 | |
| 932 | * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss. |
| 933 | * i386-tbl.h: Regenerated. |
| 934 | |
| 935 | 2018-09-15 H.J. Lu <hongjiu.lu@intel.com> |
| 936 | |
| 937 | PR gas/23665 |
| 938 | * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and |
| 939 | VEX_LEN_0FD6_P_2 entries. |
| 940 | * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. |
| 941 | * i386-tbl.h: Regenerated. |
| 942 | |
| 943 | 2018-09-14 H.J. Lu <hongjiu.lu@intel.com> |
| 944 | |
| 945 | PR gas/23642 |
| 946 | * i386-opc.h (VEXWIG): New. |
| 947 | * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions. |
| 948 | * i386-tbl.h: Regenerated. |
| 949 | |
| 950 | 2018-09-14 H.J. Lu <hongjiu.lu@intel.com> |
| 951 | |
| 952 | PR binutils/23655 |
| 953 | * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for |
| 954 | vcvtsi2sd%LQ and vcvtusi2sd%LQ. |
| 955 | * i386-dis.c (EXxEVexR64): New. |
| 956 | (evex_rounding_64_mode): Likewise. |
| 957 | (OP_Rounding): Handle evex_rounding_64_mode. |
| 958 | |
| 959 | 2018-09-14 H.J. Lu <hongjiu.lu@intel.com> |
| 960 | |
| 961 | PR binutils/23655 |
| 962 | * i386-dis-evex.h (evex_table): Replace Eq with Edqa for |
| 963 | vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. |
| 964 | * i386-dis.c (Edqa): New. |
| 965 | (dqa_mode): Likewise. |
| 966 | (intel_operand_size): Handle dqa_mode as m_mode. |
| 967 | (OP_E_register): Handle dqa_mode as dq_mode. |
| 968 | (OP_E_memory): Set shift for dqa_mode based on address_mode. |
| 969 | |
| 970 | 2018-09-14 H.J. Lu <hongjiu.lu@intel.com> |
| 971 | |
| 972 | * i386-dis.c (OP_E_memory): Reformat. |
| 973 | |
| 974 | 2018-09-14 Jan Beulich <jbeulich@suse.com> |
| 975 | |
| 976 | * i386-opc.tbl (crc32): Fold byte and word forms. |
| 977 | * i386-tbl.h: Re-generate. |
| 978 | |
| 979 | 2018-09-13 H.J. Lu <hongjiu.lu@intel.com> |
| 980 | |
| 981 | * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd, |
| 982 | pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd. |
| 983 | Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and |
| 984 | vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq. |
| 985 | * i386-tbl.h: Regenerated. |
| 986 | |
| 987 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 988 | |
| 989 | * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where |
| 990 | meaningless. |
| 991 | (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors, |
| 992 | xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq, |
| 993 | rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize. |
| 994 | * i386-tbl.h: Re-generate. |
| 995 | |
| 996 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 997 | |
| 998 | * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and |
| 999 | AVX512_4VNNIW insns. |
| 1000 | * i386-tbl.h: Re-generate. |
| 1001 | |
| 1002 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1003 | |
| 1004 | * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where |
| 1005 | meaningless. |
| 1006 | * i386-tbl.h: Re-generate. |
| 1007 | |
| 1008 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1009 | |
| 1010 | * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where |
| 1011 | meaningless. |
| 1012 | * i386-tbl.h: Re-generate. |
| 1013 | |
| 1014 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1015 | |
| 1016 | * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where |
| 1017 | meaningless. |
| 1018 | * i386-tbl.h: Re-generate. |
| 1019 | |
| 1020 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1021 | |
| 1022 | * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where |
| 1023 | meaningless. |
| 1024 | * i386-tbl.h: Re-generate. |
| 1025 | |
| 1026 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1027 | |
| 1028 | * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where |
| 1029 | meaningless. |
| 1030 | * i386-tbl.h: Re-generate. |
| 1031 | |
| 1032 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1033 | |
| 1034 | * i386-opc.tbl: Drop IgnoreSize from SHA insns. |
| 1035 | * i386-tbl.h: Re-generate. |
| 1036 | |
| 1037 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1038 | |
| 1039 | * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns. |
| 1040 | * i386-tbl.h: Re-generate. |
| 1041 | |
| 1042 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1043 | |
| 1044 | * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where |
| 1045 | meaningless. |
| 1046 | * i386-tbl.h: Re-generate. |
| 1047 | |
| 1048 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1049 | |
| 1050 | * i386-opc.tbl: Drop IgnoreSize from AVX insns where |
| 1051 | meaningless. |
| 1052 | * i386-tbl.h: Re-generate. |
| 1053 | |
| 1054 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1055 | |
| 1056 | * i386-opc.tbl: Drop IgnoreSize from GNFI insns. |
| 1057 | * i386-tbl.h: Re-generate. |
| 1058 | |
| 1059 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1060 | |
| 1061 | * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns. |
| 1062 | * i386-tbl.h: Re-generate. |
| 1063 | |
| 1064 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1065 | |
| 1066 | * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns. |
| 1067 | * i386-tbl.h: Re-generate. |
| 1068 | |
| 1069 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1070 | |
| 1071 | * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where |
| 1072 | meaningless. |
| 1073 | * i386-tbl.h: Re-generate. |
| 1074 | |
| 1075 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1076 | |
| 1077 | * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where |
| 1078 | meaningless. |
| 1079 | * i386-tbl.h: Re-generate. |
| 1080 | |
| 1081 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1082 | |
| 1083 | * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where |
| 1084 | meaningless. |
| 1085 | * i386-tbl.h: Re-generate. |
| 1086 | |
| 1087 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1088 | |
| 1089 | * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless. |
| 1090 | * i386-tbl.h: Re-generate. |
| 1091 | |
| 1092 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1093 | |
| 1094 | * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless. |
| 1095 | * i386-tbl.h: Re-generate. |
| 1096 | |
| 1097 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1098 | |
| 1099 | * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless. |
| 1100 | * i386-tbl.h: Re-generate. |
| 1101 | |
| 1102 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1103 | |
| 1104 | * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64. |
| 1105 | (vpbroadcastw, rdpid): Drop NoRex64. |
| 1106 | * i386-tbl.h: Re-generate. |
| 1107 | |
| 1108 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1109 | |
| 1110 | * i386-opc.tbl (vmovsd, vmovss): Fold register form load and |
| 1111 | store templates, adding D. |
| 1112 | * i386-tbl.h: Re-generate. |
| 1113 | |
| 1114 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1115 | |
| 1116 | * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd, |
| 1117 | movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps, |
| 1118 | movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd, |
| 1119 | vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32, |
| 1120 | vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups): |
| 1121 | Fold load and store templates where possible, adding D. Drop |
| 1122 | IgnoreSize where it was pointlessly present. Drop redundant |
| 1123 | *word. |
| 1124 | * i386-tbl.h: Re-generate. |
| 1125 | |
| 1126 | 2018-09-13 Jan Beulich <jbeulich@suse.com> |
| 1127 | |
| 1128 | * i386-dis.c (Mv_bnd, v_bndmk_mode): New. |
| 1129 | (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk. |
| 1130 | (intel_operand_size): Handle v_bndmk_mode. |
| 1131 | (OP_E_memory): Likewise. Produce (bad) when also riprel. |
| 1132 | |
| 1133 | 2018-09-08 John Darrington <john@darrington.wattle.id.au> |
| 1134 | |
| 1135 | * disassemble.c (ARCH_s12z): Define if ARCH_all. |
| 1136 | |
| 1137 | 2018-08-31 Kito Cheng <kito@andestech.com> |
| 1138 | |
| 1139 | * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for |
| 1140 | compressed floating point instructions. |
| 1141 | |
| 1142 | 2018-08-30 Kito Cheng <kito@andestech.com> |
| 1143 | |
| 1144 | * riscv-dis.c (riscv_disassemble_insn): Check XLEN by |
| 1145 | riscv_opcode.xlen_requirement. |
| 1146 | * riscv-opc.c (riscv_opcodes): Update for struct change. |
| 1147 | |
| 1148 | 2018-08-29 Martin Aberg <maberg@gaisler.com> |
| 1149 | |
| 1150 | * sparc-opc.c (sparc_opcodes): Add Leon specific partial write |
| 1151 | psr (PWRPSR) instruction. |
| 1152 | |
| 1153 | 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1154 | |
| 1155 | * mips-dis.c (mips_arch_choices): Add gs264e descriptors. |
| 1156 | |
| 1157 | 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1158 | |
| 1159 | * mips-dis.c (mips_arch_choices): Add gs464e descriptors. |
| 1160 | |
| 1161 | 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1162 | |
| 1163 | * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep |
| 1164 | loongson3a as an alias of gs464 for compatibility. |
| 1165 | * mips-opc.c (mips_opcodes): Change Comments. |
| 1166 | |
| 1167 | 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1168 | |
| 1169 | * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext |
| 1170 | option. |
| 1171 | (print_mips_disassembler_options): Document -M loongson-ext. |
| 1172 | * mips-opc.c (LEXT2): New macro. |
| 1173 | (mips_opcodes): Add cto, ctz, dcto, dctz instructions. |
| 1174 | |
| 1175 | 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1176 | |
| 1177 | * mips-dis.c (mips_arch_choices): Add EXT to loongson3a |
| 1178 | descriptors. |
| 1179 | (parse_mips_ase_option): Handle -M loongson-ext option. |
| 1180 | (print_mips_disassembler_options): Document -M loongson-ext. |
| 1181 | * mips-opc.c (IL3A): Delete. |
| 1182 | * mips-opc.c (LEXT): New macro. |
| 1183 | (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT |
| 1184 | instructions. |
| 1185 | |
| 1186 | 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1187 | |
| 1188 | * mips-dis.c (mips_arch_choices): Add CAM to loongson3a |
| 1189 | descriptors. |
| 1190 | (parse_mips_ase_option): Handle -M loongson-cam option. |
| 1191 | (print_mips_disassembler_options): Document -M loongson-cam. |
| 1192 | * mips-opc.c (LCAM): New macro. |
| 1193 | (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM |
| 1194 | instructions. |
| 1195 | |
| 1196 | 2018-08-21 Alan Modra <amodra@gmail.com> |
| 1197 | |
| 1198 | * ppc-dis.c (operand_value_powerpc): Init "invalid". |
| 1199 | (skip_optional_operands): Count optional operands, and update |
| 1200 | ppc_optional_operand_value call. |
| 1201 | * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. |
| 1202 | (extract_vlensi): Likewise. |
| 1203 | (extract_fxm): Return default value for missing optional operand. |
| 1204 | (extract_ls, extract_raq, extract_tbr): Likewise. |
| 1205 | (insert_sxl, extract_sxl): New functions. |
| 1206 | (insert_esync, extract_esync): Remove Power9 handling and simplify. |
| 1207 | (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE |
| 1208 | flag and extra entry. |
| 1209 | (powerpc_operands <SXL>): Likewise, and use insert_sxl and |
| 1210 | extract_sxl. |
| 1211 | |
| 1212 | 2018-08-20 Alan Modra <amodra@gmail.com> |
| 1213 | |
| 1214 | * sh-opc.h (MASK): Simplify. |
| 1215 | |
| 1216 | 2018-08-18 John Darrington <john@darrington.wattle.id.au> |
| 1217 | |
| 1218 | * s12z-dis.c (bm_decode): Deal with cases where the mode is |
| 1219 | BM_RESERVED0 or BM_RESERVED1 |
| 1220 | (bm_rel_decode, bm_n_bytes): Ditto. |
| 1221 | |
| 1222 | 2018-08-18 John Darrington <john@darrington.wattle.id.au> |
| 1223 | |
| 1224 | * s12z.h: Delete. |
| 1225 | |
| 1226 | 2018-08-14 H.J. Lu <hongjiu.lu@intel.com> |
| 1227 | |
| 1228 | * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for |
| 1229 | address with the addr32 prefix and without base nor index |
| 1230 | registers. |
| 1231 | |
| 1232 | 2018-08-11 H.J. Lu <hongjiu.lu@intel.com> |
| 1233 | |
| 1234 | * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to |
| 1235 | CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS, |
| 1236 | CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS. |
| 1237 | (cpu_flags): Add CpuCMOV and CpuFXSR. |
| 1238 | * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64, |
| 1239 | fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC. |
| 1240 | * i386-init.h: Regenerated. |
| 1241 | * i386-tbl.h: Likewise. |
| 1242 | |
| 1243 | 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com> |
| 1244 | |
| 1245 | * arc-regs.h: Update auxiliary registers. |
| 1246 | |
| 1247 | 2018-08-06 Jan Beulich <jbeulich@suse.com> |
| 1248 | |
| 1249 | * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines. |
| 1250 | (RegIP, RegIZ): Define. |
| 1251 | * i386-reg.tbl: Adjust comments. |
| 1252 | (rip): Use Qword instead of BaseIndex. Use RegIP. |
| 1253 | (eip): Use Dword instead of BaseIndex. Use RegIP. |
| 1254 | (riz): Add Qword. Use RegIZ. |
| 1255 | (eiz): Add Dword. Use RegIZ. |
| 1256 | * i386-tbl.h: Re-generate. |
| 1257 | |
| 1258 | 2018-08-03 Jan Beulich <jbeulich@suse.com> |
| 1259 | |
| 1260 | * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw, |
| 1261 | pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw, |
| 1262 | vpmovzxdq, vpmovzxwd): Remove NoRex64. |
| 1263 | * i386-tbl.h: Re-generate. |
| 1264 | |
| 1265 | 2018-08-03 Jan Beulich <jbeulich@suse.com> |
| 1266 | |
| 1267 | * i386-gen.c (operand_types): Remove Mem field. |
| 1268 | * i386-opc.h (union i386_operand_type): Remove mem field. |
| 1269 | * i386-init.h, i386-tbl.h: Re-generate. |
| 1270 | |
| 1271 | 2018-08-01 Alan Modra <amodra@gmail.com> |
| 1272 | |
| 1273 | * po/POTFILES.in: Regenerate. |
| 1274 | |
| 1275 | 2018-07-31 Nick Clifton <nickc@redhat.com> |
| 1276 | |
| 1277 | * po/sv.po: Updated Swedish translation. |
| 1278 | |
| 1279 | 2018-07-31 Jan Beulich <jbeulich@suse.com> |
| 1280 | |
| 1281 | * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize. |
| 1282 | * i386-init.h, i386-tbl.h: Re-generate. |
| 1283 | |
| 1284 | 2018-07-31 Jan Beulich <jbeulich@suse.com> |
| 1285 | |
| 1286 | * i386-opc.h (ZEROING_MASKING) Rename to ... |
| 1287 | (DYNAMIC_MASKING): ... this. Adjust comment. |
| 1288 | * i386-opc.tbl (MaskingMorZ): Define. |
| 1289 | (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4, |
| 1290 | vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4, |
| 1291 | vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps, |
| 1292 | vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64, |
| 1293 | vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd, |
| 1294 | vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw, |
| 1295 | vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb, |
| 1296 | vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw, |
| 1297 | vpmovuswb, vpmovwb): Fold AVX512 register and memory forms. |
| 1298 | |
| 1299 | 2018-07-31 Jan Beulich <jbeulich@suse.com> |
| 1300 | |
| 1301 | * i386-opc.tbl: Use element rather than vector size for AVX512* |
| 1302 | scatter/gather insns. |
| 1303 | * i386-tbl.h: Re-generate. |
| 1304 | |
| 1305 | 2018-07-31 Jan Beulich <jbeulich@suse.com> |
| 1306 | |
| 1307 | * i386-gen.c (cpu_flag_init): Drop CpuVREX uses. |
| 1308 | (cpu_flags): Drop CpuVREX. |
| 1309 | * i386-opc.h (CpuVREX): Delete. |
| 1310 | (union i386_cpu_flags): Remove cpuvrex. |
| 1311 | * i386-init.h, i386-tbl.h: Re-generate. |
| 1312 | |
| 1313 | 2018-07-30 Jim Wilson <jimw@sifive.com> |
| 1314 | |
| 1315 | * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size |
| 1316 | fields. |
| 1317 | * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns. |
| 1318 | |
| 1319 | 2018-07-30 Andrew Jenner <andrew@codesourcery.com> |
| 1320 | |
| 1321 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. |
| 1322 | * Makefile.in: Regenerated. |
| 1323 | * configure.ac: Add C-SKY. |
| 1324 | * configure: Regenerated. |
| 1325 | * csky-dis.c: New file. |
| 1326 | * csky-opc.h: New file. |
| 1327 | * disassemble.c (ARCH_csky): Define. |
| 1328 | (disassembler, disassemble_init_for_target): Add case for ARCH_csky. |
| 1329 | * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. |
| 1330 | |
| 1331 | 2018-07-27 Alan Modra <amodra@gmail.com> |
| 1332 | |
| 1333 | * ppc-opc.c (insert_sprbat): Correct function parameter and |
| 1334 | return type. |
| 1335 | (extract_sprbat): Likewise, variable too. |
| 1336 | |
| 1337 | 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk> |
| 1338 | Alan Modra <amodra@gmail.com> |
| 1339 | |
| 1340 | * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. |
| 1341 | (powerpc_init_dialect): Handle bfd_mach_ppc_750. |
| 1342 | * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to |
| 1343 | support disjointed BAT. |
| 1344 | (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. |
| 1345 | (XSPRGQR_MASK, GEKKO, BROADWAY): Define. |
| 1346 | (powerpc_opcodes): Add 750cl extended mnemonics for spr access. |
| 1347 | |
| 1348 | 2018-07-25 H.J. Lu <hongjiu.lu@intel.com> |
| 1349 | Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 1350 | |
| 1351 | * i386-gen.c (adjust_broadcast_modifier): New function. |
| 1352 | (process_i386_opcode_modifier): Add an argument for operands. |
| 1353 | Adjust the Broadcast value based on operands. |
| 1354 | (output_i386_opcode): Pass operand_types to |
| 1355 | process_i386_opcode_modifier. |
| 1356 | (process_i386_opcodes): Pass NULL as operands to |
| 1357 | process_i386_opcode_modifier. |
| 1358 | * i386-opc.h (BYTE_BROADCAST): New. |
| 1359 | (WORD_BROADCAST): Likewise. |
| 1360 | (DWORD_BROADCAST): Likewise. |
| 1361 | (QWORD_BROADCAST): Likewise. |
| 1362 | (i386_opcode_modifier): Expand broadcast to 3 bits. |
| 1363 | * i386-tbl.h: Regenerated. |
| 1364 | |
| 1365 | 2018-07-24 Alan Modra <amodra@gmail.com> |
| 1366 | |
| 1367 | PR 23430 |
| 1368 | * or1k-desc.h: Regenerate. |
| 1369 | |
| 1370 | 2018-07-24 Jan Beulich <jbeulich@suse.com> |
| 1371 | |
| 1372 | * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd, |
| 1373 | vcvtusi2ss, and vcvtusi2sd. |
| 1374 | * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss): |
| 1375 | Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms. |
| 1376 | * i386-tbl.h: Re-generate. |
| 1377 | |
| 1378 | 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com> |
| 1379 | |
| 1380 | * arc-opc.c (extract_w6): Fix extending the sign. |
| 1381 | |
| 1382 | 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com> |
| 1383 | |
| 1384 | * arc-tbl.h (vewt): Allow it for ARC EM family. |
| 1385 | |
| 1386 | 2018-07-23 Alan Modra <amodra@gmail.com> |
| 1387 | |
| 1388 | PR 23419 |
| 1389 | * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended |
| 1390 | opcode variants for mtspr/mfspr encodings. |
| 1391 | |
| 1392 | 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1393 | Maciej W. Rozycki <macro@mips.com> |
| 1394 | |
| 1395 | * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and |
| 1396 | loongson3a descriptors. |
| 1397 | (parse_mips_ase_option): Handle -M loongson-mmi option. |
| 1398 | (print_mips_disassembler_options): Document -M loongson-mmi. |
| 1399 | * mips-opc.c (LMMI): New macro. |
| 1400 | (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI |
| 1401 | instructions. |
| 1402 | |
| 1403 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1404 | |
| 1405 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, |
| 1406 | vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop |
| 1407 | IgnoreSize and [XYZ]MMword where applicable. |
| 1408 | * i386-tbl.h: Re-generate. |
| 1409 | |
| 1410 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1411 | |
| 1412 | * i386-opc.tbl (vfpclasspd, vfpclassps): Fold. |
| 1413 | (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord. |
| 1414 | (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord. |
| 1415 | (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord. |
| 1416 | * i386-tbl.h: Re-generate. |
| 1417 | |
| 1418 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1419 | |
| 1420 | * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ, |
| 1421 | AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and |
| 1422 | VPCLMULQDQ templates into their respective AVX512VL counterparts |
| 1423 | where possible, using Disp8ShiftVL and CheckRegSize instead of |
| 1424 | Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate. |
| 1425 | * i386-tbl.h: Re-generate. |
| 1426 | |
| 1427 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1428 | |
| 1429 | * i386-opc.tbl: Fold AVX512DQ templates into their respective |
| 1430 | AVX512VL counterparts where possible, using Disp8ShiftVL and |
| 1431 | CheckRegSize instead of Evex= plus Disp8MemShift= (plus often |
| 1432 | IgnoreSize) as appropriate. |
| 1433 | * i386-tbl.h: Re-generate. |
| 1434 | |
| 1435 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1436 | |
| 1437 | * i386-opc.tbl: Fold AVX512BW templates into their respective |
| 1438 | AVX512VL counterparts where possible, using Disp8ShiftVL and |
| 1439 | CheckRegSize instead of Evex= plus Disp8MemShift= (plus often |
| 1440 | IgnoreSize) as appropriate. |
| 1441 | * i386-tbl.h: Re-generate. |
| 1442 | |
| 1443 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1444 | |
| 1445 | * i386-opc.tbl: Fold AVX512CD templates into their respective |
| 1446 | AVX512VL counterparts where possible, using Disp8ShiftVL and |
| 1447 | CheckRegSize instead of Evex= plus Disp8MemShift= (plus often |
| 1448 | IgnoreSize) as appropriate. |
| 1449 | * i386-tbl.h: Re-generate. |
| 1450 | |
| 1451 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1452 | |
| 1453 | * i386-opc.h (DISP8_SHIFT_VL): New. |
| 1454 | * i386-opc.tbl (Disp8ShiftVL): Define. |
| 1455 | (various): Fold AVX512VL templates into their respective |
| 1456 | AVX512F counterparts where possible, using Disp8ShiftVL and |
| 1457 | CheckRegSize instead of Evex= plus Disp8MemShift= (plus often |
| 1458 | IgnoreSize) as appropriate. |
| 1459 | * i386-tbl.h: Re-generate. |
| 1460 | |
| 1461 | 2018-07-19 Jan Beulich <jbeulich@suse.com> |
| 1462 | |
| 1463 | * Makefile.am: Change dependencies and rule for |
| 1464 | $(srcdir)/i386-init.h. |
| 1465 | * Makefile.in: Re-generate. |
| 1466 | * i386-gen.c (process_i386_opcodes): New local variable |
| 1467 | "marker". Drop opening of input file. Recognize marker and line |
| 1468 | number directives. |
| 1469 | * i386-opc.tbl (OPCODE_I386_H): Define. |
| 1470 | (i386-opc.h): Include it. |
| 1471 | (None): Undefine. |
| 1472 | |
| 1473 | 2018-07-18 H.J. Lu <hongjiu.lu@intel.com> |
| 1474 | |
| 1475 | PR gas/23418 |
| 1476 | * i386-opc.h (Byte): Update comments. |
| 1477 | (Word): Likewise. |
| 1478 | (Dword): Likewise. |
| 1479 | (Fword): Likewise. |
| 1480 | (Qword): Likewise. |
| 1481 | (Tbyte): Likewise. |
| 1482 | (Xmmword): Likewise. |
| 1483 | (Ymmword): Likewise. |
| 1484 | (Zmmword): Likewise. |
| 1485 | * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and |
| 1486 | vcvttps2uqq. |
| 1487 | * i386-tbl.h: Regenerated. |
| 1488 | |
| 1489 | 2018-07-12 Sudakshina Das <sudi.das@arm.com> |
| 1490 | |
| 1491 | * aarch64-tbl.h (aarch64_opcode_table): Add entry for |
| 1492 | ssbb and pssbb and update dsb flags to F_HAS_ALIAS. |
| 1493 | * aarch64-asm-2.c: Regenerate. |
| 1494 | * aarch64-dis-2.c: Regenerate. |
| 1495 | * aarch64-opc-2.c: Regenerate. |
| 1496 | |
| 1497 | 2018-07-12 Tamar Christina <tamar.christina@arm.com> |
| 1498 | |
| 1499 | PR binutils/23192 |
| 1500 | * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, |
| 1501 | mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, |
| 1502 | umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, |
| 1503 | sqdmulh, sqrdmulh): Use Em16. |
| 1504 | |
| 1505 | 2018-07-11 Sudakshina Das <sudi.das@arm.com> |
| 1506 | |
| 1507 | * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move |
| 1508 | csdb together with them. |
| 1509 | (thumb32_opcodes): Likewise. |
| 1510 | |
| 1511 | 2018-07-11 Jan Beulich <jbeulich@suse.com> |
| 1512 | |
| 1513 | * i386-opc.tbl (monitor, monitorx): Add 64-bit template |
| 1514 | requiring 32-bit registers as operands 2 and 3. Improve |
| 1515 | comments. |
| 1516 | (mwait, mwaitx): Fold templates. Improve comments. |
| 1517 | OPERAND_TYPE_INOUTPORTREG. |
| 1518 | * i386-tbl.h: Re-generate. |
| 1519 | |
| 1520 | 2018-07-11 Jan Beulich <jbeulich@suse.com> |
| 1521 | |
| 1522 | * i386-gen.c (operand_type_init): Remove |
| 1523 | OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of |
| 1524 | OPERAND_TYPE_INOUTPORTREG. |
| 1525 | * i386-init.h: Re-generate. |
| 1526 | |
| 1527 | 2018-07-11 Jan Beulich <jbeulich@suse.com> |
| 1528 | |
| 1529 | * i386-opc.tbl (wrssd, wrussd): Add Dword. |
| 1530 | (wrssq, wrussq): Add Qword. |
| 1531 | * i386-tbl.h: Re-generate. |
| 1532 | |
| 1533 | 2018-07-11 Jan Beulich <jbeulich@suse.com> |
| 1534 | |
| 1535 | * i386-opc.h: Rename OTMax to OTNum. |
| 1536 | (OTNumOfUints): Adjust calculation. |
| 1537 | (OTUnused): Directly alias to OTNum. |
| 1538 | |
| 1539 | 2018-07-09 Maciej W. Rozycki <macro@mips.com> |
| 1540 | |
| 1541 | * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to |
| 1542 | `reg_xys'. |
| 1543 | (lea_reg_xys): Likewise. |
| 1544 | (print_insn_loop_primitive): Rename `reg' local variable to |
| 1545 | `reg_dxy'. |
| 1546 | |
| 1547 | 2018-07-06 Tamar Christina <tamar.christina@arm.com> |
| 1548 | |
| 1549 | PR binutils/23242 |
| 1550 | * aarch64-tbl.h (ldarh): Fix disassembly mask. |
| 1551 | |
| 1552 | 2018-07-06 Tamar Christina <tamar.christina@arm.com> |
| 1553 | |
| 1554 | PR binutils/23369 |
| 1555 | * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, |
| 1556 | vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. |
| 1557 | |
| 1558 | 2018-07-02 Maciej W. Rozycki <macro@mips.com> |
| 1559 | |
| 1560 | PR tdep/8282 |
| 1561 | * mips-dis.c (mips_option_arg_t): New enumeration. |
| 1562 | (mips_options): New variable. |
| 1563 | (disassembler_options_mips): New function. |
| 1564 | (print_mips_disassembler_options): Reimplement in terms of |
| 1565 | `disassembler_options_mips'. |
| 1566 | * arm-dis.c (disassembler_options_arm): Adapt to using the |
| 1567 | `disasm_options_and_args_t' structure. |
| 1568 | * ppc-dis.c (disassembler_options_powerpc): Likewise. |
| 1569 | * s390-dis.c (disassembler_options_s390): Likewise. |
| 1570 | |
| 1571 | 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 1572 | |
| 1573 | * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in |
| 1574 | expected result. |
| 1575 | * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. |
| 1576 | * testsuite/ld-arm/tls-longplt-lib.d: Likewise. |
| 1577 | * testsuite/ld-arm/tls-longplt.d: Likewise. |
| 1578 | |
| 1579 | 2018-06-29 Tamar Christina <tamar.christina@arm.com> |
| 1580 | |
| 1581 | PR binutils/23192 |
| 1582 | * aarch64-asm-2.c: Regenerate. |
| 1583 | * aarch64-dis-2.c: Likewise. |
| 1584 | * aarch64-opc-2.c: Likewise. |
| 1585 | * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. |
| 1586 | * aarch64-opc.c (operand_general_constraint_met_p, |
| 1587 | aarch64_print_operand): Likewise. |
| 1588 | * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, |
| 1589 | smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, |
| 1590 | fmlal2, fmlsl2. |
| 1591 | (AARCH64_OPERANDS): Add Em2. |
| 1592 | |
| 1593 | 2018-06-26 Nick Clifton <nickc@redhat.com> |
| 1594 | |
| 1595 | * po/uk.po: Updated Ukranian translation. |
| 1596 | * po/de.po: Updated German translation. |
| 1597 | * po/pt_BR.po: Updated Brazilian Portuguese translation. |
| 1598 | |
| 1599 | 2018-06-26 Nick Clifton <nickc@redhat.com> |
| 1600 | |
| 1601 | * nfp-dis.c: Fix spelling mistake. |
| 1602 | |
| 1603 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
| 1604 | |
| 1605 | * configure: Regenerate. |
| 1606 | * po/opcodes.pot: Regenerate. |
| 1607 | |
| 1608 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
| 1609 | |
| 1610 | 2.31 branch created. |
| 1611 | |
| 1612 | 2018-06-19 Tamar Christina <tamar.christina@arm.com> |
| 1613 | |
| 1614 | * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs |
| 1615 | * aarch64-asm-2.c: Regenerate. |
| 1616 | * aarch64-dis-2.c: Likewise. |
| 1617 | |
| 1618 | 2018-06-21 Maciej W. Rozycki <macro@mips.com> |
| 1619 | |
| 1620 | * mips-dis.c (print_mips_disassembler_options): Fix a typo in |
| 1621 | `-M ginv' option description. |
| 1622 | |
| 1623 | 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de> |
| 1624 | |
| 1625 | PR gas/23305 |
| 1626 | * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for |
| 1627 | la and lla. |
| 1628 | |
| 1629 | 2018-06-19 Simon Marchi <simon.marchi@ericsson.com> |
| 1630 | |
| 1631 | * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. |
| 1632 | * configure.ac: Remove AC_PREREQ. |
| 1633 | * Makefile.in: Re-generate. |
| 1634 | * aclocal.m4: Re-generate. |
| 1635 | * configure: Re-generate. |
| 1636 | |
| 1637 | 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com> |
| 1638 | |
| 1639 | * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and |
| 1640 | mips64r6 descriptors. |
| 1641 | (parse_mips_ase_option): Handle -Mginv option. |
| 1642 | (print_mips_disassembler_options): Document -Mginv. |
| 1643 | * mips-opc.c (decode_mips_operand) <+\>: New operand format. |
| 1644 | (GINV): New macro. |
| 1645 | (mips_opcodes): Define ginvi and ginvt. |
| 1646 | |
| 1647 | 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> |
| 1648 | Faraz Shahbazker <Faraz.Shahbazker@mips.com> |
| 1649 | |
| 1650 | * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. |
| 1651 | * mips-opc.c (CRC, CRC64): New macros. |
| 1652 | (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, |
| 1653 | crc32cb, crc32ch and crc32cw for CRC. Define crc32d and |
| 1654 | crc32cd for CRC64. |
| 1655 | |
| 1656 | 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com> |
| 1657 | |
| 1658 | PR 20319 |
| 1659 | * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV. |
| 1660 | (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV. |
| 1661 | |
| 1662 | 2018-06-06 Alan Modra <amodra@gmail.com> |
| 1663 | |
| 1664 | * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after |
| 1665 | setjmp. Move init for some other vars later too. |
| 1666 | |
| 1667 | 2018-06-04 Max Filippov <jcmvbkbc@gmail.com> |
| 1668 | |
| 1669 | * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. |
| 1670 | (dis_private): Add new fields for property section tracking. |
| 1671 | (xtensa_coalesce_insn_tables, xtensa_find_table_entry) |
| 1672 | (xtensa_instruction_fits): New functions. |
| 1673 | (fetch_data): Bump minimal fetch size to 4. |
| 1674 | (print_insn_xtensa): Make struct dis_private static. |
| 1675 | Load and prepare property table on section change. |
| 1676 | Don't disassemble literals. Don't disassemble instructions that |
| 1677 | cross property table boundaries. |
| 1678 | |
| 1679 | 2018-06-01 H.J. Lu <hongjiu.lu@intel.com> |
| 1680 | |
| 1681 | * configure: Regenerated. |
| 1682 | |
| 1683 | 2018-06-01 Jan Beulich <jbeulich@suse.com> |
| 1684 | |
| 1685 | * i386-opc.tbl (mov, movq): Fold to/from SReg* forms. |
| 1686 | * i386-tbl.h: Re-generate. |
| 1687 | |
| 1688 | 2018-06-01 Jan Beulich <jbeulich@suse.com> |
| 1689 | |
| 1690 | * i386-opc.tbl (sldt, str): Add NoRex64. |
| 1691 | * i386-tbl.h: Re-generate. |
| 1692 | |
| 1693 | 2018-06-01 Jan Beulich <jbeulich@suse.com> |
| 1694 | |
| 1695 | * i386-opc.tbl (invpcid): Add Oword. |
| 1696 | * i386-tbl.h: Re-generate. |
| 1697 | |
| 1698 | 2018-06-01 Alan Modra <amodra@gmail.com> |
| 1699 | |
| 1700 | * sysdep.h (_bfd_error_handler): Don't declare. |
| 1701 | * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here. |
| 1702 | * rl78-decode.opc: Likewise. |
| 1703 | * msp430-decode.c: Regenerate. |
| 1704 | * rl78-decode.c: Regenerate. |
| 1705 | |
| 1706 | 2018-05-30 Amit Pawar <Amit.Pawar@amd.com> |
| 1707 | |
| 1708 | * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS. |
| 1709 | * i386-init.h : Regenerated. |
| 1710 | |
| 1711 | 2018-05-25 Alan Modra <amodra@gmail.com> |
| 1712 | |
| 1713 | * Makefile.in: Regenerate. |
| 1714 | * po/POTFILES.in: Regenerate. |
| 1715 | |
| 1716 | 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com> |
| 1717 | |
| 1718 | * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, |
| 1719 | insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. |
| 1720 | (insert_bab, extract_bab, insert_btab, extract_btab, |
| 1721 | insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. |
| 1722 | (BAT, BBA VBA RBS XB6S): Delete macros. |
| 1723 | (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. |
| 1724 | (BB, BD, RBX, XC6): Update for new macros. |
| 1725 | (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset, |
| 1726 | crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp, |
| 1727 | e_crnot, e_crclr, e_crset, e_crmove>: Likewise. |
| 1728 | * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. |
| 1729 | |
| 1730 | 2018-05-18 John Darrington <john@darrington.wattle.id.au> |
| 1731 | |
| 1732 | * Makefile.am: Add support for s12z architecture. |
| 1733 | * configure.ac: Likewise. |
| 1734 | * disassemble.c: Likewise. |
| 1735 | * disassemble.h: Likewise. |
| 1736 | * Makefile.in: Regenerate. |
| 1737 | * configure: Regenerate. |
| 1738 | * s12z-dis.c: New file. |
| 1739 | * s12z.h: New file. |
| 1740 | |
| 1741 | 2018-05-18 Alan Modra <amodra@gmail.com> |
| 1742 | |
| 1743 | * nfp-dis.c: Don't #include libbfd.h. |
| 1744 | (init_nfp3200_priv): Use bfd_get_section_contents. |
| 1745 | (nit_nfp6000_mecsr_sec): Likewise. |
| 1746 | |
| 1747 | 2018-05-17 Nick Clifton <nickc@redhat.com> |
| 1748 | |
| 1749 | * po/zh_CN.po: Updated simplified Chinese translation. |
| 1750 | |
| 1751 | 2018-05-16 Tamar Christina <tamar.christina@arm.com> |
| 1752 | |
| 1753 | PR binutils/23109 |
| 1754 | * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot. |
| 1755 | * aarch64-dis-2.c: Regenerate. |
| 1756 | |
| 1757 | 2018-05-15 Tamar Christina <tamar.christina@arm.com> |
| 1758 | |
| 1759 | PR binutils/21446 |
| 1760 | * aarch64-asm.c (opintl.h): Include. |
| 1761 | (aarch64_ins_sysreg): Enforce read/write constraints. |
| 1762 | * aarch64-dis.c (aarch64_ext_sysreg): Likewise. |
| 1763 | * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. |
| 1764 | (F_REG_READ, F_REG_WRITE): New. |
| 1765 | * aarch64-opc.c (aarch64_print_operand): Generate notes for |
| 1766 | AARCH64_OPND_SYSREG. |
| 1767 | (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. |
| 1768 | (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, |
| 1769 | mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, |
| 1770 | id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, |
| 1771 | id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, |
| 1772 | id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, |
| 1773 | mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, |
| 1774 | id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, |
| 1775 | id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, |
| 1776 | id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, |
| 1777 | csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, |
| 1778 | rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, |
| 1779 | mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, |
| 1780 | mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, |
| 1781 | pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. |
| 1782 | * aarch64-tbl.h (aarch64_opcode_table): Add constraints to |
| 1783 | msr (F_SYS_WRITE), mrs (F_SYS_READ). |
| 1784 | |
| 1785 | 2018-05-15 Tamar Christina <tamar.christina@arm.com> |
| 1786 | |
| 1787 | PR binutils/21446 |
| 1788 | * aarch64-dis.c (no_notes: New. |
| 1789 | (parse_aarch64_dis_option): Support notes. |
| 1790 | (aarch64_decode_insn, print_operands): Likewise. |
| 1791 | (print_aarch64_disassembler_options): Document notes. |
| 1792 | * aarch64-opc.c (aarch64_print_operand): Support notes. |
| 1793 | |
| 1794 | 2018-05-15 Tamar Christina <tamar.christina@arm.com> |
| 1795 | |
| 1796 | PR binutils/21446 |
| 1797 | * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean |
| 1798 | and take error struct. |
| 1799 | * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, |
| 1800 | aarch64_ins_reglist, aarch64_ins_ldst_reglist, |
| 1801 | aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, |
| 1802 | aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, |
| 1803 | aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, |
| 1804 | aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, |
| 1805 | aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, |
| 1806 | aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, |
| 1807 | aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, |
| 1808 | aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, |
| 1809 | aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, |
| 1810 | aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, |
| 1811 | aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, |
| 1812 | aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, |
| 1813 | aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, |
| 1814 | aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, |
| 1815 | aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, |
| 1816 | aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, |
| 1817 | aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, |
| 1818 | aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, |
| 1819 | aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, |
| 1820 | aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, |
| 1821 | aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, |
| 1822 | aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, |
| 1823 | aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. |
| 1824 | * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. |
| 1825 | * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, |
| 1826 | aarch64_ext_reglist, aarch64_ext_ldst_reglist, |
| 1827 | aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, |
| 1828 | aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, |
| 1829 | aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, |
| 1830 | aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, |
| 1831 | aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, |
| 1832 | aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, |
| 1833 | aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, |
| 1834 | aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, |
| 1835 | aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, |
| 1836 | aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, |
| 1837 | aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, |
| 1838 | aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, |
| 1839 | aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, |
| 1840 | aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, |
| 1841 | aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, |
| 1842 | aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, |
| 1843 | aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, |
| 1844 | aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, |
| 1845 | aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, |
| 1846 | aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, |
| 1847 | aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, |
| 1848 | aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, |
| 1849 | aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. |
| 1850 | (determine_disassembling_preference, aarch64_decode_insn, |
| 1851 | print_insn_aarch64_word, print_insn_data): Take errors struct. |
| 1852 | (print_insn_aarch64): Use errors. |
| 1853 | * aarch64-asm-2.c: Regenerate. |
| 1854 | * aarch64-dis-2.c: Regenerate. |
| 1855 | * aarch64-gen.c (print_operand_inserter): Use errors and change type to |
| 1856 | boolean in aarch64_insert_operan. |
| 1857 | (print_operand_extractor): Likewise. |
| 1858 | * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. |
| 1859 | |
| 1860 | 2018-05-15 Francois H. Theron <francois.theron@netronome.com> |
| 1861 | |
| 1862 | * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma. |
| 1863 | |
| 1864 | 2018-05-09 H.J. Lu <hongjiu.lu@intel.com> |
| 1865 | |
| 1866 | * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}. |
| 1867 | |
| 1868 | 2018-05-09 Sebastian Rasmussen <sebras@gmail.com> |
| 1869 | |
| 1870 | * cr16-opc.c (cr16_instruction): Comment typo fix. |
| 1871 | * hppa-dis.c (print_insn_hppa): Likewise. |
| 1872 | |
| 1873 | 2018-05-08 Jim Wilson <jimw@sifive.com> |
| 1874 | |
| 1875 | * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. |
| 1876 | (match_c_slli64, match_srxi_as_c_srxi): New. |
| 1877 | (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. |
| 1878 | <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. |
| 1879 | <c.slli, c.srli, c.srai>: Use match_s_slli. |
| 1880 | <c.slli64, c.srli64, c.srai64>: New. |
| 1881 | |
| 1882 | 2018-05-08 Alan Modra <amodra@gmail.com> |
| 1883 | |
| 1884 | * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP. |
| 1885 | (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to |
| 1886 | partition opcode space for index lookup. |
| 1887 | |
| 1888 | 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com> |
| 1889 | |
| 1890 | * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this... |
| 1891 | <insn_length>: ...with this. Update usage. |
| 1892 | Remove duplicate call to *info->memory_error_func. |
| 1893 | |
| 1894 | 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 1895 | H.J. Lu <hongjiu.lu@intel.com> |
| 1896 | |
| 1897 | * i386-dis.c (Gva): New. |
| 1898 | (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, |
| 1899 | MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. |
| 1900 | (prefix_table): New instructions (see prefix above). |
| 1901 | (mod_table): New instructions (see prefix above). |
| 1902 | (OP_G): Handle va_mode. |
| 1903 | * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, |
| 1904 | CPU_MOVDIR64B_FLAGS. |
| 1905 | (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. |
| 1906 | * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. |
| 1907 | (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. |
| 1908 | * i386-opc.tbl: Add movidir{i,64b}. |
| 1909 | * i386-init.h: Regenerated. |
| 1910 | * i386-tbl.h: Likewise. |
| 1911 | |
| 1912 | 2018-05-07 H.J. Lu <hongjiu.lu@intel.com> |
| 1913 | |
| 1914 | * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with |
| 1915 | AddrPrefixOpReg. |
| 1916 | * i386-opc.h (AddrPrefixOp0): Renamed to ... |
| 1917 | (AddrPrefixOpReg): This. |
| 1918 | (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg. |
| 1919 | * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg. |
| 1920 | |
| 1921 | 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com> |
| 1922 | |
| 1923 | * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned. |
| 1924 | (vle_num_opcodes): Likewise. |
| 1925 | (spe2_num_opcodes): Likewise. |
| 1926 | * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite |
| 1927 | initialization loop. |
| 1928 | (disassemble_init_powerpc) <vle_opcd_indices>: Likewise. |
| 1929 | (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize |
| 1930 | only once. |
| 1931 | |
| 1932 | 2018-05-01 Tamar Christina <tamar.christina@arm.com> |
| 1933 | |
| 1934 | * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code. |
| 1935 | |
| 1936 | 2018-04-30 Francois H. Theron <francois.theron@netronome.com> |
| 1937 | |
| 1938 | Makefile.am: Added nfp-dis.c. |
| 1939 | configure.ac: Added bfd_nfp_arch. |
| 1940 | disassemble.h: Added print_insn_nfp prototype. |
| 1941 | disassemble.c: Added ARCH_nfp and call to print_insn_nfp |
| 1942 | nfp-dis.c: New, for NFP support. |
| 1943 | po/POTFILES.in: Added nfp-dis.c to the list. |
| 1944 | Makefile.in: Regenerate. |
| 1945 | configure: Regenerate. |
| 1946 | |
| 1947 | 2018-04-26 Jan Beulich <jbeulich@suse.com> |
| 1948 | |
| 1949 | * i386-opc.tbl: Fold various non-memory operand AVX512VL |
| 1950 | templates into their base ones. |
| 1951 | * i386-tlb.h: Re-generate. |
| 1952 | |
| 1953 | 2018-04-26 Jan Beulich <jbeulich@suse.com> |
| 1954 | |
| 1955 | * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for |
| 1956 | CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use |
| 1957 | CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to |
| 1958 | CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS. |
| 1959 | * i386-init.h: Re-generate. |
| 1960 | |
| 1961 | 2018-04-26 Jan Beulich <jbeulich@suse.com> |
| 1962 | |
| 1963 | * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX, |
| 1964 | CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use |
| 1965 | CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment. |
| 1966 | Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus |
| 1967 | comment. |
| 1968 | (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM, |
| 1969 | and CpuRegMask. |
| 1970 | * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM, |
| 1971 | CpuRegMask: Delete. |
| 1972 | (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm, |
| 1973 | cpuregzmm, and cpuregmask. |
| 1974 | * i386-init.h: Re-generate. |
| 1975 | * i386-tbl.h: Re-generate. |
| 1976 | |
| 1977 | 2018-04-26 Jan Beulich <jbeulich@suse.com> |
| 1978 | |
| 1979 | * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only. |
| 1980 | CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only. |
| 1981 | * i386-init.h: Re-generate. |
| 1982 | |
| 1983 | 2018-04-26 Jan Beulich <jbeulich@suse.com> |
| 1984 | |
| 1985 | * i386-gen.c (VexImmExt): Delete. |
| 1986 | * i386-opc.h (VexImmExt, veximmext): Delete. |
| 1987 | * i386-opc.tbl: Drop all VexImmExt uses. |
| 1988 | * i386-tlb.h: Re-generate. |
| 1989 | |
| 1990 | 2018-04-25 Jan Beulich <jbeulich@suse.com> |
| 1991 | |
| 1992 | * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL |
| 1993 | register-only forms. |
| 1994 | * i386-tlb.h: Re-generate. |
| 1995 | |
| 1996 | 2018-04-25 Tamar Christina <tamar.christina@arm.com> |
| 1997 | |
| 1998 | * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks. |
| 1999 | |
| 2000 | 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2001 | |
| 2002 | * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, |
| 2003 | PREFIX_0F1C. |
| 2004 | * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, |
| 2005 | (cpu_flags): Add CpuCLDEMOTE. |
| 2006 | * i386-init.h: Regenerate. |
| 2007 | * i386-opc.h (enum): Add CpuCLDEMOTE, |
| 2008 | (i386_cpu_flags): Add cpucldemote. |
| 2009 | * i386-opc.tbl: Add cldemote. |
| 2010 | * i386-tbl.h: Regenerate. |
| 2011 | |
| 2012 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2013 | |
| 2014 | * Makefile.am: Remove sh5 and sh64 support. |
| 2015 | * configure.ac: Likewise. |
| 2016 | * disassemble.c: Likewise. |
| 2017 | * disassemble.h: Likewise. |
| 2018 | * sh-dis.c: Likewise. |
| 2019 | * sh64-dis.c: Delete. |
| 2020 | * sh64-opc.c: Delete. |
| 2021 | * sh64-opc.h: Delete. |
| 2022 | * Makefile.in: Regenerate. |
| 2023 | * configure: Regenerate. |
| 2024 | * po/POTFILES.in: Regenerate. |
| 2025 | |
| 2026 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2027 | |
| 2028 | * Makefile.am: Remove w65 support. |
| 2029 | * configure.ac: Likewise. |
| 2030 | * disassemble.c: Likewise. |
| 2031 | * disassemble.h: Likewise. |
| 2032 | * w65-dis.c: Delete. |
| 2033 | * w65-opc.h: Delete. |
| 2034 | * Makefile.in: Regenerate. |
| 2035 | * configure: Regenerate. |
| 2036 | * po/POTFILES.in: Regenerate. |
| 2037 | |
| 2038 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2039 | |
| 2040 | * configure.ac: Remove we32k support. |
| 2041 | * configure: Regenerate. |
| 2042 | |
| 2043 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2044 | |
| 2045 | * Makefile.am: Remove m88k support. |
| 2046 | * configure.ac: Likewise. |
| 2047 | * disassemble.c: Likewise. |
| 2048 | * disassemble.h: Likewise. |
| 2049 | * m88k-dis.c: Delete. |
| 2050 | * Makefile.in: Regenerate. |
| 2051 | * configure: Regenerate. |
| 2052 | * po/POTFILES.in: Regenerate. |
| 2053 | |
| 2054 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2055 | |
| 2056 | * Makefile.am: Remove i370 support. |
| 2057 | * configure.ac: Likewise. |
| 2058 | * disassemble.c: Likewise. |
| 2059 | * disassemble.h: Likewise. |
| 2060 | * i370-dis.c: Delete. |
| 2061 | * i370-opc.c: Delete. |
| 2062 | * Makefile.in: Regenerate. |
| 2063 | * configure: Regenerate. |
| 2064 | * po/POTFILES.in: Regenerate. |
| 2065 | |
| 2066 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2067 | |
| 2068 | * Makefile.am: Remove h8500 support. |
| 2069 | * configure.ac: Likewise. |
| 2070 | * disassemble.c: Likewise. |
| 2071 | * disassemble.h: Likewise. |
| 2072 | * h8500-dis.c: Delete. |
| 2073 | * h8500-opc.h: Delete. |
| 2074 | * Makefile.in: Regenerate. |
| 2075 | * configure: Regenerate. |
| 2076 | * po/POTFILES.in: Regenerate. |
| 2077 | |
| 2078 | 2018-04-16 Alan Modra <amodra@gmail.com> |
| 2079 | |
| 2080 | * configure.ac: Remove tahoe support. |
| 2081 | * configure: Regenerate. |
| 2082 | |
| 2083 | 2018-04-15 H.J. Lu <hongjiu.lu@intel.com> |
| 2084 | |
| 2085 | * i386-dis.c (prefix_table): Replace Em with Edq on tpause and |
| 2086 | umwait. |
| 2087 | * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in |
| 2088 | 64-bit mode. |
| 2089 | * i386-tbl.h: Regenerated. |
| 2090 | |
| 2091 | 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2092 | |
| 2093 | * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6, |
| 2094 | PREFIX_MOD_1_0FAE_REG_6. |
| 2095 | (va_mode): New. |
| 2096 | (OP_E_register): Use va_mode. |
| 2097 | * i386-dis-evex.h (prefix_table): |
| 2098 | New instructions (see prefixes above). |
| 2099 | * i386-gen.c (cpu_flag_init): Add WAITPKG. |
| 2100 | (cpu_flags): Likewise. |
| 2101 | * i386-opc.h (enum): Likewise. |
| 2102 | (i386_cpu_flags): Likewise. |
| 2103 | * i386-opc.tbl: Add umonitor, umwait, tpause. |
| 2104 | * i386-init.h: Regenerate. |
| 2105 | * i386-tbl.h: Likewise. |
| 2106 | |
| 2107 | 2018-04-11 Alan Modra <amodra@gmail.com> |
| 2108 | |
| 2109 | * opcodes/i860-dis.c: Delete. |
| 2110 | * opcodes/i960-dis.c: Delete. |
| 2111 | * Makefile.am: Remove i860 and i960 support. |
| 2112 | * configure.ac: Likewise. |
| 2113 | * disassemble.c: Likewise. |
| 2114 | * disassemble.h: Likewise. |
| 2115 | * Makefile.in: Regenerate. |
| 2116 | * configure: Regenerate. |
| 2117 | * po/POTFILES.in: Regenerate. |
| 2118 | |
| 2119 | 2018-04-04 H.J. Lu <hongjiu.lu@intel.com> |
| 2120 | |
| 2121 | PR binutils/23025 |
| 2122 | * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w |
| 2123 | to 0. |
| 2124 | (print_insn): Clear vex instead of vex.evex. |
| 2125 | |
| 2126 | 2018-04-04 Nick Clifton <nickc@redhat.com> |
| 2127 | |
| 2128 | * po/es.po: Updated Spanish translation. |
| 2129 | |
| 2130 | 2018-03-28 Jan Beulich <jbeulich@suse.com> |
| 2131 | |
| 2132 | * i386-gen.c (opcode_modifiers): Delete VecESize. |
| 2133 | * i386-opc.h (VecESize): Delete. |
| 2134 | (struct i386_opcode_modifier): Delete vecesize. |
| 2135 | * i386-opc.tbl: Drop VecESize. |
| 2136 | * i386-tlb.h: Re-generate. |
| 2137 | |
| 2138 | 2018-03-28 Jan Beulich <jbeulich@suse.com> |
| 2139 | |
| 2140 | * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8, |
| 2141 | BROADCAST_1TO4, BROADCAST_1TO2): Delete. |
| 2142 | (struct i386_opcode_modifier): Shrink broadcast field to 1 bit. |
| 2143 | * i386-opc.tbl: Replace Broadcast=<N> by Broadcast. |
| 2144 | * i386-tlb.h: Re-generate. |
| 2145 | |
| 2146 | 2018-03-28 Jan Beulich <jbeulich@suse.com> |
| 2147 | |
| 2148 | * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi): |
| 2149 | Fold AVX512 forms |
| 2150 | * i386-tlb.h: Re-generate. |
| 2151 | |
| 2152 | 2018-03-28 Jan Beulich <jbeulich@suse.com> |
| 2153 | |
| 2154 | * i386-dis.c (prefix_table): Drop Y for cvt*2si. |
| 2155 | (vex_len_table): Drop Y for vcvt*2si. |
| 2156 | (putop): Replace plain 'Y' handling by abort(). |
| 2157 | |
| 2158 | 2018-03-28 Nick Clifton <nickc@redhat.com> |
| 2159 | |
| 2160 | PR 22988 |
| 2161 | * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx |
| 2162 | instructions with only a base address register. |
| 2163 | * aarch64-opc.c (operand_general_constraint_met_p): Add code to |
| 2164 | handle AARHC64_OPND_SVE_ADDR_R. |
| 2165 | (aarch64_print_operand): Likewise. |
| 2166 | * aarch64-asm-2.c: Regenerate. |
| 2167 | * aarch64_dis-2.c: Regenerate. |
| 2168 | * aarch64-opc-2.c: Regenerate. |
| 2169 | |
| 2170 | 2018-03-22 Jan Beulich <jbeulich@suse.com> |
| 2171 | |
| 2172 | * i386-opc.tbl: Drop VecESize from register only insn forms and |
| 2173 | memory forms not allowing broadcast. |
| 2174 | * i386-tlb.h: Re-generate. |
| 2175 | |
| 2176 | 2018-03-22 Jan Beulich <jbeulich@suse.com> |
| 2177 | |
| 2178 | * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*, |
| 2179 | vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*, |
| 2180 | sha256*): Drop Disp<N>. |
| 2181 | |
| 2182 | 2018-03-22 Jan Beulich <jbeulich@suse.com> |
| 2183 | |
| 2184 | * i386-dis.c (EbndS, bnd_swap_mode): New. |
| 2185 | (prefix_table): Use EbndS. |
| 2186 | (OP_E_register, OP_E_memory): Also handle bnd_swap_mode. |
| 2187 | * i386-opc.tbl (bndmov): Move misplaced Load. |
| 2188 | * i386-tlb.h: Re-generate. |
| 2189 | |
| 2190 | 2018-03-22 Jan Beulich <jbeulich@suse.com> |
| 2191 | |
| 2192 | * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate |
| 2193 | templates allowing memory operands and folded ones for register |
| 2194 | only flavors. |
| 2195 | * i386-tlb.h: Re-generate. |
| 2196 | |
| 2197 | 2018-03-22 Jan Beulich <jbeulich@suse.com> |
| 2198 | |
| 2199 | * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and |
| 2200 | 256-bit templates. Drop redundant leftover Disp<N>. |
| 2201 | * i386-tlb.h: Re-generate. |
| 2202 | |
| 2203 | 2018-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 2204 | |
| 2205 | * riscv-opc.c (riscv_insn_types): New. |
| 2206 | |
| 2207 | 2018-03-13 Nick Clifton <nickc@redhat.com> |
| 2208 | |
| 2209 | * po/pt_BR.po: Updated Brazilian Portuguese translation. |
| 2210 | |
| 2211 | 2018-03-08 H.J. Lu <hongjiu.lu@intel.com> |
| 2212 | |
| 2213 | * i386-opc.tbl: Add Optimize to clr. |
| 2214 | * i386-tbl.h: Regenerated. |
| 2215 | |
| 2216 | 2018-03-08 H.J. Lu <hongjiu.lu@intel.com> |
| 2217 | |
| 2218 | * i386-gen.c (opcode_modifiers): Remove OldGcc. |
| 2219 | * i386-opc.h (OldGcc): Removed. |
| 2220 | (i386_opcode_modifier): Remove oldgcc. |
| 2221 | * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp |
| 2222 | instructions for old (<= 2.8.1) versions of gcc. |
| 2223 | * i386-tbl.h: Regenerated. |
| 2224 | |
| 2225 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2226 | |
| 2227 | * i386-opc.h (EVEXDYN): New. |
| 2228 | * i386-opc.tbl: Fold various AVX512VL templates. |
| 2229 | * i386-tlb.h: Re-generate. |
| 2230 | |
| 2231 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2232 | |
| 2233 | * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps, |
| 2234 | vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups, |
| 2235 | vpexpandd, vpexpandq): Fold AFX512VF templates. |
| 2236 | * i386-tlb.h: Re-generate. |
| 2237 | |
| 2238 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2239 | |
| 2240 | * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb): |
| 2241 | Fold 128- and 256-bit VEX-encoded templates. |
| 2242 | * i386-tlb.h: Re-generate. |
| 2243 | |
| 2244 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2245 | |
| 2246 | * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps, |
| 2247 | vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups, |
| 2248 | vpexpandd, vpexpandq): Fold AVX512F templates. |
| 2249 | * i386-tlb.h: Re-generate. |
| 2250 | |
| 2251 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2252 | |
| 2253 | * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and |
| 2254 | 64-bit templates. Drop Disp<N>. |
| 2255 | * i386-tlb.h: Re-generate. |
| 2256 | |
| 2257 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2258 | |
| 2259 | * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128- |
| 2260 | and 256-bit templates. |
| 2261 | * i386-tlb.h: Re-generate. |
| 2262 | |
| 2263 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2264 | |
| 2265 | * i386-opc.tbl (cmpxchg8b): Add NoRex64. |
| 2266 | * i386-tlb.h: Re-generate. |
| 2267 | |
| 2268 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2269 | |
| 2270 | * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx): |
| 2271 | Drop NoAVX. |
| 2272 | * i386-tlb.h: Re-generate. |
| 2273 | |
| 2274 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2275 | |
| 2276 | * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX. |
| 2277 | * i386-tlb.h: Re-generate. |
| 2278 | |
| 2279 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2280 | |
| 2281 | * i386-gen.c (opcode_modifiers): Delete FloatD. |
| 2282 | * i386-opc.h (FloatD): Delete. |
| 2283 | (struct i386_opcode_modifier): Delete floatd. |
| 2284 | * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace |
| 2285 | FloatD by D. |
| 2286 | * i386-tlb.h: Re-generate. |
| 2287 | |
| 2288 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2289 | |
| 2290 | * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns. |
| 2291 | |
| 2292 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2293 | |
| 2294 | * i386-opc.tbl (vmovd): Disallow Qword memory operands. |
| 2295 | * i386-tlb.h: Re-generate. |
| 2296 | |
| 2297 | 2018-03-08 Jan Beulich <jbeulich@suse.com> |
| 2298 | |
| 2299 | * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory |
| 2300 | forms. |
| 2301 | * i386-tlb.h: Re-generate. |
| 2302 | |
| 2303 | 2018-03-07 Alan Modra <amodra@gmail.com> |
| 2304 | |
| 2305 | * disassemble.c (disassembler): Use bfd_arch_powerpc entry for |
| 2306 | bfd_arch_rs6000. |
| 2307 | * disassemble.h (print_insn_rs6000): Delete. |
| 2308 | * ppc-dis.c (powerpc_init_dialect): Handle rs6000. |
| 2309 | (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. |
| 2310 | (print_insn_rs6000): Delete. |
| 2311 | |
| 2312 | 2018-03-03 Alan Modra <amodra@gmail.com> |
| 2313 | |
| 2314 | * sysdep.h (opcodes_error_handler): Define. |
| 2315 | (_bfd_error_handler): Declare. |
| 2316 | * Makefile.am: Remove stray #. |
| 2317 | * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT |
| 2318 | EDIT" comment. |
| 2319 | * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, |
| 2320 | * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, |
| 2321 | * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use |
| 2322 | opcodes_error_handler to print errors. Standardize error messages. |
| 2323 | * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, |
| 2324 | and include opintl.h. |
| 2325 | * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. |
| 2326 | * i386-gen.c: Standardize error messages. |
| 2327 | * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. |
| 2328 | * Makefile.in: Regenerate. |
| 2329 | * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, |
| 2330 | * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, |
| 2331 | * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, |
| 2332 | * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, |
| 2333 | * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, |
| 2334 | * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, |
| 2335 | * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, |
| 2336 | * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, |
| 2337 | * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, |
| 2338 | * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, |
| 2339 | * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, |
| 2340 | * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, |
| 2341 | * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate. |
| 2342 | |
| 2343 | 2018-03-01 H.J. Lu <hongjiu.lu@intel.com> |
| 2344 | |
| 2345 | * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 |
| 2346 | vpsub[bwdq] instructions. |
| 2347 | * i386-tbl.h: Regenerated. |
| 2348 | |
| 2349 | 2018-03-01 Alan Modra <amodra@gmail.com> |
| 2350 | |
| 2351 | * configure.ac (ALL_LINGUAS): Sort. |
| 2352 | * configure: Regenerate. |
| 2353 | |
| 2354 | 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 2355 | |
| 2356 | * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY |
| 2357 | macro by assignements. |
| 2358 | |
| 2359 | 2018-02-27 H.J. Lu <hongjiu.lu@intel.com> |
| 2360 | |
| 2361 | PR gas/22871 |
| 2362 | * i386-gen.c (opcode_modifiers): Add Optimize. |
| 2363 | * i386-opc.h (Optimize): New enum. |
| 2364 | (i386_opcode_modifier): Add optimize. |
| 2365 | * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", |
| 2366 | "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", |
| 2367 | "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", |
| 2368 | "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, |
| 2369 | vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, |
| 2370 | vpxord and vpxorq. |
| 2371 | * i386-tbl.h: Regenerated. |
| 2372 | |
| 2373 | 2018-02-26 Alan Modra <amodra@gmail.com> |
| 2374 | |
| 2375 | * crx-dis.c (getregliststring): Allocate a large enough buffer |
| 2376 | to silence false positive gcc8 warning. |
| 2377 | |
| 2378 | 2018-02-22 Shea Levy <shea@shealevy.com> |
| 2379 | |
| 2380 | * disassemble.c (ARCH_riscv): Define if ARCH_all. |
| 2381 | |
| 2382 | 2018-02-22 H.J. Lu <hongjiu.lu@intel.com> |
| 2383 | |
| 2384 | * i386-opc.tbl: Add {rex}, |
| 2385 | * i386-tbl.h: Regenerated. |
| 2386 | |
| 2387 | 2018-02-20 Maciej W. Rozycki <macro@mips.com> |
| 2388 | |
| 2389 | * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. |
| 2390 | (mips16_opcodes): Replace `M' with `m' for "restore". |
| 2391 | |
| 2392 | 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 2393 | |
| 2394 | * arm-dis.c (thumb_opcodes): Fix BXNS mask. |
| 2395 | |
| 2396 | 2018-02-13 Maciej W. Rozycki <macro@mips.com> |
| 2397 | |
| 2398 | * wasm32-dis.c (print_insn_wasm32): Rename `index' local |
| 2399 | variable to `function_index'. |
| 2400 | |
| 2401 | 2018-02-13 Nick Clifton <nickc@redhat.com> |
| 2402 | |
| 2403 | PR 22823 |
| 2404 | * metag-dis.c (print_fmmov): Double buffer size to avoid warning |
| 2405 | about truncation of printing. |
| 2406 | |
| 2407 | 2018-02-12 Henry Wong <henry@stuffedcow.net> |
| 2408 | |
| 2409 | * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. |
| 2410 | |
| 2411 | 2018-02-05 Nick Clifton <nickc@redhat.com> |
| 2412 | |
| 2413 | * po/pt_BR.po: Updated Brazilian Portuguese translation. |
| 2414 | |
| 2415 | 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2416 | |
| 2417 | * i386-dis.c (enum): Add pconfig. |
| 2418 | * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. |
| 2419 | (cpu_flags): Add CpuPCONFIG. |
| 2420 | * i386-opc.h (enum): Add CpuPCONFIG. |
| 2421 | (i386_cpu_flags): Add cpupconfig. |
| 2422 | * i386-opc.tbl: Add PCONFIG instruction. |
| 2423 | * i386-init.h: Regenerate. |
| 2424 | * i386-tbl.h: Likewise. |
| 2425 | |
| 2426 | 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2427 | |
| 2428 | * i386-dis.c (enum): Add PREFIX_0F09. |
| 2429 | * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. |
| 2430 | (cpu_flags): Add CpuWBNOINVD. |
| 2431 | * i386-opc.h (enum): Add CpuWBNOINVD. |
| 2432 | (i386_cpu_flags): Add cpuwbnoinvd. |
| 2433 | * i386-opc.tbl: Add WBNOINVD instruction. |
| 2434 | * i386-init.h: Regenerate. |
| 2435 | * i386-tbl.h: Likewise. |
| 2436 | |
| 2437 | 2018-01-17 Jim Wilson <jimw@sifive.com> |
| 2438 | |
| 2439 | * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0. |
| 2440 | |
| 2441 | 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2442 | |
| 2443 | * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. |
| 2444 | Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, |
| 2445 | CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. |
| 2446 | (cpu_flags): Add CpuIBT, CpuSHSTK. |
| 2447 | * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. |
| 2448 | (i386_cpu_flags): Add cpuibt, cpushstk. |
| 2449 | * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. |
| 2450 | * i386-init.h: Regenerate. |
| 2451 | * i386-tbl.h: Likewise. |
| 2452 | |
| 2453 | 2018-01-16 Nick Clifton <nickc@redhat.com> |
| 2454 | |
| 2455 | * po/pt_BR.po: Updated Brazilian Portugese translation. |
| 2456 | * po/de.po: Updated German translation. |
| 2457 | |
| 2458 | 2018-01-15 Jim Wilson <jimw@sifive.com> |
| 2459 | |
| 2460 | * riscv-opc.c (match_c_nop): New. |
| 2461 | (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop. |
| 2462 | |
| 2463 | 2018-01-15 Nick Clifton <nickc@redhat.com> |
| 2464 | |
| 2465 | * po/uk.po: Updated Ukranian translation. |
| 2466 | |
| 2467 | 2018-01-13 Nick Clifton <nickc@redhat.com> |
| 2468 | |
| 2469 | * po/opcodes.pot: Regenerated. |
| 2470 | |
| 2471 | 2018-01-13 Nick Clifton <nickc@redhat.com> |
| 2472 | |
| 2473 | * configure: Regenerate. |
| 2474 | |
| 2475 | 2018-01-13 Nick Clifton <nickc@redhat.com> |
| 2476 | |
| 2477 | 2.30 branch created. |
| 2478 | |
| 2479 | 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2480 | |
| 2481 | * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. |
| 2482 | * i386-tbl.h: Regenerate. |
| 2483 | |
| 2484 | 2018-01-10 Jan Beulich <jbeulich@suse.com> |
| 2485 | |
| 2486 | * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift. |
| 2487 | * i386-tbl.h: Re-generate. |
| 2488 | |
| 2489 | 2018-01-10 Jan Beulich <jbeulich@suse.com> |
| 2490 | |
| 2491 | * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, |
| 2492 | vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub, |
| 2493 | vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew, |
| 2494 | vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw, |
| 2495 | vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust |
| 2496 | Disp8MemShift of AVX512VL forms. |
| 2497 | * i386-tbl.h: Re-generate. |
| 2498 | |
| 2499 | 2018-01-09 Jim Wilson <jimw@sifive.com> |
| 2500 | |
| 2501 | * riscv-dis.c (maybe_print_address): If base_reg is zero, |
| 2502 | then the hi_addr value is zero. |
| 2503 | |
| 2504 | 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> |
| 2505 | |
| 2506 | * arm-dis.c (arm_opcodes): Add csdb. |
| 2507 | (thumb32_opcodes): Add csdb. |
| 2508 | |
| 2509 | 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> |
| 2510 | |
| 2511 | * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". |
| 2512 | * aarch64-asm-2.c: Regenerate. |
| 2513 | * aarch64-dis-2.c: Regenerate. |
| 2514 | * aarch64-opc-2.c: Regenerate. |
| 2515 | |
| 2516 | 2018-01-08 H.J. Lu <hongjiu.lu@intel.com> |
| 2517 | |
| 2518 | PR gas/22681 |
| 2519 | * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. |
| 2520 | Remove AVX512 vmovd with 64-bit operands. |
| 2521 | * i386-tbl.h: Regenerated. |
| 2522 | |
| 2523 | 2018-01-05 Jim Wilson <jimw@sifive.com> |
| 2524 | |
| 2525 | * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a |
| 2526 | jalr. |
| 2527 | |
| 2528 | 2018-01-03 Alan Modra <amodra@gmail.com> |
| 2529 | |
| 2530 | Update year range in copyright notice of all files. |
| 2531 | |
| 2532 | 2018-01-02 Jan Beulich <jbeulich@suse.com> |
| 2533 | |
| 2534 | * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM |
| 2535 | and OPERAND_TYPE_REGZMM entries. |
| 2536 | |
| 2537 | For older changes see ChangeLog-2017 |
| 2538 | \f |
| 2539 | Copyright (C) 2018 Free Software Foundation, Inc. |
| 2540 | |
| 2541 | Copying and distribution of this file, with or without modification, |
| 2542 | are permitted in any medium without royalty provided the copyright |
| 2543 | notice and this notice are preserved. |
| 2544 | |
| 2545 | Local Variables: |
| 2546 | mode: change-log |
| 2547 | left-margin: 8 |
| 2548 | fill-column: 74 |
| 2549 | version-control: never |
| 2550 | End: |