| 1 | /**** Bit Manipulation Instructions ****/ |
| 2 | |
| 3 | /* movl<.cl> */ |
| 4 | { "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, |
| 5 | { "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, |
| 6 | |
| 7 | /* movl<.cl> */ |
| 8 | { "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, |
| 9 | { "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, |
| 10 | |
| 11 | /* movb<.f><.cl> */ |
| 12 | { "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 13 | { "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, |
| 14 | |
| 15 | /* movbi<.f><.cl> */ |
| 16 | { "movbi", 0x480f0000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B }, { C_NPS_F }}, |
| 17 | { "movbi", 0x480f8000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B }, { C_NPS_F, C_NPS_CL }}, |
| 18 | |
| 19 | /* decode1<.f> */ |
| 20 | { "decode1", 0x48038040, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 21 | |
| 22 | /* decode1.cl<.f> */ |
| 23 | { "decode1", 0x48038060, 0xf80803e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS_SZ }, { C_NPS_CL, C_NPS_F }}, |
| 24 | |
| 25 | /* fbset<.f> */ |
| 26 | { "fbset", 0x48038000, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 27 | |
| 28 | /* fbclr<.f> */ |
| 29 | { "fbclr", 0x48030000, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 30 | |
| 31 | /* encode0<.f> */ |
| 32 | { "encode0", 0x48040000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 33 | |
| 34 | /* encode1<.f> */ |
| 35 | { "encode1", 0x48048000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 36 | |
| 37 | /* rflt a,b,c 00111bbb00101110FBBBCCCCCCAAAAAA */ |
| 38 | { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { 0 }}, |
| 39 | |
| 40 | /* rflt a,limm,c 0011111000101110F111CCCCCCAAAAAA */ |
| 41 | { "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { 0 }}, |
| 42 | |
| 43 | /* rflt 0,b,c 00111bbb00101110FBBBCCCCCC111110 */ |
| 44 | { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { 0 }}, |
| 45 | |
| 46 | /* rflt 0,limm,c 0011111000101110F111CCCCCC111110 */ |
| 47 | { "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { 0 }}, |
| 48 | |
| 49 | /* rflt a,b,u6 00111bbb01101110FBBBuuuuuuAAAAAA */ |
| 50 | { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, |
| 51 | |
| 52 | /* rflt a,limm,u6 0011111001101110F111uuuuuuAAAAAA */ |
| 53 | { "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, |
| 54 | |
| 55 | /* rflt 0,b,u6 00111bbb01101110FBBBuuuuuu111110 */ |
| 56 | { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, |
| 57 | |
| 58 | /* rflt 0,limm,u6 0011111001101110F111uuuuuu111110 */ |
| 59 | { "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, |
| 60 | |
| 61 | /* crc16<.r> a,b,c 00111bbb00110011RBBBCCCCCCAAAAAA */ |
| 62 | { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { C_NPS_R }}, |
| 63 | |
| 64 | /* crc16<.r> a,limm,c 0011111000110011R111CCCCCCAAAAAA */ |
| 65 | { "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { C_NPS_R }}, |
| 66 | |
| 67 | /* crc16<.r> a,b,u6 00111bbb01110011RBBBuuuuuuAAAAAA */ |
| 68 | { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 69 | |
| 70 | /* crc16<.r> 0,b,c 00111bbb00110011RBBBCCCCCC111110 */ |
| 71 | { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { C_NPS_R }}, |
| 72 | |
| 73 | /* crc16<.r> 0,limm,c 0011111000110011R111CCCCCC111110 */ |
| 74 | { "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { C_NPS_R }}, |
| 75 | |
| 76 | /* crc16<.r> 0,b,u6 00111bbb01110011RBBBuuuuuu111110 */ |
| 77 | { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 78 | |
| 79 | /* crc16<.r> 0,b,limm 00111bbb00110011RBBB111110111110 */ |
| 80 | { "crc16", 0x38330fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { C_NPS_R }}, |
| 81 | |
| 82 | /* crc16<.r> a,b,limm 00111bbb00110011RBBB111110AAAAAA */ |
| 83 | { "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { C_NPS_R }}, |
| 84 | |
| 85 | /* crc16<.r> a,limm,limm 0011111000110011R111111110AAAAAA */ |
| 86 | { "crc16", 0x3e337f80, 0xffff7fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { C_NPS_R }}, |
| 87 | |
| 88 | /* crc16<.r> a,limm,u6 0011111001110011R111uuuuuuAAAAAA */ |
| 89 | { "crc16", 0x3e737000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 90 | |
| 91 | /* crc16<.r> 0,limm,u6 0011111001110011R111uuuuuu111110 */ |
| 92 | { "crc16", 0x3e73703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 93 | |
| 94 | /* crc32<.r> a,b,c 00111 bbb 00 110100 R BBB CCCCCC AAAAAA */ |
| 95 | { "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { C_NPS_R }}, |
| 96 | |
| 97 | /* crc32<.r> a,limm,c 00111 110 00 110100 R 111 CCCCCC AAAAAA */ |
| 98 | { "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { C_NPS_R }}, |
| 99 | |
| 100 | /* crc32<.r> a,b,u6 00111 bbb 01 110100 R BBB uuuuuu AAAAAA */ |
| 101 | { "crc32", 0x38740000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 102 | |
| 103 | /* crc32<.r> 0,b,c 00111 bbb 00 110100 R BBB CCCCCC 111110 */ |
| 104 | { "crc32", 0x3834003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { C_NPS_R }}, |
| 105 | |
| 106 | /* crc32<.r> 0,limm,c 00111 110 00 110100 R 111 CCCCCC 111110 */ |
| 107 | { "crc32", 0x3e34703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { C_NPS_R }}, |
| 108 | |
| 109 | /* crc32<.r> 0,b,u6 00111 bbb 01 110100 R BBB uuuuuu 111110 */ |
| 110 | { "crc32", 0x3874003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 111 | |
| 112 | /* crc32<.r> 0,b,limm 00111 bbb 00 110100 R BBB 111110 111110 */ |
| 113 | { "crc32", 0x38340fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { C_NPS_R }}, |
| 114 | |
| 115 | /* crc32<.r> a,b,limm 00111 bbb 00 110100 R BBB 111110 AAAAAA */ |
| 116 | { "crc32", 0x38340f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { C_NPS_R }}, |
| 117 | |
| 118 | /* crc32<.r> a,limm,limm 00111 110 00 110100 R 111 111110 AAAAAA */ |
| 119 | { "crc32", 0x3e347f80, 0xffff7fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { C_NPS_R }}, |
| 120 | |
| 121 | /* crc32<.r> a,limm,u6 00111 110 01 110100 R 111 uuuuuu AAAAAA */ |
| 122 | { "crc32", 0x3e747000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 123 | |
| 124 | /* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */ |
| 125 | { "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 126 | |
| 127 | /**** Arithmetic & Logic Instructions ****/ |
| 128 | |
| 129 | #define ADDB_LIKE(NAME,SUBOP2) \ |
| 130 | { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, NPS_ADDB_SIZE }, { C_NPS_F, C_NPS_SX }}, |
| 131 | |
| 132 | ADDB_LIKE ("addb", 0) |
| 133 | ADDB_LIKE ("subb", 4) |
| 134 | ADDB_LIKE ("adcb", 5) |
| 135 | ADDB_LIKE ("sbcb", 6) |
| 136 | |
| 137 | #define ANDB_LIKE(NAME,SUBOP2,SIZE_OPERAND) \ |
| 138 | { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, SIZE_OPERAND }, { C_NPS_F }}, |
| 139 | |
| 140 | ANDB_LIKE ("andb", 1, NPS_ANDB_SIZE) |
| 141 | ANDB_LIKE ("xorb", 2, NPS_ANDB_SIZE) |
| 142 | ANDB_LIKE ("orb", 3, NPS_ANDB_SIZE) |
| 143 | ANDB_LIKE ("fxorb", 7, NPS_FXORB_SIZE) |
| 144 | ANDB_LIKE ("wxorb", 8, NPS_WXORB_SIZE) |
| 145 | ANDB_LIKE ("shlb", 0xb, NPS_ANDB_SIZE) |
| 146 | ANDB_LIKE ("shrb", 0xc, NPS_ANDB_SIZE) |
| 147 | |
| 148 | #define NOTB_LIKE(NAME,SUBOP2) \ |
| 149 | { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_ANDB_SIZE }, { C_NPS_F }}, |
| 150 | |
| 151 | NOTB_LIKE ("notb", 0x9) |
| 152 | NOTB_LIKE ("cntbb", 0xa) |
| 153 | |
| 154 | #define DIV_LIKE(NAME,DIV_MODE) \ |
| 155 | { NAME, (0x4800000d | DIV_MODE << 14), 0xf80fc3ff, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, }, { C_NPS_F }}, \ |
| 156 | { NAME, (0x4800020d | DIV_MODE << 14), 0xf8efc21f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_DIV_UIMM4, NPS_SRC1_POS }, { C_NPS_F }}, |
| 157 | |
| 158 | DIV_LIKE ("div", 0x1) |
| 159 | DIV_LIKE ("mod", 0x2) |
| 160 | DIV_LIKE ("divm", 0x0) |
| 161 | |
| 162 | { "qcmp", 0x4810000e, 0xf81f001e, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, NPS_QCMP_M3 }, { C_NPS_AR_AL }}, |
| 163 | { "qcmp", 0x481001ee, 0xf81f01fe, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2 }, { C_NPS_AR_AL }}, |
| 164 | { "qcmp", 0x481001ee, 0xf81f81fe, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1 }, { C_NPS_AR_AL }}, |
| 165 | { "qcmp", 0x481001ee, 0xf81fc1fe, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE }, { C_NPS_AR_AL }}, |
| 166 | |
| 167 | { "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }}, |
| 168 | { "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }}, |
| 169 | |
| 170 | /**** Protocol Decoder Instructions ****/ |
| 171 | |
| 172 | /* dctcp b,c 00111bbb001011110bbbcccccc000000 */ |
| 173 | { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }}, |
| 174 | |
| 175 | /* dcip a,b,c 00111bbb001011110bbbccccccaaaaaa */ |
| 176 | { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }}, |
| 177 | |
| 178 | /* dcet b,c 00111bbb001011110bbbcccccc000010 */ |
| 179 | { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }}, |
| 180 | |
| 181 | /* dcet a,b,c 00111bbb001000000bbbccccccaaaaaa */ |
| 182 | { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }}, |
| 183 | |
| 184 | /**** ACL Instructions ****/ |
| 185 | |
| 186 | /* dcacl<.f> a,b,c 00111bbb001001010bbbccccccaaaaaa */ |
| 187 | { "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_NPS400, ACL, NONE, { RA, RB, RC }, { C_F }}, |
| 188 | |
| 189 | /**** Pipeline Control Instructions ****/ |
| 190 | |
| 191 | /* schd<.rw|.rd> */ |
| 192 | { "schd", 0x3e6f7004, 0xffffff7f, ARC_OPCODE_NPS400, CONTROL, NONE, { 0 }, { C_NPS_SCHD_RW }}, |
| 193 | |
| 194 | /* schd.wft.<.ie1|.ie2|.ie12> */ |
| 195 | { "schd", 0x3e6f7044, 0xfffffcff, ARC_OPCODE_NPS400, CONTROL, NONE, { 0 }, { C_NPS_SCHD_TRIG, C_NPS_SCHD_IE }}, |
| 196 | |
| 197 | /* sync<.rd|.wr> */ |
| 198 | { "sync", 0x3e6f703f, 0xffffffbf, ARC_OPCODE_NPS400, CONTROL, NONE, { 0 }, { C_NPS_SYNC }}, |
| 199 | |
| 200 | /* hwscd.off B */ |
| 201 | { "hwschd", 0x386f00bf, 0xf8ff8fff, ARC_OPCODE_NPS400, CONTROL, NONE, { RB }, { C_NPS_HWS_OFF }}, |
| 202 | |
| 203 | /* hwscd.restore 0,C */ |
| 204 | { "hwschd", 0x3e6f7003, 0xfffff03f, ARC_OPCODE_NPS400, CONTROL, NONE, { ZA, RC }, { C_NPS_HWS_RESTORE }}, |
| 205 | |
| 206 | /**** Load / Store From (0x57f00000 + Offset) Instructions ****/ |
| 207 | |
| 208 | #define XLDST_LIKE(NAME,SUBOP2) \ |
| 209 | { NAME, (0x58000000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_NPS400, MEMORY, NONE, { NPS_R_DST, BRAKET, NPS_XLDST_UIMM16, BRAKETdup }, { 0 }}, |
| 210 | |
| 211 | XLDST_LIKE("xldb", 0x8) |
| 212 | XLDST_LIKE("xldw", 0x9) |
| 213 | XLDST_LIKE("xld", 0xa) |
| 214 | XLDST_LIKE("xstb", 0xc) |
| 215 | XLDST_LIKE("xstw", 0xd) |
| 216 | XLDST_LIKE("xst", 0xe) |