| 1 | /* Bit Manipulation Instructions. */ |
| 2 | |
| 3 | /* movl<.cl> */ |
| 4 | { "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, |
| 5 | { "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, |
| 6 | |
| 7 | /* movl<.cl> */ |
| 8 | { "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, |
| 9 | { "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, |
| 10 | |
| 11 | /* movb<.f><.cl> */ |
| 12 | { "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 13 | { "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, |
| 14 | |
| 15 | /* movbi<.f><.cl> */ |
| 16 | { "movbi", 0x480f0000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B }, { C_NPS_F }}, |
| 17 | { "movbi", 0x480f8000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B }, { C_NPS_F, C_NPS_CL }}, |
| 18 | |
| 19 | /* decode1<.f> */ |
| 20 | { "decode1", 0x48038040, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 21 | |
| 22 | /* decode1.cl<.f> */ |
| 23 | { "decode1", 0x48038060, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS_SZ }, { C_NPS_CL, C_NPS_F }}, |
| 24 | |
| 25 | /* fbset<.f> */ |
| 26 | { "fbset", 0x48038000, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 27 | |
| 28 | /* fbclr<.f> */ |
| 29 | { "fbclr", 0x48030000, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 30 | |
| 31 | /* encode0<.f> */ |
| 32 | { "encode0", 0x48040000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 33 | |
| 34 | /* encode1<.f> */ |
| 35 | { "encode1", 0x48048000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, |
| 36 | |
| 37 | /* mrgb - 48 bit instruction. */ |
| 38 | { "mrgb", 0x580300000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC1_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }, { 0 }}, |
| 39 | |
| 40 | /* mrgb.cl - 48 bit instruction. */ |
| 41 | { "mrgb", 0x580380000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC1_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }, { C_NPS_CL }}, |
| 42 | |
| 43 | /* mov2b - 48 bit instruction. */ |
| 44 | { "mov2b", 0x580000000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC1_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }, { 0 }}, |
| 45 | |
| 46 | /* mov2b.cl - 48 bit instruction. */ |
| 47 | { "mov2b", 0x580080000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }, { C_NPS_CL }}, |
| 48 | |
| 49 | /* ext4 - 48 bit instruction. */ |
| 50 | { "ext4b", 0x580100000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC1_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }, { 0 }}, |
| 51 | |
| 52 | /* ext4.cl - 48 bit instruction. */ |
| 53 | { "ext4b", 0x580180000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }, { C_NPS_CL }}, |
| 54 | |
| 55 | /* ins4 - 48 bit instruction. */ |
| 56 | { "ins4b", 0x580200000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC1_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }, { 0 }}, |
| 57 | |
| 58 | /* ins4.cl - 48 bit instruction. */ |
| 59 | { "ins4b", 0x580280000000, 0xf81f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_48, NPS_R_SRC2_3B_48, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }, { C_NPS_CL }}, |
| 60 | |
| 61 | /* mov3b - 64 bit instruction. */ |
| 62 | { "mov3b", 0x5810000080000000, 0xf81f801f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_64, NPS_R_SRC1_3B_64, NPS_R_SRC2_3B_64, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS3_POS4, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3}, { 0 }}, |
| 63 | |
| 64 | /* mov4b - 64 bit instruction. */ |
| 65 | { "mov4b", 0x5810000000000000, 0xf81f000000000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_64, NPS_R_SRC1_3B_64, NPS_R_SRC2_3B_64, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS3, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4, NPS_BITOP_SRC_POS4}, { 0 }}, |
| 66 | |
| 67 | /* mov3bcl - 64 bit instruction. */ |
| 68 | { "mov3bcl", 0x5811000080000000, 0xf81f801f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_64, NPS_R_SRC2_3B_64, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS3_POS4, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3}, { 0 }}, |
| 69 | |
| 70 | /* mov4bcl - 64 bit instruction. */ |
| 71 | { "mov4bcl", 0x5811000000000000, 0xf81f000000000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_64, NPS_R_SRC2_3B_64, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS3, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4, NPS_BITOP_SRC_POS4 }, { 0 }}, |
| 72 | |
| 73 | /* mov3b.cl - 64 bit instruction. */ |
| 74 | { "mov3b", 0x5811000080000000, 0xf81f801f80000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_64, NPS_R_SRC2_3B_64, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS3_POS4, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }, { C_NPS_CL }}, |
| 75 | |
| 76 | /* mov4b.cl - 64 bit instruction. */ |
| 77 | { "mov4b", 0x5811000000000000, 0xf81f000000000000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_64, NPS_R_SRC2_3B_64, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS3, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4, NPS_BITOP_SRC_POS4}, { C_NPS_CL }}, |
| 78 | |
| 79 | /* rflt a,b,c 00111bbb00101110FBBBCCCCCCAAAAAA */ |
| 80 | { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, |
| 81 | |
| 82 | /* rflt a,limm,c 0011111000101110F111CCCCCCAAAAAA */ |
| 83 | { "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { 0 }}, |
| 84 | |
| 85 | /* rflt a,b,u6 00111bbb01101110FBBBuuuuuuAAAAAA */ |
| 86 | { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, |
| 87 | |
| 88 | /* rflt 0,b,c 00111bbb00101110FBBBCCCCCC111110 */ |
| 89 | { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, |
| 90 | |
| 91 | /* rflt 0,limm,c 0011111000101110F111CCCCCC111110 */ |
| 92 | { "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { 0 }}, |
| 93 | |
| 94 | /* rflt 0,b,u6 00111bbb01101110FBBBuuuuuu111110 */ |
| 95 | { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, |
| 96 | |
| 97 | /* rflt 0,b,limm 00111bbb00101110FBBB111110111110 */ |
| 98 | { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }}, |
| 99 | |
| 100 | /* rflt a,b,limm 00111bbb00101110FBBB111110AAAAAA */ |
| 101 | { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }}, |
| 102 | |
| 103 | /* rflt a,limm,limm 0011111000101110F111111110AAAAAA */ |
| 104 | { "rflt", 0x3e2e7f80, 0xffffffc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { 0 }}, |
| 105 | |
| 106 | /* rflt a,limm,u6 0011111001101110F111uuuuuuAAAAAA */ |
| 107 | { "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, |
| 108 | |
| 109 | /* rflt 0,limm,u6 0011111001101110F111uuuuuu111110 */ |
| 110 | { "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, |
| 111 | |
| 112 | /* crc16<.r> a,b,c 00111bbb00110011RBBBCCCCCCAAAAAA */ |
| 113 | { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }}, |
| 114 | |
| 115 | /* crc16<.r> a,limm,c 0011111000110011R111CCCCCCAAAAAA */ |
| 116 | { "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }}, |
| 117 | |
| 118 | /* crc16<.r> a,b,u6 00111bbb01110011RBBBuuuuuuAAAAAA */ |
| 119 | { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 120 | |
| 121 | /* crc16<.r> 0,b,c 00111bbb00110011RBBBCCCCCC111110 */ |
| 122 | { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }}, |
| 123 | |
| 124 | /* crc16<.r> 0,limm,c 0011111000110011R111CCCCCC111110 */ |
| 125 | { "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }}, |
| 126 | |
| 127 | /* crc16<.r> 0,b,u6 00111bbb01110011RBBBuuuuuu111110 */ |
| 128 | { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 129 | |
| 130 | /* crc16<.r> 0,b,limm 00111bbb00110011RBBB111110111110 */ |
| 131 | { "crc16", 0x38330fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { C_NPS_R }}, |
| 132 | |
| 133 | /* crc16<.r> a,b,limm 00111bbb00110011RBBB111110AAAAAA */ |
| 134 | { "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }}, |
| 135 | |
| 136 | /* crc16<.r> a,limm,limm 0011111000110011R111111110AAAAAA */ |
| 137 | { "crc16", 0x3e337f80, 0xffff7fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_R }}, |
| 138 | |
| 139 | /* crc16<.r> a,limm,u6 0011111001110011R111uuuuuuAAAAAA */ |
| 140 | { "crc16", 0x3e737000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 141 | |
| 142 | /* crc16<.r> 0,limm,u6 0011111001110011R111uuuuuu111110 */ |
| 143 | { "crc16", 0x3e73703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 144 | |
| 145 | /* crc32<.r> a,b,c 00111 bbb 00 110100 R BBB CCCCCC AAAAAA */ |
| 146 | { "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }}, |
| 147 | |
| 148 | /* crc32<.r> a,limm,c 00111 110 00 110100 R 111 CCCCCC AAAAAA */ |
| 149 | { "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }}, |
| 150 | |
| 151 | /* crc32<.r> a,b,u6 00111 bbb 01 110100 R BBB uuuuuu AAAAAA */ |
| 152 | { "crc32", 0x38740000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 153 | |
| 154 | /* crc32<.r> 0,b,c 00111 bbb 00 110100 R BBB CCCCCC 111110 */ |
| 155 | { "crc32", 0x3834003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }}, |
| 156 | |
| 157 | /* crc32<.r> 0,limm,c 00111 110 00 110100 R 111 CCCCCC 111110 */ |
| 158 | { "crc32", 0x3e34703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }}, |
| 159 | |
| 160 | /* crc32<.r> 0,b,u6 00111 bbb 01 110100 R BBB uuuuuu 111110 */ |
| 161 | { "crc32", 0x3874003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }}, |
| 162 | |
| 163 | /* crc32<.r> 0,b,limm 00111 bbb 00 110100 R BBB 111110 111110 */ |
| 164 | { "crc32", 0x38340fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { C_NPS_R }}, |
| 165 | |
| 166 | /* crc32<.r> a,b,limm 00111 bbb 00 110100 R BBB 111110 AAAAAA */ |
| 167 | { "crc32", 0x38340f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }}, |
| 168 | |
| 169 | /* crc32<.r> a,limm,limm 00111 110 00 110100 R 111 111110 AAAAAA */ |
| 170 | { "crc32", 0x3e347f80, 0xffff7fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_R }}, |
| 171 | |
| 172 | /* crc32<.r> a,limm,u6 00111 110 01 110100 R 111 uuuuuu AAAAAA */ |
| 173 | { "crc32", 0x3e747000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 174 | |
| 175 | /* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */ |
| 176 | { "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, |
| 177 | |
| 178 | /* Arithmetic & Logic Instructions. */ |
| 179 | |
| 180 | #define ADDB_LIKE(NAME,SUBOP2) \ |
| 181 | { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, NPS_ADDB_SIZE }, { C_NPS_F, C_NPS_SX }}, |
| 182 | |
| 183 | ADDB_LIKE ("addb", 0) |
| 184 | ADDB_LIKE ("subb", 4) |
| 185 | ADDB_LIKE ("adcb", 5) |
| 186 | ADDB_LIKE ("sbcb", 6) |
| 187 | |
| 188 | #define ANDB_LIKE(NAME,SUBOP2,SIZE_OPERAND) \ |
| 189 | { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, SIZE_OPERAND }, { C_NPS_F }}, |
| 190 | |
| 191 | ANDB_LIKE ("andb", 1, NPS_ANDB_SIZE) |
| 192 | ANDB_LIKE ("xorb", 2, NPS_ANDB_SIZE) |
| 193 | ANDB_LIKE ("orb", 3, NPS_ANDB_SIZE) |
| 194 | ANDB_LIKE ("fxorb", 7, NPS_FXORB_SIZE) |
| 195 | ANDB_LIKE ("wxorb", 8, NPS_WXORB_SIZE) |
| 196 | ANDB_LIKE ("shlb", 0xb, NPS_ANDB_SIZE) |
| 197 | ANDB_LIKE ("shrb", 0xc, NPS_ANDB_SIZE) |
| 198 | |
| 199 | #define NOTB_LIKE(NAME,SUBOP2) \ |
| 200 | { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_ANDB_SIZE }, { C_NPS_F }}, |
| 201 | |
| 202 | NOTB_LIKE ("notb", 0x9) |
| 203 | NOTB_LIKE ("cntbb", 0xa) |
| 204 | |
| 205 | #define DIV_LIKE(NAME,DIV_MODE) \ |
| 206 | { NAME, (0x4800000d | DIV_MODE << 14), 0xf80fc3ff, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, }, { C_NPS_F }}, \ |
| 207 | { NAME, (0x4800020d | DIV_MODE << 14), 0xf8efc21f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_DIV_UIMM4, NPS_SRC1_POS }, { C_NPS_F }}, |
| 208 | |
| 209 | DIV_LIKE ("div", 0x1) |
| 210 | DIV_LIKE ("mod", 0x2) |
| 211 | DIV_LIKE ("divm", 0x0) |
| 212 | |
| 213 | { "qcmp", 0x4810000e, 0xf81f001e, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, NPS_QCMP_M3 }, { C_NPS_AR_AL }}, |
| 214 | { "qcmp", 0x481001ee, 0xf81f01fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2 }, { C_NPS_AR_AL }}, |
| 215 | { "qcmp", 0x481001ee, 0xf81f81fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1 }, { C_NPS_AR_AL }}, |
| 216 | { "qcmp", 0x481001ee, 0xf81fc1fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE }, { C_NPS_AR_AL }}, |
| 217 | |
| 218 | { "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }}, |
| 219 | { "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }}, |
| 220 | |
| 221 | { "calcbsd", 0x48000030, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }}, |
| 222 | { "calcbxd", 0x48004030, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }}, |
| 223 | |
| 224 | { "calckey", 0x48000050, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }}, |
| 225 | { "calcxkey", 0x48004050, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }}, |
| 226 | |
| 227 | { "mxb", 0x580b0000, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }}, |
| 228 | { "mxb", 0x580b8000, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }}, |
| 229 | { "imxb", 0x580b0001, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }}, |
| 230 | { "imxb", 0x580b8001, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }}, |
| 231 | |
| 232 | #define ADDL_LIKE(NAME,SUBOP2,SHIM) \ |
| 233 | { NAME, (0x48000000 | (SUBOP2 << 16)), 0xf80f0000, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST, NPS_R_SRC1, SHIM }, { C_NPS_F }}, |
| 234 | |
| 235 | ADDL_LIKE ("addl", 0xA, NPS_SIMM16) |
| 236 | ADDL_LIKE ("subl", 0xB, NPS_SIMM16) |
| 237 | ADDL_LIKE ("orl", 0xC, NPS_UIMM16) |
| 238 | ADDL_LIKE ("andl", 0xD, NPS_UIMM16) |
| 239 | ADDL_LIKE ("xorl", 0xE, NPS_UIMM16) |
| 240 | |
| 241 | { "andab", 0x48000011, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } }, |
| 242 | { "andab", 0x48008011, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } }, |
| 243 | { "orab", 0x48000012, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } }, |
| 244 | { "orab", 0x48008012, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } }, |
| 245 | |
| 246 | { "lbdsize", 0x382f0005, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { RB, RC }, { C_F }}, |
| 247 | |
| 248 | { "bdlen", 0x48000013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }}, |
| 249 | { "bdlen", 0x48004013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B }, { C_NPS_F }}, |
| 250 | { "bdlen", 0x48008013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }}, |
| 251 | { "bdlen", 0x4800c013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }}, |
| 252 | |
| 253 | /* csma a,b,c 00111bbb00100001FBBBCCCCCCAAAAAA */ |
| 254 | { "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }}, |
| 255 | |
| 256 | /* csma a,limm,c 0011111000100001F111CCCCCCAAAAAA */ |
| 257 | { "csma", 0x3e2a7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { 0 }}, |
| 258 | |
| 259 | /* csma a,b,u6 00111bbb01100001FBBBuuuuuuAAAAAA */ |
| 260 | { "csma", 0x386a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { 0 }}, |
| 261 | |
| 262 | /* csma 0,b,c 00111bbb00100001FBBBCCCCCC111110 */ |
| 263 | { "csma", 0x382a003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { 0 }}, |
| 264 | |
| 265 | /* csma 0,limm,c 0011111000100001F111CCCCCC111110 */ |
| 266 | { "csma", 0x3e2a703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { 0 }}, |
| 267 | |
| 268 | /* csma 0,b,u6 00111bbb01100001FBBBuuuuuu111110 */ |
| 269 | { "csma", 0x386a003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { 0 }}, |
| 270 | |
| 271 | /* csma 0,b,limm 00111bbb00100001FBBB111110111110 */ |
| 272 | { "csma", 0x382a0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { 0 }}, |
| 273 | |
| 274 | /* csma a,b,limm 00111bbb00100001FBBB111110AAAAAA */ |
| 275 | { "csma", 0x382a0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { 0 }}, |
| 276 | |
| 277 | /* csma a,limm,limm 0011111000100001F111111110AAAAAA */ |
| 278 | { "csma", 0x3e2a7f80, 0xffffffc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { 0 }}, |
| 279 | |
| 280 | /* csma a,limm,u6 0011111001100001F111uuuuuuAAAAAA */ |
| 281 | { "csma", 0x3e6a7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { 0 }}, |
| 282 | |
| 283 | /* csma 0,limm,u6 0011111001100001F111uuuuuu111110 */ |
| 284 | { "csma", 0x3e6a703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { 0 }}, |
| 285 | |
| 286 | /* csms a,b,c 00111bbb00101100FBBBCCCCCCAAAAAA */ |
| 287 | { "csms", 0x382c0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }}, |
| 288 | |
| 289 | /* csma a,limm,c 0011111000101100F111CCCCCCAAAAAA */ |
| 290 | { "csms", 0x3e2c7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { 0 }}, |
| 291 | |
| 292 | /* csms a,b,u6 00111bbb01101100FBBBuuuuuuAAAAAA */ |
| 293 | { "csms", 0x386c0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { 0 }}, |
| 294 | |
| 295 | /* csms 0,b,c 00111bbb00101100FBBBCCCCCC111110 */ |
| 296 | { "csms", 0x382c003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { 0 }}, |
| 297 | |
| 298 | /* csms 0,limm,c 0011111000101100F111CCCCCC111110 */ |
| 299 | { "csms", 0x3e2c703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { 0 }}, |
| 300 | |
| 301 | /* csms 0,b,u6 00111bbb01101100FBBBuuuuuu111110 */ |
| 302 | { "csms", 0x386c003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { 0 }}, |
| 303 | |
| 304 | /* csms 0,b,limm 00111bbb00101100FBBB111110111110 */ |
| 305 | { "csms", 0x382c0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { 0 }}, |
| 306 | |
| 307 | /* csms a,b,limm 00111bbb00101100FBBB111110AAAAAA */ |
| 308 | { "csms", 0x382c0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { 0 }}, |
| 309 | |
| 310 | /* csms a,limm,limm 0011111000101100F111111110AAAAAA */ |
| 311 | { "csms", 0x3e2c7f80, 0xffffffc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { 0 }}, |
| 312 | |
| 313 | /* csms a,limm,u6 0011111001101100F111uuuuuuAAAAAA */ |
| 314 | { "csms", 0x3e6c7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { 0 }}, |
| 315 | |
| 316 | /* csms 0,limm,u6 0011111001101100F111uuuuuu111110 */ |
| 317 | { "csms", 0x3e6c703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { 0 }}, |
| 318 | |
| 319 | /* cbba a,b,c 00111bbb00101101FBBBCCCCCCAAAAAA */ |
| 320 | { "cbba", 0x382d0000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_F }}, |
| 321 | |
| 322 | /* cbba a,limm,c 0011111000101101F111CCCCCCAAAAAA */ |
| 323 | { "cbba", 0x3e2d7000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { C_F }}, |
| 324 | |
| 325 | /* cbba a,b,u6 00111bbb01101101FBBBuuuuuuAAAAAA */ |
| 326 | { "cbba", 0x386d0000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { C_F }}, |
| 327 | |
| 328 | /* cbba 0,b,c 00111bbb00101101FBBBCCCCCC111110 */ |
| 329 | { "cbba", 0x382d003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { C_F }}, |
| 330 | |
| 331 | /* cbba 0,limm,c 0011111000101101F111CCCCCC111110 */ |
| 332 | { "cbba", 0x3e2d703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { C_F }}, |
| 333 | |
| 334 | /* cbba 0,b,u6 00111bbb01101101FBBBuuuuuu111110 */ |
| 335 | { "cbba", 0x386d003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { C_F }}, |
| 336 | |
| 337 | /* cbba 0,b,limm 00111bbb00101101FBBB111110111110 */ |
| 338 | { "cbba", 0x382d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { C_F }}, |
| 339 | |
| 340 | /* cbba a,b,limm 00111bbb00101101FBBB111110AAAAAA */ |
| 341 | { "cbba", 0x382d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { C_F }}, |
| 342 | |
| 343 | /* cbba a,limm,limm 0011111000101101F111111110AAAAAA */ |
| 344 | { "cbba", 0x3e2d7f80, 0xffff7fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { C_F }}, |
| 345 | |
| 346 | /* cbba a,limm,u6 0011111001101101F111uuuuuuAAAAAA */ |
| 347 | { "cbba", 0x3e6d7000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }}, |
| 348 | |
| 349 | /* cbba 0,limm,u6 0011111001101101F111uuuuuu111110 */ |
| 350 | { "cbba", 0x3e6d703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }}, |
| 351 | |
| 352 | /* zncv<.rd|.wr> a,b,c 00111bbb001101010BBBCCCCCCAAAAAA */ |
| 353 | { "zncv", 0x38350000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_NPS_ZNCV }}, |
| 354 | |
| 355 | /* zncv<.rd|.wr> a,b,u6 00111bbb011101010BBBuuuuuuAAAAAA */ |
| 356 | { "zncv", 0x38750000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20}, { C_NPS_ZNCV }}, |
| 357 | |
| 358 | /* zncv<.rd|.wr> b,b,s12 00111bbb101101010BBBssssssSSSSSS */ |
| 359 | { "zncv", 0x38b50000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RB, RBdup, SIMM12_20 }, { C_NPS_ZNCV }}, |
| 360 | |
| 361 | /* zncv<.rd|.wr> a,b,limm 00111bbb001101010BBB111110AAAAAA */ |
| 362 | { "zncv", 0x38350f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { C_NPS_ZNCV }}, |
| 363 | |
| 364 | /* zncv<.rd|.wr> a,limm,c 00111110001101010111CCCCCCAAAAAA */ |
| 365 | { "zncv", 0x3e357000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { C_NPS_ZNCV }}, |
| 366 | |
| 367 | /* zncv<.rd|.wr> a,limm,u6 00111110011101010111uuuuuuAAAAAA */ |
| 368 | { "zncv", 0x3e757000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }}, |
| 369 | |
| 370 | /* zncv<.rd|.wr> a,limm,limm 00111110001101010111111110AAAAAA */ |
| 371 | { "zncv", 0x3e357f80, 0xffff7fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_ZNCV }}, |
| 372 | |
| 373 | /* zncv<.rd|.wr> 0,b,c 00111bbb001101010BBBCCCCCC111110 */ |
| 374 | { "zncv", 0x3835003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { C_NPS_ZNCV }}, |
| 375 | |
| 376 | /* zncv<.rd|.wr> 0,b,u6 00111bbb011101010BBBuuuuuu111110 */ |
| 377 | { "zncv", 0x3875003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_ZNCV }}, |
| 378 | |
| 379 | /* zncv<.rd|.wr> 0,b,limm 00111bbb001101010BBB111110111110 */ |
| 380 | { "zncv", 0x38350fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { C_NPS_ZNCV }}, |
| 381 | |
| 382 | /* zncv<.rd|.wr> 0,limm,c 00111110001101010111CCCCCC111110 */ |
| 383 | { "zncv", 0x3e35703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { C_NPS_ZNCV }}, |
| 384 | |
| 385 | /* zncv<.rd|.wr> 0,limm,u6 00111110011101010111uuuuuu111110 */ |
| 386 | { "zncv", 0x3e75703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }}, |
| 387 | |
| 388 | /* zncv<.rd|.wr> 0,limm,s12 00111110101101010111ssssssSSSSSS */ |
| 389 | { "zncv", 0x3eb57000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, SIMM12_20 }, { C_NPS_ZNCV }}, |
| 390 | |
| 391 | /* hofs a,b,c */ |
| 392 | { "hofs", 0x38360000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_F }}, |
| 393 | |
| 394 | /* hofs a,b,min_hofs,psbc */ |
| 395 | { "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }}, |
| 396 | |
| 397 | /* Protocol Decoder Instructions. */ |
| 398 | |
| 399 | /* dctcp b,c 00111bbb001011110bbbcccccc000000 */ |
| 400 | { "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, |
| 401 | |
| 402 | /* dcip a,b,c 00111bbb001011110bbbccccccaaaaaa */ |
| 403 | { "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, |
| 404 | |
| 405 | /* dcet b,c 00111bbb001011110bbbcccccc000010 */ |
| 406 | { "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }}, |
| 407 | |
| 408 | /* dcet a,b,c 00111bbb001000000bbbccccccaaaaaa */ |
| 409 | { "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }}, |
| 410 | |
| 411 | /* ACL Instructions. */ |
| 412 | |
| 413 | /* dcacl<.f> a,b,c 00111bbb001001010bbbccccccaaaaaa */ |
| 414 | { "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_ARC700, ACL, NPS400, { RA, RB, RC }, { C_F }}, |
| 415 | |
| 416 | /* DPI Instructions. */ |
| 417 | |
| 418 | /* hash dst,src1,src2,width,perm,nonlinear,basemat */ |
| 419 | { "hash", 0x58180000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_PERM, NPS_HASH_NONLINEAR, NPS_HASH_BASEMAT }, { 0 }}, |
| 420 | |
| 421 | /* hash.pN dst,src1,src2,width,len,ofs,basemat */ |
| 422 | |
| 423 | #define HASH_P(FUNC, SUBOP2) \ |
| 424 | { "hash", (0x58100000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_LEN, NPS_HASH_OFS, NPS_HASH_BASEMAT2 }, { C_NPS_P##FUNC }}, |
| 425 | |
| 426 | HASH_P(0, 0x9) |
| 427 | HASH_P(1, 0xA) |
| 428 | HASH_P(2, 0xB) |
| 429 | HASH_P(3, 0xC) |
| 430 | |
| 431 | /* tr<.f> a,b,c 00111bbb00100001FBBBCCCCCCAAAAAA */ |
| 432 | { "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, |
| 433 | |
| 434 | /* tr<.f> a,limm,c 0011111000100001F111CCCCCCAAAAAA */ |
| 435 | { "tr", 0x3e217000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }}, |
| 436 | |
| 437 | /* tr<.f> a,b,u6 00111bbb01100001FBBBuuuuuuAAAAAA */ |
| 438 | { "tr", 0x38610000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }}, |
| 439 | |
| 440 | /* tr<.f> 0,b,c 00111bbb00100001FBBBCCCCCC111110 */ |
| 441 | { "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, |
| 442 | |
| 443 | /* tr<.f> 0,limm,c 0011111000100001F111CCCCCC111110 */ |
| 444 | { "tr", 0x3e21703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }}, |
| 445 | |
| 446 | /* tr<.f> 0,b,u6 00111bbb01100001FBBBuuuuuu111110 */ |
| 447 | { "tr", 0x3861003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }}, |
| 448 | |
| 449 | /* tr<.f> 0,b,limm 00111bbb00100001FBBB111110111110 */ |
| 450 | { "tr", 0x38210fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }}, |
| 451 | |
| 452 | /* tr<.f> a,b,limm 00111bbb00100001FBBB111110AAAAAA */ |
| 453 | { "tr", 0x38210f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }}, |
| 454 | |
| 455 | /* tr<.f> a,limm,limm 0011111000100001F111111110AAAAAA */ |
| 456 | { "tr", 0x3e217f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }}, |
| 457 | |
| 458 | /* tr<.f> a,limm,u6 0011111001100001F111uuuuuuAAAAAA */ |
| 459 | { "tr", 0x3e617000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }}, |
| 460 | |
| 461 | /* tr<.f> 0,limm,u6 0011111001100001F111uuuuuu111110 */ |
| 462 | { "tr", 0x3e61703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }}, |
| 463 | |
| 464 | /* utf8 a,b,c 00111bbb00100011FBBBCCCCCCAAAAAA */ |
| 465 | { "utf8", 0x38220000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, |
| 466 | |
| 467 | /* utf8 a,limm,c 0011111000100011F111CCCCCCAAAAAA */ |
| 468 | { "utf8", 0x3e227000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }}, |
| 469 | |
| 470 | /* utf8 a,b,u6 00111bbb01100011FBBBuuuuuuAAAAAA */ |
| 471 | { "utf8", 0x38620000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }}, |
| 472 | |
| 473 | /* utf8 0,b,c 00111bbb00100011FBBBCCCCCC111110 */ |
| 474 | { "utf8", 0x3822003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, |
| 475 | |
| 476 | /* utf8 0,limm,c 0011111000100011F111CCCCCC111110 */ |
| 477 | { "utf8", 0x3e22703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }}, |
| 478 | |
| 479 | /* utf8 0,b,u6 00111bbb01100011FBBBuuuuuu111110 */ |
| 480 | { "utf8", 0x3862003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }}, |
| 481 | |
| 482 | /* utf8 0,b,limm 00111bbb00100011FBBB111110111110 */ |
| 483 | { "utf8", 0x38220fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }}, |
| 484 | |
| 485 | /* utf8 a,b,limm 00111bbb00100011FBBB111110AAAAAA */ |
| 486 | { "utf8", 0x38220f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }}, |
| 487 | |
| 488 | /* utf8 a,limm,limm 0011111000100011F111111110AAAAAA */ |
| 489 | { "utf8", 0x3e227f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }}, |
| 490 | |
| 491 | /* utf8 a,limm,u6 0011111001100011F111uuuuuuAAAAAA */ |
| 492 | { "utf8", 0x3e627000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }}, |
| 493 | |
| 494 | /* utf8 0,limm,u6 0011111001100011F111uuuuuu111110 */ |
| 495 | { "utf8", 0x3e62703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }}, |
| 496 | |
| 497 | /* e4by dst,src1,src2,index0,index1,index2,index3 */ |
| 498 | { "e4by", 0x581d0000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_E4BY_INDEX0, NPS_E4BY_INDEX1, NPS_E4BY_INDEX2, NPS_E4BY_INDEX3 }, { 0 }}, |
| 499 | |
| 500 | /* addf<.f> a,b,c 00111bbb00100011FBBBCCCCCCAAAAAA */ |
| 501 | { "addf", 0x38230000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }}, |
| 502 | |
| 503 | /* addf<.f> a,limm,c 0011111000100011F111CCCCCCAAAAAA */ |
| 504 | { "addf", 0x3e237000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }}, |
| 505 | |
| 506 | /* addf<.f> a,b,u6 00111bbb01100011FBBBuuuuuuAAAAAA */ |
| 507 | { "addf", 0x38630000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }}, |
| 508 | |
| 509 | /* addf<.f> 0,b,c 00111bbb00100011FBBBCCCCCC111110 */ |
| 510 | { "addf", 0x3823003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }}, |
| 511 | |
| 512 | /* addf<.f> 0,limm,c 0011111000100011F111CCCCCC111110 */ |
| 513 | { "addf", 0x3e23703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }}, |
| 514 | |
| 515 | /* addf<.f> 0,b,u6 00111bbb01100011FBBBuuuuuu111110 */ |
| 516 | { "addf", 0x3863003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }}, |
| 517 | |
| 518 | /* addf<.f> 0,b,limm 00111bbb00100011FBBB111110111110 */ |
| 519 | { "addf", 0x38230fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }}, |
| 520 | |
| 521 | /* addf<.f> a,b,limm 00111bbb00100011FBBB111110AAAAAA */ |
| 522 | { "addf", 0x38230f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }}, |
| 523 | |
| 524 | /* addf<.f> a,limm,limm 0011111000100011F111111110AAAAAA */ |
| 525 | { "addf", 0x3e237f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }}, |
| 526 | |
| 527 | /* addf<.f> a,limm,u6 0011111001100011F111uuuuuuAAAAAA */ |
| 528 | { "addf", 0x3e637000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }}, |
| 529 | |
| 530 | /* addf<.f> 0,limm,u6 0011111001100011F111uuuuuu111110 */ |
| 531 | { "addf", 0x3e63703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }}, |
| 532 | |
| 533 | /* ldbit<.x2|.x4>.di<.cl> a,[b] 00010bbb00000000SBBB10011XAAAAAA */ |
| 534 | { "ldbit", 0x10000980, 0xf8ff8980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, |
| 535 | |
| 536 | /* ldbit<.x2|.x4>.di<.cl> a,[b,s9] 00010bbbssssssssSBBB10011XAAAAAA */ |
| 537 | { "ldbit", 0x10000980, 0xf8000980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, |
| 538 | |
| 539 | /* ldbit<.x2|.x4>.di<.cl> a,[limm] 0001011000000000011110011XAAAAAA */ |
| 540 | { "ldbit", 0x16007980, 0xfffff980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, |
| 541 | |
| 542 | /* ldbit<.x2|.x4>.di<.cl> a,[limm,s9] 00010110ssssssssS11110011XAAAAAA */ |
| 543 | { "ldbit", 0x16007980, 0xff007980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, |
| 544 | |
| 545 | /* ldbit<.x2|.x4>.di<.cl> a,[b,c] 00100bbb0011011X1BBBCCCCCCAAAAAA */ |
| 546 | { "ldbit", 0x20368000, 0xf83e8000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }}, |
| 547 | |
| 548 | /* ldbit<.x2|.x4>.di<.cl> a,[b,limm] 00100bbb0011011X1BBB111110AAAAAA */ |
| 549 | { "ldbit", 0x20368f80, 0xf83e8fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }}, |
| 550 | |
| 551 | /* ldbit<.x2|.x4>.di<.cl> a,[limm,c] 001001100011011X1111CCCCCCAAAAAA */ |
| 552 | { "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }}, |
| 553 | |
| 554 | /* Pipeline Control Instructions. */ |
| 555 | |
| 556 | /* schd<.rw|.rd> */ |
| 557 | { "schd", 0x3e6f7004, 0xffffff7f, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_RW }}, |
| 558 | |
| 559 | /* schd.wft.<.ie1|.ie2|.ie12> */ |
| 560 | { "schd", 0x3e6f7044, 0xfffffcff, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_TRIG, C_NPS_SCHD_IE }}, |
| 561 | |
| 562 | /* sync<.rd|.wr> */ |
| 563 | { "sync", 0x3e6f703f, 0xffffffbf, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SYNC }}, |
| 564 | |
| 565 | /* hwscd.off B */ |
| 566 | { "hwschd", 0x386f00bf, 0xf8ff8fff, ARC_OPCODE_ARC700, CONTROL, NPS400, { RB }, { C_NPS_HWS_OFF }}, |
| 567 | |
| 568 | /* hwscd.restore 0,C */ |
| 569 | { "hwschd", 0x3e6f7003, 0xfffff03f, ARC_OPCODE_ARC700, CONTROL, NPS400, { ZA, RC }, { C_NPS_HWS_RESTORE }}, |
| 570 | |
| 571 | /* Load / Store From (0x57f00000 + Offset) Instructions. */ |
| 572 | |
| 573 | #define XLDST_LIKE(NAME,SUBOP2) \ |
| 574 | { NAME, (0x58000000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, MEMORY, NPS400, { NPS_R_DST, BRAKET, NPS_XLDST_UIMM16, BRAKETdup }, { 0 }}, |
| 575 | |
| 576 | XLDST_LIKE("xldb", 0x8) |
| 577 | XLDST_LIKE("xldw", 0x9) |
| 578 | XLDST_LIKE("xld", 0xa) |
| 579 | XLDST_LIKE("xstb", 0xc) |
| 580 | XLDST_LIKE("xstw", 0xd) |
| 581 | XLDST_LIKE("xst", 0xe) |
| 582 | |
| 583 | /* BMU Instructions. */ |
| 584 | |
| 585 | /* sbdalc dst, src1, type */ |
| 586 | { "sbdalc", 0x38500040, 0xf8ff09c0, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, NPS_BD_TYPE }, { 0 }}, |
| 587 | |
| 588 | /* bdalc dst, [cm:src1], src1, src2 */ |
| 589 | { "bdalc", 0x38100000, 0xf8ff0000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }}, |
| 590 | |
| 591 | /* bdalc dst, [cm:src1], src1, type, num_buff */ |
| 592 | { "bdalc", 0x38500800, 0xf8ff0800, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BD_TYPE, NPS_BMU_NUM }, { 0 }}, |
| 593 | |
| 594 | /* sbdfre 0, src1, src2 */ |
| 595 | { "sbdfre", 0x3817003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }}, |
| 596 | |
| 597 | /* bdfre 0, [cm:src1], src1, src2 */ |
| 598 | { "bdfre", 0x3811003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }}, |
| 599 | |
| 600 | /* bdfre 0, [cm:src1], src1, type, num_buff */ |
| 601 | { "bdfre", 0x3851083e, 0xf8ff083f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BD_TYPE, NPS_BMU_NUM }, { 0 }}, |
| 602 | |
| 603 | /* bdfre 0, [cm:src1], src1, num_buff */ |
| 604 | { "bdfre", 0x3851003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }}, |
| 605 | |
| 606 | /* bdbgt 0, src1, src2 */ |
| 607 | { "bdbgt", 0x3818003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }}, |
| 608 | |
| 609 | /* sidxalc dst, src1 */ |
| 610 | { "sidxalc", 0x385c0040, 0xf8ff0040, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB }, { 0 }}, |
| 611 | |
| 612 | /* idxalc dst, [cm:src1], src1, src2 */ |
| 613 | { "idxalc", 0x381c0000, 0xf8ff0000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }}, |
| 614 | |
| 615 | /* idxalc dst, [cm:src1], src1, num_idx */ |
| 616 | { "idxalc", 0x385c0800, 0xf8ff0800, ARC_OPCODE_ARC700, BMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }}, |
| 617 | |
| 618 | /* sidxfre 0, src1, src2 */ |
| 619 | { "sidxfre", 0x381d003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }}, |
| 620 | |
| 621 | /* idxfre 0, [cm:src1], src1, src2 */ |
| 622 | { "idxfre", 0x381e003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }}, |
| 623 | |
| 624 | /* idxfre 0, [cm:src1], src1, num_buff */ |
| 625 | { "idxfre", 0x385e003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_BMU_NUM }, { 0 }}, |
| 626 | |
| 627 | /* idxbgt 0, src1, src2 */ |
| 628 | { "idxbgt", 0x3819003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }}, |
| 629 | |
| 630 | /* efabgt 0, limm, src2 */ |
| 631 | { "efabgt", 0x3e0d703e, 0xfffff03f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, LIMM, RC }, { 0 }}, |
| 632 | |
| 633 | /* efabgt 0, src1, limm */ |
| 634 | { "efabgt", 0x380d0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, LIMM }, { 0 }}, |
| 635 | |
| 636 | /* efabgt 0, src1, src2 */ |
| 637 | { "efabgt", 0x380d003e, 0xf8ff003f, ARC_OPCODE_ARC700, BMU, NPS400, { ZA, RB, RC }, { 0 }}, |
| 638 | |
| 639 | /* efabgt dst, limm, src2 */ |
| 640 | { "efabgt", 0x3e0d7000, 0xfffff000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, LIMM, RC }, { 0 }}, |
| 641 | |
| 642 | /* efabgt dst, src1, limm */ |
| 643 | { "efabgt", 0x380d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, LIMM }, { 0 }}, |
| 644 | |
| 645 | /* efabgt dst, src1, src2 */ |
| 646 | { "efabgt", 0x380d0000, 0xf8ff8000, ARC_OPCODE_ARC700, BMU, NPS400, { RA, RB, RC }, { 0 }}, |
| 647 | |
| 648 | /* PMU Instructions. */ |
| 649 | |
| 650 | /* jobget<.cl> 0, [cjid:src1] */ |
| 651 | { "jobget", 0x3e2f7020, 0xfffff03f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RC, BRAKET }, { 0 }}, |
| 652 | |
| 653 | { "jobget", 0x3e2f7021, 0xfffff03f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RC, BRAKET }, { C_NPS_CL }}, |
| 654 | |
| 655 | /* jobdn 0, [cjid:src1], src1, src2 */ |
| 656 | { "jobdn", 0x3812003e, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }}, |
| 657 | |
| 658 | /* jobdn 0, [cjid:src1], src1, nxt_dst */ |
| 659 | { "jobdn", 0x3852003e, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { ZA, BRAKET, NPS_CJID, COLON, RB, BRAKETdup, RBdup, NPS_PMU_NXT_DST }, { 0 }}, |
| 660 | |
| 661 | /* sjobalc dst, src1 */ |
| 662 | { "sjobalc", 0x385f0040, 0xf8ff8fc0, ARC_OPCODE_ARC700, PMU, NPS400, { RA, RB }, { 0 }}, |
| 663 | |
| 664 | /* jobalc dst, [cm:src1], src1, num_job */ |
| 665 | { "jobalc", 0x385f0800, 0xf8ff8800, ARC_OPCODE_ARC700, PMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, NPS_PMU_NUM_JOB }, { 0 }}, |
| 666 | |
| 667 | /* jobalc dst, [cm:src1], src1, src2 */ |
| 668 | { "jobalc", 0x381f0000, 0xf8ff8000, ARC_OPCODE_ARC700, PMU, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RBdup, RC }, { 0 }}, |
| 669 | |
| 670 | /* jobbgt dst, src1, src2 */ |
| 671 | { "jobbgt", 0x381a0000, 0xf8ff0000, ARC_OPCODE_ARC700, PMU, NPS400, { RA, RB, RC }, { 0 }}, |
| 672 | |
| 673 | /* cnljob 0 */ |
| 674 | { "cnljob", 0x3e6f70ff, 0xffffffff, ARC_OPCODE_ARC700, PMU, NPS400, { ZA }, { 0 }}, |
| 675 | |
| 676 | /* qseq dst, [src1] */ |
| 677 | { "qseq", 0x386f0028, 0xf8ff803f, ARC_OPCODE_ARC700, PMU, NPS400, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, |