| 1 | /* Disassemble AVR instructions. |
| 2 | Copyright (C) 1999, 2000 Free Software Foundation, Inc. |
| 3 | |
| 4 | Contributed by Denis Chertykov <denisc@overta.ru> |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 19 | |
| 20 | #include <assert.h> |
| 21 | #include "sysdep.h" |
| 22 | #include "dis-asm.h" |
| 23 | #include "opintl.h" |
| 24 | |
| 25 | |
| 26 | struct avr_opcodes_s |
| 27 | { |
| 28 | char *name; |
| 29 | char *constraints; |
| 30 | char *opcode; |
| 31 | int insn_size; /* in words */ |
| 32 | int isa; |
| 33 | unsigned int bin_opcode; |
| 34 | unsigned int bin_mask; |
| 35 | }; |
| 36 | |
| 37 | #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ |
| 38 | {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0}, |
| 39 | |
| 40 | struct avr_opcodes_s avr_opcodes[] = |
| 41 | { |
| 42 | #include "opcode/avr.h" |
| 43 | {NULL, NULL, NULL, 0, 0, 0, 0} |
| 44 | }; |
| 45 | |
| 46 | |
| 47 | static void avr_operand (unsigned int insn, unsigned int insn2, |
| 48 | unsigned int pc, int constraint, char *buf, |
| 49 | char *comment, int regs); |
| 50 | |
| 51 | static void |
| 52 | avr_operand (insn, insn2, pc, constraint, buf, comment, regs) |
| 53 | unsigned int insn; |
| 54 | unsigned int insn2; |
| 55 | unsigned int pc; |
| 56 | int constraint; |
| 57 | char *buf; |
| 58 | char *comment; |
| 59 | int regs; |
| 60 | { |
| 61 | switch (constraint) |
| 62 | { |
| 63 | /* Any register operand. */ |
| 64 | case 'r': |
| 65 | if (regs) |
| 66 | insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */ |
| 67 | else |
| 68 | insn = (insn & 0x01f0) >> 4; /* destination register */ |
| 69 | |
| 70 | sprintf (buf, "r%d", insn); |
| 71 | break; |
| 72 | |
| 73 | case 'd': |
| 74 | if (regs) |
| 75 | sprintf (buf, "r%d", 16 + (insn & 0xf)); |
| 76 | else |
| 77 | sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4)); |
| 78 | break; |
| 79 | |
| 80 | case 'w': |
| 81 | sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3)); |
| 82 | break; |
| 83 | |
| 84 | case 'a': |
| 85 | if (regs) |
| 86 | sprintf (buf, "r%d", 16 + (insn & 7)); |
| 87 | else |
| 88 | sprintf (buf, "r%d", 16 + ((insn >> 4) & 7)); |
| 89 | break; |
| 90 | |
| 91 | case 'v': |
| 92 | if (regs) |
| 93 | sprintf (buf, "r%d", (insn & 0xf) * 2); |
| 94 | else |
| 95 | sprintf (buf, "r%d", ((insn & 0xf0) >> 3)); |
| 96 | break; |
| 97 | |
| 98 | case 'e': |
| 99 | if (insn & 0x2) |
| 100 | *buf++ = '-'; |
| 101 | switch ((insn >> 2) & 0x3) |
| 102 | { |
| 103 | case 0: *buf++ = 'Z'; break; |
| 104 | case 2: *buf++ = 'Y'; break; |
| 105 | case 3: *buf++ = 'X'; break; |
| 106 | default: buf += sprintf (buf, _(" unknown register ")); break; |
| 107 | } |
| 108 | if (insn & 0x1) |
| 109 | *buf++ = '+'; |
| 110 | *buf = '\0'; |
| 111 | break; |
| 112 | |
| 113 | case 'z': |
| 114 | *buf++ = 'Z'; |
| 115 | if (insn & 0x1) |
| 116 | *buf++ = '+'; |
| 117 | *buf = '\0'; |
| 118 | break; |
| 119 | |
| 120 | case 'b': |
| 121 | { |
| 122 | unsigned int x = insn; |
| 123 | |
| 124 | x = (insn & 7); |
| 125 | x |= (insn >> 7) & (3 << 3); |
| 126 | x |= (insn >> 8) & (1 << 5); |
| 127 | |
| 128 | if (insn & 0x8) |
| 129 | *buf++ = 'Y'; |
| 130 | else |
| 131 | *buf++ = 'Z'; |
| 132 | sprintf (buf, "+%d", x); |
| 133 | sprintf (comment, "0x%02x", x); |
| 134 | } |
| 135 | break; |
| 136 | |
| 137 | case 'h': |
| 138 | sprintf (buf, "0x%x", |
| 139 | ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2); |
| 140 | break; |
| 141 | |
| 142 | case 'L': |
| 143 | { |
| 144 | int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2; |
| 145 | sprintf (buf, ".%+-8d", rel_addr); |
| 146 | sprintf (comment, "0x%x", pc + 2 + rel_addr); |
| 147 | } |
| 148 | break; |
| 149 | |
| 150 | case 'l': |
| 151 | { |
| 152 | int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2; |
| 153 | sprintf (buf, ".%+-8d", rel_addr); |
| 154 | sprintf (comment, "0x%x", pc + 2 + rel_addr); |
| 155 | } |
| 156 | break; |
| 157 | |
| 158 | case 'i': |
| 159 | sprintf (buf, "0x%04X", insn2); |
| 160 | break; |
| 161 | |
| 162 | case 'M': |
| 163 | sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf)); |
| 164 | sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf)); |
| 165 | break; |
| 166 | |
| 167 | case 'n': |
| 168 | sprintf (buf, _("Internal disassembler error")); |
| 169 | break; |
| 170 | |
| 171 | case 'K': |
| 172 | sprintf (buf, "%d", (insn & 0xf) | ((insn >> 2) & 0x30)); |
| 173 | break; |
| 174 | |
| 175 | case 's': |
| 176 | sprintf (buf, "%d", insn & 7); |
| 177 | break; |
| 178 | |
| 179 | case 'S': |
| 180 | sprintf (buf, "%d", (insn >> 4) & 7); |
| 181 | break; |
| 182 | |
| 183 | case 'P': |
| 184 | { |
| 185 | unsigned int x; |
| 186 | x = (insn & 0xf); |
| 187 | x |= (insn >> 5) & 0x30; |
| 188 | sprintf (buf, "0x%02x", x); |
| 189 | sprintf (comment, "%d", x); |
| 190 | } |
| 191 | break; |
| 192 | |
| 193 | case 'p': |
| 194 | { |
| 195 | unsigned int x; |
| 196 | |
| 197 | x = (insn >> 3) & 0x1f; |
| 198 | sprintf (buf, "0x%02x", x); |
| 199 | sprintf (comment, "%d", x); |
| 200 | } |
| 201 | break; |
| 202 | |
| 203 | case '?': |
| 204 | *buf = '\0'; |
| 205 | break; |
| 206 | |
| 207 | default: |
| 208 | sprintf (buf, _("unknown constraint `%c'"), constraint); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *)); |
| 213 | |
| 214 | static unsigned short |
| 215 | avrdis_opcode (addr, info) |
| 216 | bfd_vma addr; |
| 217 | disassemble_info *info; |
| 218 | { |
| 219 | bfd_byte buffer[2]; |
| 220 | int status; |
| 221 | status = info->read_memory_func(addr, buffer, 2, info); |
| 222 | if (status != 0) |
| 223 | { |
| 224 | info->memory_error_func(status, addr, info); |
| 225 | return -1; |
| 226 | } |
| 227 | return bfd_getl16 (buffer); |
| 228 | } |
| 229 | |
| 230 | |
| 231 | int |
| 232 | print_insn_avr(addr, info) |
| 233 | bfd_vma addr; |
| 234 | disassemble_info *info; |
| 235 | { |
| 236 | unsigned int insn, insn2; |
| 237 | struct avr_opcodes_s *opcode; |
| 238 | void *stream = info->stream; |
| 239 | fprintf_ftype prin = info->fprintf_func; |
| 240 | static int initialized; |
| 241 | int cmd_len = 2; |
| 242 | |
| 243 | if (!initialized) |
| 244 | { |
| 245 | initialized = 1; |
| 246 | |
| 247 | for (opcode = avr_opcodes; opcode->name; opcode++) |
| 248 | { |
| 249 | char * s; |
| 250 | unsigned int bin = 0; |
| 251 | unsigned int mask = 0; |
| 252 | |
| 253 | for (s = opcode->opcode; *s; ++s) |
| 254 | { |
| 255 | bin <<= 1; |
| 256 | mask <<= 1; |
| 257 | bin |= (*s == '1'); |
| 258 | mask |= (*s == '1' || *s == '0'); |
| 259 | } |
| 260 | assert (s - opcode->opcode == 16); |
| 261 | assert (opcode->bin_opcode == bin); |
| 262 | opcode->bin_mask = mask; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | insn = avrdis_opcode (addr, info); |
| 267 | |
| 268 | for (opcode = avr_opcodes; opcode->name; opcode++) |
| 269 | { |
| 270 | if ((insn & opcode->bin_mask) == opcode->bin_opcode) |
| 271 | break; |
| 272 | } |
| 273 | |
| 274 | if (opcode->name) |
| 275 | { |
| 276 | char op1[20], op2[20], comment1[40], comment2[40]; |
| 277 | char *op = opcode->constraints; |
| 278 | |
| 279 | op1[0] = 0; |
| 280 | op2[0] = 0; |
| 281 | comment1[0] = 0; |
| 282 | comment2[0] = 0; |
| 283 | insn2 = 0; |
| 284 | |
| 285 | if (opcode->insn_size > 1) |
| 286 | { |
| 287 | insn2 = avrdis_opcode (addr + 2, info); |
| 288 | cmd_len = 4; |
| 289 | } |
| 290 | |
| 291 | if (*op && *op != '?') |
| 292 | { |
| 293 | int regs = REGISTER_P (*op); |
| 294 | |
| 295 | avr_operand (insn, insn2, addr, *op, op1, comment1, 0); |
| 296 | |
| 297 | if (*(++op) == ',') |
| 298 | avr_operand (insn, insn2, addr, *(++op), op2, |
| 299 | *comment1 ? comment2 : comment1, regs); |
| 300 | } |
| 301 | |
| 302 | (*prin) (stream, " %-8s", opcode->name); |
| 303 | |
| 304 | if (*op1) |
| 305 | (*prin) (stream, "%s", op1); |
| 306 | |
| 307 | if (*op2) |
| 308 | (*prin) (stream, ", %s", op2); |
| 309 | |
| 310 | if (*comment1) |
| 311 | (*prin) (stream, "\t; %s", comment1); |
| 312 | |
| 313 | if (*comment2) |
| 314 | (*prin) (stream, " %s", comment2); |
| 315 | } |
| 316 | else |
| 317 | (*prin) (stream, ".word 0x%04x\t; ????", insn); |
| 318 | |
| 319 | return cmd_len; |
| 320 | } |