| 1 | /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c. |
| 2 | Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc. |
| 3 | |
| 4 | Contributed by the Center for Software Science at the |
| 5 | University of Utah (pa-gdb-bugs@cs.utah.edu). |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
| 20 | |
| 21 | #include <ansidecl.h> |
| 22 | #include "sysdep.h" |
| 23 | #include "dis-asm.h" |
| 24 | #include "opcode/hppa.h" |
| 25 | |
| 26 | /* Integer register names, indexed by the numbers which appear in the |
| 27 | opcodes. */ |
| 28 | static const char *const reg_names[] = |
| 29 | {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", |
| 30 | "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", |
| 31 | "r20", "r21", "r22", "arg3", "arg2", "arg1", "arg0", "dp", "ret0", "ret1", |
| 32 | "sp", "r31"}; |
| 33 | |
| 34 | /* Floating point register names, indexed by the numbers which appear in the |
| 35 | opcodes. */ |
| 36 | static const char *const fp_reg_names[] = |
| 37 | {"fpsr", "fpe2", "fpe4", "fpe6", |
| 38 | "fr4", "fr5", "fr6", "fr7", "fr8", |
| 39 | "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", |
| 40 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", |
| 41 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"}; |
| 42 | |
| 43 | typedef unsigned int CORE_ADDR; |
| 44 | |
| 45 | /* Get at various relevent fields of an instruction word. */ |
| 46 | |
| 47 | #define MASK_5 0x1f |
| 48 | #define MASK_11 0x7ff |
| 49 | #define MASK_14 0x3fff |
| 50 | #define MASK_21 0x1fffff |
| 51 | |
| 52 | /* This macro gets bit fields using HP's numbering (MSB = 0) */ |
| 53 | |
| 54 | #define GET_FIELD(X, FROM, TO) \ |
| 55 | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
| 56 | |
| 57 | /* Some of these have been converted to 2-d arrays because they |
| 58 | consume less storage this way. If the maintenance becomes a |
| 59 | problem, convert them back to const 1-d pointer arrays. */ |
| 60 | static const char control_reg[][6] = { |
| 61 | "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", |
| 62 | "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", |
| 63 | "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr", |
| 64 | "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3", |
| 65 | "tr4", "tr5", "tr6", "tr7" |
| 66 | }; |
| 67 | |
| 68 | static const char compare_cond_names[][5] = { |
| 69 | "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", |
| 70 | ",od", ",tr", ",<>", ",>=", ",>", ",>>=", |
| 71 | ",>>", ",nsv", ",ev" |
| 72 | }; |
| 73 | static const char add_cond_names[][5] = { |
| 74 | "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", |
| 75 | ",od", ",tr", ",<>", ",>=", ",>", ",uv", |
| 76 | ",vnz", ",nsv", ",ev" |
| 77 | }; |
| 78 | static const char *const logical_cond_names[] = { |
| 79 | "", ",=", ",<", ",<=", 0, 0, 0, ",od", |
| 80 | ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"}; |
| 81 | static const char *const unit_cond_names[] = { |
| 82 | "", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc", |
| 83 | ",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc" |
| 84 | }; |
| 85 | static const char shift_cond_names[][4] = { |
| 86 | "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev" |
| 87 | }; |
| 88 | static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"}; |
| 89 | static const char short_ldst_compl_names[][4] = {"", ",ma", "", ",mb"}; |
| 90 | static const char *const short_bytes_compl_names[] = { |
| 91 | "", ",b,m", ",e", ",e,m" |
| 92 | }; |
| 93 | static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"}; |
| 94 | static const char float_comp_names[][8] = |
| 95 | { |
| 96 | ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>", |
| 97 | ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>", |
| 98 | ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<", |
| 99 | ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true" |
| 100 | }; |
| 101 | |
| 102 | /* For a bunch of different instructions form an index into a |
| 103 | completer name table. */ |
| 104 | #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ |
| 105 | GET_FIELD (insn, 18, 18) << 1) |
| 106 | |
| 107 | #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ |
| 108 | (GET_FIELD ((insn), 19, 19) ? 8 : 0)) |
| 109 | |
| 110 | /* Utility function to print registers. Put these first, so gcc's function |
| 111 | inlining can do its stuff. */ |
| 112 | |
| 113 | #define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR) |
| 114 | |
| 115 | static void |
| 116 | fput_reg (reg, info) |
| 117 | unsigned reg; |
| 118 | disassemble_info *info; |
| 119 | { |
| 120 | (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0"); |
| 121 | } |
| 122 | |
| 123 | static void |
| 124 | fput_fp_reg (reg, info) |
| 125 | unsigned reg; |
| 126 | disassemble_info *info; |
| 127 | { |
| 128 | (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0"); |
| 129 | } |
| 130 | |
| 131 | static void |
| 132 | fput_fp_reg_r (reg, info) |
| 133 | unsigned reg; |
| 134 | disassemble_info *info; |
| 135 | { |
| 136 | /* Special case floating point exception registers. */ |
| 137 | if (reg < 4) |
| 138 | (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1); |
| 139 | else |
| 140 | (*info->fprintf_func) (info->stream, "%sR", reg ? fp_reg_names[reg] |
| 141 | : "fr0"); |
| 142 | } |
| 143 | |
| 144 | static void |
| 145 | fput_creg (reg, info) |
| 146 | unsigned reg; |
| 147 | disassemble_info *info; |
| 148 | { |
| 149 | (*info->fprintf_func) (info->stream, control_reg[reg]); |
| 150 | } |
| 151 | |
| 152 | /* print constants with sign */ |
| 153 | |
| 154 | static void |
| 155 | fput_const (num, info) |
| 156 | unsigned num; |
| 157 | disassemble_info *info; |
| 158 | { |
| 159 | if ((int)num < 0) |
| 160 | (*info->fprintf_func) (info->stream, "-%x", -(int)num); |
| 161 | else |
| 162 | (*info->fprintf_func) (info->stream, "%x", num); |
| 163 | } |
| 164 | |
| 165 | /* Routines to extract various sized constants out of hppa |
| 166 | instructions. */ |
| 167 | |
| 168 | /* This assumes that no garbage lies outside of the lower bits of |
| 169 | value. */ |
| 170 | |
| 171 | static int |
| 172 | sign_extend (val, bits) |
| 173 | unsigned val, bits; |
| 174 | { |
| 175 | return (int)(val >> (bits - 1) ? (-1 << bits) | val : val); |
| 176 | } |
| 177 | |
| 178 | /* For many immediate values the sign bit is the low bit! */ |
| 179 | |
| 180 | static int |
| 181 | low_sign_extend (val, bits) |
| 182 | unsigned val, bits; |
| 183 | { |
| 184 | return (int)((val & 0x1 ? (-1 << (bits - 1)) : 0) | val >> 1); |
| 185 | } |
| 186 | /* extract the immediate field from a ld{bhw}s instruction */ |
| 187 | |
| 188 | #if 0 /* not used */ |
| 189 | static unsigned |
| 190 | get_field (val, from, to) |
| 191 | unsigned val, from, to; |
| 192 | { |
| 193 | val = val >> (31 - to); |
| 194 | return val & ((1 << (32 - from)) - 1); |
| 195 | } |
| 196 | |
| 197 | static unsigned |
| 198 | set_field (val, from, to, new_val) |
| 199 | unsigned *val, from, to, new_val; |
| 200 | { |
| 201 | unsigned mask = ~((1 << (to - from + 1)) << (31 - from)); |
| 202 | return *val = (*val & mask) | (new_val << (31 - from)); |
| 203 | } |
| 204 | #endif |
| 205 | |
| 206 | /* extract a 3-bit space register number from a be, ble, mtsp or mfsp */ |
| 207 | static int |
| 208 | extract_3 (word) |
| 209 | unsigned word; |
| 210 | { |
| 211 | return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17); |
| 212 | } |
| 213 | |
| 214 | static int |
| 215 | extract_5_load (word) |
| 216 | unsigned word; |
| 217 | { |
| 218 | return low_sign_extend (word >> 16 & MASK_5, 5); |
| 219 | } |
| 220 | |
| 221 | /* extract the immediate field from a st{bhw}s instruction */ |
| 222 | static int |
| 223 | extract_5_store (word) |
| 224 | unsigned word; |
| 225 | { |
| 226 | return low_sign_extend (word & MASK_5, 5); |
| 227 | } |
| 228 | |
| 229 | /* extract the immediate field from a break instruction */ |
| 230 | static unsigned |
| 231 | extract_5r_store (word) |
| 232 | unsigned word; |
| 233 | { |
| 234 | return (word & MASK_5); |
| 235 | } |
| 236 | |
| 237 | /* extract the immediate field from a {sr}sm instruction */ |
| 238 | static unsigned |
| 239 | extract_5R_store (word) |
| 240 | unsigned word; |
| 241 | { |
| 242 | return (word >> 16 & MASK_5); |
| 243 | } |
| 244 | |
| 245 | /* extract the immediate field from a bb instruction */ |
| 246 | static unsigned |
| 247 | extract_5Q_store (word) |
| 248 | unsigned word; |
| 249 | { |
| 250 | return (word >> 21 & MASK_5); |
| 251 | } |
| 252 | |
| 253 | /* extract an 11 bit immediate field */ |
| 254 | static int |
| 255 | extract_11 (word) |
| 256 | unsigned word; |
| 257 | { |
| 258 | return low_sign_extend (word & MASK_11, 11); |
| 259 | } |
| 260 | |
| 261 | /* extract a 14 bit immediate field */ |
| 262 | static int |
| 263 | extract_14 (word) |
| 264 | unsigned word; |
| 265 | { |
| 266 | return low_sign_extend (word & MASK_14, 14); |
| 267 | } |
| 268 | |
| 269 | #if 0 |
| 270 | /* deposit a 14 bit constant in a word */ |
| 271 | static unsigned |
| 272 | deposit_14 (opnd, word) |
| 273 | int opnd; |
| 274 | unsigned word; |
| 275 | { |
| 276 | unsigned sign = (opnd < 0 ? 1 : 0); |
| 277 | |
| 278 | return word | ((unsigned)opnd << 1 & MASK_14) | sign; |
| 279 | } |
| 280 | #endif |
| 281 | |
| 282 | /* extract a 21 bit constant */ |
| 283 | |
| 284 | static int |
| 285 | extract_21 (word) |
| 286 | unsigned word; |
| 287 | { |
| 288 | int val; |
| 289 | |
| 290 | word &= MASK_21; |
| 291 | word <<= 11; |
| 292 | val = GET_FIELD (word, 20, 20); |
| 293 | val <<= 11; |
| 294 | val |= GET_FIELD (word, 9, 19); |
| 295 | val <<= 2; |
| 296 | val |= GET_FIELD (word, 5, 6); |
| 297 | val <<= 5; |
| 298 | val |= GET_FIELD (word, 0, 4); |
| 299 | val <<= 2; |
| 300 | val |= GET_FIELD (word, 7, 8); |
| 301 | return sign_extend (val, 21) << 11; |
| 302 | } |
| 303 | |
| 304 | #if 0 |
| 305 | /* deposit a 21 bit constant in a word. Although 21 bit constants are |
| 306 | usually the top 21 bits of a 32 bit constant, we assume that only |
| 307 | the low 21 bits of opnd are relevant */ |
| 308 | |
| 309 | static unsigned |
| 310 | deposit_21 (opnd, word) |
| 311 | unsigned opnd, word; |
| 312 | { |
| 313 | unsigned val = 0; |
| 314 | |
| 315 | val |= GET_FIELD (opnd, 11 + 14, 11 + 18); |
| 316 | val <<= 2; |
| 317 | val |= GET_FIELD (opnd, 11 + 12, 11 + 13); |
| 318 | val <<= 2; |
| 319 | val |= GET_FIELD (opnd, 11 + 19, 11 + 20); |
| 320 | val <<= 11; |
| 321 | val |= GET_FIELD (opnd, 11 + 1, 11 + 11); |
| 322 | val <<= 1; |
| 323 | val |= GET_FIELD (opnd, 11 + 0, 11 + 0); |
| 324 | return word | val; |
| 325 | } |
| 326 | #endif |
| 327 | |
| 328 | /* extract a 12 bit constant from branch instructions */ |
| 329 | |
| 330 | static int |
| 331 | extract_12 (word) |
| 332 | unsigned word; |
| 333 | { |
| 334 | return sign_extend (GET_FIELD (word, 19, 28) | |
| 335 | GET_FIELD (word, 29, 29) << 10 | |
| 336 | (word & 0x1) << 11, 12) << 2; |
| 337 | } |
| 338 | |
| 339 | /* extract a 17 bit constant from branch instructions, returning the |
| 340 | 19 bit signed value. */ |
| 341 | |
| 342 | static int |
| 343 | extract_17 (word) |
| 344 | unsigned word; |
| 345 | { |
| 346 | return sign_extend (GET_FIELD (word, 19, 28) | |
| 347 | GET_FIELD (word, 29, 29) << 10 | |
| 348 | GET_FIELD (word, 11, 15) << 11 | |
| 349 | (word & 0x1) << 16, 17) << 2; |
| 350 | } |
| 351 | |
| 352 | /* Print one instruction. */ |
| 353 | int |
| 354 | print_insn_hppa (memaddr, info) |
| 355 | bfd_vma memaddr; |
| 356 | disassemble_info *info; |
| 357 | { |
| 358 | unsigned int insn, i, op; |
| 359 | |
| 360 | { |
| 361 | int status = |
| 362 | (*info->read_memory_func) (memaddr, (bfd_byte*) &insn, sizeof (insn), |
| 363 | info); |
| 364 | if (status != 0) |
| 365 | { |
| 366 | (*info->memory_error_func) (status, memaddr, info); |
| 367 | return -1; |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | for (i = 0; i < NUMOPCODES; ++i) |
| 372 | { |
| 373 | const struct pa_opcode *opcode = &pa_opcodes[i]; |
| 374 | if ((insn & opcode->mask) == opcode->match) |
| 375 | { |
| 376 | register const char *s; |
| 377 | |
| 378 | (*info->fprintf_func) (info->stream, "%s", opcode->name); |
| 379 | |
| 380 | if (!strchr ("cfCY<?!@-+&U>~nHNZFIMadu|", opcode->args[0])) |
| 381 | (*info->fprintf_func) (info->stream, " "); |
| 382 | for (s = opcode->args; *s != '\0'; ++s) |
| 383 | { |
| 384 | switch (*s) |
| 385 | { |
| 386 | case 'x': |
| 387 | fput_reg (GET_FIELD (insn, 11, 15), info); |
| 388 | break; |
| 389 | case 'X': |
| 390 | if (GET_FIELD (insn, 25, 25)) |
| 391 | fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); |
| 392 | else |
| 393 | fput_fp_reg (GET_FIELD (insn, 11, 15), info); |
| 394 | break; |
| 395 | case 'b': |
| 396 | fput_reg (GET_FIELD (insn, 6, 10), info); |
| 397 | break; |
| 398 | case '^': |
| 399 | fput_creg (GET_FIELD (insn, 6, 10), info); |
| 400 | break; |
| 401 | case 'E': |
| 402 | if (GET_FIELD (insn, 25, 25)) |
| 403 | fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); |
| 404 | else |
| 405 | fput_fp_reg (GET_FIELD (insn, 6, 10), info); |
| 406 | break; |
| 407 | case 't': |
| 408 | fput_reg (GET_FIELD (insn, 27, 31), info); |
| 409 | break; |
| 410 | case 'v': |
| 411 | if (GET_FIELD (insn, 25, 25)) |
| 412 | fput_fp_reg_r (GET_FIELD (insn, 27, 31), info); |
| 413 | else |
| 414 | fput_fp_reg (GET_FIELD (insn, 27, 31), info); |
| 415 | break; |
| 416 | case 'y': |
| 417 | fput_fp_reg (GET_FIELD (insn, 27, 31), info); |
| 418 | break; |
| 419 | case '4': |
| 420 | { |
| 421 | int reg = GET_FIELD (insn, 6, 10); |
| 422 | |
| 423 | reg |= (GET_FIELD (insn, 26, 26) << 4); |
| 424 | fput_fp_reg (reg, info); |
| 425 | break; |
| 426 | } |
| 427 | case '6': |
| 428 | { |
| 429 | int reg = GET_FIELD (insn, 11, 15); |
| 430 | |
| 431 | reg |= (GET_FIELD (insn, 26, 26) << 4); |
| 432 | fput_fp_reg (reg, info); |
| 433 | break; |
| 434 | } |
| 435 | case '7': |
| 436 | { |
| 437 | int reg = GET_FIELD (insn, 27, 31); |
| 438 | |
| 439 | reg |= (GET_FIELD (insn, 26, 26) << 4); |
| 440 | fput_fp_reg (reg, info); |
| 441 | break; |
| 442 | } |
| 443 | case '8': |
| 444 | { |
| 445 | int reg = GET_FIELD (insn, 16, 20); |
| 446 | |
| 447 | reg |= (GET_FIELD (insn, 26, 26) << 4); |
| 448 | fput_fp_reg (reg, info); |
| 449 | break; |
| 450 | } |
| 451 | case '9': |
| 452 | { |
| 453 | int reg = GET_FIELD (insn, 21, 25); |
| 454 | |
| 455 | reg |= (GET_FIELD (insn, 26, 26) << 4); |
| 456 | fput_fp_reg (reg, info); |
| 457 | break; |
| 458 | } |
| 459 | case '5': |
| 460 | fput_const (extract_5_load (insn), info); |
| 461 | break; |
| 462 | case 's': |
| 463 | (*info->fprintf_func) (info->stream, |
| 464 | "sr%d", GET_FIELD (insn, 16, 17)); |
| 465 | break; |
| 466 | case 'S': |
| 467 | (*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn)); |
| 468 | break; |
| 469 | case 'c': |
| 470 | (*info->fprintf_func) (info->stream, "%s ", |
| 471 | index_compl_names[GET_COMPL (insn)]); |
| 472 | break; |
| 473 | case 'C': |
| 474 | (*info->fprintf_func) (info->stream, "%s ", |
| 475 | short_ldst_compl_names[GET_COMPL (insn)]); |
| 476 | break; |
| 477 | case 'Y': |
| 478 | (*info->fprintf_func) (info->stream, "%s ", |
| 479 | short_bytes_compl_names[GET_COMPL (insn)]); |
| 480 | break; |
| 481 | /* these four conditions are for the set of instructions |
| 482 | which distinguish true/false conditions by opcode rather |
| 483 | than by the 'f' bit (sigh): comb, comib, addb, addib */ |
| 484 | case '<': |
| 485 | fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)], |
| 486 | info); |
| 487 | break; |
| 488 | case '?': |
| 489 | fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18) + 8], |
| 490 | info); |
| 491 | break; |
| 492 | case '@': |
| 493 | fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18) + 8], |
| 494 | info); |
| 495 | break; |
| 496 | case 'a': |
| 497 | (*info->fprintf_func) (info->stream, "%s ", |
| 498 | compare_cond_names[GET_COND (insn)]); |
| 499 | break; |
| 500 | case 'd': |
| 501 | (*info->fprintf_func) (info->stream, "%s ", |
| 502 | add_cond_names[GET_COND (insn)]); |
| 503 | break; |
| 504 | case '!': |
| 505 | (*info->fprintf_func) (info->stream, "%s", |
| 506 | add_cond_names[GET_FIELD (insn, 16, 18)]); |
| 507 | break; |
| 508 | |
| 509 | case '&': |
| 510 | (*info->fprintf_func) (info->stream, "%s ", |
| 511 | logical_cond_names[GET_COND (insn)]); |
| 512 | break; |
| 513 | case 'U': |
| 514 | (*info->fprintf_func) (info->stream, "%s ", |
| 515 | unit_cond_names[GET_COND (insn)]); |
| 516 | break; |
| 517 | case '|': |
| 518 | case '>': |
| 519 | case '~': |
| 520 | (*info->fprintf_func) |
| 521 | (info->stream, "%s", |
| 522 | shift_cond_names[GET_FIELD (insn, 16, 18)]); |
| 523 | |
| 524 | /* If the next character in args is 'n', it will handle |
| 525 | putting out the space. */ |
| 526 | if (s[1] != 'n') |
| 527 | (*info->fprintf_func) (info->stream, " "); |
| 528 | break; |
| 529 | case 'V': |
| 530 | fput_const (extract_5_store (insn), info); |
| 531 | break; |
| 532 | case 'r': |
| 533 | fput_const (extract_5r_store (insn), info); |
| 534 | break; |
| 535 | case 'R': |
| 536 | fput_const (extract_5R_store (insn), info); |
| 537 | break; |
| 538 | case 'Q': |
| 539 | fput_const (extract_5Q_store (insn), info); |
| 540 | break; |
| 541 | case 'i': |
| 542 | fput_const (extract_11 (insn), info); |
| 543 | break; |
| 544 | case 'j': |
| 545 | fput_const (extract_14 (insn), info); |
| 546 | break; |
| 547 | case 'k': |
| 548 | fput_const (extract_21 (insn), info); |
| 549 | break; |
| 550 | case 'n': |
| 551 | if (insn & 0x2) |
| 552 | (*info->fprintf_func) (info->stream, ",n "); |
| 553 | else |
| 554 | (*info->fprintf_func) (info->stream, " "); |
| 555 | break; |
| 556 | case 'N': |
| 557 | if ((insn & 0x20) && s[1]) |
| 558 | (*info->fprintf_func) (info->stream, ",n "); |
| 559 | else if (insn & 0x20) |
| 560 | (*info->fprintf_func) (info->stream, ",n"); |
| 561 | else if (s[1]) |
| 562 | (*info->fprintf_func) (info->stream, " "); |
| 563 | break; |
| 564 | case 'w': |
| 565 | (*info->print_address_func) (memaddr + 8 + extract_12 (insn), |
| 566 | info); |
| 567 | break; |
| 568 | case 'W': |
| 569 | /* 17 bit PC-relative branch. */ |
| 570 | (*info->print_address_func) ((memaddr + 8 |
| 571 | + extract_17 (insn)), |
| 572 | info); |
| 573 | break; |
| 574 | case 'z': |
| 575 | /* 17 bit displacement. This is an offset from a register |
| 576 | so it gets disasssembled as just a number, not any sort |
| 577 | of address. */ |
| 578 | fput_const (extract_17 (insn), info); |
| 579 | break; |
| 580 | case 'p': |
| 581 | (*info->fprintf_func) (info->stream, "%d", |
| 582 | 31 - GET_FIELD (insn, 22, 26)); |
| 583 | break; |
| 584 | case 'P': |
| 585 | (*info->fprintf_func) (info->stream, "%d", |
| 586 | GET_FIELD (insn, 22, 26)); |
| 587 | break; |
| 588 | case 'T': |
| 589 | (*info->fprintf_func) (info->stream, "%d", |
| 590 | 32 - GET_FIELD (insn, 27, 31)); |
| 591 | break; |
| 592 | case 'A': |
| 593 | fput_const (GET_FIELD (insn, 6, 18), info); |
| 594 | break; |
| 595 | case 'Z': |
| 596 | if (GET_FIELD (insn, 26, 26)) |
| 597 | (*info->fprintf_func) (info->stream, ",m "); |
| 598 | else |
| 599 | (*info->fprintf_func) (info->stream, " "); |
| 600 | break; |
| 601 | case 'D': |
| 602 | fput_const (GET_FIELD (insn, 6, 31), info); |
| 603 | break; |
| 604 | case 'f': |
| 605 | (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25)); |
| 606 | break; |
| 607 | case 'O': |
| 608 | fput_const ((GET_FIELD (insn, 6,20) << 5 | |
| 609 | GET_FIELD (insn, 27, 31)), info); |
| 610 | break; |
| 611 | case 'o': |
| 612 | fput_const (GET_FIELD (insn, 6, 20), info); |
| 613 | break; |
| 614 | case '2': |
| 615 | fput_const ((GET_FIELD (insn, 6, 22) << 5 | |
| 616 | GET_FIELD (insn, 27, 31)), info); |
| 617 | break; |
| 618 | case '1': |
| 619 | fput_const ((GET_FIELD (insn, 11, 20) << 5 | |
| 620 | GET_FIELD (insn, 27, 31)), info); |
| 621 | break; |
| 622 | case '0': |
| 623 | fput_const ((GET_FIELD (insn, 16, 20) << 5 | |
| 624 | GET_FIELD (insn, 27, 31)), info); |
| 625 | break; |
| 626 | case 'u': |
| 627 | (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25)); |
| 628 | break; |
| 629 | case 'F': |
| 630 | /* if no destination completer and not before a completer |
| 631 | for fcmp, need a space here */ |
| 632 | if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M') |
| 633 | fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)], |
| 634 | info); |
| 635 | else |
| 636 | (*info->fprintf_func) (info->stream, "%s ", |
| 637 | float_format_names[GET_FIELD |
| 638 | (insn, 19, 20)]); |
| 639 | break; |
| 640 | case 'G': |
| 641 | (*info->fprintf_func) (info->stream, "%s ", |
| 642 | float_format_names[GET_FIELD (insn, |
| 643 | 17, 18)]); |
| 644 | break; |
| 645 | case 'H': |
| 646 | if (GET_FIELD (insn, 26, 26) == 1) |
| 647 | (*info->fprintf_func) (info->stream, "%s ", |
| 648 | float_format_names[0]); |
| 649 | else |
| 650 | (*info->fprintf_func) (info->stream, "%s ", |
| 651 | float_format_names[1]); |
| 652 | break; |
| 653 | case 'I': |
| 654 | /* if no destination completer and not before a completer |
| 655 | for fcmp, need a space here */ |
| 656 | if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M') |
| 657 | fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)], |
| 658 | info); |
| 659 | else |
| 660 | (*info->fprintf_func) (info->stream, "%s ", |
| 661 | float_format_names[GET_FIELD |
| 662 | (insn, 20, 20)]); |
| 663 | break; |
| 664 | case 'J': |
| 665 | if (GET_FIELD (insn, 24, 24)) |
| 666 | fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); |
| 667 | else |
| 668 | fput_fp_reg (GET_FIELD (insn, 6, 10), info); |
| 669 | |
| 670 | break; |
| 671 | case 'K': |
| 672 | if (GET_FIELD (insn, 19, 19)) |
| 673 | fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); |
| 674 | else |
| 675 | fput_fp_reg (GET_FIELD (insn, 11, 15), info); |
| 676 | break; |
| 677 | case 'M': |
| 678 | (*info->fprintf_func) (info->stream, "%s ", |
| 679 | float_comp_names[GET_FIELD |
| 680 | (insn, 27, 31)]); |
| 681 | break; |
| 682 | default: |
| 683 | (*info->fprintf_func) (info->stream, "%c", *s); |
| 684 | break; |
| 685 | } |
| 686 | } |
| 687 | return sizeof(insn); |
| 688 | } |
| 689 | } |
| 690 | (*info->fprintf_func) (info->stream, "#%8x", insn); |
| 691 | return sizeof(insn); |
| 692 | } |