| 1 | /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list |
| 2 | Copyright 1994, 1999, 2000, 2001, 2003, 2005, 2007 |
| 3 | Free Software Foundation, Inc. |
| 4 | PowerPC version written by Ian Lance Taylor, Cygnus Support |
| 5 | Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999 |
| 6 | |
| 7 | This file is part of the GNU opcodes library. |
| 8 | |
| 9 | This library is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this file; see the file COPYING. If not, write to the Free |
| 21 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 22 | 02110-1301, USA. */ |
| 23 | |
| 24 | #include <stdio.h> |
| 25 | #include "sysdep.h" |
| 26 | #include "opcode/i370.h" |
| 27 | |
| 28 | /* This file holds the i370 opcode table. The opcode table |
| 29 | includes almost all of the extended instruction mnemonics. This |
| 30 | permits the disassembler to use them, and simplifies the assembler |
| 31 | logic, at the cost of increasing the table size. The table is |
| 32 | strictly constant data, so the compiler should be able to put it in |
| 33 | the .text section. |
| 34 | |
| 35 | This file also holds the operand table. All knowledge about |
| 36 | inserting operands into instructions and vice-versa is kept in this |
| 37 | file. */ |
| 38 | \f |
| 39 | /* The functions used to insert and extract complicated operands. */ |
| 40 | |
| 41 | static i370_insn_t |
| 42 | insert_ss_b2 (i370_insn_t insn, long value, |
| 43 | const char **errmsg ATTRIBUTE_UNUSED) |
| 44 | { |
| 45 | insn.i[1] |= (value & 0xf) << 28; |
| 46 | return insn; |
| 47 | } |
| 48 | |
| 49 | static i370_insn_t |
| 50 | insert_ss_d2 (i370_insn_t insn, long value, |
| 51 | const char **errmsg ATTRIBUTE_UNUSED) |
| 52 | { |
| 53 | insn.i[1] |= (value & 0xfff) << 16; |
| 54 | return insn; |
| 55 | } |
| 56 | |
| 57 | static i370_insn_t |
| 58 | insert_rxf_r3 (i370_insn_t insn, long value, |
| 59 | const char **errmsg ATTRIBUTE_UNUSED) |
| 60 | { |
| 61 | insn.i[1] |= (value & 0xf) << 28; |
| 62 | return insn; |
| 63 | } |
| 64 | |
| 65 | static long |
| 66 | extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) |
| 67 | { |
| 68 | return (insn.i[1] >>28) & 0xf; |
| 69 | } |
| 70 | |
| 71 | static long |
| 72 | extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) |
| 73 | { |
| 74 | return (insn.i[1] >>16) & 0xfff; |
| 75 | } |
| 76 | |
| 77 | static long |
| 78 | extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) |
| 79 | { |
| 80 | return (insn.i[1] >>28) & 0xf; |
| 81 | } |
| 82 | \f |
| 83 | /* The operands table. |
| 84 | The fields are bits, shift, insert, extract, flags, name. |
| 85 | The types: |
| 86 | I370_OPERAND_GPR register, must name a register, must be present |
| 87 | I370_OPERAND_RELATIVE displacement or legnth field, must be present |
| 88 | I370_OPERAND_BASE base register; if present, must name a register |
| 89 | if absent, should take value of zero |
| 90 | I370_OPERAND_INDEX index register; if present, must name a register |
| 91 | if absent, should take value of zero |
| 92 | I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */ |
| 93 | |
| 94 | const struct i370_operand i370_operands[] = |
| 95 | { |
| 96 | /* The zero index is used to indicate the end of the list of |
| 97 | operands. */ |
| 98 | #define UNUSED 0 |
| 99 | { 0, 0, 0, 0, 0, "unused" }, |
| 100 | |
| 101 | /* The R1 register field in an RR form instruction. */ |
| 102 | #define RR_R1 (UNUSED + 1) |
| 103 | #define RR_R1_MASK (0xf << 4) |
| 104 | { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" }, |
| 105 | |
| 106 | /* The R2 register field in an RR form instruction. */ |
| 107 | #define RR_R2 (RR_R1 + 1) |
| 108 | #define RR_R2_MASK (0xf) |
| 109 | { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" }, |
| 110 | |
| 111 | /* The I field in an RR form SVC-style instruction. */ |
| 112 | #define RR_I (RR_R2 + 1) |
| 113 | #define RR_I_MASK (0xff) |
| 114 | { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" }, |
| 115 | |
| 116 | /* The R1 register field in an RRE form instruction. */ |
| 117 | #define RRE_R1 (RR_I + 1) |
| 118 | #define RRE_R1_MASK (0xf << 4) |
| 119 | { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" }, |
| 120 | |
| 121 | /* The R2 register field in an RRE form instruction. */ |
| 122 | #define RRE_R2 (RRE_R1 + 1) |
| 123 | #define RRE_R2_MASK (0xf) |
| 124 | { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" }, |
| 125 | |
| 126 | /* The R1 register field in an RRF form instruction. */ |
| 127 | #define RRF_R1 (RRE_R2 + 1) |
| 128 | #define RRF_R1_MASK (0xf << 4) |
| 129 | { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" }, |
| 130 | |
| 131 | /* The R2 register field in an RRF form instruction. */ |
| 132 | #define RRF_R2 (RRF_R1 + 1) |
| 133 | #define RRF_R2_MASK (0xf) |
| 134 | { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" }, |
| 135 | |
| 136 | /* The R3 register field in an RRF form instruction. */ |
| 137 | #define RRF_R3 (RRF_R2 + 1) |
| 138 | #define RRF_R3_MASK (0xf << 12) |
| 139 | { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" }, |
| 140 | |
| 141 | /* The R1 register field in an RX or RS form instruction. */ |
| 142 | #define RX_R1 (RRF_R3 + 1) |
| 143 | #define RX_R1_MASK (0xf << 20) |
| 144 | { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" }, |
| 145 | |
| 146 | /* The X2 index field in an RX form instruction. */ |
| 147 | #define RX_X2 (RX_R1 + 1) |
| 148 | #define RX_X2_MASK (0xf << 16) |
| 149 | { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"}, |
| 150 | |
| 151 | /* The B2 base field in an RX form instruction. */ |
| 152 | #define RX_B2 (RX_X2 + 1) |
| 153 | #define RX_B2_MASK (0xf << 12) |
| 154 | { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"}, |
| 155 | |
| 156 | /* The D2 displacement field in an RX form instruction. */ |
| 157 | #define RX_D2 (RX_B2 + 1) |
| 158 | #define RX_D2_MASK (0xfff) |
| 159 | { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"}, |
| 160 | |
| 161 | /* The R3 register field in an RXF form instruction. */ |
| 162 | #define RXF_R3 (RX_D2 + 1) |
| 163 | #define RXF_R3_MASK (0xf << 12) |
| 164 | { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" }, |
| 165 | |
| 166 | /* The D2 displacement field in an RS form instruction. */ |
| 167 | #define RS_D2 (RXF_R3 + 1) |
| 168 | #define RS_D2_MASK (0xfff) |
| 169 | { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"}, |
| 170 | |
| 171 | /* The R3 register field in an RS form instruction. */ |
| 172 | #define RS_R3 (RS_D2 + 1) |
| 173 | #define RS_R3_MASK (0xf << 16) |
| 174 | { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" }, |
| 175 | |
| 176 | /* The B2 base field in an RS form instruction. */ |
| 177 | #define RS_B2 (RS_R3 + 1) |
| 178 | #define RS_B2_MASK (0xf << 12) |
| 179 | { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"}, |
| 180 | |
| 181 | /* The optional B2 base field in an RS form instruction. */ |
| 182 | /* Note that this field will almost always be absent */ |
| 183 | #define RS_B2_OPT (RS_B2 + 1) |
| 184 | #define RS_B2_OPT_MASK (0xf << 12) |
| 185 | { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"}, |
| 186 | |
| 187 | /* The R1 register field in an RSI form instruction. */ |
| 188 | #define RSI_R1 (RS_B2_OPT + 1) |
| 189 | #define RSI_R1_MASK (0xf << 20) |
| 190 | { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" }, |
| 191 | |
| 192 | /* The R3 register field in an RSI form instruction. */ |
| 193 | #define RSI_R3 (RSI_R1 + 1) |
| 194 | #define RSI_R3_MASK (0xf << 16) |
| 195 | { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" }, |
| 196 | |
| 197 | /* The I2 immediate field in an RSI form instruction. */ |
| 198 | #define RSI_I2 (RSI_R3 + 1) |
| 199 | #define RSI_I2_MASK (0xffff) |
| 200 | { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" }, |
| 201 | |
| 202 | /* The R1 register field in an RI form instruction. */ |
| 203 | #define RI_R1 (RSI_I2 + 1) |
| 204 | #define RI_R1_MASK (0xf << 20) |
| 205 | { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" }, |
| 206 | |
| 207 | /* The I2 immediate field in an RI form instruction. */ |
| 208 | #define RI_I2 (RI_R1 + 1) |
| 209 | #define RI_I2_MASK (0xffff) |
| 210 | { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" }, |
| 211 | |
| 212 | /* The I2 index field in an SI form instruction. */ |
| 213 | #define SI_I2 (RI_I2 + 1) |
| 214 | #define SI_I2_MASK (0xff << 16) |
| 215 | { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"}, |
| 216 | |
| 217 | /* The B1 base register field in an SI form instruction. */ |
| 218 | #define SI_B1 (SI_I2 + 1) |
| 219 | #define SI_B1_MASK (0xf << 12) |
| 220 | { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" }, |
| 221 | |
| 222 | /* The D1 displacement field in an SI form instruction. */ |
| 223 | #define SI_D1 (SI_B1 + 1) |
| 224 | #define SI_D1_MASK (0xfff) |
| 225 | { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" }, |
| 226 | |
| 227 | /* The B2 base register field in an S form instruction. */ |
| 228 | #define S_B2 (SI_D1 + 1) |
| 229 | #define S_B2_MASK (0xf << 12) |
| 230 | { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" }, |
| 231 | |
| 232 | /* The D2 displacement field in an S form instruction. */ |
| 233 | #define S_D2 (S_B2 + 1) |
| 234 | #define S_D2_MASK (0xfff) |
| 235 | { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" }, |
| 236 | |
| 237 | /* The L length field in an SS form instruction. */ |
| 238 | #define SS_L (S_D2 + 1) |
| 239 | #define SS_L_MASK (0xffff<<16) |
| 240 | { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" }, |
| 241 | |
| 242 | /* The B1 base register field in an SS form instruction. */ |
| 243 | #define SS_B1 (SS_L + 1) |
| 244 | #define SS_B1_MASK (0xf << 12) |
| 245 | { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" }, |
| 246 | |
| 247 | /* The D1 displacement field in an SS form instruction. */ |
| 248 | #define SS_D1 (SS_B1 + 1) |
| 249 | #define SS_D1_MASK (0xfff) |
| 250 | { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" }, |
| 251 | |
| 252 | /* The B2 base register field in an SS form instruction. */ |
| 253 | #define SS_B2 (SS_D1 + 1) |
| 254 | #define SS_B2_MASK (0xf << 12) |
| 255 | { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" }, |
| 256 | |
| 257 | /* The D2 displacement field in an SS form instruction. */ |
| 258 | #define SS_D2 (SS_B2 + 1) |
| 259 | #define SS_D2_MASK (0xfff) |
| 260 | { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" }, |
| 261 | |
| 262 | }; |
| 263 | |
| 264 | \f |
| 265 | /* Macros used to form opcodes. */ |
| 266 | |
| 267 | /* The short-instruction opcode. */ |
| 268 | #define OPS(x) ((((unsigned short) (x)) & 0xff) << 8) |
| 269 | #define OPS_MASK OPS (0xff) |
| 270 | |
| 271 | /* the extended instruction opcode */ |
| 272 | #define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24) |
| 273 | #define XOPS_MASK XOPS (0xff) |
| 274 | |
| 275 | /* the S instruction opcode */ |
| 276 | #define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16) |
| 277 | #define SOPS_MASK SOPS (0xffff) |
| 278 | |
| 279 | /* the E instruction opcode */ |
| 280 | #define EOPS(x) (((unsigned short) (x)) & 0xffff) |
| 281 | #define EOPS_MASK EOPS (0xffff) |
| 282 | |
| 283 | /* the RI instruction opcode */ |
| 284 | #define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \ |
| 285 | ((((unsigned short) (x)) & 0x00f) << 16)) |
| 286 | #define ROPS_MASK ROPS (0xfff) |
| 287 | |
| 288 | \f |
| 289 | /* An E form instruction. */ |
| 290 | #define E(op) (EOPS (op)) |
| 291 | #define E_MASK E (0xffff) |
| 292 | |
| 293 | /* An RR form instruction. */ |
| 294 | #define RR(op, r1, r2) \ |
| 295 | (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ |
| 296 | ((((unsigned short) (r2)) & 0xf) )) |
| 297 | |
| 298 | #define RR_MASK RR (0xff, 0x0, 0x0) |
| 299 | |
| 300 | /* An SVC-style instruction. */ |
| 301 | #define SVC(op, i) \ |
| 302 | (OPS (op) | (((unsigned short) (i)) & 0xff)) |
| 303 | |
| 304 | #define SVC_MASK SVC (0xff, 0x0) |
| 305 | |
| 306 | /* An RRE form instruction. */ |
| 307 | #define RRE(op, r1, r2) \ |
| 308 | (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ |
| 309 | ((((unsigned short) (r2)) & 0xf) )) |
| 310 | |
| 311 | #define RRE_MASK RRE (0xffff, 0x0, 0x0) |
| 312 | |
| 313 | /* An RRF form instruction. */ |
| 314 | #define RRF(op, r3, r1, r2) \ |
| 315 | (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \ |
| 316 | ((((unsigned short) (r1)) & 0xf) << 4) | \ |
| 317 | ((((unsigned short) (r2)) & 0xf) )) |
| 318 | |
| 319 | #define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0) |
| 320 | |
| 321 | /* An RX form instruction. */ |
| 322 | #define RX(op, r1, x2, b2, d2) \ |
| 323 | (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ |
| 324 | ((((unsigned short) (x2)) & 0xf) << 16) | \ |
| 325 | ((((unsigned short) (b2)) & 0xf) << 12) | \ |
| 326 | ((((unsigned short) (d2)) & 0xfff))) |
| 327 | |
| 328 | #define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0) |
| 329 | |
| 330 | /* An RXE form instruction high word. */ |
| 331 | #define RXEH(op, r1, x2, b2, d2) \ |
| 332 | (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ |
| 333 | ((((unsigned short) (x2)) & 0xf) << 16) | \ |
| 334 | ((((unsigned short) (b2)) & 0xf) << 12) | \ |
| 335 | ((((unsigned short) (d2)) & 0xfff))) |
| 336 | |
| 337 | #define RXEH_MASK RXEH (0xff, 0, 0, 0, 0) |
| 338 | |
| 339 | /* An RXE form instruction low word. */ |
| 340 | #define RXEL(op) \ |
| 341 | ((((unsigned short) (op)) & 0xff) << 16 ) |
| 342 | |
| 343 | #define RXEL_MASK RXEL (0xff) |
| 344 | |
| 345 | /* An RXF form instruction high word. */ |
| 346 | #define RXFH(op, r1, x2, b2, d2) \ |
| 347 | (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ |
| 348 | ((((unsigned short) (x2)) & 0xf) << 16) | \ |
| 349 | ((((unsigned short) (b2)) & 0xf) << 12) | \ |
| 350 | ((((unsigned short) (d2)) & 0xfff))) |
| 351 | |
| 352 | #define RXFH_MASK RXFH (0xff, 0, 0, 0, 0) |
| 353 | |
| 354 | /* An RXF form instruction low word. */ |
| 355 | #define RXFL(op, r3) \ |
| 356 | (((((unsigned short) (r3)) & 0xf) << 28 ) | \ |
| 357 | ((((unsigned short) (op)) & 0xff) << 16 )) |
| 358 | |
| 359 | #define RXFL_MASK RXFL (0xff, 0) |
| 360 | |
| 361 | /* An RS form instruction. */ |
| 362 | #define RS(op, r1, b3, b2, d2) \ |
| 363 | (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ |
| 364 | ((((unsigned short) (b3)) & 0xf) << 16) | \ |
| 365 | ((((unsigned short) (b2)) & 0xf) << 12) | \ |
| 366 | ((((unsigned short) (d2)) & 0xfff))) |
| 367 | |
| 368 | #define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0) |
| 369 | |
| 370 | /* An RSI form instruction. */ |
| 371 | #define RSI(op, r1, r3, i2) \ |
| 372 | (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ |
| 373 | ((((unsigned short) (r3)) & 0xf) << 16) | \ |
| 374 | ((((unsigned short) (i2)) & 0xffff))) |
| 375 | |
| 376 | #define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0) |
| 377 | |
| 378 | /* An RI form instruction. */ |
| 379 | #define RI(op, r1, i2) \ |
| 380 | (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ |
| 381 | ((((unsigned short) (i2)) & 0xffff))) |
| 382 | |
| 383 | #define RI_MASK RI (0xfff, 0x0, 0x0) |
| 384 | |
| 385 | /* An SI form instruction. */ |
| 386 | #define SI(op, i2, b1, d1) \ |
| 387 | (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \ |
| 388 | ((((unsigned short) (b1)) & 0xf) << 12) | \ |
| 389 | ((((unsigned short) (d1)) & 0xfff))) |
| 390 | |
| 391 | #define SI_MASK SI (0xff, 0x0, 0x0, 0x0) |
| 392 | |
| 393 | /* An S form instruction. */ |
| 394 | #define S(op, b2, d2) \ |
| 395 | (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \ |
| 396 | ((((unsigned short)(d2)) & 0xfff))) |
| 397 | |
| 398 | #define S_MASK S (0xffff, 0x0, 0x0) |
| 399 | |
| 400 | /* An SS form instruction high word. */ |
| 401 | #define SSH(op, l, b1, d1) \ |
| 402 | (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \ |
| 403 | ((((unsigned short) (b1)) & 0xf) << 12) | \ |
| 404 | ((((unsigned short) (d1)) & 0xfff))) |
| 405 | |
| 406 | /* An SS form instruction low word. */ |
| 407 | #define SSL(b2, d2) \ |
| 408 | ( ((((unsigned short) (b1)) & 0xf) << 28) | \ |
| 409 | ((((unsigned short) (d1)) & 0xfff) << 16 )) |
| 410 | |
| 411 | #define SS_MASK SSH (0xff, 0x0, 0x0, 0x0) |
| 412 | |
| 413 | /* An SSE form instruction high word. */ |
| 414 | #define SSEH(op, b1, d1) \ |
| 415 | (SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \ |
| 416 | ((((unsigned short) (d1)) & 0xfff))) |
| 417 | |
| 418 | /* An SSE form instruction low word. */ |
| 419 | #define SSEL(b2, d2) \ |
| 420 | ( ((((unsigned short) (b1)) & 0xf) << 28) | \ |
| 421 | ((((unsigned short) (d1)) & 0xfff) << 16 )) |
| 422 | |
| 423 | #define SSE_MASK SSEH (0xffff, 0x0, 0x0) |
| 424 | |
| 425 | \f |
| 426 | /* Smaller names for the flags so each entry in the opcodes table will |
| 427 | fit on a single line. These flags are set up so that e.g. IXA means |
| 428 | the insn is supported on the 370/XA or newer architecture. |
| 429 | Note that 370 or older obsolete insn's are not supported ... */ |
| 430 | #define IBF I370_OPCODE_ESA390_BF |
| 431 | #define IBS I370_OPCODE_ESA390_BS |
| 432 | #define ICK I370_OPCODE_ESA390_CK |
| 433 | #define ICM I370_OPCODE_ESA390_CM |
| 434 | #define IFX I370_OPCODE_ESA390_FX |
| 435 | #define IHX I370_OPCODE_ESA390_HX |
| 436 | #define IIR I370_OPCODE_ESA390_IR |
| 437 | #define IMI I370_OPCODE_ESA390_MI |
| 438 | #define IPC I370_OPCODE_ESA390_PC |
| 439 | #define IPL I370_OPCODE_ESA390_PL |
| 440 | #define IQR I370_OPCODE_ESA390_QR |
| 441 | #define IRP I370_OPCODE_ESA390_RP |
| 442 | #define ISA I370_OPCODE_ESA390_SA |
| 443 | #define ISG I370_OPCODE_ESA390_SG |
| 444 | #define ISR I370_OPCODE_ESA390_SR |
| 445 | #define ITR I370_OPCODE_ESA390_SR |
| 446 | #define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390 |
| 447 | #define IESA I390 | I370_OPCODE_ESA370 |
| 448 | #define IXA IESA | I370_OPCODE_370_XA |
| 449 | #define I370 IXA | I370_OPCODE_370 |
| 450 | #define I360 I370 | I370_OPCODE_360 |
| 451 | |
| 452 | \f |
| 453 | /* The opcode table. |
| 454 | |
| 455 | The format of the opcode table is: |
| 456 | |
| 457 | NAME LEN OPCODE_HI OPCODE_LO MASK_HI MASK_LO FLAGS { OPERANDS } |
| 458 | |
| 459 | NAME is the name of the instruction. |
| 460 | OPCODE is the instruction opcode. |
| 461 | MASK is the opcode mask; this is used to tell the disassembler |
| 462 | which bits in the actual opcode must match OPCODE. |
| 463 | FLAGS are flags indicated what processors support the instruction. |
| 464 | OPERANDS is the list of operands. |
| 465 | |
| 466 | The disassembler reads the table in order and prints the first |
| 467 | instruction which matches, so this table is sorted to put more |
| 468 | specific instructions before more general instructions. It is also |
| 469 | sorted by major opcode. */ |
| 470 | |
| 471 | const struct i370_opcode i370_opcodes[] = |
| 472 | { |
| 473 | /* E form instructions */ |
| 474 | { "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} }, |
| 475 | |
| 476 | { "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} }, |
| 477 | { "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} }, |
| 478 | |
| 479 | /* RR form instructions */ |
| 480 | { "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 481 | { "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 482 | { "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 483 | { "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 484 | { "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 485 | { "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 486 | { "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 487 | { "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 488 | { "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, |
| 489 | { "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, |
| 490 | { "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, |
| 491 | { "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 492 | { "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 493 | { "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 494 | { "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 495 | { "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 496 | { "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 497 | { "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 498 | { "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 499 | { "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 500 | { "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 501 | { "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 502 | { "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 503 | { "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 504 | { "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 505 | { "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 506 | { "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 507 | { "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 508 | { "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 509 | { "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 510 | { "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 511 | { "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 512 | { "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 513 | { "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 514 | { "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 515 | { "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 516 | { "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 517 | { "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 518 | { "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 519 | { "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 520 | { "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 521 | { "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 522 | { "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 523 | { "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 524 | { "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 525 | { "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 526 | { "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 527 | { "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 528 | { "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 529 | { "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 530 | { "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 531 | { "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} }, |
| 532 | { "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 533 | { "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 534 | { "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 535 | { "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 536 | { "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, |
| 537 | |
| 538 | /* Unusual RR formats. */ |
| 539 | { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} }, |
| 540 | |
| 541 | /* RRE form instructions. */ |
| 542 | { "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 543 | { "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 544 | { "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 545 | { "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 546 | { "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} }, |
| 547 | { "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} }, |
| 548 | { "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 549 | { "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 550 | { "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 551 | { "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 552 | { "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 553 | { "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 554 | { "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} }, |
| 555 | { "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, |
| 556 | { "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 557 | { "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 558 | { "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 559 | { "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 560 | { "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 561 | { "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 562 | { "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 563 | { "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 564 | { "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 565 | { "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 566 | { "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 567 | { "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 568 | { "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, |
| 569 | { "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 570 | { "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, |
| 571 | { "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 572 | { "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 573 | { "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 574 | { "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 575 | { "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, |
| 576 | { "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, |
| 577 | { "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 578 | { "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 579 | { "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 580 | { "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 581 | { "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 582 | { "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 583 | { "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 584 | { "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 585 | { "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 586 | { "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 587 | { "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 588 | { "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 589 | { "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 590 | { "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 591 | { "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 592 | { "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 593 | { "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 594 | { "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 595 | { "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 596 | { "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 597 | { "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 598 | { "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 599 | { "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 600 | { "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 601 | { "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 602 | { "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 603 | { "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 604 | { "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 605 | { "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 606 | { "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 607 | { "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, |
| 608 | { "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, |
| 609 | { "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, |
| 610 | { "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, |
| 611 | { "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 612 | { "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 613 | { "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 614 | { "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 615 | { "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} }, |
| 616 | { "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} }, |
| 617 | { "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 618 | { "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, |
| 619 | { "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 620 | { "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 621 | { "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} }, |
| 622 | { "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} }, |
| 623 | { "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 624 | { "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 625 | { "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 626 | { "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 627 | { "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 628 | { "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 629 | { "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 630 | { "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 631 | { "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, |
| 632 | { "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 633 | { "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, |
| 634 | { "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 635 | { "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, |
| 636 | { "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, |
| 637 | { "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, |
| 638 | { "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 639 | { "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 640 | { "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, |
| 641 | { "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, |
| 642 | { "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, |
| 643 | { "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, |
| 644 | { "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, |
| 645 | |
| 646 | /* RRF form instructions. */ |
| 647 | { "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 648 | { "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, |
| 649 | { "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 650 | { "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, |
| 651 | { "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 652 | { "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, |
| 653 | { "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 654 | { "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 655 | { "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 656 | { "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 657 | { "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 658 | { "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 659 | { "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 660 | { "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 661 | { "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, |
| 662 | { "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, |
| 663 | { "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, |
| 664 | |
| 665 | /* RX form instructions. */ |
| 666 | { "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 667 | { "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 668 | { "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 669 | { "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 670 | { "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 671 | { "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 672 | { "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 673 | { "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 674 | { "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 675 | { "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 676 | { "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 677 | { "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 678 | { "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 679 | { "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 680 | { "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 681 | { "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 682 | { "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 683 | { "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 684 | { "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 685 | { "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 686 | { "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 687 | { "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 688 | { "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 689 | { "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 690 | { "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 691 | { "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 692 | { "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 693 | { "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 694 | { "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 695 | { "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 696 | { "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 697 | { "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 698 | { "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 699 | { "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 700 | { "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 701 | { "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 702 | { "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 703 | { "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 704 | { "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 705 | { "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 706 | { "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 707 | { "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 708 | { "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 709 | { "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 710 | { "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 711 | { "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 712 | { "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 713 | { "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 714 | { "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 715 | { "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 716 | { "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 717 | |
| 718 | /* RXE form instructions. */ |
| 719 | { "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 720 | { "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 721 | { "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 722 | { "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 723 | { "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 724 | { "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 725 | { "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 726 | { "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 727 | { "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 728 | { "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 729 | { "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 730 | { "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 731 | { "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 732 | { "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 733 | { "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 734 | { "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 735 | { "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 736 | { "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 737 | { "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 738 | { "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 739 | { "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 740 | { "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 741 | { "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 742 | { "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 743 | { "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 744 | { "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 745 | { "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 746 | { "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, |
| 747 | |
| 748 | /* RXF form instructions. */ |
| 749 | { "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, |
| 750 | { "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, |
| 751 | { "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, |
| 752 | { "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, |
| 753 | |
| 754 | /* RS form instructions. */ |
| 755 | { "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 756 | { "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 757 | { "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 758 | { "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 759 | { "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 760 | { "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 761 | { "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 762 | { "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 763 | { "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 764 | { "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 765 | { "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 766 | { "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 767 | { "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 768 | { "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 769 | { "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 770 | { "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 771 | { "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, |
| 772 | |
| 773 | /* RS form instructions with blank R3 and optional B2 (shift left/right). */ |
| 774 | { "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 775 | { "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 776 | { "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 777 | { "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 778 | { "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 779 | { "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 780 | { "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 781 | { "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, |
| 782 | |
| 783 | /* RSI form instructions. */ |
| 784 | { "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, |
| 785 | { "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, |
| 786 | |
| 787 | /* RI form instructions. */ |
| 788 | { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 789 | { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 790 | { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 791 | { "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 792 | { "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 793 | { "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 794 | { "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 795 | { "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 796 | { "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, |
| 797 | |
| 798 | /* SI form instructions. */ |
| 799 | { "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 800 | { "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 801 | { "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 802 | { "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 803 | { "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 804 | { "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, |
| 805 | { "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, |
| 806 | { "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 807 | { "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, |
| 808 | |
| 809 | /* S form instructions. */ |
| 810 | { "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 811 | { "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 812 | { "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 813 | { "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 814 | { "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, |
| 815 | { "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, |
| 816 | { "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 817 | { "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 818 | { "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} }, |
| 819 | { "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 820 | { "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 821 | { "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} }, |
| 822 | { "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 823 | { "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 824 | { "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} }, |
| 825 | { "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 826 | { "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, |
| 827 | { "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, |
| 828 | { "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 829 | { "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 830 | { "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 831 | { "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 832 | { "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, |
| 833 | { "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 834 | { "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, |
| 835 | { "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 836 | { "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 837 | { "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, |
| 838 | { "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 839 | { "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 840 | { "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, |
| 841 | { "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, |
| 842 | { "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 843 | { "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 844 | { "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 845 | { "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 846 | { "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} }, |
| 847 | { "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, |
| 848 | { "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, |
| 849 | |
| 850 | /* SS form instructions. */ |
| 851 | { "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 852 | { "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 853 | { "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 854 | { "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 855 | { "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 856 | { "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 857 | { "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 858 | { "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 859 | { "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 860 | { "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 861 | { "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 862 | { "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 863 | { "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 864 | { "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 865 | { "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 866 | { "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 867 | { "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 868 | { "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 869 | { "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 870 | { "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 871 | { "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 872 | { "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 873 | { "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 874 | { "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 875 | { "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, |
| 876 | |
| 877 | /* SSE form instructions. */ |
| 878 | { "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, |
| 879 | { "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, |
| 880 | { "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, |
| 881 | { "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, |
| 882 | |
| 883 | /* */ |
| 884 | }; |
| 885 | |
| 886 | const int i370_num_opcodes = |
| 887 | sizeof (i370_opcodes) / sizeof (i370_opcodes[0]); |
| 888 | \f |
| 889 | /* The macro table. This is only used by the assembler. */ |
| 890 | |
| 891 | const struct i370_macro i370_macros[] = |
| 892 | { |
| 893 | { "b", 1, I370, "bc 15,%0" }, |
| 894 | { "br", 1, I370, "bcr 15,%0" }, |
| 895 | |
| 896 | { "nop", 1, I370, "bc 0,%0" }, |
| 897 | { "nopr", 1, I370, "bcr 0,%0" }, |
| 898 | |
| 899 | { "bh", 1, I370, "bc 2,%0" }, |
| 900 | { "bhr", 1, I370, "bcr 2,%0" }, |
| 901 | { "bl", 1, I370, "bc 4,%0" }, |
| 902 | { "blr", 1, I370, "bcr 4,%0" }, |
| 903 | { "be", 1, I370, "bc 8,%0" }, |
| 904 | { "ber", 1, I370, "bcr 8,%0" }, |
| 905 | |
| 906 | { "bnh", 1, I370, "bc 13,%0" }, |
| 907 | { "bnhr", 1, I370, "bcr 13,%0" }, |
| 908 | { "bnl", 1, I370, "bc 11,%0" }, |
| 909 | { "bnlr", 1, I370, "bcr 11,%0" }, |
| 910 | { "bne", 1, I370, "bc 7,%0" }, |
| 911 | { "bner", 1, I370, "bcr 7,%0" }, |
| 912 | |
| 913 | { "bp", 1, I370, "bc 2,%0" }, |
| 914 | { "bpr", 1, I370, "bcr 2,%0" }, |
| 915 | { "bm", 1, I370, "bc 4,%0" }, |
| 916 | { "bmr", 1, I370, "bcr 4,%0" }, |
| 917 | { "bz", 1, I370, "bc 8,%0" }, |
| 918 | { "bzr", 1, I370, "bcr 8,%0" }, |
| 919 | { "bo", 1, I370, "bc 1,%0" }, |
| 920 | { "bor", 1, I370, "bcr 1,%0" }, |
| 921 | |
| 922 | { "bnp", 1, I370, "bc 13,%0" }, |
| 923 | { "bnpr", 1, I370, "bcr 13,%0" }, |
| 924 | { "bnm", 1, I370, "bc 11,%0" }, |
| 925 | { "bnmr", 1, I370, "bcr 11,%0" }, |
| 926 | { "bnz", 1, I370, "bc 7,%0" }, |
| 927 | { "bnzr", 1, I370, "bcr 7,%0" }, |
| 928 | { "bno", 1, I370, "bc 14,%0" }, |
| 929 | { "bnor", 1, I370, "bcr 14,%0" }, |
| 930 | |
| 931 | { "sync", 0, I370, "bcr 15,0" }, |
| 932 | |
| 933 | }; |
| 934 | |
| 935 | const int i370_num_macros = |
| 936 | sizeof (i370_macros) / sizeof (i370_macros[0]); |