| 1 | /* Print i386 instructions for GDB, the GNU debugger. |
| 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
| 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
| 4 | Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of the GNU opcodes library. |
| 7 | |
| 8 | This library is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3, or (at your option) |
| 11 | any later version. |
| 12 | |
| 13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 16 | License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 21 | MA 02110-1301, USA. */ |
| 22 | |
| 23 | |
| 24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) |
| 25 | July 1988 |
| 26 | modified by John Hassey (hassey@dg-rtp.dg.com) |
| 27 | x86-64 support added by Jan Hubicka (jh@suse.cz) |
| 28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ |
| 29 | |
| 30 | /* The main tables describing the instructions is essentially a copy |
| 31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 |
| 32 | Programmers Manual. Usually, there is a capital letter, followed |
| 33 | by a small letter. The capital letter tell the addressing mode, |
| 34 | and the small letter tells about the operand size. Refer to |
| 35 | the Intel manual for details. */ |
| 36 | |
| 37 | #include "sysdep.h" |
| 38 | #include "dis-asm.h" |
| 39 | #include "opintl.h" |
| 40 | #include "opcode/i386.h" |
| 41 | #include "libiberty.h" |
| 42 | |
| 43 | #include <setjmp.h> |
| 44 | |
| 45 | static int print_insn (bfd_vma, disassemble_info *); |
| 46 | static void dofloat (int); |
| 47 | static void OP_ST (int, int); |
| 48 | static void OP_STi (int, int); |
| 49 | static int putop (const char *, int); |
| 50 | static void oappend (const char *); |
| 51 | static void append_seg (void); |
| 52 | static void OP_indirE (int, int); |
| 53 | static void print_operand_value (char *, int, bfd_vma); |
| 54 | static void OP_E_register (int, int); |
| 55 | static void OP_E_memory (int, int); |
| 56 | static void print_displacement (char *, bfd_vma); |
| 57 | static void OP_E (int, int); |
| 58 | static void OP_G (int, int); |
| 59 | static bfd_vma get64 (void); |
| 60 | static bfd_signed_vma get32 (void); |
| 61 | static bfd_signed_vma get32s (void); |
| 62 | static int get16 (void); |
| 63 | static void set_op (bfd_vma, int); |
| 64 | static void OP_Skip_MODRM (int, int); |
| 65 | static void OP_REG (int, int); |
| 66 | static void OP_IMREG (int, int); |
| 67 | static void OP_I (int, int); |
| 68 | static void OP_I64 (int, int); |
| 69 | static void OP_sI (int, int); |
| 70 | static void OP_J (int, int); |
| 71 | static void OP_SEG (int, int); |
| 72 | static void OP_DIR (int, int); |
| 73 | static void OP_OFF (int, int); |
| 74 | static void OP_OFF64 (int, int); |
| 75 | static void ptr_reg (int, int); |
| 76 | static void OP_ESreg (int, int); |
| 77 | static void OP_DSreg (int, int); |
| 78 | static void OP_C (int, int); |
| 79 | static void OP_D (int, int); |
| 80 | static void OP_T (int, int); |
| 81 | static void OP_R (int, int); |
| 82 | static void OP_MMX (int, int); |
| 83 | static void OP_XMM (int, int); |
| 84 | static void OP_EM (int, int); |
| 85 | static void OP_EX (int, int); |
| 86 | static void OP_EMC (int,int); |
| 87 | static void OP_MXC (int,int); |
| 88 | static void OP_MS (int, int); |
| 89 | static void OP_XS (int, int); |
| 90 | static void OP_M (int, int); |
| 91 | static void OP_VEX (int, int); |
| 92 | static void OP_EX_Vex (int, int); |
| 93 | static void OP_EX_VexW (int, int); |
| 94 | static void OP_EX_VexImmW (int, int); |
| 95 | static void OP_XMM_Vex (int, int); |
| 96 | static void OP_XMM_VexW (int, int); |
| 97 | static void OP_REG_VexI4 (int, int); |
| 98 | static void PCLMUL_Fixup (int, int); |
| 99 | static void VEXI4_Fixup (int, int); |
| 100 | static void VZERO_Fixup (int, int); |
| 101 | static void VCMP_Fixup (int, int); |
| 102 | static void OP_0f07 (int, int); |
| 103 | static void OP_Monitor (int, int); |
| 104 | static void OP_Mwait (int, int); |
| 105 | static void NOP_Fixup1 (int, int); |
| 106 | static void NOP_Fixup2 (int, int); |
| 107 | static void OP_3DNowSuffix (int, int); |
| 108 | static void CMP_Fixup (int, int); |
| 109 | static void BadOp (void); |
| 110 | static void REP_Fixup (int, int); |
| 111 | static void HLE_Fixup1 (int, int); |
| 112 | static void HLE_Fixup2 (int, int); |
| 113 | static void HLE_Fixup3 (int, int); |
| 114 | static void CMPXCHG8B_Fixup (int, int); |
| 115 | static void XMM_Fixup (int, int); |
| 116 | static void CRC32_Fixup (int, int); |
| 117 | static void FXSAVE_Fixup (int, int); |
| 118 | static void OP_LWPCB_E (int, int); |
| 119 | static void OP_LWP_E (int, int); |
| 120 | static void OP_Vex_2src_1 (int, int); |
| 121 | static void OP_Vex_2src_2 (int, int); |
| 122 | |
| 123 | static void MOVBE_Fixup (int, int); |
| 124 | |
| 125 | struct dis_private { |
| 126 | /* Points to first byte not fetched. */ |
| 127 | bfd_byte *max_fetched; |
| 128 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
| 129 | bfd_vma insn_start; |
| 130 | int orig_sizeflag; |
| 131 | jmp_buf bailout; |
| 132 | }; |
| 133 | |
| 134 | enum address_mode |
| 135 | { |
| 136 | mode_16bit, |
| 137 | mode_32bit, |
| 138 | mode_64bit |
| 139 | }; |
| 140 | |
| 141 | enum address_mode address_mode; |
| 142 | |
| 143 | /* Flags for the prefixes for the current instruction. See below. */ |
| 144 | static int prefixes; |
| 145 | |
| 146 | /* REX prefix the current instruction. See below. */ |
| 147 | static int rex; |
| 148 | /* Bits of REX we've already used. */ |
| 149 | static int rex_used; |
| 150 | /* REX bits in original REX prefix ignored. */ |
| 151 | static int rex_ignored; |
| 152 | /* Mark parts used in the REX prefix. When we are testing for |
| 153 | empty prefix (for 8bit register REX extension), just mask it |
| 154 | out. Otherwise test for REX bit is excuse for existence of REX |
| 155 | only in case value is nonzero. */ |
| 156 | #define USED_REX(value) \ |
| 157 | { \ |
| 158 | if (value) \ |
| 159 | { \ |
| 160 | if ((rex & value)) \ |
| 161 | rex_used |= (value) | REX_OPCODE; \ |
| 162 | } \ |
| 163 | else \ |
| 164 | rex_used |= REX_OPCODE; \ |
| 165 | } |
| 166 | |
| 167 | /* Flags for prefixes which we somehow handled when printing the |
| 168 | current instruction. */ |
| 169 | static int used_prefixes; |
| 170 | |
| 171 | /* Flags stored in PREFIXES. */ |
| 172 | #define PREFIX_REPZ 1 |
| 173 | #define PREFIX_REPNZ 2 |
| 174 | #define PREFIX_LOCK 4 |
| 175 | #define PREFIX_CS 8 |
| 176 | #define PREFIX_SS 0x10 |
| 177 | #define PREFIX_DS 0x20 |
| 178 | #define PREFIX_ES 0x40 |
| 179 | #define PREFIX_FS 0x80 |
| 180 | #define PREFIX_GS 0x100 |
| 181 | #define PREFIX_DATA 0x200 |
| 182 | #define PREFIX_ADDR 0x400 |
| 183 | #define PREFIX_FWAIT 0x800 |
| 184 | |
| 185 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
| 186 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps |
| 187 | on error. */ |
| 188 | #define FETCH_DATA(info, addr) \ |
| 189 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
| 190 | ? 1 : fetch_data ((info), (addr))) |
| 191 | |
| 192 | static int |
| 193 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
| 194 | { |
| 195 | int status; |
| 196 | struct dis_private *priv = (struct dis_private *) info->private_data; |
| 197 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
| 198 | |
| 199 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
| 200 | status = (*info->read_memory_func) (start, |
| 201 | priv->max_fetched, |
| 202 | addr - priv->max_fetched, |
| 203 | info); |
| 204 | else |
| 205 | status = -1; |
| 206 | if (status != 0) |
| 207 | { |
| 208 | /* If we did manage to read at least one byte, then |
| 209 | print_insn_i386 will do something sensible. Otherwise, print |
| 210 | an error. We do that here because this is where we know |
| 211 | STATUS. */ |
| 212 | if (priv->max_fetched == priv->the_buffer) |
| 213 | (*info->memory_error_func) (status, start, info); |
| 214 | longjmp (priv->bailout, 1); |
| 215 | } |
| 216 | else |
| 217 | priv->max_fetched = addr; |
| 218 | return 1; |
| 219 | } |
| 220 | |
| 221 | #define XX { NULL, 0 } |
| 222 | #define Bad_Opcode NULL, { { NULL, 0 } } |
| 223 | |
| 224 | #define Eb { OP_E, b_mode } |
| 225 | #define EbS { OP_E, b_swap_mode } |
| 226 | #define Ev { OP_E, v_mode } |
| 227 | #define EvS { OP_E, v_swap_mode } |
| 228 | #define Ed { OP_E, d_mode } |
| 229 | #define Edq { OP_E, dq_mode } |
| 230 | #define Edqw { OP_E, dqw_mode } |
| 231 | #define Edqb { OP_E, dqb_mode } |
| 232 | #define Edqd { OP_E, dqd_mode } |
| 233 | #define Eq { OP_E, q_mode } |
| 234 | #define indirEv { OP_indirE, stack_v_mode } |
| 235 | #define indirEp { OP_indirE, f_mode } |
| 236 | #define stackEv { OP_E, stack_v_mode } |
| 237 | #define Em { OP_E, m_mode } |
| 238 | #define Ew { OP_E, w_mode } |
| 239 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ |
| 240 | #define Ma { OP_M, a_mode } |
| 241 | #define Mb { OP_M, b_mode } |
| 242 | #define Md { OP_M, d_mode } |
| 243 | #define Mo { OP_M, o_mode } |
| 244 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
| 245 | #define Mq { OP_M, q_mode } |
| 246 | #define Mx { OP_M, x_mode } |
| 247 | #define Mxmm { OP_M, xmm_mode } |
| 248 | #define Gb { OP_G, b_mode } |
| 249 | #define Gv { OP_G, v_mode } |
| 250 | #define Gd { OP_G, d_mode } |
| 251 | #define Gdq { OP_G, dq_mode } |
| 252 | #define Gm { OP_G, m_mode } |
| 253 | #define Gw { OP_G, w_mode } |
| 254 | #define Rd { OP_R, d_mode } |
| 255 | #define Rm { OP_R, m_mode } |
| 256 | #define Ib { OP_I, b_mode } |
| 257 | #define sIb { OP_sI, b_mode } /* sign extened byte */ |
| 258 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
| 259 | #define Iv { OP_I, v_mode } |
| 260 | #define sIv { OP_sI, v_mode } |
| 261 | #define Iq { OP_I, q_mode } |
| 262 | #define Iv64 { OP_I64, v_mode } |
| 263 | #define Iw { OP_I, w_mode } |
| 264 | #define I1 { OP_I, const_1_mode } |
| 265 | #define Jb { OP_J, b_mode } |
| 266 | #define Jv { OP_J, v_mode } |
| 267 | #define Cm { OP_C, m_mode } |
| 268 | #define Dm { OP_D, m_mode } |
| 269 | #define Td { OP_T, d_mode } |
| 270 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
| 271 | |
| 272 | #define RMeAX { OP_REG, eAX_reg } |
| 273 | #define RMeBX { OP_REG, eBX_reg } |
| 274 | #define RMeCX { OP_REG, eCX_reg } |
| 275 | #define RMeDX { OP_REG, eDX_reg } |
| 276 | #define RMeSP { OP_REG, eSP_reg } |
| 277 | #define RMeBP { OP_REG, eBP_reg } |
| 278 | #define RMeSI { OP_REG, eSI_reg } |
| 279 | #define RMeDI { OP_REG, eDI_reg } |
| 280 | #define RMrAX { OP_REG, rAX_reg } |
| 281 | #define RMrBX { OP_REG, rBX_reg } |
| 282 | #define RMrCX { OP_REG, rCX_reg } |
| 283 | #define RMrDX { OP_REG, rDX_reg } |
| 284 | #define RMrSP { OP_REG, rSP_reg } |
| 285 | #define RMrBP { OP_REG, rBP_reg } |
| 286 | #define RMrSI { OP_REG, rSI_reg } |
| 287 | #define RMrDI { OP_REG, rDI_reg } |
| 288 | #define RMAL { OP_REG, al_reg } |
| 289 | #define RMCL { OP_REG, cl_reg } |
| 290 | #define RMDL { OP_REG, dl_reg } |
| 291 | #define RMBL { OP_REG, bl_reg } |
| 292 | #define RMAH { OP_REG, ah_reg } |
| 293 | #define RMCH { OP_REG, ch_reg } |
| 294 | #define RMDH { OP_REG, dh_reg } |
| 295 | #define RMBH { OP_REG, bh_reg } |
| 296 | #define RMAX { OP_REG, ax_reg } |
| 297 | #define RMDX { OP_REG, dx_reg } |
| 298 | |
| 299 | #define eAX { OP_IMREG, eAX_reg } |
| 300 | #define eBX { OP_IMREG, eBX_reg } |
| 301 | #define eCX { OP_IMREG, eCX_reg } |
| 302 | #define eDX { OP_IMREG, eDX_reg } |
| 303 | #define eSP { OP_IMREG, eSP_reg } |
| 304 | #define eBP { OP_IMREG, eBP_reg } |
| 305 | #define eSI { OP_IMREG, eSI_reg } |
| 306 | #define eDI { OP_IMREG, eDI_reg } |
| 307 | #define AL { OP_IMREG, al_reg } |
| 308 | #define CL { OP_IMREG, cl_reg } |
| 309 | #define DL { OP_IMREG, dl_reg } |
| 310 | #define BL { OP_IMREG, bl_reg } |
| 311 | #define AH { OP_IMREG, ah_reg } |
| 312 | #define CH { OP_IMREG, ch_reg } |
| 313 | #define DH { OP_IMREG, dh_reg } |
| 314 | #define BH { OP_IMREG, bh_reg } |
| 315 | #define AX { OP_IMREG, ax_reg } |
| 316 | #define DX { OP_IMREG, dx_reg } |
| 317 | #define zAX { OP_IMREG, z_mode_ax_reg } |
| 318 | #define indirDX { OP_IMREG, indir_dx_reg } |
| 319 | |
| 320 | #define Sw { OP_SEG, w_mode } |
| 321 | #define Sv { OP_SEG, v_mode } |
| 322 | #define Ap { OP_DIR, 0 } |
| 323 | #define Ob { OP_OFF64, b_mode } |
| 324 | #define Ov { OP_OFF64, v_mode } |
| 325 | #define Xb { OP_DSreg, eSI_reg } |
| 326 | #define Xv { OP_DSreg, eSI_reg } |
| 327 | #define Xz { OP_DSreg, eSI_reg } |
| 328 | #define Yb { OP_ESreg, eDI_reg } |
| 329 | #define Yv { OP_ESreg, eDI_reg } |
| 330 | #define DSBX { OP_DSreg, eBX_reg } |
| 331 | |
| 332 | #define es { OP_REG, es_reg } |
| 333 | #define ss { OP_REG, ss_reg } |
| 334 | #define cs { OP_REG, cs_reg } |
| 335 | #define ds { OP_REG, ds_reg } |
| 336 | #define fs { OP_REG, fs_reg } |
| 337 | #define gs { OP_REG, gs_reg } |
| 338 | |
| 339 | #define MX { OP_MMX, 0 } |
| 340 | #define XM { OP_XMM, 0 } |
| 341 | #define XMScalar { OP_XMM, scalar_mode } |
| 342 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
| 343 | #define XMM { OP_XMM, xmm_mode } |
| 344 | #define EM { OP_EM, v_mode } |
| 345 | #define EMS { OP_EM, v_swap_mode } |
| 346 | #define EMd { OP_EM, d_mode } |
| 347 | #define EMx { OP_EM, x_mode } |
| 348 | #define EXw { OP_EX, w_mode } |
| 349 | #define EXd { OP_EX, d_mode } |
| 350 | #define EXdScalar { OP_EX, d_scalar_mode } |
| 351 | #define EXdS { OP_EX, d_swap_mode } |
| 352 | #define EXq { OP_EX, q_mode } |
| 353 | #define EXqScalar { OP_EX, q_scalar_mode } |
| 354 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } |
| 355 | #define EXqS { OP_EX, q_swap_mode } |
| 356 | #define EXx { OP_EX, x_mode } |
| 357 | #define EXxS { OP_EX, x_swap_mode } |
| 358 | #define EXxmm { OP_EX, xmm_mode } |
| 359 | #define EXxmmq { OP_EX, xmmq_mode } |
| 360 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
| 361 | #define EXxmm_mw { OP_EX, xmm_mw_mode } |
| 362 | #define EXxmm_md { OP_EX, xmm_md_mode } |
| 363 | #define EXxmm_mq { OP_EX, xmm_mq_mode } |
| 364 | #define EXxmmdw { OP_EX, xmmdw_mode } |
| 365 | #define EXxmmqd { OP_EX, xmmqd_mode } |
| 366 | #define EXymmq { OP_EX, ymmq_mode } |
| 367 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
| 368 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
| 369 | #define MS { OP_MS, v_mode } |
| 370 | #define XS { OP_XS, v_mode } |
| 371 | #define EMCq { OP_EMC, q_mode } |
| 372 | #define MXC { OP_MXC, 0 } |
| 373 | #define OPSUF { OP_3DNowSuffix, 0 } |
| 374 | #define CMP { CMP_Fixup, 0 } |
| 375 | #define XMM0 { XMM_Fixup, 0 } |
| 376 | #define FXSAVE { FXSAVE_Fixup, 0 } |
| 377 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
| 378 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } |
| 379 | |
| 380 | #define Vex { OP_VEX, vex_mode } |
| 381 | #define VexScalar { OP_VEX, vex_scalar_mode } |
| 382 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
| 383 | #define Vex128 { OP_VEX, vex128_mode } |
| 384 | #define Vex256 { OP_VEX, vex256_mode } |
| 385 | #define VexGdq { OP_VEX, dq_mode } |
| 386 | #define VexI4 { VEXI4_Fixup, 0} |
| 387 | #define EXdVex { OP_EX_Vex, d_mode } |
| 388 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
| 389 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
| 390 | #define EXqVex { OP_EX_Vex, q_mode } |
| 391 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
| 392 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
| 393 | #define EXVexW { OP_EX_VexW, x_mode } |
| 394 | #define EXdVexW { OP_EX_VexW, d_mode } |
| 395 | #define EXqVexW { OP_EX_VexW, q_mode } |
| 396 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
| 397 | #define XMVex { OP_XMM_Vex, 0 } |
| 398 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
| 399 | #define XMVexW { OP_XMM_VexW, 0 } |
| 400 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
| 401 | #define PCLMUL { PCLMUL_Fixup, 0 } |
| 402 | #define VZERO { VZERO_Fixup, 0 } |
| 403 | #define VCMP { VCMP_Fixup, 0 } |
| 404 | |
| 405 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
| 406 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
| 407 | |
| 408 | /* Used handle "rep" prefix for string instructions. */ |
| 409 | #define Xbr { REP_Fixup, eSI_reg } |
| 410 | #define Xvr { REP_Fixup, eSI_reg } |
| 411 | #define Ybr { REP_Fixup, eDI_reg } |
| 412 | #define Yvr { REP_Fixup, eDI_reg } |
| 413 | #define Yzr { REP_Fixup, eDI_reg } |
| 414 | #define indirDXr { REP_Fixup, indir_dx_reg } |
| 415 | #define ALr { REP_Fixup, al_reg } |
| 416 | #define eAXr { REP_Fixup, eAX_reg } |
| 417 | |
| 418 | /* Used handle HLE prefix for lockable instructions. */ |
| 419 | #define Ebh1 { HLE_Fixup1, b_mode } |
| 420 | #define Evh1 { HLE_Fixup1, v_mode } |
| 421 | #define Ebh2 { HLE_Fixup2, b_mode } |
| 422 | #define Evh2 { HLE_Fixup2, v_mode } |
| 423 | #define Ebh3 { HLE_Fixup3, b_mode } |
| 424 | #define Evh3 { HLE_Fixup3, v_mode } |
| 425 | |
| 426 | #define cond_jump_flag { NULL, cond_jump_mode } |
| 427 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } |
| 428 | |
| 429 | /* bits in sizeflag */ |
| 430 | #define SUFFIX_ALWAYS 4 |
| 431 | #define AFLAG 2 |
| 432 | #define DFLAG 1 |
| 433 | |
| 434 | enum |
| 435 | { |
| 436 | /* byte operand */ |
| 437 | b_mode = 1, |
| 438 | /* byte operand with operand swapped */ |
| 439 | b_swap_mode, |
| 440 | /* byte operand, sign extend like 'T' suffix */ |
| 441 | b_T_mode, |
| 442 | /* operand size depends on prefixes */ |
| 443 | v_mode, |
| 444 | /* operand size depends on prefixes with operand swapped */ |
| 445 | v_swap_mode, |
| 446 | /* word operand */ |
| 447 | w_mode, |
| 448 | /* double word operand */ |
| 449 | d_mode, |
| 450 | /* double word operand with operand swapped */ |
| 451 | d_swap_mode, |
| 452 | /* quad word operand */ |
| 453 | q_mode, |
| 454 | /* quad word operand with operand swapped */ |
| 455 | q_swap_mode, |
| 456 | /* ten-byte operand */ |
| 457 | t_mode, |
| 458 | /* 16-byte XMM or 32-byte YMM operand */ |
| 459 | x_mode, |
| 460 | /* 16-byte XMM or 32-byte YMM operand with operand swapped */ |
| 461 | x_swap_mode, |
| 462 | /* 16-byte XMM operand */ |
| 463 | xmm_mode, |
| 464 | /* 16-byte XMM or quad word operand */ |
| 465 | xmmq_mode, |
| 466 | /* XMM register or byte memory operand */ |
| 467 | xmm_mb_mode, |
| 468 | /* XMM register or word memory operand */ |
| 469 | xmm_mw_mode, |
| 470 | /* XMM register or double word memory operand */ |
| 471 | xmm_md_mode, |
| 472 | /* XMM register or quad word memory operand */ |
| 473 | xmm_mq_mode, |
| 474 | /* 16-byte XMM, word or double word operand */ |
| 475 | xmmdw_mode, |
| 476 | /* 16-byte XMM, double word or quad word operand */ |
| 477 | xmmqd_mode, |
| 478 | /* 32-byte YMM or quad word operand */ |
| 479 | ymmq_mode, |
| 480 | /* 32-byte YMM or 16-byte word operand */ |
| 481 | ymmxmm_mode, |
| 482 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
| 483 | m_mode, |
| 484 | /* pair of v_mode operands */ |
| 485 | a_mode, |
| 486 | cond_jump_mode, |
| 487 | loop_jcxz_mode, |
| 488 | /* operand size depends on REX prefixes. */ |
| 489 | dq_mode, |
| 490 | /* registers like dq_mode, memory like w_mode. */ |
| 491 | dqw_mode, |
| 492 | /* 4- or 6-byte pointer operand */ |
| 493 | f_mode, |
| 494 | const_1_mode, |
| 495 | /* v_mode for stack-related opcodes. */ |
| 496 | stack_v_mode, |
| 497 | /* non-quad operand size depends on prefixes */ |
| 498 | z_mode, |
| 499 | /* 16-byte operand */ |
| 500 | o_mode, |
| 501 | /* registers like dq_mode, memory like b_mode. */ |
| 502 | dqb_mode, |
| 503 | /* registers like dq_mode, memory like d_mode. */ |
| 504 | dqd_mode, |
| 505 | /* normal vex mode */ |
| 506 | vex_mode, |
| 507 | /* 128bit vex mode */ |
| 508 | vex128_mode, |
| 509 | /* 256bit vex mode */ |
| 510 | vex256_mode, |
| 511 | /* operand size depends on the VEX.W bit. */ |
| 512 | vex_w_dq_mode, |
| 513 | |
| 514 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
| 515 | vex_vsib_d_w_dq_mode, |
| 516 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
| 517 | vex_vsib_q_w_dq_mode, |
| 518 | |
| 519 | /* scalar, ignore vector length. */ |
| 520 | scalar_mode, |
| 521 | /* like d_mode, ignore vector length. */ |
| 522 | d_scalar_mode, |
| 523 | /* like d_swap_mode, ignore vector length. */ |
| 524 | d_scalar_swap_mode, |
| 525 | /* like q_mode, ignore vector length. */ |
| 526 | q_scalar_mode, |
| 527 | /* like q_swap_mode, ignore vector length. */ |
| 528 | q_scalar_swap_mode, |
| 529 | /* like vex_mode, ignore vector length. */ |
| 530 | vex_scalar_mode, |
| 531 | /* like vex_w_dq_mode, ignore vector length. */ |
| 532 | vex_scalar_w_dq_mode, |
| 533 | |
| 534 | es_reg, |
| 535 | cs_reg, |
| 536 | ss_reg, |
| 537 | ds_reg, |
| 538 | fs_reg, |
| 539 | gs_reg, |
| 540 | |
| 541 | eAX_reg, |
| 542 | eCX_reg, |
| 543 | eDX_reg, |
| 544 | eBX_reg, |
| 545 | eSP_reg, |
| 546 | eBP_reg, |
| 547 | eSI_reg, |
| 548 | eDI_reg, |
| 549 | |
| 550 | al_reg, |
| 551 | cl_reg, |
| 552 | dl_reg, |
| 553 | bl_reg, |
| 554 | ah_reg, |
| 555 | ch_reg, |
| 556 | dh_reg, |
| 557 | bh_reg, |
| 558 | |
| 559 | ax_reg, |
| 560 | cx_reg, |
| 561 | dx_reg, |
| 562 | bx_reg, |
| 563 | sp_reg, |
| 564 | bp_reg, |
| 565 | si_reg, |
| 566 | di_reg, |
| 567 | |
| 568 | rAX_reg, |
| 569 | rCX_reg, |
| 570 | rDX_reg, |
| 571 | rBX_reg, |
| 572 | rSP_reg, |
| 573 | rBP_reg, |
| 574 | rSI_reg, |
| 575 | rDI_reg, |
| 576 | |
| 577 | z_mode_ax_reg, |
| 578 | indir_dx_reg |
| 579 | }; |
| 580 | |
| 581 | enum |
| 582 | { |
| 583 | FLOATCODE = 1, |
| 584 | USE_REG_TABLE, |
| 585 | USE_MOD_TABLE, |
| 586 | USE_RM_TABLE, |
| 587 | USE_PREFIX_TABLE, |
| 588 | USE_X86_64_TABLE, |
| 589 | USE_3BYTE_TABLE, |
| 590 | USE_XOP_8F_TABLE, |
| 591 | USE_VEX_C4_TABLE, |
| 592 | USE_VEX_C5_TABLE, |
| 593 | USE_VEX_LEN_TABLE, |
| 594 | USE_VEX_W_TABLE |
| 595 | }; |
| 596 | |
| 597 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
| 598 | |
| 599 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
| 600 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
| 601 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
| 602 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
| 603 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
| 604 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
| 605 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
| 606 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
| 607 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
| 608 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
| 609 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) |
| 610 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
| 611 | |
| 612 | enum |
| 613 | { |
| 614 | REG_80 = 0, |
| 615 | REG_81, |
| 616 | REG_82, |
| 617 | REG_8F, |
| 618 | REG_C0, |
| 619 | REG_C1, |
| 620 | REG_C6, |
| 621 | REG_C7, |
| 622 | REG_D0, |
| 623 | REG_D1, |
| 624 | REG_D2, |
| 625 | REG_D3, |
| 626 | REG_F6, |
| 627 | REG_F7, |
| 628 | REG_FE, |
| 629 | REG_FF, |
| 630 | REG_0F00, |
| 631 | REG_0F01, |
| 632 | REG_0F0D, |
| 633 | REG_0F18, |
| 634 | REG_0F71, |
| 635 | REG_0F72, |
| 636 | REG_0F73, |
| 637 | REG_0FA6, |
| 638 | REG_0FA7, |
| 639 | REG_0FAE, |
| 640 | REG_0FBA, |
| 641 | REG_0FC7, |
| 642 | REG_VEX_0F71, |
| 643 | REG_VEX_0F72, |
| 644 | REG_VEX_0F73, |
| 645 | REG_VEX_0FAE, |
| 646 | REG_VEX_0F38F3, |
| 647 | REG_XOP_LWPCB, |
| 648 | REG_XOP_LWP, |
| 649 | REG_XOP_TBM_01, |
| 650 | REG_XOP_TBM_02 |
| 651 | }; |
| 652 | |
| 653 | enum |
| 654 | { |
| 655 | MOD_8D = 0, |
| 656 | MOD_C6_REG_7, |
| 657 | MOD_C7_REG_7, |
| 658 | MOD_0F01_REG_0, |
| 659 | MOD_0F01_REG_1, |
| 660 | MOD_0F01_REG_2, |
| 661 | MOD_0F01_REG_3, |
| 662 | MOD_0F01_REG_7, |
| 663 | MOD_0F12_PREFIX_0, |
| 664 | MOD_0F13, |
| 665 | MOD_0F16_PREFIX_0, |
| 666 | MOD_0F17, |
| 667 | MOD_0F18_REG_0, |
| 668 | MOD_0F18_REG_1, |
| 669 | MOD_0F18_REG_2, |
| 670 | MOD_0F18_REG_3, |
| 671 | MOD_0F20, |
| 672 | MOD_0F21, |
| 673 | MOD_0F22, |
| 674 | MOD_0F23, |
| 675 | MOD_0F24, |
| 676 | MOD_0F26, |
| 677 | MOD_0F2B_PREFIX_0, |
| 678 | MOD_0F2B_PREFIX_1, |
| 679 | MOD_0F2B_PREFIX_2, |
| 680 | MOD_0F2B_PREFIX_3, |
| 681 | MOD_0F51, |
| 682 | MOD_0F71_REG_2, |
| 683 | MOD_0F71_REG_4, |
| 684 | MOD_0F71_REG_6, |
| 685 | MOD_0F72_REG_2, |
| 686 | MOD_0F72_REG_4, |
| 687 | MOD_0F72_REG_6, |
| 688 | MOD_0F73_REG_2, |
| 689 | MOD_0F73_REG_3, |
| 690 | MOD_0F73_REG_6, |
| 691 | MOD_0F73_REG_7, |
| 692 | MOD_0FAE_REG_0, |
| 693 | MOD_0FAE_REG_1, |
| 694 | MOD_0FAE_REG_2, |
| 695 | MOD_0FAE_REG_3, |
| 696 | MOD_0FAE_REG_4, |
| 697 | MOD_0FAE_REG_5, |
| 698 | MOD_0FAE_REG_6, |
| 699 | MOD_0FAE_REG_7, |
| 700 | MOD_0FB2, |
| 701 | MOD_0FB4, |
| 702 | MOD_0FB5, |
| 703 | MOD_0FC7_REG_6, |
| 704 | MOD_0FC7_REG_7, |
| 705 | MOD_0FD7, |
| 706 | MOD_0FE7_PREFIX_2, |
| 707 | MOD_0FF0_PREFIX_3, |
| 708 | MOD_0F382A_PREFIX_2, |
| 709 | MOD_62_32BIT, |
| 710 | MOD_C4_32BIT, |
| 711 | MOD_C5_32BIT, |
| 712 | MOD_VEX_0F12_PREFIX_0, |
| 713 | MOD_VEX_0F13, |
| 714 | MOD_VEX_0F16_PREFIX_0, |
| 715 | MOD_VEX_0F17, |
| 716 | MOD_VEX_0F2B, |
| 717 | MOD_VEX_0F50, |
| 718 | MOD_VEX_0F71_REG_2, |
| 719 | MOD_VEX_0F71_REG_4, |
| 720 | MOD_VEX_0F71_REG_6, |
| 721 | MOD_VEX_0F72_REG_2, |
| 722 | MOD_VEX_0F72_REG_4, |
| 723 | MOD_VEX_0F72_REG_6, |
| 724 | MOD_VEX_0F73_REG_2, |
| 725 | MOD_VEX_0F73_REG_3, |
| 726 | MOD_VEX_0F73_REG_6, |
| 727 | MOD_VEX_0F73_REG_7, |
| 728 | MOD_VEX_0FAE_REG_2, |
| 729 | MOD_VEX_0FAE_REG_3, |
| 730 | MOD_VEX_0FD7_PREFIX_2, |
| 731 | MOD_VEX_0FE7_PREFIX_2, |
| 732 | MOD_VEX_0FF0_PREFIX_3, |
| 733 | MOD_VEX_0F381A_PREFIX_2, |
| 734 | MOD_VEX_0F382A_PREFIX_2, |
| 735 | MOD_VEX_0F382C_PREFIX_2, |
| 736 | MOD_VEX_0F382D_PREFIX_2, |
| 737 | MOD_VEX_0F382E_PREFIX_2, |
| 738 | MOD_VEX_0F382F_PREFIX_2, |
| 739 | MOD_VEX_0F385A_PREFIX_2, |
| 740 | MOD_VEX_0F388C_PREFIX_2, |
| 741 | MOD_VEX_0F388E_PREFIX_2, |
| 742 | }; |
| 743 | |
| 744 | enum |
| 745 | { |
| 746 | RM_C6_REG_7 = 0, |
| 747 | RM_C7_REG_7, |
| 748 | RM_0F01_REG_0, |
| 749 | RM_0F01_REG_1, |
| 750 | RM_0F01_REG_2, |
| 751 | RM_0F01_REG_3, |
| 752 | RM_0F01_REG_7, |
| 753 | RM_0FAE_REG_5, |
| 754 | RM_0FAE_REG_6, |
| 755 | RM_0FAE_REG_7 |
| 756 | }; |
| 757 | |
| 758 | enum |
| 759 | { |
| 760 | PREFIX_90 = 0, |
| 761 | PREFIX_0F10, |
| 762 | PREFIX_0F11, |
| 763 | PREFIX_0F12, |
| 764 | PREFIX_0F16, |
| 765 | PREFIX_0F2A, |
| 766 | PREFIX_0F2B, |
| 767 | PREFIX_0F2C, |
| 768 | PREFIX_0F2D, |
| 769 | PREFIX_0F2E, |
| 770 | PREFIX_0F2F, |
| 771 | PREFIX_0F51, |
| 772 | PREFIX_0F52, |
| 773 | PREFIX_0F53, |
| 774 | PREFIX_0F58, |
| 775 | PREFIX_0F59, |
| 776 | PREFIX_0F5A, |
| 777 | PREFIX_0F5B, |
| 778 | PREFIX_0F5C, |
| 779 | PREFIX_0F5D, |
| 780 | PREFIX_0F5E, |
| 781 | PREFIX_0F5F, |
| 782 | PREFIX_0F60, |
| 783 | PREFIX_0F61, |
| 784 | PREFIX_0F62, |
| 785 | PREFIX_0F6C, |
| 786 | PREFIX_0F6D, |
| 787 | PREFIX_0F6F, |
| 788 | PREFIX_0F70, |
| 789 | PREFIX_0F73_REG_3, |
| 790 | PREFIX_0F73_REG_7, |
| 791 | PREFIX_0F78, |
| 792 | PREFIX_0F79, |
| 793 | PREFIX_0F7C, |
| 794 | PREFIX_0F7D, |
| 795 | PREFIX_0F7E, |
| 796 | PREFIX_0F7F, |
| 797 | PREFIX_0FAE_REG_0, |
| 798 | PREFIX_0FAE_REG_1, |
| 799 | PREFIX_0FAE_REG_2, |
| 800 | PREFIX_0FAE_REG_3, |
| 801 | PREFIX_0FB8, |
| 802 | PREFIX_0FBC, |
| 803 | PREFIX_0FBD, |
| 804 | PREFIX_0FC2, |
| 805 | PREFIX_0FC3, |
| 806 | PREFIX_0FC7_REG_6, |
| 807 | PREFIX_0FD0, |
| 808 | PREFIX_0FD6, |
| 809 | PREFIX_0FE6, |
| 810 | PREFIX_0FE7, |
| 811 | PREFIX_0FF0, |
| 812 | PREFIX_0FF7, |
| 813 | PREFIX_0F3810, |
| 814 | PREFIX_0F3814, |
| 815 | PREFIX_0F3815, |
| 816 | PREFIX_0F3817, |
| 817 | PREFIX_0F3820, |
| 818 | PREFIX_0F3821, |
| 819 | PREFIX_0F3822, |
| 820 | PREFIX_0F3823, |
| 821 | PREFIX_0F3824, |
| 822 | PREFIX_0F3825, |
| 823 | PREFIX_0F3828, |
| 824 | PREFIX_0F3829, |
| 825 | PREFIX_0F382A, |
| 826 | PREFIX_0F382B, |
| 827 | PREFIX_0F3830, |
| 828 | PREFIX_0F3831, |
| 829 | PREFIX_0F3832, |
| 830 | PREFIX_0F3833, |
| 831 | PREFIX_0F3834, |
| 832 | PREFIX_0F3835, |
| 833 | PREFIX_0F3837, |
| 834 | PREFIX_0F3838, |
| 835 | PREFIX_0F3839, |
| 836 | PREFIX_0F383A, |
| 837 | PREFIX_0F383B, |
| 838 | PREFIX_0F383C, |
| 839 | PREFIX_0F383D, |
| 840 | PREFIX_0F383E, |
| 841 | PREFIX_0F383F, |
| 842 | PREFIX_0F3840, |
| 843 | PREFIX_0F3841, |
| 844 | PREFIX_0F3880, |
| 845 | PREFIX_0F3881, |
| 846 | PREFIX_0F3882, |
| 847 | PREFIX_0F38DB, |
| 848 | PREFIX_0F38DC, |
| 849 | PREFIX_0F38DD, |
| 850 | PREFIX_0F38DE, |
| 851 | PREFIX_0F38DF, |
| 852 | PREFIX_0F38F0, |
| 853 | PREFIX_0F38F1, |
| 854 | PREFIX_0F3A08, |
| 855 | PREFIX_0F3A09, |
| 856 | PREFIX_0F3A0A, |
| 857 | PREFIX_0F3A0B, |
| 858 | PREFIX_0F3A0C, |
| 859 | PREFIX_0F3A0D, |
| 860 | PREFIX_0F3A0E, |
| 861 | PREFIX_0F3A14, |
| 862 | PREFIX_0F3A15, |
| 863 | PREFIX_0F3A16, |
| 864 | PREFIX_0F3A17, |
| 865 | PREFIX_0F3A20, |
| 866 | PREFIX_0F3A21, |
| 867 | PREFIX_0F3A22, |
| 868 | PREFIX_0F3A40, |
| 869 | PREFIX_0F3A41, |
| 870 | PREFIX_0F3A42, |
| 871 | PREFIX_0F3A44, |
| 872 | PREFIX_0F3A60, |
| 873 | PREFIX_0F3A61, |
| 874 | PREFIX_0F3A62, |
| 875 | PREFIX_0F3A63, |
| 876 | PREFIX_0F3ADF, |
| 877 | PREFIX_VEX_0F10, |
| 878 | PREFIX_VEX_0F11, |
| 879 | PREFIX_VEX_0F12, |
| 880 | PREFIX_VEX_0F16, |
| 881 | PREFIX_VEX_0F2A, |
| 882 | PREFIX_VEX_0F2C, |
| 883 | PREFIX_VEX_0F2D, |
| 884 | PREFIX_VEX_0F2E, |
| 885 | PREFIX_VEX_0F2F, |
| 886 | PREFIX_VEX_0F51, |
| 887 | PREFIX_VEX_0F52, |
| 888 | PREFIX_VEX_0F53, |
| 889 | PREFIX_VEX_0F58, |
| 890 | PREFIX_VEX_0F59, |
| 891 | PREFIX_VEX_0F5A, |
| 892 | PREFIX_VEX_0F5B, |
| 893 | PREFIX_VEX_0F5C, |
| 894 | PREFIX_VEX_0F5D, |
| 895 | PREFIX_VEX_0F5E, |
| 896 | PREFIX_VEX_0F5F, |
| 897 | PREFIX_VEX_0F60, |
| 898 | PREFIX_VEX_0F61, |
| 899 | PREFIX_VEX_0F62, |
| 900 | PREFIX_VEX_0F63, |
| 901 | PREFIX_VEX_0F64, |
| 902 | PREFIX_VEX_0F65, |
| 903 | PREFIX_VEX_0F66, |
| 904 | PREFIX_VEX_0F67, |
| 905 | PREFIX_VEX_0F68, |
| 906 | PREFIX_VEX_0F69, |
| 907 | PREFIX_VEX_0F6A, |
| 908 | PREFIX_VEX_0F6B, |
| 909 | PREFIX_VEX_0F6C, |
| 910 | PREFIX_VEX_0F6D, |
| 911 | PREFIX_VEX_0F6E, |
| 912 | PREFIX_VEX_0F6F, |
| 913 | PREFIX_VEX_0F70, |
| 914 | PREFIX_VEX_0F71_REG_2, |
| 915 | PREFIX_VEX_0F71_REG_4, |
| 916 | PREFIX_VEX_0F71_REG_6, |
| 917 | PREFIX_VEX_0F72_REG_2, |
| 918 | PREFIX_VEX_0F72_REG_4, |
| 919 | PREFIX_VEX_0F72_REG_6, |
| 920 | PREFIX_VEX_0F73_REG_2, |
| 921 | PREFIX_VEX_0F73_REG_3, |
| 922 | PREFIX_VEX_0F73_REG_6, |
| 923 | PREFIX_VEX_0F73_REG_7, |
| 924 | PREFIX_VEX_0F74, |
| 925 | PREFIX_VEX_0F75, |
| 926 | PREFIX_VEX_0F76, |
| 927 | PREFIX_VEX_0F77, |
| 928 | PREFIX_VEX_0F7C, |
| 929 | PREFIX_VEX_0F7D, |
| 930 | PREFIX_VEX_0F7E, |
| 931 | PREFIX_VEX_0F7F, |
| 932 | PREFIX_VEX_0FC2, |
| 933 | PREFIX_VEX_0FC4, |
| 934 | PREFIX_VEX_0FC5, |
| 935 | PREFIX_VEX_0FD0, |
| 936 | PREFIX_VEX_0FD1, |
| 937 | PREFIX_VEX_0FD2, |
| 938 | PREFIX_VEX_0FD3, |
| 939 | PREFIX_VEX_0FD4, |
| 940 | PREFIX_VEX_0FD5, |
| 941 | PREFIX_VEX_0FD6, |
| 942 | PREFIX_VEX_0FD7, |
| 943 | PREFIX_VEX_0FD8, |
| 944 | PREFIX_VEX_0FD9, |
| 945 | PREFIX_VEX_0FDA, |
| 946 | PREFIX_VEX_0FDB, |
| 947 | PREFIX_VEX_0FDC, |
| 948 | PREFIX_VEX_0FDD, |
| 949 | PREFIX_VEX_0FDE, |
| 950 | PREFIX_VEX_0FDF, |
| 951 | PREFIX_VEX_0FE0, |
| 952 | PREFIX_VEX_0FE1, |
| 953 | PREFIX_VEX_0FE2, |
| 954 | PREFIX_VEX_0FE3, |
| 955 | PREFIX_VEX_0FE4, |
| 956 | PREFIX_VEX_0FE5, |
| 957 | PREFIX_VEX_0FE6, |
| 958 | PREFIX_VEX_0FE7, |
| 959 | PREFIX_VEX_0FE8, |
| 960 | PREFIX_VEX_0FE9, |
| 961 | PREFIX_VEX_0FEA, |
| 962 | PREFIX_VEX_0FEB, |
| 963 | PREFIX_VEX_0FEC, |
| 964 | PREFIX_VEX_0FED, |
| 965 | PREFIX_VEX_0FEE, |
| 966 | PREFIX_VEX_0FEF, |
| 967 | PREFIX_VEX_0FF0, |
| 968 | PREFIX_VEX_0FF1, |
| 969 | PREFIX_VEX_0FF2, |
| 970 | PREFIX_VEX_0FF3, |
| 971 | PREFIX_VEX_0FF4, |
| 972 | PREFIX_VEX_0FF5, |
| 973 | PREFIX_VEX_0FF6, |
| 974 | PREFIX_VEX_0FF7, |
| 975 | PREFIX_VEX_0FF8, |
| 976 | PREFIX_VEX_0FF9, |
| 977 | PREFIX_VEX_0FFA, |
| 978 | PREFIX_VEX_0FFB, |
| 979 | PREFIX_VEX_0FFC, |
| 980 | PREFIX_VEX_0FFD, |
| 981 | PREFIX_VEX_0FFE, |
| 982 | PREFIX_VEX_0F3800, |
| 983 | PREFIX_VEX_0F3801, |
| 984 | PREFIX_VEX_0F3802, |
| 985 | PREFIX_VEX_0F3803, |
| 986 | PREFIX_VEX_0F3804, |
| 987 | PREFIX_VEX_0F3805, |
| 988 | PREFIX_VEX_0F3806, |
| 989 | PREFIX_VEX_0F3807, |
| 990 | PREFIX_VEX_0F3808, |
| 991 | PREFIX_VEX_0F3809, |
| 992 | PREFIX_VEX_0F380A, |
| 993 | PREFIX_VEX_0F380B, |
| 994 | PREFIX_VEX_0F380C, |
| 995 | PREFIX_VEX_0F380D, |
| 996 | PREFIX_VEX_0F380E, |
| 997 | PREFIX_VEX_0F380F, |
| 998 | PREFIX_VEX_0F3813, |
| 999 | PREFIX_VEX_0F3816, |
| 1000 | PREFIX_VEX_0F3817, |
| 1001 | PREFIX_VEX_0F3818, |
| 1002 | PREFIX_VEX_0F3819, |
| 1003 | PREFIX_VEX_0F381A, |
| 1004 | PREFIX_VEX_0F381C, |
| 1005 | PREFIX_VEX_0F381D, |
| 1006 | PREFIX_VEX_0F381E, |
| 1007 | PREFIX_VEX_0F3820, |
| 1008 | PREFIX_VEX_0F3821, |
| 1009 | PREFIX_VEX_0F3822, |
| 1010 | PREFIX_VEX_0F3823, |
| 1011 | PREFIX_VEX_0F3824, |
| 1012 | PREFIX_VEX_0F3825, |
| 1013 | PREFIX_VEX_0F3828, |
| 1014 | PREFIX_VEX_0F3829, |
| 1015 | PREFIX_VEX_0F382A, |
| 1016 | PREFIX_VEX_0F382B, |
| 1017 | PREFIX_VEX_0F382C, |
| 1018 | PREFIX_VEX_0F382D, |
| 1019 | PREFIX_VEX_0F382E, |
| 1020 | PREFIX_VEX_0F382F, |
| 1021 | PREFIX_VEX_0F3830, |
| 1022 | PREFIX_VEX_0F3831, |
| 1023 | PREFIX_VEX_0F3832, |
| 1024 | PREFIX_VEX_0F3833, |
| 1025 | PREFIX_VEX_0F3834, |
| 1026 | PREFIX_VEX_0F3835, |
| 1027 | PREFIX_VEX_0F3836, |
| 1028 | PREFIX_VEX_0F3837, |
| 1029 | PREFIX_VEX_0F3838, |
| 1030 | PREFIX_VEX_0F3839, |
| 1031 | PREFIX_VEX_0F383A, |
| 1032 | PREFIX_VEX_0F383B, |
| 1033 | PREFIX_VEX_0F383C, |
| 1034 | PREFIX_VEX_0F383D, |
| 1035 | PREFIX_VEX_0F383E, |
| 1036 | PREFIX_VEX_0F383F, |
| 1037 | PREFIX_VEX_0F3840, |
| 1038 | PREFIX_VEX_0F3841, |
| 1039 | PREFIX_VEX_0F3845, |
| 1040 | PREFIX_VEX_0F3846, |
| 1041 | PREFIX_VEX_0F3847, |
| 1042 | PREFIX_VEX_0F3858, |
| 1043 | PREFIX_VEX_0F3859, |
| 1044 | PREFIX_VEX_0F385A, |
| 1045 | PREFIX_VEX_0F3878, |
| 1046 | PREFIX_VEX_0F3879, |
| 1047 | PREFIX_VEX_0F388C, |
| 1048 | PREFIX_VEX_0F388E, |
| 1049 | PREFIX_VEX_0F3890, |
| 1050 | PREFIX_VEX_0F3891, |
| 1051 | PREFIX_VEX_0F3892, |
| 1052 | PREFIX_VEX_0F3893, |
| 1053 | PREFIX_VEX_0F3896, |
| 1054 | PREFIX_VEX_0F3897, |
| 1055 | PREFIX_VEX_0F3898, |
| 1056 | PREFIX_VEX_0F3899, |
| 1057 | PREFIX_VEX_0F389A, |
| 1058 | PREFIX_VEX_0F389B, |
| 1059 | PREFIX_VEX_0F389C, |
| 1060 | PREFIX_VEX_0F389D, |
| 1061 | PREFIX_VEX_0F389E, |
| 1062 | PREFIX_VEX_0F389F, |
| 1063 | PREFIX_VEX_0F38A6, |
| 1064 | PREFIX_VEX_0F38A7, |
| 1065 | PREFIX_VEX_0F38A8, |
| 1066 | PREFIX_VEX_0F38A9, |
| 1067 | PREFIX_VEX_0F38AA, |
| 1068 | PREFIX_VEX_0F38AB, |
| 1069 | PREFIX_VEX_0F38AC, |
| 1070 | PREFIX_VEX_0F38AD, |
| 1071 | PREFIX_VEX_0F38AE, |
| 1072 | PREFIX_VEX_0F38AF, |
| 1073 | PREFIX_VEX_0F38B6, |
| 1074 | PREFIX_VEX_0F38B7, |
| 1075 | PREFIX_VEX_0F38B8, |
| 1076 | PREFIX_VEX_0F38B9, |
| 1077 | PREFIX_VEX_0F38BA, |
| 1078 | PREFIX_VEX_0F38BB, |
| 1079 | PREFIX_VEX_0F38BC, |
| 1080 | PREFIX_VEX_0F38BD, |
| 1081 | PREFIX_VEX_0F38BE, |
| 1082 | PREFIX_VEX_0F38BF, |
| 1083 | PREFIX_VEX_0F38DB, |
| 1084 | PREFIX_VEX_0F38DC, |
| 1085 | PREFIX_VEX_0F38DD, |
| 1086 | PREFIX_VEX_0F38DE, |
| 1087 | PREFIX_VEX_0F38DF, |
| 1088 | PREFIX_VEX_0F38F2, |
| 1089 | PREFIX_VEX_0F38F3_REG_1, |
| 1090 | PREFIX_VEX_0F38F3_REG_2, |
| 1091 | PREFIX_VEX_0F38F3_REG_3, |
| 1092 | PREFIX_VEX_0F38F5, |
| 1093 | PREFIX_VEX_0F38F6, |
| 1094 | PREFIX_VEX_0F38F7, |
| 1095 | PREFIX_VEX_0F3A00, |
| 1096 | PREFIX_VEX_0F3A01, |
| 1097 | PREFIX_VEX_0F3A02, |
| 1098 | PREFIX_VEX_0F3A04, |
| 1099 | PREFIX_VEX_0F3A05, |
| 1100 | PREFIX_VEX_0F3A06, |
| 1101 | PREFIX_VEX_0F3A08, |
| 1102 | PREFIX_VEX_0F3A09, |
| 1103 | PREFIX_VEX_0F3A0A, |
| 1104 | PREFIX_VEX_0F3A0B, |
| 1105 | PREFIX_VEX_0F3A0C, |
| 1106 | PREFIX_VEX_0F3A0D, |
| 1107 | PREFIX_VEX_0F3A0E, |
| 1108 | PREFIX_VEX_0F3A0F, |
| 1109 | PREFIX_VEX_0F3A14, |
| 1110 | PREFIX_VEX_0F3A15, |
| 1111 | PREFIX_VEX_0F3A16, |
| 1112 | PREFIX_VEX_0F3A17, |
| 1113 | PREFIX_VEX_0F3A18, |
| 1114 | PREFIX_VEX_0F3A19, |
| 1115 | PREFIX_VEX_0F3A1D, |
| 1116 | PREFIX_VEX_0F3A20, |
| 1117 | PREFIX_VEX_0F3A21, |
| 1118 | PREFIX_VEX_0F3A22, |
| 1119 | PREFIX_VEX_0F3A38, |
| 1120 | PREFIX_VEX_0F3A39, |
| 1121 | PREFIX_VEX_0F3A40, |
| 1122 | PREFIX_VEX_0F3A41, |
| 1123 | PREFIX_VEX_0F3A42, |
| 1124 | PREFIX_VEX_0F3A44, |
| 1125 | PREFIX_VEX_0F3A46, |
| 1126 | PREFIX_VEX_0F3A48, |
| 1127 | PREFIX_VEX_0F3A49, |
| 1128 | PREFIX_VEX_0F3A4A, |
| 1129 | PREFIX_VEX_0F3A4B, |
| 1130 | PREFIX_VEX_0F3A4C, |
| 1131 | PREFIX_VEX_0F3A5C, |
| 1132 | PREFIX_VEX_0F3A5D, |
| 1133 | PREFIX_VEX_0F3A5E, |
| 1134 | PREFIX_VEX_0F3A5F, |
| 1135 | PREFIX_VEX_0F3A60, |
| 1136 | PREFIX_VEX_0F3A61, |
| 1137 | PREFIX_VEX_0F3A62, |
| 1138 | PREFIX_VEX_0F3A63, |
| 1139 | PREFIX_VEX_0F3A68, |
| 1140 | PREFIX_VEX_0F3A69, |
| 1141 | PREFIX_VEX_0F3A6A, |
| 1142 | PREFIX_VEX_0F3A6B, |
| 1143 | PREFIX_VEX_0F3A6C, |
| 1144 | PREFIX_VEX_0F3A6D, |
| 1145 | PREFIX_VEX_0F3A6E, |
| 1146 | PREFIX_VEX_0F3A6F, |
| 1147 | PREFIX_VEX_0F3A78, |
| 1148 | PREFIX_VEX_0F3A79, |
| 1149 | PREFIX_VEX_0F3A7A, |
| 1150 | PREFIX_VEX_0F3A7B, |
| 1151 | PREFIX_VEX_0F3A7C, |
| 1152 | PREFIX_VEX_0F3A7D, |
| 1153 | PREFIX_VEX_0F3A7E, |
| 1154 | PREFIX_VEX_0F3A7F, |
| 1155 | PREFIX_VEX_0F3ADF, |
| 1156 | PREFIX_VEX_0F3AF0 |
| 1157 | }; |
| 1158 | |
| 1159 | enum |
| 1160 | { |
| 1161 | X86_64_06 = 0, |
| 1162 | X86_64_07, |
| 1163 | X86_64_0D, |
| 1164 | X86_64_16, |
| 1165 | X86_64_17, |
| 1166 | X86_64_1E, |
| 1167 | X86_64_1F, |
| 1168 | X86_64_27, |
| 1169 | X86_64_2F, |
| 1170 | X86_64_37, |
| 1171 | X86_64_3F, |
| 1172 | X86_64_60, |
| 1173 | X86_64_61, |
| 1174 | X86_64_62, |
| 1175 | X86_64_63, |
| 1176 | X86_64_6D, |
| 1177 | X86_64_6F, |
| 1178 | X86_64_9A, |
| 1179 | X86_64_C4, |
| 1180 | X86_64_C5, |
| 1181 | X86_64_CE, |
| 1182 | X86_64_D4, |
| 1183 | X86_64_D5, |
| 1184 | X86_64_EA, |
| 1185 | X86_64_0F01_REG_0, |
| 1186 | X86_64_0F01_REG_1, |
| 1187 | X86_64_0F01_REG_2, |
| 1188 | X86_64_0F01_REG_3 |
| 1189 | }; |
| 1190 | |
| 1191 | enum |
| 1192 | { |
| 1193 | THREE_BYTE_0F38 = 0, |
| 1194 | THREE_BYTE_0F3A, |
| 1195 | THREE_BYTE_0F7A |
| 1196 | }; |
| 1197 | |
| 1198 | enum |
| 1199 | { |
| 1200 | XOP_08 = 0, |
| 1201 | XOP_09, |
| 1202 | XOP_0A |
| 1203 | }; |
| 1204 | |
| 1205 | enum |
| 1206 | { |
| 1207 | VEX_0F = 0, |
| 1208 | VEX_0F38, |
| 1209 | VEX_0F3A |
| 1210 | }; |
| 1211 | |
| 1212 | enum |
| 1213 | { |
| 1214 | VEX_LEN_0F10_P_1 = 0, |
| 1215 | VEX_LEN_0F10_P_3, |
| 1216 | VEX_LEN_0F11_P_1, |
| 1217 | VEX_LEN_0F11_P_3, |
| 1218 | VEX_LEN_0F12_P_0_M_0, |
| 1219 | VEX_LEN_0F12_P_0_M_1, |
| 1220 | VEX_LEN_0F12_P_2, |
| 1221 | VEX_LEN_0F13_M_0, |
| 1222 | VEX_LEN_0F16_P_0_M_0, |
| 1223 | VEX_LEN_0F16_P_0_M_1, |
| 1224 | VEX_LEN_0F16_P_2, |
| 1225 | VEX_LEN_0F17_M_0, |
| 1226 | VEX_LEN_0F2A_P_1, |
| 1227 | VEX_LEN_0F2A_P_3, |
| 1228 | VEX_LEN_0F2C_P_1, |
| 1229 | VEX_LEN_0F2C_P_3, |
| 1230 | VEX_LEN_0F2D_P_1, |
| 1231 | VEX_LEN_0F2D_P_3, |
| 1232 | VEX_LEN_0F2E_P_0, |
| 1233 | VEX_LEN_0F2E_P_2, |
| 1234 | VEX_LEN_0F2F_P_0, |
| 1235 | VEX_LEN_0F2F_P_2, |
| 1236 | VEX_LEN_0F51_P_1, |
| 1237 | VEX_LEN_0F51_P_3, |
| 1238 | VEX_LEN_0F52_P_1, |
| 1239 | VEX_LEN_0F53_P_1, |
| 1240 | VEX_LEN_0F58_P_1, |
| 1241 | VEX_LEN_0F58_P_3, |
| 1242 | VEX_LEN_0F59_P_1, |
| 1243 | VEX_LEN_0F59_P_3, |
| 1244 | VEX_LEN_0F5A_P_1, |
| 1245 | VEX_LEN_0F5A_P_3, |
| 1246 | VEX_LEN_0F5C_P_1, |
| 1247 | VEX_LEN_0F5C_P_3, |
| 1248 | VEX_LEN_0F5D_P_1, |
| 1249 | VEX_LEN_0F5D_P_3, |
| 1250 | VEX_LEN_0F5E_P_1, |
| 1251 | VEX_LEN_0F5E_P_3, |
| 1252 | VEX_LEN_0F5F_P_1, |
| 1253 | VEX_LEN_0F5F_P_3, |
| 1254 | VEX_LEN_0F6E_P_2, |
| 1255 | VEX_LEN_0F7E_P_1, |
| 1256 | VEX_LEN_0F7E_P_2, |
| 1257 | VEX_LEN_0FAE_R_2_M_0, |
| 1258 | VEX_LEN_0FAE_R_3_M_0, |
| 1259 | VEX_LEN_0FC2_P_1, |
| 1260 | VEX_LEN_0FC2_P_3, |
| 1261 | VEX_LEN_0FC4_P_2, |
| 1262 | VEX_LEN_0FC5_P_2, |
| 1263 | VEX_LEN_0FD6_P_2, |
| 1264 | VEX_LEN_0FF7_P_2, |
| 1265 | VEX_LEN_0F3816_P_2, |
| 1266 | VEX_LEN_0F3819_P_2, |
| 1267 | VEX_LEN_0F381A_P_2_M_0, |
| 1268 | VEX_LEN_0F3836_P_2, |
| 1269 | VEX_LEN_0F3841_P_2, |
| 1270 | VEX_LEN_0F385A_P_2_M_0, |
| 1271 | VEX_LEN_0F38DB_P_2, |
| 1272 | VEX_LEN_0F38DC_P_2, |
| 1273 | VEX_LEN_0F38DD_P_2, |
| 1274 | VEX_LEN_0F38DE_P_2, |
| 1275 | VEX_LEN_0F38DF_P_2, |
| 1276 | VEX_LEN_0F38F2_P_0, |
| 1277 | VEX_LEN_0F38F3_R_1_P_0, |
| 1278 | VEX_LEN_0F38F3_R_2_P_0, |
| 1279 | VEX_LEN_0F38F3_R_3_P_0, |
| 1280 | VEX_LEN_0F38F5_P_0, |
| 1281 | VEX_LEN_0F38F5_P_1, |
| 1282 | VEX_LEN_0F38F5_P_3, |
| 1283 | VEX_LEN_0F38F6_P_3, |
| 1284 | VEX_LEN_0F38F7_P_0, |
| 1285 | VEX_LEN_0F38F7_P_1, |
| 1286 | VEX_LEN_0F38F7_P_2, |
| 1287 | VEX_LEN_0F38F7_P_3, |
| 1288 | VEX_LEN_0F3A00_P_2, |
| 1289 | VEX_LEN_0F3A01_P_2, |
| 1290 | VEX_LEN_0F3A06_P_2, |
| 1291 | VEX_LEN_0F3A0A_P_2, |
| 1292 | VEX_LEN_0F3A0B_P_2, |
| 1293 | VEX_LEN_0F3A14_P_2, |
| 1294 | VEX_LEN_0F3A15_P_2, |
| 1295 | VEX_LEN_0F3A16_P_2, |
| 1296 | VEX_LEN_0F3A17_P_2, |
| 1297 | VEX_LEN_0F3A18_P_2, |
| 1298 | VEX_LEN_0F3A19_P_2, |
| 1299 | VEX_LEN_0F3A20_P_2, |
| 1300 | VEX_LEN_0F3A21_P_2, |
| 1301 | VEX_LEN_0F3A22_P_2, |
| 1302 | VEX_LEN_0F3A38_P_2, |
| 1303 | VEX_LEN_0F3A39_P_2, |
| 1304 | VEX_LEN_0F3A41_P_2, |
| 1305 | VEX_LEN_0F3A44_P_2, |
| 1306 | VEX_LEN_0F3A46_P_2, |
| 1307 | VEX_LEN_0F3A60_P_2, |
| 1308 | VEX_LEN_0F3A61_P_2, |
| 1309 | VEX_LEN_0F3A62_P_2, |
| 1310 | VEX_LEN_0F3A63_P_2, |
| 1311 | VEX_LEN_0F3A6A_P_2, |
| 1312 | VEX_LEN_0F3A6B_P_2, |
| 1313 | VEX_LEN_0F3A6E_P_2, |
| 1314 | VEX_LEN_0F3A6F_P_2, |
| 1315 | VEX_LEN_0F3A7A_P_2, |
| 1316 | VEX_LEN_0F3A7B_P_2, |
| 1317 | VEX_LEN_0F3A7E_P_2, |
| 1318 | VEX_LEN_0F3A7F_P_2, |
| 1319 | VEX_LEN_0F3ADF_P_2, |
| 1320 | VEX_LEN_0F3AF0_P_3, |
| 1321 | VEX_LEN_0FXOP_09_80, |
| 1322 | VEX_LEN_0FXOP_09_81 |
| 1323 | }; |
| 1324 | |
| 1325 | enum |
| 1326 | { |
| 1327 | VEX_W_0F10_P_0 = 0, |
| 1328 | VEX_W_0F10_P_1, |
| 1329 | VEX_W_0F10_P_2, |
| 1330 | VEX_W_0F10_P_3, |
| 1331 | VEX_W_0F11_P_0, |
| 1332 | VEX_W_0F11_P_1, |
| 1333 | VEX_W_0F11_P_2, |
| 1334 | VEX_W_0F11_P_3, |
| 1335 | VEX_W_0F12_P_0_M_0, |
| 1336 | VEX_W_0F12_P_0_M_1, |
| 1337 | VEX_W_0F12_P_1, |
| 1338 | VEX_W_0F12_P_2, |
| 1339 | VEX_W_0F12_P_3, |
| 1340 | VEX_W_0F13_M_0, |
| 1341 | VEX_W_0F14, |
| 1342 | VEX_W_0F15, |
| 1343 | VEX_W_0F16_P_0_M_0, |
| 1344 | VEX_W_0F16_P_0_M_1, |
| 1345 | VEX_W_0F16_P_1, |
| 1346 | VEX_W_0F16_P_2, |
| 1347 | VEX_W_0F17_M_0, |
| 1348 | VEX_W_0F28, |
| 1349 | VEX_W_0F29, |
| 1350 | VEX_W_0F2B_M_0, |
| 1351 | VEX_W_0F2E_P_0, |
| 1352 | VEX_W_0F2E_P_2, |
| 1353 | VEX_W_0F2F_P_0, |
| 1354 | VEX_W_0F2F_P_2, |
| 1355 | VEX_W_0F50_M_0, |
| 1356 | VEX_W_0F51_P_0, |
| 1357 | VEX_W_0F51_P_1, |
| 1358 | VEX_W_0F51_P_2, |
| 1359 | VEX_W_0F51_P_3, |
| 1360 | VEX_W_0F52_P_0, |
| 1361 | VEX_W_0F52_P_1, |
| 1362 | VEX_W_0F53_P_0, |
| 1363 | VEX_W_0F53_P_1, |
| 1364 | VEX_W_0F58_P_0, |
| 1365 | VEX_W_0F58_P_1, |
| 1366 | VEX_W_0F58_P_2, |
| 1367 | VEX_W_0F58_P_3, |
| 1368 | VEX_W_0F59_P_0, |
| 1369 | VEX_W_0F59_P_1, |
| 1370 | VEX_W_0F59_P_2, |
| 1371 | VEX_W_0F59_P_3, |
| 1372 | VEX_W_0F5A_P_0, |
| 1373 | VEX_W_0F5A_P_1, |
| 1374 | VEX_W_0F5A_P_3, |
| 1375 | VEX_W_0F5B_P_0, |
| 1376 | VEX_W_0F5B_P_1, |
| 1377 | VEX_W_0F5B_P_2, |
| 1378 | VEX_W_0F5C_P_0, |
| 1379 | VEX_W_0F5C_P_1, |
| 1380 | VEX_W_0F5C_P_2, |
| 1381 | VEX_W_0F5C_P_3, |
| 1382 | VEX_W_0F5D_P_0, |
| 1383 | VEX_W_0F5D_P_1, |
| 1384 | VEX_W_0F5D_P_2, |
| 1385 | VEX_W_0F5D_P_3, |
| 1386 | VEX_W_0F5E_P_0, |
| 1387 | VEX_W_0F5E_P_1, |
| 1388 | VEX_W_0F5E_P_2, |
| 1389 | VEX_W_0F5E_P_3, |
| 1390 | VEX_W_0F5F_P_0, |
| 1391 | VEX_W_0F5F_P_1, |
| 1392 | VEX_W_0F5F_P_2, |
| 1393 | VEX_W_0F5F_P_3, |
| 1394 | VEX_W_0F60_P_2, |
| 1395 | VEX_W_0F61_P_2, |
| 1396 | VEX_W_0F62_P_2, |
| 1397 | VEX_W_0F63_P_2, |
| 1398 | VEX_W_0F64_P_2, |
| 1399 | VEX_W_0F65_P_2, |
| 1400 | VEX_W_0F66_P_2, |
| 1401 | VEX_W_0F67_P_2, |
| 1402 | VEX_W_0F68_P_2, |
| 1403 | VEX_W_0F69_P_2, |
| 1404 | VEX_W_0F6A_P_2, |
| 1405 | VEX_W_0F6B_P_2, |
| 1406 | VEX_W_0F6C_P_2, |
| 1407 | VEX_W_0F6D_P_2, |
| 1408 | VEX_W_0F6F_P_1, |
| 1409 | VEX_W_0F6F_P_2, |
| 1410 | VEX_W_0F70_P_1, |
| 1411 | VEX_W_0F70_P_2, |
| 1412 | VEX_W_0F70_P_3, |
| 1413 | VEX_W_0F71_R_2_P_2, |
| 1414 | VEX_W_0F71_R_4_P_2, |
| 1415 | VEX_W_0F71_R_6_P_2, |
| 1416 | VEX_W_0F72_R_2_P_2, |
| 1417 | VEX_W_0F72_R_4_P_2, |
| 1418 | VEX_W_0F72_R_6_P_2, |
| 1419 | VEX_W_0F73_R_2_P_2, |
| 1420 | VEX_W_0F73_R_3_P_2, |
| 1421 | VEX_W_0F73_R_6_P_2, |
| 1422 | VEX_W_0F73_R_7_P_2, |
| 1423 | VEX_W_0F74_P_2, |
| 1424 | VEX_W_0F75_P_2, |
| 1425 | VEX_W_0F76_P_2, |
| 1426 | VEX_W_0F77_P_0, |
| 1427 | VEX_W_0F7C_P_2, |
| 1428 | VEX_W_0F7C_P_3, |
| 1429 | VEX_W_0F7D_P_2, |
| 1430 | VEX_W_0F7D_P_3, |
| 1431 | VEX_W_0F7E_P_1, |
| 1432 | VEX_W_0F7F_P_1, |
| 1433 | VEX_W_0F7F_P_2, |
| 1434 | VEX_W_0FAE_R_2_M_0, |
| 1435 | VEX_W_0FAE_R_3_M_0, |
| 1436 | VEX_W_0FC2_P_0, |
| 1437 | VEX_W_0FC2_P_1, |
| 1438 | VEX_W_0FC2_P_2, |
| 1439 | VEX_W_0FC2_P_3, |
| 1440 | VEX_W_0FC4_P_2, |
| 1441 | VEX_W_0FC5_P_2, |
| 1442 | VEX_W_0FD0_P_2, |
| 1443 | VEX_W_0FD0_P_3, |
| 1444 | VEX_W_0FD1_P_2, |
| 1445 | VEX_W_0FD2_P_2, |
| 1446 | VEX_W_0FD3_P_2, |
| 1447 | VEX_W_0FD4_P_2, |
| 1448 | VEX_W_0FD5_P_2, |
| 1449 | VEX_W_0FD6_P_2, |
| 1450 | VEX_W_0FD7_P_2_M_1, |
| 1451 | VEX_W_0FD8_P_2, |
| 1452 | VEX_W_0FD9_P_2, |
| 1453 | VEX_W_0FDA_P_2, |
| 1454 | VEX_W_0FDB_P_2, |
| 1455 | VEX_W_0FDC_P_2, |
| 1456 | VEX_W_0FDD_P_2, |
| 1457 | VEX_W_0FDE_P_2, |
| 1458 | VEX_W_0FDF_P_2, |
| 1459 | VEX_W_0FE0_P_2, |
| 1460 | VEX_W_0FE1_P_2, |
| 1461 | VEX_W_0FE2_P_2, |
| 1462 | VEX_W_0FE3_P_2, |
| 1463 | VEX_W_0FE4_P_2, |
| 1464 | VEX_W_0FE5_P_2, |
| 1465 | VEX_W_0FE6_P_1, |
| 1466 | VEX_W_0FE6_P_2, |
| 1467 | VEX_W_0FE6_P_3, |
| 1468 | VEX_W_0FE7_P_2_M_0, |
| 1469 | VEX_W_0FE8_P_2, |
| 1470 | VEX_W_0FE9_P_2, |
| 1471 | VEX_W_0FEA_P_2, |
| 1472 | VEX_W_0FEB_P_2, |
| 1473 | VEX_W_0FEC_P_2, |
| 1474 | VEX_W_0FED_P_2, |
| 1475 | VEX_W_0FEE_P_2, |
| 1476 | VEX_W_0FEF_P_2, |
| 1477 | VEX_W_0FF0_P_3_M_0, |
| 1478 | VEX_W_0FF1_P_2, |
| 1479 | VEX_W_0FF2_P_2, |
| 1480 | VEX_W_0FF3_P_2, |
| 1481 | VEX_W_0FF4_P_2, |
| 1482 | VEX_W_0FF5_P_2, |
| 1483 | VEX_W_0FF6_P_2, |
| 1484 | VEX_W_0FF7_P_2, |
| 1485 | VEX_W_0FF8_P_2, |
| 1486 | VEX_W_0FF9_P_2, |
| 1487 | VEX_W_0FFA_P_2, |
| 1488 | VEX_W_0FFB_P_2, |
| 1489 | VEX_W_0FFC_P_2, |
| 1490 | VEX_W_0FFD_P_2, |
| 1491 | VEX_W_0FFE_P_2, |
| 1492 | VEX_W_0F3800_P_2, |
| 1493 | VEX_W_0F3801_P_2, |
| 1494 | VEX_W_0F3802_P_2, |
| 1495 | VEX_W_0F3803_P_2, |
| 1496 | VEX_W_0F3804_P_2, |
| 1497 | VEX_W_0F3805_P_2, |
| 1498 | VEX_W_0F3806_P_2, |
| 1499 | VEX_W_0F3807_P_2, |
| 1500 | VEX_W_0F3808_P_2, |
| 1501 | VEX_W_0F3809_P_2, |
| 1502 | VEX_W_0F380A_P_2, |
| 1503 | VEX_W_0F380B_P_2, |
| 1504 | VEX_W_0F380C_P_2, |
| 1505 | VEX_W_0F380D_P_2, |
| 1506 | VEX_W_0F380E_P_2, |
| 1507 | VEX_W_0F380F_P_2, |
| 1508 | VEX_W_0F3816_P_2, |
| 1509 | VEX_W_0F3817_P_2, |
| 1510 | VEX_W_0F3818_P_2, |
| 1511 | VEX_W_0F3819_P_2, |
| 1512 | VEX_W_0F381A_P_2_M_0, |
| 1513 | VEX_W_0F381C_P_2, |
| 1514 | VEX_W_0F381D_P_2, |
| 1515 | VEX_W_0F381E_P_2, |
| 1516 | VEX_W_0F3820_P_2, |
| 1517 | VEX_W_0F3821_P_2, |
| 1518 | VEX_W_0F3822_P_2, |
| 1519 | VEX_W_0F3823_P_2, |
| 1520 | VEX_W_0F3824_P_2, |
| 1521 | VEX_W_0F3825_P_2, |
| 1522 | VEX_W_0F3828_P_2, |
| 1523 | VEX_W_0F3829_P_2, |
| 1524 | VEX_W_0F382A_P_2_M_0, |
| 1525 | VEX_W_0F382B_P_2, |
| 1526 | VEX_W_0F382C_P_2_M_0, |
| 1527 | VEX_W_0F382D_P_2_M_0, |
| 1528 | VEX_W_0F382E_P_2_M_0, |
| 1529 | VEX_W_0F382F_P_2_M_0, |
| 1530 | VEX_W_0F3830_P_2, |
| 1531 | VEX_W_0F3831_P_2, |
| 1532 | VEX_W_0F3832_P_2, |
| 1533 | VEX_W_0F3833_P_2, |
| 1534 | VEX_W_0F3834_P_2, |
| 1535 | VEX_W_0F3835_P_2, |
| 1536 | VEX_W_0F3836_P_2, |
| 1537 | VEX_W_0F3837_P_2, |
| 1538 | VEX_W_0F3838_P_2, |
| 1539 | VEX_W_0F3839_P_2, |
| 1540 | VEX_W_0F383A_P_2, |
| 1541 | VEX_W_0F383B_P_2, |
| 1542 | VEX_W_0F383C_P_2, |
| 1543 | VEX_W_0F383D_P_2, |
| 1544 | VEX_W_0F383E_P_2, |
| 1545 | VEX_W_0F383F_P_2, |
| 1546 | VEX_W_0F3840_P_2, |
| 1547 | VEX_W_0F3841_P_2, |
| 1548 | VEX_W_0F3846_P_2, |
| 1549 | VEX_W_0F3858_P_2, |
| 1550 | VEX_W_0F3859_P_2, |
| 1551 | VEX_W_0F385A_P_2_M_0, |
| 1552 | VEX_W_0F3878_P_2, |
| 1553 | VEX_W_0F3879_P_2, |
| 1554 | VEX_W_0F38DB_P_2, |
| 1555 | VEX_W_0F38DC_P_2, |
| 1556 | VEX_W_0F38DD_P_2, |
| 1557 | VEX_W_0F38DE_P_2, |
| 1558 | VEX_W_0F38DF_P_2, |
| 1559 | VEX_W_0F3A00_P_2, |
| 1560 | VEX_W_0F3A01_P_2, |
| 1561 | VEX_W_0F3A02_P_2, |
| 1562 | VEX_W_0F3A04_P_2, |
| 1563 | VEX_W_0F3A05_P_2, |
| 1564 | VEX_W_0F3A06_P_2, |
| 1565 | VEX_W_0F3A08_P_2, |
| 1566 | VEX_W_0F3A09_P_2, |
| 1567 | VEX_W_0F3A0A_P_2, |
| 1568 | VEX_W_0F3A0B_P_2, |
| 1569 | VEX_W_0F3A0C_P_2, |
| 1570 | VEX_W_0F3A0D_P_2, |
| 1571 | VEX_W_0F3A0E_P_2, |
| 1572 | VEX_W_0F3A0F_P_2, |
| 1573 | VEX_W_0F3A14_P_2, |
| 1574 | VEX_W_0F3A15_P_2, |
| 1575 | VEX_W_0F3A18_P_2, |
| 1576 | VEX_W_0F3A19_P_2, |
| 1577 | VEX_W_0F3A20_P_2, |
| 1578 | VEX_W_0F3A21_P_2, |
| 1579 | VEX_W_0F3A38_P_2, |
| 1580 | VEX_W_0F3A39_P_2, |
| 1581 | VEX_W_0F3A40_P_2, |
| 1582 | VEX_W_0F3A41_P_2, |
| 1583 | VEX_W_0F3A42_P_2, |
| 1584 | VEX_W_0F3A44_P_2, |
| 1585 | VEX_W_0F3A46_P_2, |
| 1586 | VEX_W_0F3A48_P_2, |
| 1587 | VEX_W_0F3A49_P_2, |
| 1588 | VEX_W_0F3A4A_P_2, |
| 1589 | VEX_W_0F3A4B_P_2, |
| 1590 | VEX_W_0F3A4C_P_2, |
| 1591 | VEX_W_0F3A60_P_2, |
| 1592 | VEX_W_0F3A61_P_2, |
| 1593 | VEX_W_0F3A62_P_2, |
| 1594 | VEX_W_0F3A63_P_2, |
| 1595 | VEX_W_0F3ADF_P_2 |
| 1596 | }; |
| 1597 | |
| 1598 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
| 1599 | |
| 1600 | struct dis386 { |
| 1601 | const char *name; |
| 1602 | struct |
| 1603 | { |
| 1604 | op_rtn rtn; |
| 1605 | int bytemode; |
| 1606 | } op[MAX_OPERANDS]; |
| 1607 | }; |
| 1608 | |
| 1609 | /* Upper case letters in the instruction names here are macros. |
| 1610 | 'A' => print 'b' if no register operands or suffix_always is true |
| 1611 | 'B' => print 'b' if suffix_always is true |
| 1612 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
| 1613 | size prefix |
| 1614 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
| 1615 | suffix_always is true |
| 1616 | 'E' => print 'e' if 32-bit form of jcxz |
| 1617 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
| 1618 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
| 1619 | 'H' => print ",pt" or ",pn" branch hint |
| 1620 | 'I' => honor following macro letter even in Intel mode (implemented only |
| 1621 | for some of the macro letters) |
| 1622 | 'J' => print 'l' |
| 1623 | 'K' => print 'd' or 'q' if rex prefix is present. |
| 1624 | 'L' => print 'l' if suffix_always is true |
| 1625 | 'M' => print 'r' if intel_mnemonic is false. |
| 1626 | 'N' => print 'n' if instruction has no wait "prefix" |
| 1627 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
| 1628 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
| 1629 | or suffix_always is true. print 'q' if rex prefix is present. |
| 1630 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
| 1631 | is true |
| 1632 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
| 1633 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
| 1634 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
| 1635 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise |
| 1636 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
| 1637 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
| 1638 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
| 1639 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
| 1640 | suffix_always is true. |
| 1641 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
| 1642 | '!' => change condition from true to false or from false to true. |
| 1643 | '%' => add 1 upper case letter to the macro. |
| 1644 | |
| 1645 | 2 upper case letter macros: |
| 1646 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
| 1647 | is true. |
| 1648 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
| 1649 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
| 1650 | or suffix_always is true |
| 1651 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
| 1652 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
| 1653 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
| 1654 | "LW" => print 'd', 'q' depending on the VEX.W bit |
| 1655 | |
| 1656 | Many of the above letters print nothing in Intel mode. See "putop" |
| 1657 | for the details. |
| 1658 | |
| 1659 | Braces '{' and '}', and vertical bars '|', indicate alternative |
| 1660 | mnemonic strings for AT&T and Intel. */ |
| 1661 | |
| 1662 | static const struct dis386 dis386[] = { |
| 1663 | /* 00 */ |
| 1664 | { "addB", { Ebh1, Gb } }, |
| 1665 | { "addS", { Evh1, Gv } }, |
| 1666 | { "addB", { Gb, EbS } }, |
| 1667 | { "addS", { Gv, EvS } }, |
| 1668 | { "addB", { AL, Ib } }, |
| 1669 | { "addS", { eAX, Iv } }, |
| 1670 | { X86_64_TABLE (X86_64_06) }, |
| 1671 | { X86_64_TABLE (X86_64_07) }, |
| 1672 | /* 08 */ |
| 1673 | { "orB", { Ebh1, Gb } }, |
| 1674 | { "orS", { Evh1, Gv } }, |
| 1675 | { "orB", { Gb, EbS } }, |
| 1676 | { "orS", { Gv, EvS } }, |
| 1677 | { "orB", { AL, Ib } }, |
| 1678 | { "orS", { eAX, Iv } }, |
| 1679 | { X86_64_TABLE (X86_64_0D) }, |
| 1680 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
| 1681 | /* 10 */ |
| 1682 | { "adcB", { Ebh1, Gb } }, |
| 1683 | { "adcS", { Evh1, Gv } }, |
| 1684 | { "adcB", { Gb, EbS } }, |
| 1685 | { "adcS", { Gv, EvS } }, |
| 1686 | { "adcB", { AL, Ib } }, |
| 1687 | { "adcS", { eAX, Iv } }, |
| 1688 | { X86_64_TABLE (X86_64_16) }, |
| 1689 | { X86_64_TABLE (X86_64_17) }, |
| 1690 | /* 18 */ |
| 1691 | { "sbbB", { Ebh1, Gb } }, |
| 1692 | { "sbbS", { Evh1, Gv } }, |
| 1693 | { "sbbB", { Gb, EbS } }, |
| 1694 | { "sbbS", { Gv, EvS } }, |
| 1695 | { "sbbB", { AL, Ib } }, |
| 1696 | { "sbbS", { eAX, Iv } }, |
| 1697 | { X86_64_TABLE (X86_64_1E) }, |
| 1698 | { X86_64_TABLE (X86_64_1F) }, |
| 1699 | /* 20 */ |
| 1700 | { "andB", { Ebh1, Gb } }, |
| 1701 | { "andS", { Evh1, Gv } }, |
| 1702 | { "andB", { Gb, EbS } }, |
| 1703 | { "andS", { Gv, EvS } }, |
| 1704 | { "andB", { AL, Ib } }, |
| 1705 | { "andS", { eAX, Iv } }, |
| 1706 | { Bad_Opcode }, /* SEG ES prefix */ |
| 1707 | { X86_64_TABLE (X86_64_27) }, |
| 1708 | /* 28 */ |
| 1709 | { "subB", { Ebh1, Gb } }, |
| 1710 | { "subS", { Evh1, Gv } }, |
| 1711 | { "subB", { Gb, EbS } }, |
| 1712 | { "subS", { Gv, EvS } }, |
| 1713 | { "subB", { AL, Ib } }, |
| 1714 | { "subS", { eAX, Iv } }, |
| 1715 | { Bad_Opcode }, /* SEG CS prefix */ |
| 1716 | { X86_64_TABLE (X86_64_2F) }, |
| 1717 | /* 30 */ |
| 1718 | { "xorB", { Ebh1, Gb } }, |
| 1719 | { "xorS", { Evh1, Gv } }, |
| 1720 | { "xorB", { Gb, EbS } }, |
| 1721 | { "xorS", { Gv, EvS } }, |
| 1722 | { "xorB", { AL, Ib } }, |
| 1723 | { "xorS", { eAX, Iv } }, |
| 1724 | { Bad_Opcode }, /* SEG SS prefix */ |
| 1725 | { X86_64_TABLE (X86_64_37) }, |
| 1726 | /* 38 */ |
| 1727 | { "cmpB", { Eb, Gb } }, |
| 1728 | { "cmpS", { Ev, Gv } }, |
| 1729 | { "cmpB", { Gb, EbS } }, |
| 1730 | { "cmpS", { Gv, EvS } }, |
| 1731 | { "cmpB", { AL, Ib } }, |
| 1732 | { "cmpS", { eAX, Iv } }, |
| 1733 | { Bad_Opcode }, /* SEG DS prefix */ |
| 1734 | { X86_64_TABLE (X86_64_3F) }, |
| 1735 | /* 40 */ |
| 1736 | { "inc{S|}", { RMeAX } }, |
| 1737 | { "inc{S|}", { RMeCX } }, |
| 1738 | { "inc{S|}", { RMeDX } }, |
| 1739 | { "inc{S|}", { RMeBX } }, |
| 1740 | { "inc{S|}", { RMeSP } }, |
| 1741 | { "inc{S|}", { RMeBP } }, |
| 1742 | { "inc{S|}", { RMeSI } }, |
| 1743 | { "inc{S|}", { RMeDI } }, |
| 1744 | /* 48 */ |
| 1745 | { "dec{S|}", { RMeAX } }, |
| 1746 | { "dec{S|}", { RMeCX } }, |
| 1747 | { "dec{S|}", { RMeDX } }, |
| 1748 | { "dec{S|}", { RMeBX } }, |
| 1749 | { "dec{S|}", { RMeSP } }, |
| 1750 | { "dec{S|}", { RMeBP } }, |
| 1751 | { "dec{S|}", { RMeSI } }, |
| 1752 | { "dec{S|}", { RMeDI } }, |
| 1753 | /* 50 */ |
| 1754 | { "pushV", { RMrAX } }, |
| 1755 | { "pushV", { RMrCX } }, |
| 1756 | { "pushV", { RMrDX } }, |
| 1757 | { "pushV", { RMrBX } }, |
| 1758 | { "pushV", { RMrSP } }, |
| 1759 | { "pushV", { RMrBP } }, |
| 1760 | { "pushV", { RMrSI } }, |
| 1761 | { "pushV", { RMrDI } }, |
| 1762 | /* 58 */ |
| 1763 | { "popV", { RMrAX } }, |
| 1764 | { "popV", { RMrCX } }, |
| 1765 | { "popV", { RMrDX } }, |
| 1766 | { "popV", { RMrBX } }, |
| 1767 | { "popV", { RMrSP } }, |
| 1768 | { "popV", { RMrBP } }, |
| 1769 | { "popV", { RMrSI } }, |
| 1770 | { "popV", { RMrDI } }, |
| 1771 | /* 60 */ |
| 1772 | { X86_64_TABLE (X86_64_60) }, |
| 1773 | { X86_64_TABLE (X86_64_61) }, |
| 1774 | { X86_64_TABLE (X86_64_62) }, |
| 1775 | { X86_64_TABLE (X86_64_63) }, |
| 1776 | { Bad_Opcode }, /* seg fs */ |
| 1777 | { Bad_Opcode }, /* seg gs */ |
| 1778 | { Bad_Opcode }, /* op size prefix */ |
| 1779 | { Bad_Opcode }, /* adr size prefix */ |
| 1780 | /* 68 */ |
| 1781 | { "pushT", { sIv } }, |
| 1782 | { "imulS", { Gv, Ev, Iv } }, |
| 1783 | { "pushT", { sIbT } }, |
| 1784 | { "imulS", { Gv, Ev, sIb } }, |
| 1785 | { "ins{b|}", { Ybr, indirDX } }, |
| 1786 | { X86_64_TABLE (X86_64_6D) }, |
| 1787 | { "outs{b|}", { indirDXr, Xb } }, |
| 1788 | { X86_64_TABLE (X86_64_6F) }, |
| 1789 | /* 70 */ |
| 1790 | { "joH", { Jb, XX, cond_jump_flag } }, |
| 1791 | { "jnoH", { Jb, XX, cond_jump_flag } }, |
| 1792 | { "jbH", { Jb, XX, cond_jump_flag } }, |
| 1793 | { "jaeH", { Jb, XX, cond_jump_flag } }, |
| 1794 | { "jeH", { Jb, XX, cond_jump_flag } }, |
| 1795 | { "jneH", { Jb, XX, cond_jump_flag } }, |
| 1796 | { "jbeH", { Jb, XX, cond_jump_flag } }, |
| 1797 | { "jaH", { Jb, XX, cond_jump_flag } }, |
| 1798 | /* 78 */ |
| 1799 | { "jsH", { Jb, XX, cond_jump_flag } }, |
| 1800 | { "jnsH", { Jb, XX, cond_jump_flag } }, |
| 1801 | { "jpH", { Jb, XX, cond_jump_flag } }, |
| 1802 | { "jnpH", { Jb, XX, cond_jump_flag } }, |
| 1803 | { "jlH", { Jb, XX, cond_jump_flag } }, |
| 1804 | { "jgeH", { Jb, XX, cond_jump_flag } }, |
| 1805 | { "jleH", { Jb, XX, cond_jump_flag } }, |
| 1806 | { "jgH", { Jb, XX, cond_jump_flag } }, |
| 1807 | /* 80 */ |
| 1808 | { REG_TABLE (REG_80) }, |
| 1809 | { REG_TABLE (REG_81) }, |
| 1810 | { Bad_Opcode }, |
| 1811 | { REG_TABLE (REG_82) }, |
| 1812 | { "testB", { Eb, Gb } }, |
| 1813 | { "testS", { Ev, Gv } }, |
| 1814 | { "xchgB", { Ebh2, Gb } }, |
| 1815 | { "xchgS", { Evh2, Gv } }, |
| 1816 | /* 88 */ |
| 1817 | { "movB", { Ebh3, Gb } }, |
| 1818 | { "movS", { Evh3, Gv } }, |
| 1819 | { "movB", { Gb, EbS } }, |
| 1820 | { "movS", { Gv, EvS } }, |
| 1821 | { "movD", { Sv, Sw } }, |
| 1822 | { MOD_TABLE (MOD_8D) }, |
| 1823 | { "movD", { Sw, Sv } }, |
| 1824 | { REG_TABLE (REG_8F) }, |
| 1825 | /* 90 */ |
| 1826 | { PREFIX_TABLE (PREFIX_90) }, |
| 1827 | { "xchgS", { RMeCX, eAX } }, |
| 1828 | { "xchgS", { RMeDX, eAX } }, |
| 1829 | { "xchgS", { RMeBX, eAX } }, |
| 1830 | { "xchgS", { RMeSP, eAX } }, |
| 1831 | { "xchgS", { RMeBP, eAX } }, |
| 1832 | { "xchgS", { RMeSI, eAX } }, |
| 1833 | { "xchgS", { RMeDI, eAX } }, |
| 1834 | /* 98 */ |
| 1835 | { "cW{t|}R", { XX } }, |
| 1836 | { "cR{t|}O", { XX } }, |
| 1837 | { X86_64_TABLE (X86_64_9A) }, |
| 1838 | { Bad_Opcode }, /* fwait */ |
| 1839 | { "pushfT", { XX } }, |
| 1840 | { "popfT", { XX } }, |
| 1841 | { "sahf", { XX } }, |
| 1842 | { "lahf", { XX } }, |
| 1843 | /* a0 */ |
| 1844 | { "mov%LB", { AL, Ob } }, |
| 1845 | { "mov%LS", { eAX, Ov } }, |
| 1846 | { "mov%LB", { Ob, AL } }, |
| 1847 | { "mov%LS", { Ov, eAX } }, |
| 1848 | { "movs{b|}", { Ybr, Xb } }, |
| 1849 | { "movs{R|}", { Yvr, Xv } }, |
| 1850 | { "cmps{b|}", { Xb, Yb } }, |
| 1851 | { "cmps{R|}", { Xv, Yv } }, |
| 1852 | /* a8 */ |
| 1853 | { "testB", { AL, Ib } }, |
| 1854 | { "testS", { eAX, Iv } }, |
| 1855 | { "stosB", { Ybr, AL } }, |
| 1856 | { "stosS", { Yvr, eAX } }, |
| 1857 | { "lodsB", { ALr, Xb } }, |
| 1858 | { "lodsS", { eAXr, Xv } }, |
| 1859 | { "scasB", { AL, Yb } }, |
| 1860 | { "scasS", { eAX, Yv } }, |
| 1861 | /* b0 */ |
| 1862 | { "movB", { RMAL, Ib } }, |
| 1863 | { "movB", { RMCL, Ib } }, |
| 1864 | { "movB", { RMDL, Ib } }, |
| 1865 | { "movB", { RMBL, Ib } }, |
| 1866 | { "movB", { RMAH, Ib } }, |
| 1867 | { "movB", { RMCH, Ib } }, |
| 1868 | { "movB", { RMDH, Ib } }, |
| 1869 | { "movB", { RMBH, Ib } }, |
| 1870 | /* b8 */ |
| 1871 | { "mov%LV", { RMeAX, Iv64 } }, |
| 1872 | { "mov%LV", { RMeCX, Iv64 } }, |
| 1873 | { "mov%LV", { RMeDX, Iv64 } }, |
| 1874 | { "mov%LV", { RMeBX, Iv64 } }, |
| 1875 | { "mov%LV", { RMeSP, Iv64 } }, |
| 1876 | { "mov%LV", { RMeBP, Iv64 } }, |
| 1877 | { "mov%LV", { RMeSI, Iv64 } }, |
| 1878 | { "mov%LV", { RMeDI, Iv64 } }, |
| 1879 | /* c0 */ |
| 1880 | { REG_TABLE (REG_C0) }, |
| 1881 | { REG_TABLE (REG_C1) }, |
| 1882 | { "retT", { Iw } }, |
| 1883 | { "retT", { XX } }, |
| 1884 | { X86_64_TABLE (X86_64_C4) }, |
| 1885 | { X86_64_TABLE (X86_64_C5) }, |
| 1886 | { REG_TABLE (REG_C6) }, |
| 1887 | { REG_TABLE (REG_C7) }, |
| 1888 | /* c8 */ |
| 1889 | { "enterT", { Iw, Ib } }, |
| 1890 | { "leaveT", { XX } }, |
| 1891 | { "Jret{|f}P", { Iw } }, |
| 1892 | { "Jret{|f}P", { XX } }, |
| 1893 | { "int3", { XX } }, |
| 1894 | { "int", { Ib } }, |
| 1895 | { X86_64_TABLE (X86_64_CE) }, |
| 1896 | { "iretP", { XX } }, |
| 1897 | /* d0 */ |
| 1898 | { REG_TABLE (REG_D0) }, |
| 1899 | { REG_TABLE (REG_D1) }, |
| 1900 | { REG_TABLE (REG_D2) }, |
| 1901 | { REG_TABLE (REG_D3) }, |
| 1902 | { X86_64_TABLE (X86_64_D4) }, |
| 1903 | { X86_64_TABLE (X86_64_D5) }, |
| 1904 | { Bad_Opcode }, |
| 1905 | { "xlat", { DSBX } }, |
| 1906 | /* d8 */ |
| 1907 | { FLOAT }, |
| 1908 | { FLOAT }, |
| 1909 | { FLOAT }, |
| 1910 | { FLOAT }, |
| 1911 | { FLOAT }, |
| 1912 | { FLOAT }, |
| 1913 | { FLOAT }, |
| 1914 | { FLOAT }, |
| 1915 | /* e0 */ |
| 1916 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
| 1917 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, |
| 1918 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, |
| 1919 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, |
| 1920 | { "inB", { AL, Ib } }, |
| 1921 | { "inG", { zAX, Ib } }, |
| 1922 | { "outB", { Ib, AL } }, |
| 1923 | { "outG", { Ib, zAX } }, |
| 1924 | /* e8 */ |
| 1925 | { "callT", { Jv } }, |
| 1926 | { "jmpT", { Jv } }, |
| 1927 | { X86_64_TABLE (X86_64_EA) }, |
| 1928 | { "jmp", { Jb } }, |
| 1929 | { "inB", { AL, indirDX } }, |
| 1930 | { "inG", { zAX, indirDX } }, |
| 1931 | { "outB", { indirDX, AL } }, |
| 1932 | { "outG", { indirDX, zAX } }, |
| 1933 | /* f0 */ |
| 1934 | { Bad_Opcode }, /* lock prefix */ |
| 1935 | { "icebp", { XX } }, |
| 1936 | { Bad_Opcode }, /* repne */ |
| 1937 | { Bad_Opcode }, /* repz */ |
| 1938 | { "hlt", { XX } }, |
| 1939 | { "cmc", { XX } }, |
| 1940 | { REG_TABLE (REG_F6) }, |
| 1941 | { REG_TABLE (REG_F7) }, |
| 1942 | /* f8 */ |
| 1943 | { "clc", { XX } }, |
| 1944 | { "stc", { XX } }, |
| 1945 | { "cli", { XX } }, |
| 1946 | { "sti", { XX } }, |
| 1947 | { "cld", { XX } }, |
| 1948 | { "std", { XX } }, |
| 1949 | { REG_TABLE (REG_FE) }, |
| 1950 | { REG_TABLE (REG_FF) }, |
| 1951 | }; |
| 1952 | |
| 1953 | static const struct dis386 dis386_twobyte[] = { |
| 1954 | /* 00 */ |
| 1955 | { REG_TABLE (REG_0F00 ) }, |
| 1956 | { REG_TABLE (REG_0F01 ) }, |
| 1957 | { "larS", { Gv, Ew } }, |
| 1958 | { "lslS", { Gv, Ew } }, |
| 1959 | { Bad_Opcode }, |
| 1960 | { "syscall", { XX } }, |
| 1961 | { "clts", { XX } }, |
| 1962 | { "sysretP", { XX } }, |
| 1963 | /* 08 */ |
| 1964 | { "invd", { XX } }, |
| 1965 | { "wbinvd", { XX } }, |
| 1966 | { Bad_Opcode }, |
| 1967 | { "ud2", { XX } }, |
| 1968 | { Bad_Opcode }, |
| 1969 | { REG_TABLE (REG_0F0D) }, |
| 1970 | { "femms", { XX } }, |
| 1971 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ |
| 1972 | /* 10 */ |
| 1973 | { PREFIX_TABLE (PREFIX_0F10) }, |
| 1974 | { PREFIX_TABLE (PREFIX_0F11) }, |
| 1975 | { PREFIX_TABLE (PREFIX_0F12) }, |
| 1976 | { MOD_TABLE (MOD_0F13) }, |
| 1977 | { "unpcklpX", { XM, EXx } }, |
| 1978 | { "unpckhpX", { XM, EXx } }, |
| 1979 | { PREFIX_TABLE (PREFIX_0F16) }, |
| 1980 | { MOD_TABLE (MOD_0F17) }, |
| 1981 | /* 18 */ |
| 1982 | { REG_TABLE (REG_0F18) }, |
| 1983 | { "nopQ", { Ev } }, |
| 1984 | { "nopQ", { Ev } }, |
| 1985 | { "nopQ", { Ev } }, |
| 1986 | { "nopQ", { Ev } }, |
| 1987 | { "nopQ", { Ev } }, |
| 1988 | { "nopQ", { Ev } }, |
| 1989 | { "nopQ", { Ev } }, |
| 1990 | /* 20 */ |
| 1991 | { MOD_TABLE (MOD_0F20) }, |
| 1992 | { MOD_TABLE (MOD_0F21) }, |
| 1993 | { MOD_TABLE (MOD_0F22) }, |
| 1994 | { MOD_TABLE (MOD_0F23) }, |
| 1995 | { MOD_TABLE (MOD_0F24) }, |
| 1996 | { Bad_Opcode }, |
| 1997 | { MOD_TABLE (MOD_0F26) }, |
| 1998 | { Bad_Opcode }, |
| 1999 | /* 28 */ |
| 2000 | { "movapX", { XM, EXx } }, |
| 2001 | { "movapX", { EXxS, XM } }, |
| 2002 | { PREFIX_TABLE (PREFIX_0F2A) }, |
| 2003 | { PREFIX_TABLE (PREFIX_0F2B) }, |
| 2004 | { PREFIX_TABLE (PREFIX_0F2C) }, |
| 2005 | { PREFIX_TABLE (PREFIX_0F2D) }, |
| 2006 | { PREFIX_TABLE (PREFIX_0F2E) }, |
| 2007 | { PREFIX_TABLE (PREFIX_0F2F) }, |
| 2008 | /* 30 */ |
| 2009 | { "wrmsr", { XX } }, |
| 2010 | { "rdtsc", { XX } }, |
| 2011 | { "rdmsr", { XX } }, |
| 2012 | { "rdpmc", { XX } }, |
| 2013 | { "sysenter", { XX } }, |
| 2014 | { "sysexit", { XX } }, |
| 2015 | { Bad_Opcode }, |
| 2016 | { "getsec", { XX } }, |
| 2017 | /* 38 */ |
| 2018 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
| 2019 | { Bad_Opcode }, |
| 2020 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
| 2021 | { Bad_Opcode }, |
| 2022 | { Bad_Opcode }, |
| 2023 | { Bad_Opcode }, |
| 2024 | { Bad_Opcode }, |
| 2025 | { Bad_Opcode }, |
| 2026 | /* 40 */ |
| 2027 | { "cmovoS", { Gv, Ev } }, |
| 2028 | { "cmovnoS", { Gv, Ev } }, |
| 2029 | { "cmovbS", { Gv, Ev } }, |
| 2030 | { "cmovaeS", { Gv, Ev } }, |
| 2031 | { "cmoveS", { Gv, Ev } }, |
| 2032 | { "cmovneS", { Gv, Ev } }, |
| 2033 | { "cmovbeS", { Gv, Ev } }, |
| 2034 | { "cmovaS", { Gv, Ev } }, |
| 2035 | /* 48 */ |
| 2036 | { "cmovsS", { Gv, Ev } }, |
| 2037 | { "cmovnsS", { Gv, Ev } }, |
| 2038 | { "cmovpS", { Gv, Ev } }, |
| 2039 | { "cmovnpS", { Gv, Ev } }, |
| 2040 | { "cmovlS", { Gv, Ev } }, |
| 2041 | { "cmovgeS", { Gv, Ev } }, |
| 2042 | { "cmovleS", { Gv, Ev } }, |
| 2043 | { "cmovgS", { Gv, Ev } }, |
| 2044 | /* 50 */ |
| 2045 | { MOD_TABLE (MOD_0F51) }, |
| 2046 | { PREFIX_TABLE (PREFIX_0F51) }, |
| 2047 | { PREFIX_TABLE (PREFIX_0F52) }, |
| 2048 | { PREFIX_TABLE (PREFIX_0F53) }, |
| 2049 | { "andpX", { XM, EXx } }, |
| 2050 | { "andnpX", { XM, EXx } }, |
| 2051 | { "orpX", { XM, EXx } }, |
| 2052 | { "xorpX", { XM, EXx } }, |
| 2053 | /* 58 */ |
| 2054 | { PREFIX_TABLE (PREFIX_0F58) }, |
| 2055 | { PREFIX_TABLE (PREFIX_0F59) }, |
| 2056 | { PREFIX_TABLE (PREFIX_0F5A) }, |
| 2057 | { PREFIX_TABLE (PREFIX_0F5B) }, |
| 2058 | { PREFIX_TABLE (PREFIX_0F5C) }, |
| 2059 | { PREFIX_TABLE (PREFIX_0F5D) }, |
| 2060 | { PREFIX_TABLE (PREFIX_0F5E) }, |
| 2061 | { PREFIX_TABLE (PREFIX_0F5F) }, |
| 2062 | /* 60 */ |
| 2063 | { PREFIX_TABLE (PREFIX_0F60) }, |
| 2064 | { PREFIX_TABLE (PREFIX_0F61) }, |
| 2065 | { PREFIX_TABLE (PREFIX_0F62) }, |
| 2066 | { "packsswb", { MX, EM } }, |
| 2067 | { "pcmpgtb", { MX, EM } }, |
| 2068 | { "pcmpgtw", { MX, EM } }, |
| 2069 | { "pcmpgtd", { MX, EM } }, |
| 2070 | { "packuswb", { MX, EM } }, |
| 2071 | /* 68 */ |
| 2072 | { "punpckhbw", { MX, EM } }, |
| 2073 | { "punpckhwd", { MX, EM } }, |
| 2074 | { "punpckhdq", { MX, EM } }, |
| 2075 | { "packssdw", { MX, EM } }, |
| 2076 | { PREFIX_TABLE (PREFIX_0F6C) }, |
| 2077 | { PREFIX_TABLE (PREFIX_0F6D) }, |
| 2078 | { "movK", { MX, Edq } }, |
| 2079 | { PREFIX_TABLE (PREFIX_0F6F) }, |
| 2080 | /* 70 */ |
| 2081 | { PREFIX_TABLE (PREFIX_0F70) }, |
| 2082 | { REG_TABLE (REG_0F71) }, |
| 2083 | { REG_TABLE (REG_0F72) }, |
| 2084 | { REG_TABLE (REG_0F73) }, |
| 2085 | { "pcmpeqb", { MX, EM } }, |
| 2086 | { "pcmpeqw", { MX, EM } }, |
| 2087 | { "pcmpeqd", { MX, EM } }, |
| 2088 | { "emms", { XX } }, |
| 2089 | /* 78 */ |
| 2090 | { PREFIX_TABLE (PREFIX_0F78) }, |
| 2091 | { PREFIX_TABLE (PREFIX_0F79) }, |
| 2092 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
| 2093 | { Bad_Opcode }, |
| 2094 | { PREFIX_TABLE (PREFIX_0F7C) }, |
| 2095 | { PREFIX_TABLE (PREFIX_0F7D) }, |
| 2096 | { PREFIX_TABLE (PREFIX_0F7E) }, |
| 2097 | { PREFIX_TABLE (PREFIX_0F7F) }, |
| 2098 | /* 80 */ |
| 2099 | { "joH", { Jv, XX, cond_jump_flag } }, |
| 2100 | { "jnoH", { Jv, XX, cond_jump_flag } }, |
| 2101 | { "jbH", { Jv, XX, cond_jump_flag } }, |
| 2102 | { "jaeH", { Jv, XX, cond_jump_flag } }, |
| 2103 | { "jeH", { Jv, XX, cond_jump_flag } }, |
| 2104 | { "jneH", { Jv, XX, cond_jump_flag } }, |
| 2105 | { "jbeH", { Jv, XX, cond_jump_flag } }, |
| 2106 | { "jaH", { Jv, XX, cond_jump_flag } }, |
| 2107 | /* 88 */ |
| 2108 | { "jsH", { Jv, XX, cond_jump_flag } }, |
| 2109 | { "jnsH", { Jv, XX, cond_jump_flag } }, |
| 2110 | { "jpH", { Jv, XX, cond_jump_flag } }, |
| 2111 | { "jnpH", { Jv, XX, cond_jump_flag } }, |
| 2112 | { "jlH", { Jv, XX, cond_jump_flag } }, |
| 2113 | { "jgeH", { Jv, XX, cond_jump_flag } }, |
| 2114 | { "jleH", { Jv, XX, cond_jump_flag } }, |
| 2115 | { "jgH", { Jv, XX, cond_jump_flag } }, |
| 2116 | /* 90 */ |
| 2117 | { "seto", { Eb } }, |
| 2118 | { "setno", { Eb } }, |
| 2119 | { "setb", { Eb } }, |
| 2120 | { "setae", { Eb } }, |
| 2121 | { "sete", { Eb } }, |
| 2122 | { "setne", { Eb } }, |
| 2123 | { "setbe", { Eb } }, |
| 2124 | { "seta", { Eb } }, |
| 2125 | /* 98 */ |
| 2126 | { "sets", { Eb } }, |
| 2127 | { "setns", { Eb } }, |
| 2128 | { "setp", { Eb } }, |
| 2129 | { "setnp", { Eb } }, |
| 2130 | { "setl", { Eb } }, |
| 2131 | { "setge", { Eb } }, |
| 2132 | { "setle", { Eb } }, |
| 2133 | { "setg", { Eb } }, |
| 2134 | /* a0 */ |
| 2135 | { "pushT", { fs } }, |
| 2136 | { "popT", { fs } }, |
| 2137 | { "cpuid", { XX } }, |
| 2138 | { "btS", { Ev, Gv } }, |
| 2139 | { "shldS", { Ev, Gv, Ib } }, |
| 2140 | { "shldS", { Ev, Gv, CL } }, |
| 2141 | { REG_TABLE (REG_0FA6) }, |
| 2142 | { REG_TABLE (REG_0FA7) }, |
| 2143 | /* a8 */ |
| 2144 | { "pushT", { gs } }, |
| 2145 | { "popT", { gs } }, |
| 2146 | { "rsm", { XX } }, |
| 2147 | { "btsS", { Evh1, Gv } }, |
| 2148 | { "shrdS", { Ev, Gv, Ib } }, |
| 2149 | { "shrdS", { Ev, Gv, CL } }, |
| 2150 | { REG_TABLE (REG_0FAE) }, |
| 2151 | { "imulS", { Gv, Ev } }, |
| 2152 | /* b0 */ |
| 2153 | { "cmpxchgB", { Ebh1, Gb } }, |
| 2154 | { "cmpxchgS", { Evh1, Gv } }, |
| 2155 | { MOD_TABLE (MOD_0FB2) }, |
| 2156 | { "btrS", { Evh1, Gv } }, |
| 2157 | { MOD_TABLE (MOD_0FB4) }, |
| 2158 | { MOD_TABLE (MOD_0FB5) }, |
| 2159 | { "movz{bR|x}", { Gv, Eb } }, |
| 2160 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ |
| 2161 | /* b8 */ |
| 2162 | { PREFIX_TABLE (PREFIX_0FB8) }, |
| 2163 | { "ud1", { XX } }, |
| 2164 | { REG_TABLE (REG_0FBA) }, |
| 2165 | { "btcS", { Evh1, Gv } }, |
| 2166 | { PREFIX_TABLE (PREFIX_0FBC) }, |
| 2167 | { PREFIX_TABLE (PREFIX_0FBD) }, |
| 2168 | { "movs{bR|x}", { Gv, Eb } }, |
| 2169 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ |
| 2170 | /* c0 */ |
| 2171 | { "xaddB", { Ebh1, Gb } }, |
| 2172 | { "xaddS", { Evh1, Gv } }, |
| 2173 | { PREFIX_TABLE (PREFIX_0FC2) }, |
| 2174 | { PREFIX_TABLE (PREFIX_0FC3) }, |
| 2175 | { "pinsrw", { MX, Edqw, Ib } }, |
| 2176 | { "pextrw", { Gdq, MS, Ib } }, |
| 2177 | { "shufpX", { XM, EXx, Ib } }, |
| 2178 | { REG_TABLE (REG_0FC7) }, |
| 2179 | /* c8 */ |
| 2180 | { "bswap", { RMeAX } }, |
| 2181 | { "bswap", { RMeCX } }, |
| 2182 | { "bswap", { RMeDX } }, |
| 2183 | { "bswap", { RMeBX } }, |
| 2184 | { "bswap", { RMeSP } }, |
| 2185 | { "bswap", { RMeBP } }, |
| 2186 | { "bswap", { RMeSI } }, |
| 2187 | { "bswap", { RMeDI } }, |
| 2188 | /* d0 */ |
| 2189 | { PREFIX_TABLE (PREFIX_0FD0) }, |
| 2190 | { "psrlw", { MX, EM } }, |
| 2191 | { "psrld", { MX, EM } }, |
| 2192 | { "psrlq", { MX, EM } }, |
| 2193 | { "paddq", { MX, EM } }, |
| 2194 | { "pmullw", { MX, EM } }, |
| 2195 | { PREFIX_TABLE (PREFIX_0FD6) }, |
| 2196 | { MOD_TABLE (MOD_0FD7) }, |
| 2197 | /* d8 */ |
| 2198 | { "psubusb", { MX, EM } }, |
| 2199 | { "psubusw", { MX, EM } }, |
| 2200 | { "pminub", { MX, EM } }, |
| 2201 | { "pand", { MX, EM } }, |
| 2202 | { "paddusb", { MX, EM } }, |
| 2203 | { "paddusw", { MX, EM } }, |
| 2204 | { "pmaxub", { MX, EM } }, |
| 2205 | { "pandn", { MX, EM } }, |
| 2206 | /* e0 */ |
| 2207 | { "pavgb", { MX, EM } }, |
| 2208 | { "psraw", { MX, EM } }, |
| 2209 | { "psrad", { MX, EM } }, |
| 2210 | { "pavgw", { MX, EM } }, |
| 2211 | { "pmulhuw", { MX, EM } }, |
| 2212 | { "pmulhw", { MX, EM } }, |
| 2213 | { PREFIX_TABLE (PREFIX_0FE6) }, |
| 2214 | { PREFIX_TABLE (PREFIX_0FE7) }, |
| 2215 | /* e8 */ |
| 2216 | { "psubsb", { MX, EM } }, |
| 2217 | { "psubsw", { MX, EM } }, |
| 2218 | { "pminsw", { MX, EM } }, |
| 2219 | { "por", { MX, EM } }, |
| 2220 | { "paddsb", { MX, EM } }, |
| 2221 | { "paddsw", { MX, EM } }, |
| 2222 | { "pmaxsw", { MX, EM } }, |
| 2223 | { "pxor", { MX, EM } }, |
| 2224 | /* f0 */ |
| 2225 | { PREFIX_TABLE (PREFIX_0FF0) }, |
| 2226 | { "psllw", { MX, EM } }, |
| 2227 | { "pslld", { MX, EM } }, |
| 2228 | { "psllq", { MX, EM } }, |
| 2229 | { "pmuludq", { MX, EM } }, |
| 2230 | { "pmaddwd", { MX, EM } }, |
| 2231 | { "psadbw", { MX, EM } }, |
| 2232 | { PREFIX_TABLE (PREFIX_0FF7) }, |
| 2233 | /* f8 */ |
| 2234 | { "psubb", { MX, EM } }, |
| 2235 | { "psubw", { MX, EM } }, |
| 2236 | { "psubd", { MX, EM } }, |
| 2237 | { "psubq", { MX, EM } }, |
| 2238 | { "paddb", { MX, EM } }, |
| 2239 | { "paddw", { MX, EM } }, |
| 2240 | { "paddd", { MX, EM } }, |
| 2241 | { Bad_Opcode }, |
| 2242 | }; |
| 2243 | |
| 2244 | static const unsigned char onebyte_has_modrm[256] = { |
| 2245 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 2246 | /* ------------------------------- */ |
| 2247 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ |
| 2248 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ |
| 2249 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ |
| 2250 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ |
| 2251 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ |
| 2252 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ |
| 2253 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ |
| 2254 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ |
| 2255 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ |
| 2256 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ |
| 2257 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ |
| 2258 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ |
| 2259 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ |
| 2260 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ |
| 2261 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ |
| 2262 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ |
| 2263 | /* ------------------------------- */ |
| 2264 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 2265 | }; |
| 2266 | |
| 2267 | static const unsigned char twobyte_has_modrm[256] = { |
| 2268 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 2269 | /* ------------------------------- */ |
| 2270 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
| 2271 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
| 2272 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
| 2273 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
| 2274 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
| 2275 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
| 2276 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ |
| 2277 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
| 2278 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
| 2279 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ |
| 2280 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
| 2281 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
| 2282 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
| 2283 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
| 2284 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
| 2285 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
| 2286 | /* ------------------------------- */ |
| 2287 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 2288 | }; |
| 2289 | |
| 2290 | static char obuf[100]; |
| 2291 | static char *obufp; |
| 2292 | static char *mnemonicendp; |
| 2293 | static char scratchbuf[100]; |
| 2294 | static unsigned char *start_codep; |
| 2295 | static unsigned char *insn_codep; |
| 2296 | static unsigned char *codep; |
| 2297 | static int last_lock_prefix; |
| 2298 | static int last_repz_prefix; |
| 2299 | static int last_repnz_prefix; |
| 2300 | static int last_data_prefix; |
| 2301 | static int last_addr_prefix; |
| 2302 | static int last_rex_prefix; |
| 2303 | static int last_seg_prefix; |
| 2304 | #define MAX_CODE_LENGTH 15 |
| 2305 | /* We can up to 14 prefixes since the maximum instruction length is |
| 2306 | 15bytes. */ |
| 2307 | static int all_prefixes[MAX_CODE_LENGTH - 1]; |
| 2308 | static disassemble_info *the_info; |
| 2309 | static struct |
| 2310 | { |
| 2311 | int mod; |
| 2312 | int reg; |
| 2313 | int rm; |
| 2314 | } |
| 2315 | modrm; |
| 2316 | static unsigned char need_modrm; |
| 2317 | static struct |
| 2318 | { |
| 2319 | int scale; |
| 2320 | int index; |
| 2321 | int base; |
| 2322 | } |
| 2323 | sib; |
| 2324 | static struct |
| 2325 | { |
| 2326 | int register_specifier; |
| 2327 | int length; |
| 2328 | int prefix; |
| 2329 | int w; |
| 2330 | } |
| 2331 | vex; |
| 2332 | static unsigned char need_vex; |
| 2333 | static unsigned char need_vex_reg; |
| 2334 | static unsigned char vex_w_done; |
| 2335 | |
| 2336 | struct op |
| 2337 | { |
| 2338 | const char *name; |
| 2339 | unsigned int len; |
| 2340 | }; |
| 2341 | |
| 2342 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
| 2343 | values are stale. Hitting this abort likely indicates that you |
| 2344 | need to update onebyte_has_modrm or twobyte_has_modrm. */ |
| 2345 | #define MODRM_CHECK if (!need_modrm) abort () |
| 2346 | |
| 2347 | static const char **names64; |
| 2348 | static const char **names32; |
| 2349 | static const char **names16; |
| 2350 | static const char **names8; |
| 2351 | static const char **names8rex; |
| 2352 | static const char **names_seg; |
| 2353 | static const char *index64; |
| 2354 | static const char *index32; |
| 2355 | static const char **index16; |
| 2356 | |
| 2357 | static const char *intel_names64[] = { |
| 2358 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
| 2359 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
| 2360 | }; |
| 2361 | static const char *intel_names32[] = { |
| 2362 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", |
| 2363 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" |
| 2364 | }; |
| 2365 | static const char *intel_names16[] = { |
| 2366 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", |
| 2367 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
| 2368 | }; |
| 2369 | static const char *intel_names8[] = { |
| 2370 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", |
| 2371 | }; |
| 2372 | static const char *intel_names8rex[] = { |
| 2373 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", |
| 2374 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" |
| 2375 | }; |
| 2376 | static const char *intel_names_seg[] = { |
| 2377 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", |
| 2378 | }; |
| 2379 | static const char *intel_index64 = "riz"; |
| 2380 | static const char *intel_index32 = "eiz"; |
| 2381 | static const char *intel_index16[] = { |
| 2382 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" |
| 2383 | }; |
| 2384 | |
| 2385 | static const char *att_names64[] = { |
| 2386 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", |
| 2387 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
| 2388 | }; |
| 2389 | static const char *att_names32[] = { |
| 2390 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", |
| 2391 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
| 2392 | }; |
| 2393 | static const char *att_names16[] = { |
| 2394 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", |
| 2395 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
| 2396 | }; |
| 2397 | static const char *att_names8[] = { |
| 2398 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", |
| 2399 | }; |
| 2400 | static const char *att_names8rex[] = { |
| 2401 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", |
| 2402 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
| 2403 | }; |
| 2404 | static const char *att_names_seg[] = { |
| 2405 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", |
| 2406 | }; |
| 2407 | static const char *att_index64 = "%riz"; |
| 2408 | static const char *att_index32 = "%eiz"; |
| 2409 | static const char *att_index16[] = { |
| 2410 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" |
| 2411 | }; |
| 2412 | |
| 2413 | static const char **names_mm; |
| 2414 | static const char *intel_names_mm[] = { |
| 2415 | "mm0", "mm1", "mm2", "mm3", |
| 2416 | "mm4", "mm5", "mm6", "mm7" |
| 2417 | }; |
| 2418 | static const char *att_names_mm[] = { |
| 2419 | "%mm0", "%mm1", "%mm2", "%mm3", |
| 2420 | "%mm4", "%mm5", "%mm6", "%mm7" |
| 2421 | }; |
| 2422 | |
| 2423 | static const char **names_xmm; |
| 2424 | static const char *intel_names_xmm[] = { |
| 2425 | "xmm0", "xmm1", "xmm2", "xmm3", |
| 2426 | "xmm4", "xmm5", "xmm6", "xmm7", |
| 2427 | "xmm8", "xmm9", "xmm10", "xmm11", |
| 2428 | "xmm12", "xmm13", "xmm14", "xmm15" |
| 2429 | }; |
| 2430 | static const char *att_names_xmm[] = { |
| 2431 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
| 2432 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", |
| 2433 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", |
| 2434 | "%xmm12", "%xmm13", "%xmm14", "%xmm15" |
| 2435 | }; |
| 2436 | |
| 2437 | static const char **names_ymm; |
| 2438 | static const char *intel_names_ymm[] = { |
| 2439 | "ymm0", "ymm1", "ymm2", "ymm3", |
| 2440 | "ymm4", "ymm5", "ymm6", "ymm7", |
| 2441 | "ymm8", "ymm9", "ymm10", "ymm11", |
| 2442 | "ymm12", "ymm13", "ymm14", "ymm15" |
| 2443 | }; |
| 2444 | static const char *att_names_ymm[] = { |
| 2445 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", |
| 2446 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", |
| 2447 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", |
| 2448 | "%ymm12", "%ymm13", "%ymm14", "%ymm15" |
| 2449 | }; |
| 2450 | |
| 2451 | static const struct dis386 reg_table[][8] = { |
| 2452 | /* REG_80 */ |
| 2453 | { |
| 2454 | { "addA", { Ebh1, Ib } }, |
| 2455 | { "orA", { Ebh1, Ib } }, |
| 2456 | { "adcA", { Ebh1, Ib } }, |
| 2457 | { "sbbA", { Ebh1, Ib } }, |
| 2458 | { "andA", { Ebh1, Ib } }, |
| 2459 | { "subA", { Ebh1, Ib } }, |
| 2460 | { "xorA", { Ebh1, Ib } }, |
| 2461 | { "cmpA", { Eb, Ib } }, |
| 2462 | }, |
| 2463 | /* REG_81 */ |
| 2464 | { |
| 2465 | { "addQ", { Evh1, Iv } }, |
| 2466 | { "orQ", { Evh1, Iv } }, |
| 2467 | { "adcQ", { Evh1, Iv } }, |
| 2468 | { "sbbQ", { Evh1, Iv } }, |
| 2469 | { "andQ", { Evh1, Iv } }, |
| 2470 | { "subQ", { Evh1, Iv } }, |
| 2471 | { "xorQ", { Evh1, Iv } }, |
| 2472 | { "cmpQ", { Ev, Iv } }, |
| 2473 | }, |
| 2474 | /* REG_82 */ |
| 2475 | { |
| 2476 | { "addQ", { Evh1, sIb } }, |
| 2477 | { "orQ", { Evh1, sIb } }, |
| 2478 | { "adcQ", { Evh1, sIb } }, |
| 2479 | { "sbbQ", { Evh1, sIb } }, |
| 2480 | { "andQ", { Evh1, sIb } }, |
| 2481 | { "subQ", { Evh1, sIb } }, |
| 2482 | { "xorQ", { Evh1, sIb } }, |
| 2483 | { "cmpQ", { Ev, sIb } }, |
| 2484 | }, |
| 2485 | /* REG_8F */ |
| 2486 | { |
| 2487 | { "popU", { stackEv } }, |
| 2488 | { XOP_8F_TABLE (XOP_09) }, |
| 2489 | { Bad_Opcode }, |
| 2490 | { Bad_Opcode }, |
| 2491 | { Bad_Opcode }, |
| 2492 | { XOP_8F_TABLE (XOP_09) }, |
| 2493 | }, |
| 2494 | /* REG_C0 */ |
| 2495 | { |
| 2496 | { "rolA", { Eb, Ib } }, |
| 2497 | { "rorA", { Eb, Ib } }, |
| 2498 | { "rclA", { Eb, Ib } }, |
| 2499 | { "rcrA", { Eb, Ib } }, |
| 2500 | { "shlA", { Eb, Ib } }, |
| 2501 | { "shrA", { Eb, Ib } }, |
| 2502 | { Bad_Opcode }, |
| 2503 | { "sarA", { Eb, Ib } }, |
| 2504 | }, |
| 2505 | /* REG_C1 */ |
| 2506 | { |
| 2507 | { "rolQ", { Ev, Ib } }, |
| 2508 | { "rorQ", { Ev, Ib } }, |
| 2509 | { "rclQ", { Ev, Ib } }, |
| 2510 | { "rcrQ", { Ev, Ib } }, |
| 2511 | { "shlQ", { Ev, Ib } }, |
| 2512 | { "shrQ", { Ev, Ib } }, |
| 2513 | { Bad_Opcode }, |
| 2514 | { "sarQ", { Ev, Ib } }, |
| 2515 | }, |
| 2516 | /* REG_C6 */ |
| 2517 | { |
| 2518 | { "movA", { Ebh3, Ib } }, |
| 2519 | { Bad_Opcode }, |
| 2520 | { Bad_Opcode }, |
| 2521 | { Bad_Opcode }, |
| 2522 | { Bad_Opcode }, |
| 2523 | { Bad_Opcode }, |
| 2524 | { Bad_Opcode }, |
| 2525 | { MOD_TABLE (MOD_C6_REG_7) }, |
| 2526 | }, |
| 2527 | /* REG_C7 */ |
| 2528 | { |
| 2529 | { "movQ", { Evh3, Iv } }, |
| 2530 | { Bad_Opcode }, |
| 2531 | { Bad_Opcode }, |
| 2532 | { Bad_Opcode }, |
| 2533 | { Bad_Opcode }, |
| 2534 | { Bad_Opcode }, |
| 2535 | { Bad_Opcode }, |
| 2536 | { MOD_TABLE (MOD_C7_REG_7) }, |
| 2537 | }, |
| 2538 | /* REG_D0 */ |
| 2539 | { |
| 2540 | { "rolA", { Eb, I1 } }, |
| 2541 | { "rorA", { Eb, I1 } }, |
| 2542 | { "rclA", { Eb, I1 } }, |
| 2543 | { "rcrA", { Eb, I1 } }, |
| 2544 | { "shlA", { Eb, I1 } }, |
| 2545 | { "shrA", { Eb, I1 } }, |
| 2546 | { Bad_Opcode }, |
| 2547 | { "sarA", { Eb, I1 } }, |
| 2548 | }, |
| 2549 | /* REG_D1 */ |
| 2550 | { |
| 2551 | { "rolQ", { Ev, I1 } }, |
| 2552 | { "rorQ", { Ev, I1 } }, |
| 2553 | { "rclQ", { Ev, I1 } }, |
| 2554 | { "rcrQ", { Ev, I1 } }, |
| 2555 | { "shlQ", { Ev, I1 } }, |
| 2556 | { "shrQ", { Ev, I1 } }, |
| 2557 | { Bad_Opcode }, |
| 2558 | { "sarQ", { Ev, I1 } }, |
| 2559 | }, |
| 2560 | /* REG_D2 */ |
| 2561 | { |
| 2562 | { "rolA", { Eb, CL } }, |
| 2563 | { "rorA", { Eb, CL } }, |
| 2564 | { "rclA", { Eb, CL } }, |
| 2565 | { "rcrA", { Eb, CL } }, |
| 2566 | { "shlA", { Eb, CL } }, |
| 2567 | { "shrA", { Eb, CL } }, |
| 2568 | { Bad_Opcode }, |
| 2569 | { "sarA", { Eb, CL } }, |
| 2570 | }, |
| 2571 | /* REG_D3 */ |
| 2572 | { |
| 2573 | { "rolQ", { Ev, CL } }, |
| 2574 | { "rorQ", { Ev, CL } }, |
| 2575 | { "rclQ", { Ev, CL } }, |
| 2576 | { "rcrQ", { Ev, CL } }, |
| 2577 | { "shlQ", { Ev, CL } }, |
| 2578 | { "shrQ", { Ev, CL } }, |
| 2579 | { Bad_Opcode }, |
| 2580 | { "sarQ", { Ev, CL } }, |
| 2581 | }, |
| 2582 | /* REG_F6 */ |
| 2583 | { |
| 2584 | { "testA", { Eb, Ib } }, |
| 2585 | { Bad_Opcode }, |
| 2586 | { "notA", { Ebh1 } }, |
| 2587 | { "negA", { Ebh1 } }, |
| 2588 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
| 2589 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ |
| 2590 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ |
| 2591 | { "idivA", { Eb } }, /* and idiv for consistency. */ |
| 2592 | }, |
| 2593 | /* REG_F7 */ |
| 2594 | { |
| 2595 | { "testQ", { Ev, Iv } }, |
| 2596 | { Bad_Opcode }, |
| 2597 | { "notQ", { Evh1 } }, |
| 2598 | { "negQ", { Evh1 } }, |
| 2599 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
| 2600 | { "imulQ", { Ev } }, |
| 2601 | { "divQ", { Ev } }, |
| 2602 | { "idivQ", { Ev } }, |
| 2603 | }, |
| 2604 | /* REG_FE */ |
| 2605 | { |
| 2606 | { "incA", { Ebh1 } }, |
| 2607 | { "decA", { Ebh1 } }, |
| 2608 | }, |
| 2609 | /* REG_FF */ |
| 2610 | { |
| 2611 | { "incQ", { Evh1 } }, |
| 2612 | { "decQ", { Evh1 } }, |
| 2613 | { "call{T|}", { indirEv } }, |
| 2614 | { "Jcall{T|}", { indirEp } }, |
| 2615 | { "jmp{T|}", { indirEv } }, |
| 2616 | { "Jjmp{T|}", { indirEp } }, |
| 2617 | { "pushU", { stackEv } }, |
| 2618 | { Bad_Opcode }, |
| 2619 | }, |
| 2620 | /* REG_0F00 */ |
| 2621 | { |
| 2622 | { "sldtD", { Sv } }, |
| 2623 | { "strD", { Sv } }, |
| 2624 | { "lldt", { Ew } }, |
| 2625 | { "ltr", { Ew } }, |
| 2626 | { "verr", { Ew } }, |
| 2627 | { "verw", { Ew } }, |
| 2628 | { Bad_Opcode }, |
| 2629 | { Bad_Opcode }, |
| 2630 | }, |
| 2631 | /* REG_0F01 */ |
| 2632 | { |
| 2633 | { MOD_TABLE (MOD_0F01_REG_0) }, |
| 2634 | { MOD_TABLE (MOD_0F01_REG_1) }, |
| 2635 | { MOD_TABLE (MOD_0F01_REG_2) }, |
| 2636 | { MOD_TABLE (MOD_0F01_REG_3) }, |
| 2637 | { "smswD", { Sv } }, |
| 2638 | { Bad_Opcode }, |
| 2639 | { "lmsw", { Ew } }, |
| 2640 | { MOD_TABLE (MOD_0F01_REG_7) }, |
| 2641 | }, |
| 2642 | /* REG_0F0D */ |
| 2643 | { |
| 2644 | { "prefetch", { Mb } }, |
| 2645 | { "prefetchw", { Mb } }, |
| 2646 | }, |
| 2647 | /* REG_0F18 */ |
| 2648 | { |
| 2649 | { MOD_TABLE (MOD_0F18_REG_0) }, |
| 2650 | { MOD_TABLE (MOD_0F18_REG_1) }, |
| 2651 | { MOD_TABLE (MOD_0F18_REG_2) }, |
| 2652 | { MOD_TABLE (MOD_0F18_REG_3) }, |
| 2653 | }, |
| 2654 | /* REG_0F71 */ |
| 2655 | { |
| 2656 | { Bad_Opcode }, |
| 2657 | { Bad_Opcode }, |
| 2658 | { MOD_TABLE (MOD_0F71_REG_2) }, |
| 2659 | { Bad_Opcode }, |
| 2660 | { MOD_TABLE (MOD_0F71_REG_4) }, |
| 2661 | { Bad_Opcode }, |
| 2662 | { MOD_TABLE (MOD_0F71_REG_6) }, |
| 2663 | }, |
| 2664 | /* REG_0F72 */ |
| 2665 | { |
| 2666 | { Bad_Opcode }, |
| 2667 | { Bad_Opcode }, |
| 2668 | { MOD_TABLE (MOD_0F72_REG_2) }, |
| 2669 | { Bad_Opcode }, |
| 2670 | { MOD_TABLE (MOD_0F72_REG_4) }, |
| 2671 | { Bad_Opcode }, |
| 2672 | { MOD_TABLE (MOD_0F72_REG_6) }, |
| 2673 | }, |
| 2674 | /* REG_0F73 */ |
| 2675 | { |
| 2676 | { Bad_Opcode }, |
| 2677 | { Bad_Opcode }, |
| 2678 | { MOD_TABLE (MOD_0F73_REG_2) }, |
| 2679 | { MOD_TABLE (MOD_0F73_REG_3) }, |
| 2680 | { Bad_Opcode }, |
| 2681 | { Bad_Opcode }, |
| 2682 | { MOD_TABLE (MOD_0F73_REG_6) }, |
| 2683 | { MOD_TABLE (MOD_0F73_REG_7) }, |
| 2684 | }, |
| 2685 | /* REG_0FA6 */ |
| 2686 | { |
| 2687 | { "montmul", { { OP_0f07, 0 } } }, |
| 2688 | { "xsha1", { { OP_0f07, 0 } } }, |
| 2689 | { "xsha256", { { OP_0f07, 0 } } }, |
| 2690 | }, |
| 2691 | /* REG_0FA7 */ |
| 2692 | { |
| 2693 | { "xstore-rng", { { OP_0f07, 0 } } }, |
| 2694 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, |
| 2695 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, |
| 2696 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, |
| 2697 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, |
| 2698 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, |
| 2699 | }, |
| 2700 | /* REG_0FAE */ |
| 2701 | { |
| 2702 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
| 2703 | { MOD_TABLE (MOD_0FAE_REG_1) }, |
| 2704 | { MOD_TABLE (MOD_0FAE_REG_2) }, |
| 2705 | { MOD_TABLE (MOD_0FAE_REG_3) }, |
| 2706 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
| 2707 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
| 2708 | { MOD_TABLE (MOD_0FAE_REG_6) }, |
| 2709 | { MOD_TABLE (MOD_0FAE_REG_7) }, |
| 2710 | }, |
| 2711 | /* REG_0FBA */ |
| 2712 | { |
| 2713 | { Bad_Opcode }, |
| 2714 | { Bad_Opcode }, |
| 2715 | { Bad_Opcode }, |
| 2716 | { Bad_Opcode }, |
| 2717 | { "btQ", { Ev, Ib } }, |
| 2718 | { "btsQ", { Evh1, Ib } }, |
| 2719 | { "btrQ", { Evh1, Ib } }, |
| 2720 | { "btcQ", { Evh1, Ib } }, |
| 2721 | }, |
| 2722 | /* REG_0FC7 */ |
| 2723 | { |
| 2724 | { Bad_Opcode }, |
| 2725 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
| 2726 | { Bad_Opcode }, |
| 2727 | { Bad_Opcode }, |
| 2728 | { Bad_Opcode }, |
| 2729 | { Bad_Opcode }, |
| 2730 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
| 2731 | { MOD_TABLE (MOD_0FC7_REG_7) }, |
| 2732 | }, |
| 2733 | /* REG_VEX_0F71 */ |
| 2734 | { |
| 2735 | { Bad_Opcode }, |
| 2736 | { Bad_Opcode }, |
| 2737 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
| 2738 | { Bad_Opcode }, |
| 2739 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
| 2740 | { Bad_Opcode }, |
| 2741 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
| 2742 | }, |
| 2743 | /* REG_VEX_0F72 */ |
| 2744 | { |
| 2745 | { Bad_Opcode }, |
| 2746 | { Bad_Opcode }, |
| 2747 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
| 2748 | { Bad_Opcode }, |
| 2749 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
| 2750 | { Bad_Opcode }, |
| 2751 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
| 2752 | }, |
| 2753 | /* REG_VEX_0F73 */ |
| 2754 | { |
| 2755 | { Bad_Opcode }, |
| 2756 | { Bad_Opcode }, |
| 2757 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
| 2758 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, |
| 2759 | { Bad_Opcode }, |
| 2760 | { Bad_Opcode }, |
| 2761 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
| 2762 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, |
| 2763 | }, |
| 2764 | /* REG_VEX_0FAE */ |
| 2765 | { |
| 2766 | { Bad_Opcode }, |
| 2767 | { Bad_Opcode }, |
| 2768 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
| 2769 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, |
| 2770 | }, |
| 2771 | /* REG_VEX_0F38F3 */ |
| 2772 | { |
| 2773 | { Bad_Opcode }, |
| 2774 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, |
| 2775 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, |
| 2776 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, |
| 2777 | }, |
| 2778 | /* REG_XOP_LWPCB */ |
| 2779 | { |
| 2780 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, |
| 2781 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, |
| 2782 | }, |
| 2783 | /* REG_XOP_LWP */ |
| 2784 | { |
| 2785 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
| 2786 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, |
| 2787 | }, |
| 2788 | /* REG_XOP_TBM_01 */ |
| 2789 | { |
| 2790 | { Bad_Opcode }, |
| 2791 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, |
| 2792 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, |
| 2793 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, |
| 2794 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, |
| 2795 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, |
| 2796 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, |
| 2797 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, |
| 2798 | }, |
| 2799 | /* REG_XOP_TBM_02 */ |
| 2800 | { |
| 2801 | { Bad_Opcode }, |
| 2802 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, |
| 2803 | { Bad_Opcode }, |
| 2804 | { Bad_Opcode }, |
| 2805 | { Bad_Opcode }, |
| 2806 | { Bad_Opcode }, |
| 2807 | { "blci", { { OP_LWP_E, 0 }, Ev } }, |
| 2808 | }, |
| 2809 | }; |
| 2810 | |
| 2811 | static const struct dis386 prefix_table[][4] = { |
| 2812 | /* PREFIX_90 */ |
| 2813 | { |
| 2814 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
| 2815 | { "pause", { XX } }, |
| 2816 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
| 2817 | }, |
| 2818 | |
| 2819 | /* PREFIX_0F10 */ |
| 2820 | { |
| 2821 | { "movups", { XM, EXx } }, |
| 2822 | { "movss", { XM, EXd } }, |
| 2823 | { "movupd", { XM, EXx } }, |
| 2824 | { "movsd", { XM, EXq } }, |
| 2825 | }, |
| 2826 | |
| 2827 | /* PREFIX_0F11 */ |
| 2828 | { |
| 2829 | { "movups", { EXxS, XM } }, |
| 2830 | { "movss", { EXdS, XM } }, |
| 2831 | { "movupd", { EXxS, XM } }, |
| 2832 | { "movsd", { EXqS, XM } }, |
| 2833 | }, |
| 2834 | |
| 2835 | /* PREFIX_0F12 */ |
| 2836 | { |
| 2837 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
| 2838 | { "movsldup", { XM, EXx } }, |
| 2839 | { "movlpd", { XM, EXq } }, |
| 2840 | { "movddup", { XM, EXq } }, |
| 2841 | }, |
| 2842 | |
| 2843 | /* PREFIX_0F16 */ |
| 2844 | { |
| 2845 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
| 2846 | { "movshdup", { XM, EXx } }, |
| 2847 | { "movhpd", { XM, EXq } }, |
| 2848 | }, |
| 2849 | |
| 2850 | /* PREFIX_0F2A */ |
| 2851 | { |
| 2852 | { "cvtpi2ps", { XM, EMCq } }, |
| 2853 | { "cvtsi2ss%LQ", { XM, Ev } }, |
| 2854 | { "cvtpi2pd", { XM, EMCq } }, |
| 2855 | { "cvtsi2sd%LQ", { XM, Ev } }, |
| 2856 | }, |
| 2857 | |
| 2858 | /* PREFIX_0F2B */ |
| 2859 | { |
| 2860 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
| 2861 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, |
| 2862 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, |
| 2863 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, |
| 2864 | }, |
| 2865 | |
| 2866 | /* PREFIX_0F2C */ |
| 2867 | { |
| 2868 | { "cvttps2pi", { MXC, EXq } }, |
| 2869 | { "cvttss2siY", { Gv, EXd } }, |
| 2870 | { "cvttpd2pi", { MXC, EXx } }, |
| 2871 | { "cvttsd2siY", { Gv, EXq } }, |
| 2872 | }, |
| 2873 | |
| 2874 | /* PREFIX_0F2D */ |
| 2875 | { |
| 2876 | { "cvtps2pi", { MXC, EXq } }, |
| 2877 | { "cvtss2siY", { Gv, EXd } }, |
| 2878 | { "cvtpd2pi", { MXC, EXx } }, |
| 2879 | { "cvtsd2siY", { Gv, EXq } }, |
| 2880 | }, |
| 2881 | |
| 2882 | /* PREFIX_0F2E */ |
| 2883 | { |
| 2884 | { "ucomiss",{ XM, EXd } }, |
| 2885 | { Bad_Opcode }, |
| 2886 | { "ucomisd",{ XM, EXq } }, |
| 2887 | }, |
| 2888 | |
| 2889 | /* PREFIX_0F2F */ |
| 2890 | { |
| 2891 | { "comiss", { XM, EXd } }, |
| 2892 | { Bad_Opcode }, |
| 2893 | { "comisd", { XM, EXq } }, |
| 2894 | }, |
| 2895 | |
| 2896 | /* PREFIX_0F51 */ |
| 2897 | { |
| 2898 | { "sqrtps", { XM, EXx } }, |
| 2899 | { "sqrtss", { XM, EXd } }, |
| 2900 | { "sqrtpd", { XM, EXx } }, |
| 2901 | { "sqrtsd", { XM, EXq } }, |
| 2902 | }, |
| 2903 | |
| 2904 | /* PREFIX_0F52 */ |
| 2905 | { |
| 2906 | { "rsqrtps",{ XM, EXx } }, |
| 2907 | { "rsqrtss",{ XM, EXd } }, |
| 2908 | }, |
| 2909 | |
| 2910 | /* PREFIX_0F53 */ |
| 2911 | { |
| 2912 | { "rcpps", { XM, EXx } }, |
| 2913 | { "rcpss", { XM, EXd } }, |
| 2914 | }, |
| 2915 | |
| 2916 | /* PREFIX_0F58 */ |
| 2917 | { |
| 2918 | { "addps", { XM, EXx } }, |
| 2919 | { "addss", { XM, EXd } }, |
| 2920 | { "addpd", { XM, EXx } }, |
| 2921 | { "addsd", { XM, EXq } }, |
| 2922 | }, |
| 2923 | |
| 2924 | /* PREFIX_0F59 */ |
| 2925 | { |
| 2926 | { "mulps", { XM, EXx } }, |
| 2927 | { "mulss", { XM, EXd } }, |
| 2928 | { "mulpd", { XM, EXx } }, |
| 2929 | { "mulsd", { XM, EXq } }, |
| 2930 | }, |
| 2931 | |
| 2932 | /* PREFIX_0F5A */ |
| 2933 | { |
| 2934 | { "cvtps2pd", { XM, EXq } }, |
| 2935 | { "cvtss2sd", { XM, EXd } }, |
| 2936 | { "cvtpd2ps", { XM, EXx } }, |
| 2937 | { "cvtsd2ss", { XM, EXq } }, |
| 2938 | }, |
| 2939 | |
| 2940 | /* PREFIX_0F5B */ |
| 2941 | { |
| 2942 | { "cvtdq2ps", { XM, EXx } }, |
| 2943 | { "cvttps2dq", { XM, EXx } }, |
| 2944 | { "cvtps2dq", { XM, EXx } }, |
| 2945 | }, |
| 2946 | |
| 2947 | /* PREFIX_0F5C */ |
| 2948 | { |
| 2949 | { "subps", { XM, EXx } }, |
| 2950 | { "subss", { XM, EXd } }, |
| 2951 | { "subpd", { XM, EXx } }, |
| 2952 | { "subsd", { XM, EXq } }, |
| 2953 | }, |
| 2954 | |
| 2955 | /* PREFIX_0F5D */ |
| 2956 | { |
| 2957 | { "minps", { XM, EXx } }, |
| 2958 | { "minss", { XM, EXd } }, |
| 2959 | { "minpd", { XM, EXx } }, |
| 2960 | { "minsd", { XM, EXq } }, |
| 2961 | }, |
| 2962 | |
| 2963 | /* PREFIX_0F5E */ |
| 2964 | { |
| 2965 | { "divps", { XM, EXx } }, |
| 2966 | { "divss", { XM, EXd } }, |
| 2967 | { "divpd", { XM, EXx } }, |
| 2968 | { "divsd", { XM, EXq } }, |
| 2969 | }, |
| 2970 | |
| 2971 | /* PREFIX_0F5F */ |
| 2972 | { |
| 2973 | { "maxps", { XM, EXx } }, |
| 2974 | { "maxss", { XM, EXd } }, |
| 2975 | { "maxpd", { XM, EXx } }, |
| 2976 | { "maxsd", { XM, EXq } }, |
| 2977 | }, |
| 2978 | |
| 2979 | /* PREFIX_0F60 */ |
| 2980 | { |
| 2981 | { "punpcklbw",{ MX, EMd } }, |
| 2982 | { Bad_Opcode }, |
| 2983 | { "punpcklbw",{ MX, EMx } }, |
| 2984 | }, |
| 2985 | |
| 2986 | /* PREFIX_0F61 */ |
| 2987 | { |
| 2988 | { "punpcklwd",{ MX, EMd } }, |
| 2989 | { Bad_Opcode }, |
| 2990 | { "punpcklwd",{ MX, EMx } }, |
| 2991 | }, |
| 2992 | |
| 2993 | /* PREFIX_0F62 */ |
| 2994 | { |
| 2995 | { "punpckldq",{ MX, EMd } }, |
| 2996 | { Bad_Opcode }, |
| 2997 | { "punpckldq",{ MX, EMx } }, |
| 2998 | }, |
| 2999 | |
| 3000 | /* PREFIX_0F6C */ |
| 3001 | { |
| 3002 | { Bad_Opcode }, |
| 3003 | { Bad_Opcode }, |
| 3004 | { "punpcklqdq", { XM, EXx } }, |
| 3005 | }, |
| 3006 | |
| 3007 | /* PREFIX_0F6D */ |
| 3008 | { |
| 3009 | { Bad_Opcode }, |
| 3010 | { Bad_Opcode }, |
| 3011 | { "punpckhqdq", { XM, EXx } }, |
| 3012 | }, |
| 3013 | |
| 3014 | /* PREFIX_0F6F */ |
| 3015 | { |
| 3016 | { "movq", { MX, EM } }, |
| 3017 | { "movdqu", { XM, EXx } }, |
| 3018 | { "movdqa", { XM, EXx } }, |
| 3019 | }, |
| 3020 | |
| 3021 | /* PREFIX_0F70 */ |
| 3022 | { |
| 3023 | { "pshufw", { MX, EM, Ib } }, |
| 3024 | { "pshufhw",{ XM, EXx, Ib } }, |
| 3025 | { "pshufd", { XM, EXx, Ib } }, |
| 3026 | { "pshuflw",{ XM, EXx, Ib } }, |
| 3027 | }, |
| 3028 | |
| 3029 | /* PREFIX_0F73_REG_3 */ |
| 3030 | { |
| 3031 | { Bad_Opcode }, |
| 3032 | { Bad_Opcode }, |
| 3033 | { "psrldq", { XS, Ib } }, |
| 3034 | }, |
| 3035 | |
| 3036 | /* PREFIX_0F73_REG_7 */ |
| 3037 | { |
| 3038 | { Bad_Opcode }, |
| 3039 | { Bad_Opcode }, |
| 3040 | { "pslldq", { XS, Ib } }, |
| 3041 | }, |
| 3042 | |
| 3043 | /* PREFIX_0F78 */ |
| 3044 | { |
| 3045 | {"vmread", { Em, Gm } }, |
| 3046 | { Bad_Opcode }, |
| 3047 | {"extrq", { XS, Ib, Ib } }, |
| 3048 | {"insertq", { XM, XS, Ib, Ib } }, |
| 3049 | }, |
| 3050 | |
| 3051 | /* PREFIX_0F79 */ |
| 3052 | { |
| 3053 | {"vmwrite", { Gm, Em } }, |
| 3054 | { Bad_Opcode }, |
| 3055 | {"extrq", { XM, XS } }, |
| 3056 | {"insertq", { XM, XS } }, |
| 3057 | }, |
| 3058 | |
| 3059 | /* PREFIX_0F7C */ |
| 3060 | { |
| 3061 | { Bad_Opcode }, |
| 3062 | { Bad_Opcode }, |
| 3063 | { "haddpd", { XM, EXx } }, |
| 3064 | { "haddps", { XM, EXx } }, |
| 3065 | }, |
| 3066 | |
| 3067 | /* PREFIX_0F7D */ |
| 3068 | { |
| 3069 | { Bad_Opcode }, |
| 3070 | { Bad_Opcode }, |
| 3071 | { "hsubpd", { XM, EXx } }, |
| 3072 | { "hsubps", { XM, EXx } }, |
| 3073 | }, |
| 3074 | |
| 3075 | /* PREFIX_0F7E */ |
| 3076 | { |
| 3077 | { "movK", { Edq, MX } }, |
| 3078 | { "movq", { XM, EXq } }, |
| 3079 | { "movK", { Edq, XM } }, |
| 3080 | }, |
| 3081 | |
| 3082 | /* PREFIX_0F7F */ |
| 3083 | { |
| 3084 | { "movq", { EMS, MX } }, |
| 3085 | { "movdqu", { EXxS, XM } }, |
| 3086 | { "movdqa", { EXxS, XM } }, |
| 3087 | }, |
| 3088 | |
| 3089 | /* PREFIX_0FAE_REG_0 */ |
| 3090 | { |
| 3091 | { Bad_Opcode }, |
| 3092 | { "rdfsbase", { Ev } }, |
| 3093 | }, |
| 3094 | |
| 3095 | /* PREFIX_0FAE_REG_1 */ |
| 3096 | { |
| 3097 | { Bad_Opcode }, |
| 3098 | { "rdgsbase", { Ev } }, |
| 3099 | }, |
| 3100 | |
| 3101 | /* PREFIX_0FAE_REG_2 */ |
| 3102 | { |
| 3103 | { Bad_Opcode }, |
| 3104 | { "wrfsbase", { Ev } }, |
| 3105 | }, |
| 3106 | |
| 3107 | /* PREFIX_0FAE_REG_3 */ |
| 3108 | { |
| 3109 | { Bad_Opcode }, |
| 3110 | { "wrgsbase", { Ev } }, |
| 3111 | }, |
| 3112 | |
| 3113 | /* PREFIX_0FB8 */ |
| 3114 | { |
| 3115 | { Bad_Opcode }, |
| 3116 | { "popcntS", { Gv, Ev } }, |
| 3117 | }, |
| 3118 | |
| 3119 | /* PREFIX_0FBC */ |
| 3120 | { |
| 3121 | { "bsfS", { Gv, Ev } }, |
| 3122 | { "tzcntS", { Gv, Ev } }, |
| 3123 | { "bsfS", { Gv, Ev } }, |
| 3124 | }, |
| 3125 | |
| 3126 | /* PREFIX_0FBD */ |
| 3127 | { |
| 3128 | { "bsrS", { Gv, Ev } }, |
| 3129 | { "lzcntS", { Gv, Ev } }, |
| 3130 | { "bsrS", { Gv, Ev } }, |
| 3131 | }, |
| 3132 | |
| 3133 | /* PREFIX_0FC2 */ |
| 3134 | { |
| 3135 | { "cmpps", { XM, EXx, CMP } }, |
| 3136 | { "cmpss", { XM, EXd, CMP } }, |
| 3137 | { "cmppd", { XM, EXx, CMP } }, |
| 3138 | { "cmpsd", { XM, EXq, CMP } }, |
| 3139 | }, |
| 3140 | |
| 3141 | /* PREFIX_0FC3 */ |
| 3142 | { |
| 3143 | { "movntiS", { Ma, Gv } }, |
| 3144 | }, |
| 3145 | |
| 3146 | /* PREFIX_0FC7_REG_6 */ |
| 3147 | { |
| 3148 | { "vmptrld",{ Mq } }, |
| 3149 | { "vmxon", { Mq } }, |
| 3150 | { "vmclear",{ Mq } }, |
| 3151 | }, |
| 3152 | |
| 3153 | /* PREFIX_0FD0 */ |
| 3154 | { |
| 3155 | { Bad_Opcode }, |
| 3156 | { Bad_Opcode }, |
| 3157 | { "addsubpd", { XM, EXx } }, |
| 3158 | { "addsubps", { XM, EXx } }, |
| 3159 | }, |
| 3160 | |
| 3161 | /* PREFIX_0FD6 */ |
| 3162 | { |
| 3163 | { Bad_Opcode }, |
| 3164 | { "movq2dq",{ XM, MS } }, |
| 3165 | { "movq", { EXqS, XM } }, |
| 3166 | { "movdq2q",{ MX, XS } }, |
| 3167 | }, |
| 3168 | |
| 3169 | /* PREFIX_0FE6 */ |
| 3170 | { |
| 3171 | { Bad_Opcode }, |
| 3172 | { "cvtdq2pd", { XM, EXq } }, |
| 3173 | { "cvttpd2dq", { XM, EXx } }, |
| 3174 | { "cvtpd2dq", { XM, EXx } }, |
| 3175 | }, |
| 3176 | |
| 3177 | /* PREFIX_0FE7 */ |
| 3178 | { |
| 3179 | { "movntq", { Mq, MX } }, |
| 3180 | { Bad_Opcode }, |
| 3181 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
| 3182 | }, |
| 3183 | |
| 3184 | /* PREFIX_0FF0 */ |
| 3185 | { |
| 3186 | { Bad_Opcode }, |
| 3187 | { Bad_Opcode }, |
| 3188 | { Bad_Opcode }, |
| 3189 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
| 3190 | }, |
| 3191 | |
| 3192 | /* PREFIX_0FF7 */ |
| 3193 | { |
| 3194 | { "maskmovq", { MX, MS } }, |
| 3195 | { Bad_Opcode }, |
| 3196 | { "maskmovdqu", { XM, XS } }, |
| 3197 | }, |
| 3198 | |
| 3199 | /* PREFIX_0F3810 */ |
| 3200 | { |
| 3201 | { Bad_Opcode }, |
| 3202 | { Bad_Opcode }, |
| 3203 | { "pblendvb", { XM, EXx, XMM0 } }, |
| 3204 | }, |
| 3205 | |
| 3206 | /* PREFIX_0F3814 */ |
| 3207 | { |
| 3208 | { Bad_Opcode }, |
| 3209 | { Bad_Opcode }, |
| 3210 | { "blendvps", { XM, EXx, XMM0 } }, |
| 3211 | }, |
| 3212 | |
| 3213 | /* PREFIX_0F3815 */ |
| 3214 | { |
| 3215 | { Bad_Opcode }, |
| 3216 | { Bad_Opcode }, |
| 3217 | { "blendvpd", { XM, EXx, XMM0 } }, |
| 3218 | }, |
| 3219 | |
| 3220 | /* PREFIX_0F3817 */ |
| 3221 | { |
| 3222 | { Bad_Opcode }, |
| 3223 | { Bad_Opcode }, |
| 3224 | { "ptest", { XM, EXx } }, |
| 3225 | }, |
| 3226 | |
| 3227 | /* PREFIX_0F3820 */ |
| 3228 | { |
| 3229 | { Bad_Opcode }, |
| 3230 | { Bad_Opcode }, |
| 3231 | { "pmovsxbw", { XM, EXq } }, |
| 3232 | }, |
| 3233 | |
| 3234 | /* PREFIX_0F3821 */ |
| 3235 | { |
| 3236 | { Bad_Opcode }, |
| 3237 | { Bad_Opcode }, |
| 3238 | { "pmovsxbd", { XM, EXd } }, |
| 3239 | }, |
| 3240 | |
| 3241 | /* PREFIX_0F3822 */ |
| 3242 | { |
| 3243 | { Bad_Opcode }, |
| 3244 | { Bad_Opcode }, |
| 3245 | { "pmovsxbq", { XM, EXw } }, |
| 3246 | }, |
| 3247 | |
| 3248 | /* PREFIX_0F3823 */ |
| 3249 | { |
| 3250 | { Bad_Opcode }, |
| 3251 | { Bad_Opcode }, |
| 3252 | { "pmovsxwd", { XM, EXq } }, |
| 3253 | }, |
| 3254 | |
| 3255 | /* PREFIX_0F3824 */ |
| 3256 | { |
| 3257 | { Bad_Opcode }, |
| 3258 | { Bad_Opcode }, |
| 3259 | { "pmovsxwq", { XM, EXd } }, |
| 3260 | }, |
| 3261 | |
| 3262 | /* PREFIX_0F3825 */ |
| 3263 | { |
| 3264 | { Bad_Opcode }, |
| 3265 | { Bad_Opcode }, |
| 3266 | { "pmovsxdq", { XM, EXq } }, |
| 3267 | }, |
| 3268 | |
| 3269 | /* PREFIX_0F3828 */ |
| 3270 | { |
| 3271 | { Bad_Opcode }, |
| 3272 | { Bad_Opcode }, |
| 3273 | { "pmuldq", { XM, EXx } }, |
| 3274 | }, |
| 3275 | |
| 3276 | /* PREFIX_0F3829 */ |
| 3277 | { |
| 3278 | { Bad_Opcode }, |
| 3279 | { Bad_Opcode }, |
| 3280 | { "pcmpeqq", { XM, EXx } }, |
| 3281 | }, |
| 3282 | |
| 3283 | /* PREFIX_0F382A */ |
| 3284 | { |
| 3285 | { Bad_Opcode }, |
| 3286 | { Bad_Opcode }, |
| 3287 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
| 3288 | }, |
| 3289 | |
| 3290 | /* PREFIX_0F382B */ |
| 3291 | { |
| 3292 | { Bad_Opcode }, |
| 3293 | { Bad_Opcode }, |
| 3294 | { "packusdw", { XM, EXx } }, |
| 3295 | }, |
| 3296 | |
| 3297 | /* PREFIX_0F3830 */ |
| 3298 | { |
| 3299 | { Bad_Opcode }, |
| 3300 | { Bad_Opcode }, |
| 3301 | { "pmovzxbw", { XM, EXq } }, |
| 3302 | }, |
| 3303 | |
| 3304 | /* PREFIX_0F3831 */ |
| 3305 | { |
| 3306 | { Bad_Opcode }, |
| 3307 | { Bad_Opcode }, |
| 3308 | { "pmovzxbd", { XM, EXd } }, |
| 3309 | }, |
| 3310 | |
| 3311 | /* PREFIX_0F3832 */ |
| 3312 | { |
| 3313 | { Bad_Opcode }, |
| 3314 | { Bad_Opcode }, |
| 3315 | { "pmovzxbq", { XM, EXw } }, |
| 3316 | }, |
| 3317 | |
| 3318 | /* PREFIX_0F3833 */ |
| 3319 | { |
| 3320 | { Bad_Opcode }, |
| 3321 | { Bad_Opcode }, |
| 3322 | { "pmovzxwd", { XM, EXq } }, |
| 3323 | }, |
| 3324 | |
| 3325 | /* PREFIX_0F3834 */ |
| 3326 | { |
| 3327 | { Bad_Opcode }, |
| 3328 | { Bad_Opcode }, |
| 3329 | { "pmovzxwq", { XM, EXd } }, |
| 3330 | }, |
| 3331 | |
| 3332 | /* PREFIX_0F3835 */ |
| 3333 | { |
| 3334 | { Bad_Opcode }, |
| 3335 | { Bad_Opcode }, |
| 3336 | { "pmovzxdq", { XM, EXq } }, |
| 3337 | }, |
| 3338 | |
| 3339 | /* PREFIX_0F3837 */ |
| 3340 | { |
| 3341 | { Bad_Opcode }, |
| 3342 | { Bad_Opcode }, |
| 3343 | { "pcmpgtq", { XM, EXx } }, |
| 3344 | }, |
| 3345 | |
| 3346 | /* PREFIX_0F3838 */ |
| 3347 | { |
| 3348 | { Bad_Opcode }, |
| 3349 | { Bad_Opcode }, |
| 3350 | { "pminsb", { XM, EXx } }, |
| 3351 | }, |
| 3352 | |
| 3353 | /* PREFIX_0F3839 */ |
| 3354 | { |
| 3355 | { Bad_Opcode }, |
| 3356 | { Bad_Opcode }, |
| 3357 | { "pminsd", { XM, EXx } }, |
| 3358 | }, |
| 3359 | |
| 3360 | /* PREFIX_0F383A */ |
| 3361 | { |
| 3362 | { Bad_Opcode }, |
| 3363 | { Bad_Opcode }, |
| 3364 | { "pminuw", { XM, EXx } }, |
| 3365 | }, |
| 3366 | |
| 3367 | /* PREFIX_0F383B */ |
| 3368 | { |
| 3369 | { Bad_Opcode }, |
| 3370 | { Bad_Opcode }, |
| 3371 | { "pminud", { XM, EXx } }, |
| 3372 | }, |
| 3373 | |
| 3374 | /* PREFIX_0F383C */ |
| 3375 | { |
| 3376 | { Bad_Opcode }, |
| 3377 | { Bad_Opcode }, |
| 3378 | { "pmaxsb", { XM, EXx } }, |
| 3379 | }, |
| 3380 | |
| 3381 | /* PREFIX_0F383D */ |
| 3382 | { |
| 3383 | { Bad_Opcode }, |
| 3384 | { Bad_Opcode }, |
| 3385 | { "pmaxsd", { XM, EXx } }, |
| 3386 | }, |
| 3387 | |
| 3388 | /* PREFIX_0F383E */ |
| 3389 | { |
| 3390 | { Bad_Opcode }, |
| 3391 | { Bad_Opcode }, |
| 3392 | { "pmaxuw", { XM, EXx } }, |
| 3393 | }, |
| 3394 | |
| 3395 | /* PREFIX_0F383F */ |
| 3396 | { |
| 3397 | { Bad_Opcode }, |
| 3398 | { Bad_Opcode }, |
| 3399 | { "pmaxud", { XM, EXx } }, |
| 3400 | }, |
| 3401 | |
| 3402 | /* PREFIX_0F3840 */ |
| 3403 | { |
| 3404 | { Bad_Opcode }, |
| 3405 | { Bad_Opcode }, |
| 3406 | { "pmulld", { XM, EXx } }, |
| 3407 | }, |
| 3408 | |
| 3409 | /* PREFIX_0F3841 */ |
| 3410 | { |
| 3411 | { Bad_Opcode }, |
| 3412 | { Bad_Opcode }, |
| 3413 | { "phminposuw", { XM, EXx } }, |
| 3414 | }, |
| 3415 | |
| 3416 | /* PREFIX_0F3880 */ |
| 3417 | { |
| 3418 | { Bad_Opcode }, |
| 3419 | { Bad_Opcode }, |
| 3420 | { "invept", { Gm, Mo } }, |
| 3421 | }, |
| 3422 | |
| 3423 | /* PREFIX_0F3881 */ |
| 3424 | { |
| 3425 | { Bad_Opcode }, |
| 3426 | { Bad_Opcode }, |
| 3427 | { "invvpid", { Gm, Mo } }, |
| 3428 | }, |
| 3429 | |
| 3430 | /* PREFIX_0F3882 */ |
| 3431 | { |
| 3432 | { Bad_Opcode }, |
| 3433 | { Bad_Opcode }, |
| 3434 | { "invpcid", { Gm, M } }, |
| 3435 | }, |
| 3436 | |
| 3437 | /* PREFIX_0F38DB */ |
| 3438 | { |
| 3439 | { Bad_Opcode }, |
| 3440 | { Bad_Opcode }, |
| 3441 | { "aesimc", { XM, EXx } }, |
| 3442 | }, |
| 3443 | |
| 3444 | /* PREFIX_0F38DC */ |
| 3445 | { |
| 3446 | { Bad_Opcode }, |
| 3447 | { Bad_Opcode }, |
| 3448 | { "aesenc", { XM, EXx } }, |
| 3449 | }, |
| 3450 | |
| 3451 | /* PREFIX_0F38DD */ |
| 3452 | { |
| 3453 | { Bad_Opcode }, |
| 3454 | { Bad_Opcode }, |
| 3455 | { "aesenclast", { XM, EXx } }, |
| 3456 | }, |
| 3457 | |
| 3458 | /* PREFIX_0F38DE */ |
| 3459 | { |
| 3460 | { Bad_Opcode }, |
| 3461 | { Bad_Opcode }, |
| 3462 | { "aesdec", { XM, EXx } }, |
| 3463 | }, |
| 3464 | |
| 3465 | /* PREFIX_0F38DF */ |
| 3466 | { |
| 3467 | { Bad_Opcode }, |
| 3468 | { Bad_Opcode }, |
| 3469 | { "aesdeclast", { XM, EXx } }, |
| 3470 | }, |
| 3471 | |
| 3472 | /* PREFIX_0F38F0 */ |
| 3473 | { |
| 3474 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
| 3475 | { Bad_Opcode }, |
| 3476 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
| 3477 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
| 3478 | }, |
| 3479 | |
| 3480 | /* PREFIX_0F38F1 */ |
| 3481 | { |
| 3482 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
| 3483 | { Bad_Opcode }, |
| 3484 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
| 3485 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
| 3486 | }, |
| 3487 | |
| 3488 | /* PREFIX_0F3A08 */ |
| 3489 | { |
| 3490 | { Bad_Opcode }, |
| 3491 | { Bad_Opcode }, |
| 3492 | { "roundps", { XM, EXx, Ib } }, |
| 3493 | }, |
| 3494 | |
| 3495 | /* PREFIX_0F3A09 */ |
| 3496 | { |
| 3497 | { Bad_Opcode }, |
| 3498 | { Bad_Opcode }, |
| 3499 | { "roundpd", { XM, EXx, Ib } }, |
| 3500 | }, |
| 3501 | |
| 3502 | /* PREFIX_0F3A0A */ |
| 3503 | { |
| 3504 | { Bad_Opcode }, |
| 3505 | { Bad_Opcode }, |
| 3506 | { "roundss", { XM, EXd, Ib } }, |
| 3507 | }, |
| 3508 | |
| 3509 | /* PREFIX_0F3A0B */ |
| 3510 | { |
| 3511 | { Bad_Opcode }, |
| 3512 | { Bad_Opcode }, |
| 3513 | { "roundsd", { XM, EXq, Ib } }, |
| 3514 | }, |
| 3515 | |
| 3516 | /* PREFIX_0F3A0C */ |
| 3517 | { |
| 3518 | { Bad_Opcode }, |
| 3519 | { Bad_Opcode }, |
| 3520 | { "blendps", { XM, EXx, Ib } }, |
| 3521 | }, |
| 3522 | |
| 3523 | /* PREFIX_0F3A0D */ |
| 3524 | { |
| 3525 | { Bad_Opcode }, |
| 3526 | { Bad_Opcode }, |
| 3527 | { "blendpd", { XM, EXx, Ib } }, |
| 3528 | }, |
| 3529 | |
| 3530 | /* PREFIX_0F3A0E */ |
| 3531 | { |
| 3532 | { Bad_Opcode }, |
| 3533 | { Bad_Opcode }, |
| 3534 | { "pblendw", { XM, EXx, Ib } }, |
| 3535 | }, |
| 3536 | |
| 3537 | /* PREFIX_0F3A14 */ |
| 3538 | { |
| 3539 | { Bad_Opcode }, |
| 3540 | { Bad_Opcode }, |
| 3541 | { "pextrb", { Edqb, XM, Ib } }, |
| 3542 | }, |
| 3543 | |
| 3544 | /* PREFIX_0F3A15 */ |
| 3545 | { |
| 3546 | { Bad_Opcode }, |
| 3547 | { Bad_Opcode }, |
| 3548 | { "pextrw", { Edqw, XM, Ib } }, |
| 3549 | }, |
| 3550 | |
| 3551 | /* PREFIX_0F3A16 */ |
| 3552 | { |
| 3553 | { Bad_Opcode }, |
| 3554 | { Bad_Opcode }, |
| 3555 | { "pextrK", { Edq, XM, Ib } }, |
| 3556 | }, |
| 3557 | |
| 3558 | /* PREFIX_0F3A17 */ |
| 3559 | { |
| 3560 | { Bad_Opcode }, |
| 3561 | { Bad_Opcode }, |
| 3562 | { "extractps", { Edqd, XM, Ib } }, |
| 3563 | }, |
| 3564 | |
| 3565 | /* PREFIX_0F3A20 */ |
| 3566 | { |
| 3567 | { Bad_Opcode }, |
| 3568 | { Bad_Opcode }, |
| 3569 | { "pinsrb", { XM, Edqb, Ib } }, |
| 3570 | }, |
| 3571 | |
| 3572 | /* PREFIX_0F3A21 */ |
| 3573 | { |
| 3574 | { Bad_Opcode }, |
| 3575 | { Bad_Opcode }, |
| 3576 | { "insertps", { XM, EXd, Ib } }, |
| 3577 | }, |
| 3578 | |
| 3579 | /* PREFIX_0F3A22 */ |
| 3580 | { |
| 3581 | { Bad_Opcode }, |
| 3582 | { Bad_Opcode }, |
| 3583 | { "pinsrK", { XM, Edq, Ib } }, |
| 3584 | }, |
| 3585 | |
| 3586 | /* PREFIX_0F3A40 */ |
| 3587 | { |
| 3588 | { Bad_Opcode }, |
| 3589 | { Bad_Opcode }, |
| 3590 | { "dpps", { XM, EXx, Ib } }, |
| 3591 | }, |
| 3592 | |
| 3593 | /* PREFIX_0F3A41 */ |
| 3594 | { |
| 3595 | { Bad_Opcode }, |
| 3596 | { Bad_Opcode }, |
| 3597 | { "dppd", { XM, EXx, Ib } }, |
| 3598 | }, |
| 3599 | |
| 3600 | /* PREFIX_0F3A42 */ |
| 3601 | { |
| 3602 | { Bad_Opcode }, |
| 3603 | { Bad_Opcode }, |
| 3604 | { "mpsadbw", { XM, EXx, Ib } }, |
| 3605 | }, |
| 3606 | |
| 3607 | /* PREFIX_0F3A44 */ |
| 3608 | { |
| 3609 | { Bad_Opcode }, |
| 3610 | { Bad_Opcode }, |
| 3611 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
| 3612 | }, |
| 3613 | |
| 3614 | /* PREFIX_0F3A60 */ |
| 3615 | { |
| 3616 | { Bad_Opcode }, |
| 3617 | { Bad_Opcode }, |
| 3618 | { "pcmpestrm", { XM, EXx, Ib } }, |
| 3619 | }, |
| 3620 | |
| 3621 | /* PREFIX_0F3A61 */ |
| 3622 | { |
| 3623 | { Bad_Opcode }, |
| 3624 | { Bad_Opcode }, |
| 3625 | { "pcmpestri", { XM, EXx, Ib } }, |
| 3626 | }, |
| 3627 | |
| 3628 | /* PREFIX_0F3A62 */ |
| 3629 | { |
| 3630 | { Bad_Opcode }, |
| 3631 | { Bad_Opcode }, |
| 3632 | { "pcmpistrm", { XM, EXx, Ib } }, |
| 3633 | }, |
| 3634 | |
| 3635 | /* PREFIX_0F3A63 */ |
| 3636 | { |
| 3637 | { Bad_Opcode }, |
| 3638 | { Bad_Opcode }, |
| 3639 | { "pcmpistri", { XM, EXx, Ib } }, |
| 3640 | }, |
| 3641 | |
| 3642 | /* PREFIX_0F3ADF */ |
| 3643 | { |
| 3644 | { Bad_Opcode }, |
| 3645 | { Bad_Opcode }, |
| 3646 | { "aeskeygenassist", { XM, EXx, Ib } }, |
| 3647 | }, |
| 3648 | |
| 3649 | /* PREFIX_VEX_0F10 */ |
| 3650 | { |
| 3651 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
| 3652 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, |
| 3653 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, |
| 3654 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, |
| 3655 | }, |
| 3656 | |
| 3657 | /* PREFIX_VEX_0F11 */ |
| 3658 | { |
| 3659 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
| 3660 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, |
| 3661 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, |
| 3662 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, |
| 3663 | }, |
| 3664 | |
| 3665 | /* PREFIX_VEX_0F12 */ |
| 3666 | { |
| 3667 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
| 3668 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, |
| 3669 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
| 3670 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, |
| 3671 | }, |
| 3672 | |
| 3673 | /* PREFIX_VEX_0F16 */ |
| 3674 | { |
| 3675 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
| 3676 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, |
| 3677 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
| 3678 | }, |
| 3679 | |
| 3680 | /* PREFIX_VEX_0F2A */ |
| 3681 | { |
| 3682 | { Bad_Opcode }, |
| 3683 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
| 3684 | { Bad_Opcode }, |
| 3685 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
| 3686 | }, |
| 3687 | |
| 3688 | /* PREFIX_VEX_0F2C */ |
| 3689 | { |
| 3690 | { Bad_Opcode }, |
| 3691 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
| 3692 | { Bad_Opcode }, |
| 3693 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
| 3694 | }, |
| 3695 | |
| 3696 | /* PREFIX_VEX_0F2D */ |
| 3697 | { |
| 3698 | { Bad_Opcode }, |
| 3699 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
| 3700 | { Bad_Opcode }, |
| 3701 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
| 3702 | }, |
| 3703 | |
| 3704 | /* PREFIX_VEX_0F2E */ |
| 3705 | { |
| 3706 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
| 3707 | { Bad_Opcode }, |
| 3708 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
| 3709 | }, |
| 3710 | |
| 3711 | /* PREFIX_VEX_0F2F */ |
| 3712 | { |
| 3713 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
| 3714 | { Bad_Opcode }, |
| 3715 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
| 3716 | }, |
| 3717 | |
| 3718 | /* PREFIX_VEX_0F51 */ |
| 3719 | { |
| 3720 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
| 3721 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, |
| 3722 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, |
| 3723 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, |
| 3724 | }, |
| 3725 | |
| 3726 | /* PREFIX_VEX_0F52 */ |
| 3727 | { |
| 3728 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
| 3729 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, |
| 3730 | }, |
| 3731 | |
| 3732 | /* PREFIX_VEX_0F53 */ |
| 3733 | { |
| 3734 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
| 3735 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, |
| 3736 | }, |
| 3737 | |
| 3738 | /* PREFIX_VEX_0F58 */ |
| 3739 | { |
| 3740 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
| 3741 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, |
| 3742 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, |
| 3743 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, |
| 3744 | }, |
| 3745 | |
| 3746 | /* PREFIX_VEX_0F59 */ |
| 3747 | { |
| 3748 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
| 3749 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, |
| 3750 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, |
| 3751 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, |
| 3752 | }, |
| 3753 | |
| 3754 | /* PREFIX_VEX_0F5A */ |
| 3755 | { |
| 3756 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
| 3757 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, |
| 3758 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
| 3759 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
| 3760 | }, |
| 3761 | |
| 3762 | /* PREFIX_VEX_0F5B */ |
| 3763 | { |
| 3764 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
| 3765 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, |
| 3766 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, |
| 3767 | }, |
| 3768 | |
| 3769 | /* PREFIX_VEX_0F5C */ |
| 3770 | { |
| 3771 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
| 3772 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, |
| 3773 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, |
| 3774 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, |
| 3775 | }, |
| 3776 | |
| 3777 | /* PREFIX_VEX_0F5D */ |
| 3778 | { |
| 3779 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
| 3780 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, |
| 3781 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, |
| 3782 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, |
| 3783 | }, |
| 3784 | |
| 3785 | /* PREFIX_VEX_0F5E */ |
| 3786 | { |
| 3787 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
| 3788 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, |
| 3789 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, |
| 3790 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, |
| 3791 | }, |
| 3792 | |
| 3793 | /* PREFIX_VEX_0F5F */ |
| 3794 | { |
| 3795 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
| 3796 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, |
| 3797 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, |
| 3798 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, |
| 3799 | }, |
| 3800 | |
| 3801 | /* PREFIX_VEX_0F60 */ |
| 3802 | { |
| 3803 | { Bad_Opcode }, |
| 3804 | { Bad_Opcode }, |
| 3805 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
| 3806 | }, |
| 3807 | |
| 3808 | /* PREFIX_VEX_0F61 */ |
| 3809 | { |
| 3810 | { Bad_Opcode }, |
| 3811 | { Bad_Opcode }, |
| 3812 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
| 3813 | }, |
| 3814 | |
| 3815 | /* PREFIX_VEX_0F62 */ |
| 3816 | { |
| 3817 | { Bad_Opcode }, |
| 3818 | { Bad_Opcode }, |
| 3819 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
| 3820 | }, |
| 3821 | |
| 3822 | /* PREFIX_VEX_0F63 */ |
| 3823 | { |
| 3824 | { Bad_Opcode }, |
| 3825 | { Bad_Opcode }, |
| 3826 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
| 3827 | }, |
| 3828 | |
| 3829 | /* PREFIX_VEX_0F64 */ |
| 3830 | { |
| 3831 | { Bad_Opcode }, |
| 3832 | { Bad_Opcode }, |
| 3833 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
| 3834 | }, |
| 3835 | |
| 3836 | /* PREFIX_VEX_0F65 */ |
| 3837 | { |
| 3838 | { Bad_Opcode }, |
| 3839 | { Bad_Opcode }, |
| 3840 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
| 3841 | }, |
| 3842 | |
| 3843 | /* PREFIX_VEX_0F66 */ |
| 3844 | { |
| 3845 | { Bad_Opcode }, |
| 3846 | { Bad_Opcode }, |
| 3847 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
| 3848 | }, |
| 3849 | |
| 3850 | /* PREFIX_VEX_0F67 */ |
| 3851 | { |
| 3852 | { Bad_Opcode }, |
| 3853 | { Bad_Opcode }, |
| 3854 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
| 3855 | }, |
| 3856 | |
| 3857 | /* PREFIX_VEX_0F68 */ |
| 3858 | { |
| 3859 | { Bad_Opcode }, |
| 3860 | { Bad_Opcode }, |
| 3861 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
| 3862 | }, |
| 3863 | |
| 3864 | /* PREFIX_VEX_0F69 */ |
| 3865 | { |
| 3866 | { Bad_Opcode }, |
| 3867 | { Bad_Opcode }, |
| 3868 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
| 3869 | }, |
| 3870 | |
| 3871 | /* PREFIX_VEX_0F6A */ |
| 3872 | { |
| 3873 | { Bad_Opcode }, |
| 3874 | { Bad_Opcode }, |
| 3875 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
| 3876 | }, |
| 3877 | |
| 3878 | /* PREFIX_VEX_0F6B */ |
| 3879 | { |
| 3880 | { Bad_Opcode }, |
| 3881 | { Bad_Opcode }, |
| 3882 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
| 3883 | }, |
| 3884 | |
| 3885 | /* PREFIX_VEX_0F6C */ |
| 3886 | { |
| 3887 | { Bad_Opcode }, |
| 3888 | { Bad_Opcode }, |
| 3889 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
| 3890 | }, |
| 3891 | |
| 3892 | /* PREFIX_VEX_0F6D */ |
| 3893 | { |
| 3894 | { Bad_Opcode }, |
| 3895 | { Bad_Opcode }, |
| 3896 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
| 3897 | }, |
| 3898 | |
| 3899 | /* PREFIX_VEX_0F6E */ |
| 3900 | { |
| 3901 | { Bad_Opcode }, |
| 3902 | { Bad_Opcode }, |
| 3903 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
| 3904 | }, |
| 3905 | |
| 3906 | /* PREFIX_VEX_0F6F */ |
| 3907 | { |
| 3908 | { Bad_Opcode }, |
| 3909 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
| 3910 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, |
| 3911 | }, |
| 3912 | |
| 3913 | /* PREFIX_VEX_0F70 */ |
| 3914 | { |
| 3915 | { Bad_Opcode }, |
| 3916 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
| 3917 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, |
| 3918 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, |
| 3919 | }, |
| 3920 | |
| 3921 | /* PREFIX_VEX_0F71_REG_2 */ |
| 3922 | { |
| 3923 | { Bad_Opcode }, |
| 3924 | { Bad_Opcode }, |
| 3925 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
| 3926 | }, |
| 3927 | |
| 3928 | /* PREFIX_VEX_0F71_REG_4 */ |
| 3929 | { |
| 3930 | { Bad_Opcode }, |
| 3931 | { Bad_Opcode }, |
| 3932 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
| 3933 | }, |
| 3934 | |
| 3935 | /* PREFIX_VEX_0F71_REG_6 */ |
| 3936 | { |
| 3937 | { Bad_Opcode }, |
| 3938 | { Bad_Opcode }, |
| 3939 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
| 3940 | }, |
| 3941 | |
| 3942 | /* PREFIX_VEX_0F72_REG_2 */ |
| 3943 | { |
| 3944 | { Bad_Opcode }, |
| 3945 | { Bad_Opcode }, |
| 3946 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
| 3947 | }, |
| 3948 | |
| 3949 | /* PREFIX_VEX_0F72_REG_4 */ |
| 3950 | { |
| 3951 | { Bad_Opcode }, |
| 3952 | { Bad_Opcode }, |
| 3953 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
| 3954 | }, |
| 3955 | |
| 3956 | /* PREFIX_VEX_0F72_REG_6 */ |
| 3957 | { |
| 3958 | { Bad_Opcode }, |
| 3959 | { Bad_Opcode }, |
| 3960 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
| 3961 | }, |
| 3962 | |
| 3963 | /* PREFIX_VEX_0F73_REG_2 */ |
| 3964 | { |
| 3965 | { Bad_Opcode }, |
| 3966 | { Bad_Opcode }, |
| 3967 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
| 3968 | }, |
| 3969 | |
| 3970 | /* PREFIX_VEX_0F73_REG_3 */ |
| 3971 | { |
| 3972 | { Bad_Opcode }, |
| 3973 | { Bad_Opcode }, |
| 3974 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
| 3975 | }, |
| 3976 | |
| 3977 | /* PREFIX_VEX_0F73_REG_6 */ |
| 3978 | { |
| 3979 | { Bad_Opcode }, |
| 3980 | { Bad_Opcode }, |
| 3981 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
| 3982 | }, |
| 3983 | |
| 3984 | /* PREFIX_VEX_0F73_REG_7 */ |
| 3985 | { |
| 3986 | { Bad_Opcode }, |
| 3987 | { Bad_Opcode }, |
| 3988 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
| 3989 | }, |
| 3990 | |
| 3991 | /* PREFIX_VEX_0F74 */ |
| 3992 | { |
| 3993 | { Bad_Opcode }, |
| 3994 | { Bad_Opcode }, |
| 3995 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
| 3996 | }, |
| 3997 | |
| 3998 | /* PREFIX_VEX_0F75 */ |
| 3999 | { |
| 4000 | { Bad_Opcode }, |
| 4001 | { Bad_Opcode }, |
| 4002 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
| 4003 | }, |
| 4004 | |
| 4005 | /* PREFIX_VEX_0F76 */ |
| 4006 | { |
| 4007 | { Bad_Opcode }, |
| 4008 | { Bad_Opcode }, |
| 4009 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
| 4010 | }, |
| 4011 | |
| 4012 | /* PREFIX_VEX_0F77 */ |
| 4013 | { |
| 4014 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
| 4015 | }, |
| 4016 | |
| 4017 | /* PREFIX_VEX_0F7C */ |
| 4018 | { |
| 4019 | { Bad_Opcode }, |
| 4020 | { Bad_Opcode }, |
| 4021 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
| 4022 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, |
| 4023 | }, |
| 4024 | |
| 4025 | /* PREFIX_VEX_0F7D */ |
| 4026 | { |
| 4027 | { Bad_Opcode }, |
| 4028 | { Bad_Opcode }, |
| 4029 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
| 4030 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, |
| 4031 | }, |
| 4032 | |
| 4033 | /* PREFIX_VEX_0F7E */ |
| 4034 | { |
| 4035 | { Bad_Opcode }, |
| 4036 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
| 4037 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, |
| 4038 | }, |
| 4039 | |
| 4040 | /* PREFIX_VEX_0F7F */ |
| 4041 | { |
| 4042 | { Bad_Opcode }, |
| 4043 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
| 4044 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, |
| 4045 | }, |
| 4046 | |
| 4047 | /* PREFIX_VEX_0FC2 */ |
| 4048 | { |
| 4049 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
| 4050 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, |
| 4051 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, |
| 4052 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, |
| 4053 | }, |
| 4054 | |
| 4055 | /* PREFIX_VEX_0FC4 */ |
| 4056 | { |
| 4057 | { Bad_Opcode }, |
| 4058 | { Bad_Opcode }, |
| 4059 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
| 4060 | }, |
| 4061 | |
| 4062 | /* PREFIX_VEX_0FC5 */ |
| 4063 | { |
| 4064 | { Bad_Opcode }, |
| 4065 | { Bad_Opcode }, |
| 4066 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
| 4067 | }, |
| 4068 | |
| 4069 | /* PREFIX_VEX_0FD0 */ |
| 4070 | { |
| 4071 | { Bad_Opcode }, |
| 4072 | { Bad_Opcode }, |
| 4073 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
| 4074 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, |
| 4075 | }, |
| 4076 | |
| 4077 | /* PREFIX_VEX_0FD1 */ |
| 4078 | { |
| 4079 | { Bad_Opcode }, |
| 4080 | { Bad_Opcode }, |
| 4081 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
| 4082 | }, |
| 4083 | |
| 4084 | /* PREFIX_VEX_0FD2 */ |
| 4085 | { |
| 4086 | { Bad_Opcode }, |
| 4087 | { Bad_Opcode }, |
| 4088 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
| 4089 | }, |
| 4090 | |
| 4091 | /* PREFIX_VEX_0FD3 */ |
| 4092 | { |
| 4093 | { Bad_Opcode }, |
| 4094 | { Bad_Opcode }, |
| 4095 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
| 4096 | }, |
| 4097 | |
| 4098 | /* PREFIX_VEX_0FD4 */ |
| 4099 | { |
| 4100 | { Bad_Opcode }, |
| 4101 | { Bad_Opcode }, |
| 4102 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
| 4103 | }, |
| 4104 | |
| 4105 | /* PREFIX_VEX_0FD5 */ |
| 4106 | { |
| 4107 | { Bad_Opcode }, |
| 4108 | { Bad_Opcode }, |
| 4109 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
| 4110 | }, |
| 4111 | |
| 4112 | /* PREFIX_VEX_0FD6 */ |
| 4113 | { |
| 4114 | { Bad_Opcode }, |
| 4115 | { Bad_Opcode }, |
| 4116 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
| 4117 | }, |
| 4118 | |
| 4119 | /* PREFIX_VEX_0FD7 */ |
| 4120 | { |
| 4121 | { Bad_Opcode }, |
| 4122 | { Bad_Opcode }, |
| 4123 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
| 4124 | }, |
| 4125 | |
| 4126 | /* PREFIX_VEX_0FD8 */ |
| 4127 | { |
| 4128 | { Bad_Opcode }, |
| 4129 | { Bad_Opcode }, |
| 4130 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
| 4131 | }, |
| 4132 | |
| 4133 | /* PREFIX_VEX_0FD9 */ |
| 4134 | { |
| 4135 | { Bad_Opcode }, |
| 4136 | { Bad_Opcode }, |
| 4137 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
| 4138 | }, |
| 4139 | |
| 4140 | /* PREFIX_VEX_0FDA */ |
| 4141 | { |
| 4142 | { Bad_Opcode }, |
| 4143 | { Bad_Opcode }, |
| 4144 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
| 4145 | }, |
| 4146 | |
| 4147 | /* PREFIX_VEX_0FDB */ |
| 4148 | { |
| 4149 | { Bad_Opcode }, |
| 4150 | { Bad_Opcode }, |
| 4151 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
| 4152 | }, |
| 4153 | |
| 4154 | /* PREFIX_VEX_0FDC */ |
| 4155 | { |
| 4156 | { Bad_Opcode }, |
| 4157 | { Bad_Opcode }, |
| 4158 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
| 4159 | }, |
| 4160 | |
| 4161 | /* PREFIX_VEX_0FDD */ |
| 4162 | { |
| 4163 | { Bad_Opcode }, |
| 4164 | { Bad_Opcode }, |
| 4165 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
| 4166 | }, |
| 4167 | |
| 4168 | /* PREFIX_VEX_0FDE */ |
| 4169 | { |
| 4170 | { Bad_Opcode }, |
| 4171 | { Bad_Opcode }, |
| 4172 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
| 4173 | }, |
| 4174 | |
| 4175 | /* PREFIX_VEX_0FDF */ |
| 4176 | { |
| 4177 | { Bad_Opcode }, |
| 4178 | { Bad_Opcode }, |
| 4179 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
| 4180 | }, |
| 4181 | |
| 4182 | /* PREFIX_VEX_0FE0 */ |
| 4183 | { |
| 4184 | { Bad_Opcode }, |
| 4185 | { Bad_Opcode }, |
| 4186 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
| 4187 | }, |
| 4188 | |
| 4189 | /* PREFIX_VEX_0FE1 */ |
| 4190 | { |
| 4191 | { Bad_Opcode }, |
| 4192 | { Bad_Opcode }, |
| 4193 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
| 4194 | }, |
| 4195 | |
| 4196 | /* PREFIX_VEX_0FE2 */ |
| 4197 | { |
| 4198 | { Bad_Opcode }, |
| 4199 | { Bad_Opcode }, |
| 4200 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
| 4201 | }, |
| 4202 | |
| 4203 | /* PREFIX_VEX_0FE3 */ |
| 4204 | { |
| 4205 | { Bad_Opcode }, |
| 4206 | { Bad_Opcode }, |
| 4207 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
| 4208 | }, |
| 4209 | |
| 4210 | /* PREFIX_VEX_0FE4 */ |
| 4211 | { |
| 4212 | { Bad_Opcode }, |
| 4213 | { Bad_Opcode }, |
| 4214 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
| 4215 | }, |
| 4216 | |
| 4217 | /* PREFIX_VEX_0FE5 */ |
| 4218 | { |
| 4219 | { Bad_Opcode }, |
| 4220 | { Bad_Opcode }, |
| 4221 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
| 4222 | }, |
| 4223 | |
| 4224 | /* PREFIX_VEX_0FE6 */ |
| 4225 | { |
| 4226 | { Bad_Opcode }, |
| 4227 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
| 4228 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, |
| 4229 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, |
| 4230 | }, |
| 4231 | |
| 4232 | /* PREFIX_VEX_0FE7 */ |
| 4233 | { |
| 4234 | { Bad_Opcode }, |
| 4235 | { Bad_Opcode }, |
| 4236 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
| 4237 | }, |
| 4238 | |
| 4239 | /* PREFIX_VEX_0FE8 */ |
| 4240 | { |
| 4241 | { Bad_Opcode }, |
| 4242 | { Bad_Opcode }, |
| 4243 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
| 4244 | }, |
| 4245 | |
| 4246 | /* PREFIX_VEX_0FE9 */ |
| 4247 | { |
| 4248 | { Bad_Opcode }, |
| 4249 | { Bad_Opcode }, |
| 4250 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
| 4251 | }, |
| 4252 | |
| 4253 | /* PREFIX_VEX_0FEA */ |
| 4254 | { |
| 4255 | { Bad_Opcode }, |
| 4256 | { Bad_Opcode }, |
| 4257 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
| 4258 | }, |
| 4259 | |
| 4260 | /* PREFIX_VEX_0FEB */ |
| 4261 | { |
| 4262 | { Bad_Opcode }, |
| 4263 | { Bad_Opcode }, |
| 4264 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
| 4265 | }, |
| 4266 | |
| 4267 | /* PREFIX_VEX_0FEC */ |
| 4268 | { |
| 4269 | { Bad_Opcode }, |
| 4270 | { Bad_Opcode }, |
| 4271 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
| 4272 | }, |
| 4273 | |
| 4274 | /* PREFIX_VEX_0FED */ |
| 4275 | { |
| 4276 | { Bad_Opcode }, |
| 4277 | { Bad_Opcode }, |
| 4278 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
| 4279 | }, |
| 4280 | |
| 4281 | /* PREFIX_VEX_0FEE */ |
| 4282 | { |
| 4283 | { Bad_Opcode }, |
| 4284 | { Bad_Opcode }, |
| 4285 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
| 4286 | }, |
| 4287 | |
| 4288 | /* PREFIX_VEX_0FEF */ |
| 4289 | { |
| 4290 | { Bad_Opcode }, |
| 4291 | { Bad_Opcode }, |
| 4292 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
| 4293 | }, |
| 4294 | |
| 4295 | /* PREFIX_VEX_0FF0 */ |
| 4296 | { |
| 4297 | { Bad_Opcode }, |
| 4298 | { Bad_Opcode }, |
| 4299 | { Bad_Opcode }, |
| 4300 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
| 4301 | }, |
| 4302 | |
| 4303 | /* PREFIX_VEX_0FF1 */ |
| 4304 | { |
| 4305 | { Bad_Opcode }, |
| 4306 | { Bad_Opcode }, |
| 4307 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
| 4308 | }, |
| 4309 | |
| 4310 | /* PREFIX_VEX_0FF2 */ |
| 4311 | { |
| 4312 | { Bad_Opcode }, |
| 4313 | { Bad_Opcode }, |
| 4314 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
| 4315 | }, |
| 4316 | |
| 4317 | /* PREFIX_VEX_0FF3 */ |
| 4318 | { |
| 4319 | { Bad_Opcode }, |
| 4320 | { Bad_Opcode }, |
| 4321 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
| 4322 | }, |
| 4323 | |
| 4324 | /* PREFIX_VEX_0FF4 */ |
| 4325 | { |
| 4326 | { Bad_Opcode }, |
| 4327 | { Bad_Opcode }, |
| 4328 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
| 4329 | }, |
| 4330 | |
| 4331 | /* PREFIX_VEX_0FF5 */ |
| 4332 | { |
| 4333 | { Bad_Opcode }, |
| 4334 | { Bad_Opcode }, |
| 4335 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
| 4336 | }, |
| 4337 | |
| 4338 | /* PREFIX_VEX_0FF6 */ |
| 4339 | { |
| 4340 | { Bad_Opcode }, |
| 4341 | { Bad_Opcode }, |
| 4342 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
| 4343 | }, |
| 4344 | |
| 4345 | /* PREFIX_VEX_0FF7 */ |
| 4346 | { |
| 4347 | { Bad_Opcode }, |
| 4348 | { Bad_Opcode }, |
| 4349 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
| 4350 | }, |
| 4351 | |
| 4352 | /* PREFIX_VEX_0FF8 */ |
| 4353 | { |
| 4354 | { Bad_Opcode }, |
| 4355 | { Bad_Opcode }, |
| 4356 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
| 4357 | }, |
| 4358 | |
| 4359 | /* PREFIX_VEX_0FF9 */ |
| 4360 | { |
| 4361 | { Bad_Opcode }, |
| 4362 | { Bad_Opcode }, |
| 4363 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
| 4364 | }, |
| 4365 | |
| 4366 | /* PREFIX_VEX_0FFA */ |
| 4367 | { |
| 4368 | { Bad_Opcode }, |
| 4369 | { Bad_Opcode }, |
| 4370 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
| 4371 | }, |
| 4372 | |
| 4373 | /* PREFIX_VEX_0FFB */ |
| 4374 | { |
| 4375 | { Bad_Opcode }, |
| 4376 | { Bad_Opcode }, |
| 4377 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
| 4378 | }, |
| 4379 | |
| 4380 | /* PREFIX_VEX_0FFC */ |
| 4381 | { |
| 4382 | { Bad_Opcode }, |
| 4383 | { Bad_Opcode }, |
| 4384 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
| 4385 | }, |
| 4386 | |
| 4387 | /* PREFIX_VEX_0FFD */ |
| 4388 | { |
| 4389 | { Bad_Opcode }, |
| 4390 | { Bad_Opcode }, |
| 4391 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
| 4392 | }, |
| 4393 | |
| 4394 | /* PREFIX_VEX_0FFE */ |
| 4395 | { |
| 4396 | { Bad_Opcode }, |
| 4397 | { Bad_Opcode }, |
| 4398 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
| 4399 | }, |
| 4400 | |
| 4401 | /* PREFIX_VEX_0F3800 */ |
| 4402 | { |
| 4403 | { Bad_Opcode }, |
| 4404 | { Bad_Opcode }, |
| 4405 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
| 4406 | }, |
| 4407 | |
| 4408 | /* PREFIX_VEX_0F3801 */ |
| 4409 | { |
| 4410 | { Bad_Opcode }, |
| 4411 | { Bad_Opcode }, |
| 4412 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
| 4413 | }, |
| 4414 | |
| 4415 | /* PREFIX_VEX_0F3802 */ |
| 4416 | { |
| 4417 | { Bad_Opcode }, |
| 4418 | { Bad_Opcode }, |
| 4419 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
| 4420 | }, |
| 4421 | |
| 4422 | /* PREFIX_VEX_0F3803 */ |
| 4423 | { |
| 4424 | { Bad_Opcode }, |
| 4425 | { Bad_Opcode }, |
| 4426 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
| 4427 | }, |
| 4428 | |
| 4429 | /* PREFIX_VEX_0F3804 */ |
| 4430 | { |
| 4431 | { Bad_Opcode }, |
| 4432 | { Bad_Opcode }, |
| 4433 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
| 4434 | }, |
| 4435 | |
| 4436 | /* PREFIX_VEX_0F3805 */ |
| 4437 | { |
| 4438 | { Bad_Opcode }, |
| 4439 | { Bad_Opcode }, |
| 4440 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
| 4441 | }, |
| 4442 | |
| 4443 | /* PREFIX_VEX_0F3806 */ |
| 4444 | { |
| 4445 | { Bad_Opcode }, |
| 4446 | { Bad_Opcode }, |
| 4447 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
| 4448 | }, |
| 4449 | |
| 4450 | /* PREFIX_VEX_0F3807 */ |
| 4451 | { |
| 4452 | { Bad_Opcode }, |
| 4453 | { Bad_Opcode }, |
| 4454 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
| 4455 | }, |
| 4456 | |
| 4457 | /* PREFIX_VEX_0F3808 */ |
| 4458 | { |
| 4459 | { Bad_Opcode }, |
| 4460 | { Bad_Opcode }, |
| 4461 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
| 4462 | }, |
| 4463 | |
| 4464 | /* PREFIX_VEX_0F3809 */ |
| 4465 | { |
| 4466 | { Bad_Opcode }, |
| 4467 | { Bad_Opcode }, |
| 4468 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
| 4469 | }, |
| 4470 | |
| 4471 | /* PREFIX_VEX_0F380A */ |
| 4472 | { |
| 4473 | { Bad_Opcode }, |
| 4474 | { Bad_Opcode }, |
| 4475 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
| 4476 | }, |
| 4477 | |
| 4478 | /* PREFIX_VEX_0F380B */ |
| 4479 | { |
| 4480 | { Bad_Opcode }, |
| 4481 | { Bad_Opcode }, |
| 4482 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
| 4483 | }, |
| 4484 | |
| 4485 | /* PREFIX_VEX_0F380C */ |
| 4486 | { |
| 4487 | { Bad_Opcode }, |
| 4488 | { Bad_Opcode }, |
| 4489 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
| 4490 | }, |
| 4491 | |
| 4492 | /* PREFIX_VEX_0F380D */ |
| 4493 | { |
| 4494 | { Bad_Opcode }, |
| 4495 | { Bad_Opcode }, |
| 4496 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
| 4497 | }, |
| 4498 | |
| 4499 | /* PREFIX_VEX_0F380E */ |
| 4500 | { |
| 4501 | { Bad_Opcode }, |
| 4502 | { Bad_Opcode }, |
| 4503 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
| 4504 | }, |
| 4505 | |
| 4506 | /* PREFIX_VEX_0F380F */ |
| 4507 | { |
| 4508 | { Bad_Opcode }, |
| 4509 | { Bad_Opcode }, |
| 4510 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
| 4511 | }, |
| 4512 | |
| 4513 | /* PREFIX_VEX_0F3813 */ |
| 4514 | { |
| 4515 | { Bad_Opcode }, |
| 4516 | { Bad_Opcode }, |
| 4517 | { "vcvtph2ps", { XM, EXxmmq } }, |
| 4518 | }, |
| 4519 | |
| 4520 | /* PREFIX_VEX_0F3816 */ |
| 4521 | { |
| 4522 | { Bad_Opcode }, |
| 4523 | { Bad_Opcode }, |
| 4524 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, |
| 4525 | }, |
| 4526 | |
| 4527 | /* PREFIX_VEX_0F3817 */ |
| 4528 | { |
| 4529 | { Bad_Opcode }, |
| 4530 | { Bad_Opcode }, |
| 4531 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
| 4532 | }, |
| 4533 | |
| 4534 | /* PREFIX_VEX_0F3818 */ |
| 4535 | { |
| 4536 | { Bad_Opcode }, |
| 4537 | { Bad_Opcode }, |
| 4538 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
| 4539 | }, |
| 4540 | |
| 4541 | /* PREFIX_VEX_0F3819 */ |
| 4542 | { |
| 4543 | { Bad_Opcode }, |
| 4544 | { Bad_Opcode }, |
| 4545 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
| 4546 | }, |
| 4547 | |
| 4548 | /* PREFIX_VEX_0F381A */ |
| 4549 | { |
| 4550 | { Bad_Opcode }, |
| 4551 | { Bad_Opcode }, |
| 4552 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
| 4553 | }, |
| 4554 | |
| 4555 | /* PREFIX_VEX_0F381C */ |
| 4556 | { |
| 4557 | { Bad_Opcode }, |
| 4558 | { Bad_Opcode }, |
| 4559 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
| 4560 | }, |
| 4561 | |
| 4562 | /* PREFIX_VEX_0F381D */ |
| 4563 | { |
| 4564 | { Bad_Opcode }, |
| 4565 | { Bad_Opcode }, |
| 4566 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
| 4567 | }, |
| 4568 | |
| 4569 | /* PREFIX_VEX_0F381E */ |
| 4570 | { |
| 4571 | { Bad_Opcode }, |
| 4572 | { Bad_Opcode }, |
| 4573 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
| 4574 | }, |
| 4575 | |
| 4576 | /* PREFIX_VEX_0F3820 */ |
| 4577 | { |
| 4578 | { Bad_Opcode }, |
| 4579 | { Bad_Opcode }, |
| 4580 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
| 4581 | }, |
| 4582 | |
| 4583 | /* PREFIX_VEX_0F3821 */ |
| 4584 | { |
| 4585 | { Bad_Opcode }, |
| 4586 | { Bad_Opcode }, |
| 4587 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
| 4588 | }, |
| 4589 | |
| 4590 | /* PREFIX_VEX_0F3822 */ |
| 4591 | { |
| 4592 | { Bad_Opcode }, |
| 4593 | { Bad_Opcode }, |
| 4594 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
| 4595 | }, |
| 4596 | |
| 4597 | /* PREFIX_VEX_0F3823 */ |
| 4598 | { |
| 4599 | { Bad_Opcode }, |
| 4600 | { Bad_Opcode }, |
| 4601 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
| 4602 | }, |
| 4603 | |
| 4604 | /* PREFIX_VEX_0F3824 */ |
| 4605 | { |
| 4606 | { Bad_Opcode }, |
| 4607 | { Bad_Opcode }, |
| 4608 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
| 4609 | }, |
| 4610 | |
| 4611 | /* PREFIX_VEX_0F3825 */ |
| 4612 | { |
| 4613 | { Bad_Opcode }, |
| 4614 | { Bad_Opcode }, |
| 4615 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
| 4616 | }, |
| 4617 | |
| 4618 | /* PREFIX_VEX_0F3828 */ |
| 4619 | { |
| 4620 | { Bad_Opcode }, |
| 4621 | { Bad_Opcode }, |
| 4622 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
| 4623 | }, |
| 4624 | |
| 4625 | /* PREFIX_VEX_0F3829 */ |
| 4626 | { |
| 4627 | { Bad_Opcode }, |
| 4628 | { Bad_Opcode }, |
| 4629 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
| 4630 | }, |
| 4631 | |
| 4632 | /* PREFIX_VEX_0F382A */ |
| 4633 | { |
| 4634 | { Bad_Opcode }, |
| 4635 | { Bad_Opcode }, |
| 4636 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
| 4637 | }, |
| 4638 | |
| 4639 | /* PREFIX_VEX_0F382B */ |
| 4640 | { |
| 4641 | { Bad_Opcode }, |
| 4642 | { Bad_Opcode }, |
| 4643 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
| 4644 | }, |
| 4645 | |
| 4646 | /* PREFIX_VEX_0F382C */ |
| 4647 | { |
| 4648 | { Bad_Opcode }, |
| 4649 | { Bad_Opcode }, |
| 4650 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
| 4651 | }, |
| 4652 | |
| 4653 | /* PREFIX_VEX_0F382D */ |
| 4654 | { |
| 4655 | { Bad_Opcode }, |
| 4656 | { Bad_Opcode }, |
| 4657 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
| 4658 | }, |
| 4659 | |
| 4660 | /* PREFIX_VEX_0F382E */ |
| 4661 | { |
| 4662 | { Bad_Opcode }, |
| 4663 | { Bad_Opcode }, |
| 4664 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
| 4665 | }, |
| 4666 | |
| 4667 | /* PREFIX_VEX_0F382F */ |
| 4668 | { |
| 4669 | { Bad_Opcode }, |
| 4670 | { Bad_Opcode }, |
| 4671 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
| 4672 | }, |
| 4673 | |
| 4674 | /* PREFIX_VEX_0F3830 */ |
| 4675 | { |
| 4676 | { Bad_Opcode }, |
| 4677 | { Bad_Opcode }, |
| 4678 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
| 4679 | }, |
| 4680 | |
| 4681 | /* PREFIX_VEX_0F3831 */ |
| 4682 | { |
| 4683 | { Bad_Opcode }, |
| 4684 | { Bad_Opcode }, |
| 4685 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
| 4686 | }, |
| 4687 | |
| 4688 | /* PREFIX_VEX_0F3832 */ |
| 4689 | { |
| 4690 | { Bad_Opcode }, |
| 4691 | { Bad_Opcode }, |
| 4692 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
| 4693 | }, |
| 4694 | |
| 4695 | /* PREFIX_VEX_0F3833 */ |
| 4696 | { |
| 4697 | { Bad_Opcode }, |
| 4698 | { Bad_Opcode }, |
| 4699 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
| 4700 | }, |
| 4701 | |
| 4702 | /* PREFIX_VEX_0F3834 */ |
| 4703 | { |
| 4704 | { Bad_Opcode }, |
| 4705 | { Bad_Opcode }, |
| 4706 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
| 4707 | }, |
| 4708 | |
| 4709 | /* PREFIX_VEX_0F3835 */ |
| 4710 | { |
| 4711 | { Bad_Opcode }, |
| 4712 | { Bad_Opcode }, |
| 4713 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
| 4714 | }, |
| 4715 | |
| 4716 | /* PREFIX_VEX_0F3836 */ |
| 4717 | { |
| 4718 | { Bad_Opcode }, |
| 4719 | { Bad_Opcode }, |
| 4720 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, |
| 4721 | }, |
| 4722 | |
| 4723 | /* PREFIX_VEX_0F3837 */ |
| 4724 | { |
| 4725 | { Bad_Opcode }, |
| 4726 | { Bad_Opcode }, |
| 4727 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
| 4728 | }, |
| 4729 | |
| 4730 | /* PREFIX_VEX_0F3838 */ |
| 4731 | { |
| 4732 | { Bad_Opcode }, |
| 4733 | { Bad_Opcode }, |
| 4734 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
| 4735 | }, |
| 4736 | |
| 4737 | /* PREFIX_VEX_0F3839 */ |
| 4738 | { |
| 4739 | { Bad_Opcode }, |
| 4740 | { Bad_Opcode }, |
| 4741 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
| 4742 | }, |
| 4743 | |
| 4744 | /* PREFIX_VEX_0F383A */ |
| 4745 | { |
| 4746 | { Bad_Opcode }, |
| 4747 | { Bad_Opcode }, |
| 4748 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
| 4749 | }, |
| 4750 | |
| 4751 | /* PREFIX_VEX_0F383B */ |
| 4752 | { |
| 4753 | { Bad_Opcode }, |
| 4754 | { Bad_Opcode }, |
| 4755 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
| 4756 | }, |
| 4757 | |
| 4758 | /* PREFIX_VEX_0F383C */ |
| 4759 | { |
| 4760 | { Bad_Opcode }, |
| 4761 | { Bad_Opcode }, |
| 4762 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
| 4763 | }, |
| 4764 | |
| 4765 | /* PREFIX_VEX_0F383D */ |
| 4766 | { |
| 4767 | { Bad_Opcode }, |
| 4768 | { Bad_Opcode }, |
| 4769 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
| 4770 | }, |
| 4771 | |
| 4772 | /* PREFIX_VEX_0F383E */ |
| 4773 | { |
| 4774 | { Bad_Opcode }, |
| 4775 | { Bad_Opcode }, |
| 4776 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
| 4777 | }, |
| 4778 | |
| 4779 | /* PREFIX_VEX_0F383F */ |
| 4780 | { |
| 4781 | { Bad_Opcode }, |
| 4782 | { Bad_Opcode }, |
| 4783 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
| 4784 | }, |
| 4785 | |
| 4786 | /* PREFIX_VEX_0F3840 */ |
| 4787 | { |
| 4788 | { Bad_Opcode }, |
| 4789 | { Bad_Opcode }, |
| 4790 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
| 4791 | }, |
| 4792 | |
| 4793 | /* PREFIX_VEX_0F3841 */ |
| 4794 | { |
| 4795 | { Bad_Opcode }, |
| 4796 | { Bad_Opcode }, |
| 4797 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
| 4798 | }, |
| 4799 | |
| 4800 | /* PREFIX_VEX_0F3845 */ |
| 4801 | { |
| 4802 | { Bad_Opcode }, |
| 4803 | { Bad_Opcode }, |
| 4804 | { "vpsrlv%LW", { XM, Vex, EXx } }, |
| 4805 | }, |
| 4806 | |
| 4807 | /* PREFIX_VEX_0F3846 */ |
| 4808 | { |
| 4809 | { Bad_Opcode }, |
| 4810 | { Bad_Opcode }, |
| 4811 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, |
| 4812 | }, |
| 4813 | |
| 4814 | /* PREFIX_VEX_0F3847 */ |
| 4815 | { |
| 4816 | { Bad_Opcode }, |
| 4817 | { Bad_Opcode }, |
| 4818 | { "vpsllv%LW", { XM, Vex, EXx } }, |
| 4819 | }, |
| 4820 | |
| 4821 | /* PREFIX_VEX_0F3858 */ |
| 4822 | { |
| 4823 | { Bad_Opcode }, |
| 4824 | { Bad_Opcode }, |
| 4825 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, |
| 4826 | }, |
| 4827 | |
| 4828 | /* PREFIX_VEX_0F3859 */ |
| 4829 | { |
| 4830 | { Bad_Opcode }, |
| 4831 | { Bad_Opcode }, |
| 4832 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, |
| 4833 | }, |
| 4834 | |
| 4835 | /* PREFIX_VEX_0F385A */ |
| 4836 | { |
| 4837 | { Bad_Opcode }, |
| 4838 | { Bad_Opcode }, |
| 4839 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, |
| 4840 | }, |
| 4841 | |
| 4842 | /* PREFIX_VEX_0F3878 */ |
| 4843 | { |
| 4844 | { Bad_Opcode }, |
| 4845 | { Bad_Opcode }, |
| 4846 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, |
| 4847 | }, |
| 4848 | |
| 4849 | /* PREFIX_VEX_0F3879 */ |
| 4850 | { |
| 4851 | { Bad_Opcode }, |
| 4852 | { Bad_Opcode }, |
| 4853 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, |
| 4854 | }, |
| 4855 | |
| 4856 | /* PREFIX_VEX_0F388C */ |
| 4857 | { |
| 4858 | { Bad_Opcode }, |
| 4859 | { Bad_Opcode }, |
| 4860 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
| 4861 | }, |
| 4862 | |
| 4863 | /* PREFIX_VEX_0F388E */ |
| 4864 | { |
| 4865 | { Bad_Opcode }, |
| 4866 | { Bad_Opcode }, |
| 4867 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
| 4868 | }, |
| 4869 | |
| 4870 | /* PREFIX_VEX_0F3890 */ |
| 4871 | { |
| 4872 | { Bad_Opcode }, |
| 4873 | { Bad_Opcode }, |
| 4874 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, |
| 4875 | }, |
| 4876 | |
| 4877 | /* PREFIX_VEX_0F3891 */ |
| 4878 | { |
| 4879 | { Bad_Opcode }, |
| 4880 | { Bad_Opcode }, |
| 4881 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, |
| 4882 | }, |
| 4883 | |
| 4884 | /* PREFIX_VEX_0F3892 */ |
| 4885 | { |
| 4886 | { Bad_Opcode }, |
| 4887 | { Bad_Opcode }, |
| 4888 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, |
| 4889 | }, |
| 4890 | |
| 4891 | /* PREFIX_VEX_0F3893 */ |
| 4892 | { |
| 4893 | { Bad_Opcode }, |
| 4894 | { Bad_Opcode }, |
| 4895 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, |
| 4896 | }, |
| 4897 | |
| 4898 | /* PREFIX_VEX_0F3896 */ |
| 4899 | { |
| 4900 | { Bad_Opcode }, |
| 4901 | { Bad_Opcode }, |
| 4902 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
| 4903 | }, |
| 4904 | |
| 4905 | /* PREFIX_VEX_0F3897 */ |
| 4906 | { |
| 4907 | { Bad_Opcode }, |
| 4908 | { Bad_Opcode }, |
| 4909 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
| 4910 | }, |
| 4911 | |
| 4912 | /* PREFIX_VEX_0F3898 */ |
| 4913 | { |
| 4914 | { Bad_Opcode }, |
| 4915 | { Bad_Opcode }, |
| 4916 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
| 4917 | }, |
| 4918 | |
| 4919 | /* PREFIX_VEX_0F3899 */ |
| 4920 | { |
| 4921 | { Bad_Opcode }, |
| 4922 | { Bad_Opcode }, |
| 4923 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 4924 | }, |
| 4925 | |
| 4926 | /* PREFIX_VEX_0F389A */ |
| 4927 | { |
| 4928 | { Bad_Opcode }, |
| 4929 | { Bad_Opcode }, |
| 4930 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
| 4931 | }, |
| 4932 | |
| 4933 | /* PREFIX_VEX_0F389B */ |
| 4934 | { |
| 4935 | { Bad_Opcode }, |
| 4936 | { Bad_Opcode }, |
| 4937 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 4938 | }, |
| 4939 | |
| 4940 | /* PREFIX_VEX_0F389C */ |
| 4941 | { |
| 4942 | { Bad_Opcode }, |
| 4943 | { Bad_Opcode }, |
| 4944 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
| 4945 | }, |
| 4946 | |
| 4947 | /* PREFIX_VEX_0F389D */ |
| 4948 | { |
| 4949 | { Bad_Opcode }, |
| 4950 | { Bad_Opcode }, |
| 4951 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 4952 | }, |
| 4953 | |
| 4954 | /* PREFIX_VEX_0F389E */ |
| 4955 | { |
| 4956 | { Bad_Opcode }, |
| 4957 | { Bad_Opcode }, |
| 4958 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
| 4959 | }, |
| 4960 | |
| 4961 | /* PREFIX_VEX_0F389F */ |
| 4962 | { |
| 4963 | { Bad_Opcode }, |
| 4964 | { Bad_Opcode }, |
| 4965 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 4966 | }, |
| 4967 | |
| 4968 | /* PREFIX_VEX_0F38A6 */ |
| 4969 | { |
| 4970 | { Bad_Opcode }, |
| 4971 | { Bad_Opcode }, |
| 4972 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
| 4973 | { Bad_Opcode }, |
| 4974 | }, |
| 4975 | |
| 4976 | /* PREFIX_VEX_0F38A7 */ |
| 4977 | { |
| 4978 | { Bad_Opcode }, |
| 4979 | { Bad_Opcode }, |
| 4980 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
| 4981 | }, |
| 4982 | |
| 4983 | /* PREFIX_VEX_0F38A8 */ |
| 4984 | { |
| 4985 | { Bad_Opcode }, |
| 4986 | { Bad_Opcode }, |
| 4987 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
| 4988 | }, |
| 4989 | |
| 4990 | /* PREFIX_VEX_0F38A9 */ |
| 4991 | { |
| 4992 | { Bad_Opcode }, |
| 4993 | { Bad_Opcode }, |
| 4994 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 4995 | }, |
| 4996 | |
| 4997 | /* PREFIX_VEX_0F38AA */ |
| 4998 | { |
| 4999 | { Bad_Opcode }, |
| 5000 | { Bad_Opcode }, |
| 5001 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
| 5002 | }, |
| 5003 | |
| 5004 | /* PREFIX_VEX_0F38AB */ |
| 5005 | { |
| 5006 | { Bad_Opcode }, |
| 5007 | { Bad_Opcode }, |
| 5008 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5009 | }, |
| 5010 | |
| 5011 | /* PREFIX_VEX_0F38AC */ |
| 5012 | { |
| 5013 | { Bad_Opcode }, |
| 5014 | { Bad_Opcode }, |
| 5015 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
| 5016 | }, |
| 5017 | |
| 5018 | /* PREFIX_VEX_0F38AD */ |
| 5019 | { |
| 5020 | { Bad_Opcode }, |
| 5021 | { Bad_Opcode }, |
| 5022 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5023 | }, |
| 5024 | |
| 5025 | /* PREFIX_VEX_0F38AE */ |
| 5026 | { |
| 5027 | { Bad_Opcode }, |
| 5028 | { Bad_Opcode }, |
| 5029 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
| 5030 | }, |
| 5031 | |
| 5032 | /* PREFIX_VEX_0F38AF */ |
| 5033 | { |
| 5034 | { Bad_Opcode }, |
| 5035 | { Bad_Opcode }, |
| 5036 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5037 | }, |
| 5038 | |
| 5039 | /* PREFIX_VEX_0F38B6 */ |
| 5040 | { |
| 5041 | { Bad_Opcode }, |
| 5042 | { Bad_Opcode }, |
| 5043 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
| 5044 | }, |
| 5045 | |
| 5046 | /* PREFIX_VEX_0F38B7 */ |
| 5047 | { |
| 5048 | { Bad_Opcode }, |
| 5049 | { Bad_Opcode }, |
| 5050 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
| 5051 | }, |
| 5052 | |
| 5053 | /* PREFIX_VEX_0F38B8 */ |
| 5054 | { |
| 5055 | { Bad_Opcode }, |
| 5056 | { Bad_Opcode }, |
| 5057 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
| 5058 | }, |
| 5059 | |
| 5060 | /* PREFIX_VEX_0F38B9 */ |
| 5061 | { |
| 5062 | { Bad_Opcode }, |
| 5063 | { Bad_Opcode }, |
| 5064 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5065 | }, |
| 5066 | |
| 5067 | /* PREFIX_VEX_0F38BA */ |
| 5068 | { |
| 5069 | { Bad_Opcode }, |
| 5070 | { Bad_Opcode }, |
| 5071 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
| 5072 | }, |
| 5073 | |
| 5074 | /* PREFIX_VEX_0F38BB */ |
| 5075 | { |
| 5076 | { Bad_Opcode }, |
| 5077 | { Bad_Opcode }, |
| 5078 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5079 | }, |
| 5080 | |
| 5081 | /* PREFIX_VEX_0F38BC */ |
| 5082 | { |
| 5083 | { Bad_Opcode }, |
| 5084 | { Bad_Opcode }, |
| 5085 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
| 5086 | }, |
| 5087 | |
| 5088 | /* PREFIX_VEX_0F38BD */ |
| 5089 | { |
| 5090 | { Bad_Opcode }, |
| 5091 | { Bad_Opcode }, |
| 5092 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5093 | }, |
| 5094 | |
| 5095 | /* PREFIX_VEX_0F38BE */ |
| 5096 | { |
| 5097 | { Bad_Opcode }, |
| 5098 | { Bad_Opcode }, |
| 5099 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
| 5100 | }, |
| 5101 | |
| 5102 | /* PREFIX_VEX_0F38BF */ |
| 5103 | { |
| 5104 | { Bad_Opcode }, |
| 5105 | { Bad_Opcode }, |
| 5106 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
| 5107 | }, |
| 5108 | |
| 5109 | /* PREFIX_VEX_0F38DB */ |
| 5110 | { |
| 5111 | { Bad_Opcode }, |
| 5112 | { Bad_Opcode }, |
| 5113 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
| 5114 | }, |
| 5115 | |
| 5116 | /* PREFIX_VEX_0F38DC */ |
| 5117 | { |
| 5118 | { Bad_Opcode }, |
| 5119 | { Bad_Opcode }, |
| 5120 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
| 5121 | }, |
| 5122 | |
| 5123 | /* PREFIX_VEX_0F38DD */ |
| 5124 | { |
| 5125 | { Bad_Opcode }, |
| 5126 | { Bad_Opcode }, |
| 5127 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
| 5128 | }, |
| 5129 | |
| 5130 | /* PREFIX_VEX_0F38DE */ |
| 5131 | { |
| 5132 | { Bad_Opcode }, |
| 5133 | { Bad_Opcode }, |
| 5134 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
| 5135 | }, |
| 5136 | |
| 5137 | /* PREFIX_VEX_0F38DF */ |
| 5138 | { |
| 5139 | { Bad_Opcode }, |
| 5140 | { Bad_Opcode }, |
| 5141 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
| 5142 | }, |
| 5143 | |
| 5144 | /* PREFIX_VEX_0F38F2 */ |
| 5145 | { |
| 5146 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, |
| 5147 | }, |
| 5148 | |
| 5149 | /* PREFIX_VEX_0F38F3_REG_1 */ |
| 5150 | { |
| 5151 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, |
| 5152 | }, |
| 5153 | |
| 5154 | /* PREFIX_VEX_0F38F3_REG_2 */ |
| 5155 | { |
| 5156 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, |
| 5157 | }, |
| 5158 | |
| 5159 | /* PREFIX_VEX_0F38F3_REG_3 */ |
| 5160 | { |
| 5161 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, |
| 5162 | }, |
| 5163 | |
| 5164 | /* PREFIX_VEX_0F38F5 */ |
| 5165 | { |
| 5166 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
| 5167 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, |
| 5168 | { Bad_Opcode }, |
| 5169 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
| 5170 | }, |
| 5171 | |
| 5172 | /* PREFIX_VEX_0F38F6 */ |
| 5173 | { |
| 5174 | { Bad_Opcode }, |
| 5175 | { Bad_Opcode }, |
| 5176 | { Bad_Opcode }, |
| 5177 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, |
| 5178 | }, |
| 5179 | |
| 5180 | /* PREFIX_VEX_0F38F7 */ |
| 5181 | { |
| 5182 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
| 5183 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
| 5184 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, |
| 5185 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, |
| 5186 | }, |
| 5187 | |
| 5188 | /* PREFIX_VEX_0F3A00 */ |
| 5189 | { |
| 5190 | { Bad_Opcode }, |
| 5191 | { Bad_Opcode }, |
| 5192 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, |
| 5193 | }, |
| 5194 | |
| 5195 | /* PREFIX_VEX_0F3A01 */ |
| 5196 | { |
| 5197 | { Bad_Opcode }, |
| 5198 | { Bad_Opcode }, |
| 5199 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, |
| 5200 | }, |
| 5201 | |
| 5202 | /* PREFIX_VEX_0F3A02 */ |
| 5203 | { |
| 5204 | { Bad_Opcode }, |
| 5205 | { Bad_Opcode }, |
| 5206 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, |
| 5207 | }, |
| 5208 | |
| 5209 | /* PREFIX_VEX_0F3A04 */ |
| 5210 | { |
| 5211 | { Bad_Opcode }, |
| 5212 | { Bad_Opcode }, |
| 5213 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
| 5214 | }, |
| 5215 | |
| 5216 | /* PREFIX_VEX_0F3A05 */ |
| 5217 | { |
| 5218 | { Bad_Opcode }, |
| 5219 | { Bad_Opcode }, |
| 5220 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
| 5221 | }, |
| 5222 | |
| 5223 | /* PREFIX_VEX_0F3A06 */ |
| 5224 | { |
| 5225 | { Bad_Opcode }, |
| 5226 | { Bad_Opcode }, |
| 5227 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
| 5228 | }, |
| 5229 | |
| 5230 | /* PREFIX_VEX_0F3A08 */ |
| 5231 | { |
| 5232 | { Bad_Opcode }, |
| 5233 | { Bad_Opcode }, |
| 5234 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
| 5235 | }, |
| 5236 | |
| 5237 | /* PREFIX_VEX_0F3A09 */ |
| 5238 | { |
| 5239 | { Bad_Opcode }, |
| 5240 | { Bad_Opcode }, |
| 5241 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
| 5242 | }, |
| 5243 | |
| 5244 | /* PREFIX_VEX_0F3A0A */ |
| 5245 | { |
| 5246 | { Bad_Opcode }, |
| 5247 | { Bad_Opcode }, |
| 5248 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
| 5249 | }, |
| 5250 | |
| 5251 | /* PREFIX_VEX_0F3A0B */ |
| 5252 | { |
| 5253 | { Bad_Opcode }, |
| 5254 | { Bad_Opcode }, |
| 5255 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
| 5256 | }, |
| 5257 | |
| 5258 | /* PREFIX_VEX_0F3A0C */ |
| 5259 | { |
| 5260 | { Bad_Opcode }, |
| 5261 | { Bad_Opcode }, |
| 5262 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
| 5263 | }, |
| 5264 | |
| 5265 | /* PREFIX_VEX_0F3A0D */ |
| 5266 | { |
| 5267 | { Bad_Opcode }, |
| 5268 | { Bad_Opcode }, |
| 5269 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
| 5270 | }, |
| 5271 | |
| 5272 | /* PREFIX_VEX_0F3A0E */ |
| 5273 | { |
| 5274 | { Bad_Opcode }, |
| 5275 | { Bad_Opcode }, |
| 5276 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
| 5277 | }, |
| 5278 | |
| 5279 | /* PREFIX_VEX_0F3A0F */ |
| 5280 | { |
| 5281 | { Bad_Opcode }, |
| 5282 | { Bad_Opcode }, |
| 5283 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
| 5284 | }, |
| 5285 | |
| 5286 | /* PREFIX_VEX_0F3A14 */ |
| 5287 | { |
| 5288 | { Bad_Opcode }, |
| 5289 | { Bad_Opcode }, |
| 5290 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
| 5291 | }, |
| 5292 | |
| 5293 | /* PREFIX_VEX_0F3A15 */ |
| 5294 | { |
| 5295 | { Bad_Opcode }, |
| 5296 | { Bad_Opcode }, |
| 5297 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
| 5298 | }, |
| 5299 | |
| 5300 | /* PREFIX_VEX_0F3A16 */ |
| 5301 | { |
| 5302 | { Bad_Opcode }, |
| 5303 | { Bad_Opcode }, |
| 5304 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
| 5305 | }, |
| 5306 | |
| 5307 | /* PREFIX_VEX_0F3A17 */ |
| 5308 | { |
| 5309 | { Bad_Opcode }, |
| 5310 | { Bad_Opcode }, |
| 5311 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
| 5312 | }, |
| 5313 | |
| 5314 | /* PREFIX_VEX_0F3A18 */ |
| 5315 | { |
| 5316 | { Bad_Opcode }, |
| 5317 | { Bad_Opcode }, |
| 5318 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
| 5319 | }, |
| 5320 | |
| 5321 | /* PREFIX_VEX_0F3A19 */ |
| 5322 | { |
| 5323 | { Bad_Opcode }, |
| 5324 | { Bad_Opcode }, |
| 5325 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
| 5326 | }, |
| 5327 | |
| 5328 | /* PREFIX_VEX_0F3A1D */ |
| 5329 | { |
| 5330 | { Bad_Opcode }, |
| 5331 | { Bad_Opcode }, |
| 5332 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, |
| 5333 | }, |
| 5334 | |
| 5335 | /* PREFIX_VEX_0F3A20 */ |
| 5336 | { |
| 5337 | { Bad_Opcode }, |
| 5338 | { Bad_Opcode }, |
| 5339 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
| 5340 | }, |
| 5341 | |
| 5342 | /* PREFIX_VEX_0F3A21 */ |
| 5343 | { |
| 5344 | { Bad_Opcode }, |
| 5345 | { Bad_Opcode }, |
| 5346 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
| 5347 | }, |
| 5348 | |
| 5349 | /* PREFIX_VEX_0F3A22 */ |
| 5350 | { |
| 5351 | { Bad_Opcode }, |
| 5352 | { Bad_Opcode }, |
| 5353 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
| 5354 | }, |
| 5355 | |
| 5356 | /* PREFIX_VEX_0F3A38 */ |
| 5357 | { |
| 5358 | { Bad_Opcode }, |
| 5359 | { Bad_Opcode }, |
| 5360 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, |
| 5361 | }, |
| 5362 | |
| 5363 | /* PREFIX_VEX_0F3A39 */ |
| 5364 | { |
| 5365 | { Bad_Opcode }, |
| 5366 | { Bad_Opcode }, |
| 5367 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, |
| 5368 | }, |
| 5369 | |
| 5370 | /* PREFIX_VEX_0F3A40 */ |
| 5371 | { |
| 5372 | { Bad_Opcode }, |
| 5373 | { Bad_Opcode }, |
| 5374 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
| 5375 | }, |
| 5376 | |
| 5377 | /* PREFIX_VEX_0F3A41 */ |
| 5378 | { |
| 5379 | { Bad_Opcode }, |
| 5380 | { Bad_Opcode }, |
| 5381 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
| 5382 | }, |
| 5383 | |
| 5384 | /* PREFIX_VEX_0F3A42 */ |
| 5385 | { |
| 5386 | { Bad_Opcode }, |
| 5387 | { Bad_Opcode }, |
| 5388 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
| 5389 | }, |
| 5390 | |
| 5391 | /* PREFIX_VEX_0F3A44 */ |
| 5392 | { |
| 5393 | { Bad_Opcode }, |
| 5394 | { Bad_Opcode }, |
| 5395 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
| 5396 | }, |
| 5397 | |
| 5398 | /* PREFIX_VEX_0F3A46 */ |
| 5399 | { |
| 5400 | { Bad_Opcode }, |
| 5401 | { Bad_Opcode }, |
| 5402 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, |
| 5403 | }, |
| 5404 | |
| 5405 | /* PREFIX_VEX_0F3A48 */ |
| 5406 | { |
| 5407 | { Bad_Opcode }, |
| 5408 | { Bad_Opcode }, |
| 5409 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
| 5410 | }, |
| 5411 | |
| 5412 | /* PREFIX_VEX_0F3A49 */ |
| 5413 | { |
| 5414 | { Bad_Opcode }, |
| 5415 | { Bad_Opcode }, |
| 5416 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
| 5417 | }, |
| 5418 | |
| 5419 | /* PREFIX_VEX_0F3A4A */ |
| 5420 | { |
| 5421 | { Bad_Opcode }, |
| 5422 | { Bad_Opcode }, |
| 5423 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
| 5424 | }, |
| 5425 | |
| 5426 | /* PREFIX_VEX_0F3A4B */ |
| 5427 | { |
| 5428 | { Bad_Opcode }, |
| 5429 | { Bad_Opcode }, |
| 5430 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
| 5431 | }, |
| 5432 | |
| 5433 | /* PREFIX_VEX_0F3A4C */ |
| 5434 | { |
| 5435 | { Bad_Opcode }, |
| 5436 | { Bad_Opcode }, |
| 5437 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
| 5438 | }, |
| 5439 | |
| 5440 | /* PREFIX_VEX_0F3A5C */ |
| 5441 | { |
| 5442 | { Bad_Opcode }, |
| 5443 | { Bad_Opcode }, |
| 5444 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5445 | }, |
| 5446 | |
| 5447 | /* PREFIX_VEX_0F3A5D */ |
| 5448 | { |
| 5449 | { Bad_Opcode }, |
| 5450 | { Bad_Opcode }, |
| 5451 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5452 | }, |
| 5453 | |
| 5454 | /* PREFIX_VEX_0F3A5E */ |
| 5455 | { |
| 5456 | { Bad_Opcode }, |
| 5457 | { Bad_Opcode }, |
| 5458 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5459 | }, |
| 5460 | |
| 5461 | /* PREFIX_VEX_0F3A5F */ |
| 5462 | { |
| 5463 | { Bad_Opcode }, |
| 5464 | { Bad_Opcode }, |
| 5465 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5466 | }, |
| 5467 | |
| 5468 | /* PREFIX_VEX_0F3A60 */ |
| 5469 | { |
| 5470 | { Bad_Opcode }, |
| 5471 | { Bad_Opcode }, |
| 5472 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
| 5473 | { Bad_Opcode }, |
| 5474 | }, |
| 5475 | |
| 5476 | /* PREFIX_VEX_0F3A61 */ |
| 5477 | { |
| 5478 | { Bad_Opcode }, |
| 5479 | { Bad_Opcode }, |
| 5480 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
| 5481 | }, |
| 5482 | |
| 5483 | /* PREFIX_VEX_0F3A62 */ |
| 5484 | { |
| 5485 | { Bad_Opcode }, |
| 5486 | { Bad_Opcode }, |
| 5487 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
| 5488 | }, |
| 5489 | |
| 5490 | /* PREFIX_VEX_0F3A63 */ |
| 5491 | { |
| 5492 | { Bad_Opcode }, |
| 5493 | { Bad_Opcode }, |
| 5494 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
| 5495 | }, |
| 5496 | |
| 5497 | /* PREFIX_VEX_0F3A68 */ |
| 5498 | { |
| 5499 | { Bad_Opcode }, |
| 5500 | { Bad_Opcode }, |
| 5501 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5502 | }, |
| 5503 | |
| 5504 | /* PREFIX_VEX_0F3A69 */ |
| 5505 | { |
| 5506 | { Bad_Opcode }, |
| 5507 | { Bad_Opcode }, |
| 5508 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5509 | }, |
| 5510 | |
| 5511 | /* PREFIX_VEX_0F3A6A */ |
| 5512 | { |
| 5513 | { Bad_Opcode }, |
| 5514 | { Bad_Opcode }, |
| 5515 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
| 5516 | }, |
| 5517 | |
| 5518 | /* PREFIX_VEX_0F3A6B */ |
| 5519 | { |
| 5520 | { Bad_Opcode }, |
| 5521 | { Bad_Opcode }, |
| 5522 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
| 5523 | }, |
| 5524 | |
| 5525 | /* PREFIX_VEX_0F3A6C */ |
| 5526 | { |
| 5527 | { Bad_Opcode }, |
| 5528 | { Bad_Opcode }, |
| 5529 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5530 | }, |
| 5531 | |
| 5532 | /* PREFIX_VEX_0F3A6D */ |
| 5533 | { |
| 5534 | { Bad_Opcode }, |
| 5535 | { Bad_Opcode }, |
| 5536 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5537 | }, |
| 5538 | |
| 5539 | /* PREFIX_VEX_0F3A6E */ |
| 5540 | { |
| 5541 | { Bad_Opcode }, |
| 5542 | { Bad_Opcode }, |
| 5543 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
| 5544 | }, |
| 5545 | |
| 5546 | /* PREFIX_VEX_0F3A6F */ |
| 5547 | { |
| 5548 | { Bad_Opcode }, |
| 5549 | { Bad_Opcode }, |
| 5550 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
| 5551 | }, |
| 5552 | |
| 5553 | /* PREFIX_VEX_0F3A78 */ |
| 5554 | { |
| 5555 | { Bad_Opcode }, |
| 5556 | { Bad_Opcode }, |
| 5557 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5558 | }, |
| 5559 | |
| 5560 | /* PREFIX_VEX_0F3A79 */ |
| 5561 | { |
| 5562 | { Bad_Opcode }, |
| 5563 | { Bad_Opcode }, |
| 5564 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5565 | }, |
| 5566 | |
| 5567 | /* PREFIX_VEX_0F3A7A */ |
| 5568 | { |
| 5569 | { Bad_Opcode }, |
| 5570 | { Bad_Opcode }, |
| 5571 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
| 5572 | }, |
| 5573 | |
| 5574 | /* PREFIX_VEX_0F3A7B */ |
| 5575 | { |
| 5576 | { Bad_Opcode }, |
| 5577 | { Bad_Opcode }, |
| 5578 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
| 5579 | }, |
| 5580 | |
| 5581 | /* PREFIX_VEX_0F3A7C */ |
| 5582 | { |
| 5583 | { Bad_Opcode }, |
| 5584 | { Bad_Opcode }, |
| 5585 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5586 | { Bad_Opcode }, |
| 5587 | }, |
| 5588 | |
| 5589 | /* PREFIX_VEX_0F3A7D */ |
| 5590 | { |
| 5591 | { Bad_Opcode }, |
| 5592 | { Bad_Opcode }, |
| 5593 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 5594 | }, |
| 5595 | |
| 5596 | /* PREFIX_VEX_0F3A7E */ |
| 5597 | { |
| 5598 | { Bad_Opcode }, |
| 5599 | { Bad_Opcode }, |
| 5600 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
| 5601 | }, |
| 5602 | |
| 5603 | /* PREFIX_VEX_0F3A7F */ |
| 5604 | { |
| 5605 | { Bad_Opcode }, |
| 5606 | { Bad_Opcode }, |
| 5607 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
| 5608 | }, |
| 5609 | |
| 5610 | /* PREFIX_VEX_0F3ADF */ |
| 5611 | { |
| 5612 | { Bad_Opcode }, |
| 5613 | { Bad_Opcode }, |
| 5614 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
| 5615 | }, |
| 5616 | |
| 5617 | /* PREFIX_VEX_0F3AF0 */ |
| 5618 | { |
| 5619 | { Bad_Opcode }, |
| 5620 | { Bad_Opcode }, |
| 5621 | { Bad_Opcode }, |
| 5622 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, |
| 5623 | }, |
| 5624 | }; |
| 5625 | |
| 5626 | static const struct dis386 x86_64_table[][2] = { |
| 5627 | /* X86_64_06 */ |
| 5628 | { |
| 5629 | { "pushP", { es } }, |
| 5630 | }, |
| 5631 | |
| 5632 | /* X86_64_07 */ |
| 5633 | { |
| 5634 | { "popP", { es } }, |
| 5635 | }, |
| 5636 | |
| 5637 | /* X86_64_0D */ |
| 5638 | { |
| 5639 | { "pushP", { cs } }, |
| 5640 | }, |
| 5641 | |
| 5642 | /* X86_64_16 */ |
| 5643 | { |
| 5644 | { "pushP", { ss } }, |
| 5645 | }, |
| 5646 | |
| 5647 | /* X86_64_17 */ |
| 5648 | { |
| 5649 | { "popP", { ss } }, |
| 5650 | }, |
| 5651 | |
| 5652 | /* X86_64_1E */ |
| 5653 | { |
| 5654 | { "pushP", { ds } }, |
| 5655 | }, |
| 5656 | |
| 5657 | /* X86_64_1F */ |
| 5658 | { |
| 5659 | { "popP", { ds } }, |
| 5660 | }, |
| 5661 | |
| 5662 | /* X86_64_27 */ |
| 5663 | { |
| 5664 | { "daa", { XX } }, |
| 5665 | }, |
| 5666 | |
| 5667 | /* X86_64_2F */ |
| 5668 | { |
| 5669 | { "das", { XX } }, |
| 5670 | }, |
| 5671 | |
| 5672 | /* X86_64_37 */ |
| 5673 | { |
| 5674 | { "aaa", { XX } }, |
| 5675 | }, |
| 5676 | |
| 5677 | /* X86_64_3F */ |
| 5678 | { |
| 5679 | { "aas", { XX } }, |
| 5680 | }, |
| 5681 | |
| 5682 | /* X86_64_60 */ |
| 5683 | { |
| 5684 | { "pushaP", { XX } }, |
| 5685 | }, |
| 5686 | |
| 5687 | /* X86_64_61 */ |
| 5688 | { |
| 5689 | { "popaP", { XX } }, |
| 5690 | }, |
| 5691 | |
| 5692 | /* X86_64_62 */ |
| 5693 | { |
| 5694 | { MOD_TABLE (MOD_62_32BIT) }, |
| 5695 | }, |
| 5696 | |
| 5697 | /* X86_64_63 */ |
| 5698 | { |
| 5699 | { "arpl", { Ew, Gw } }, |
| 5700 | { "movs{lq|xd}", { Gv, Ed } }, |
| 5701 | }, |
| 5702 | |
| 5703 | /* X86_64_6D */ |
| 5704 | { |
| 5705 | { "ins{R|}", { Yzr, indirDX } }, |
| 5706 | { "ins{G|}", { Yzr, indirDX } }, |
| 5707 | }, |
| 5708 | |
| 5709 | /* X86_64_6F */ |
| 5710 | { |
| 5711 | { "outs{R|}", { indirDXr, Xz } }, |
| 5712 | { "outs{G|}", { indirDXr, Xz } }, |
| 5713 | }, |
| 5714 | |
| 5715 | /* X86_64_9A */ |
| 5716 | { |
| 5717 | { "Jcall{T|}", { Ap } }, |
| 5718 | }, |
| 5719 | |
| 5720 | /* X86_64_C4 */ |
| 5721 | { |
| 5722 | { MOD_TABLE (MOD_C4_32BIT) }, |
| 5723 | { VEX_C4_TABLE (VEX_0F) }, |
| 5724 | }, |
| 5725 | |
| 5726 | /* X86_64_C5 */ |
| 5727 | { |
| 5728 | { MOD_TABLE (MOD_C5_32BIT) }, |
| 5729 | { VEX_C5_TABLE (VEX_0F) }, |
| 5730 | }, |
| 5731 | |
| 5732 | /* X86_64_CE */ |
| 5733 | { |
| 5734 | { "into", { XX } }, |
| 5735 | }, |
| 5736 | |
| 5737 | /* X86_64_D4 */ |
| 5738 | { |
| 5739 | { "aam", { Ib } }, |
| 5740 | }, |
| 5741 | |
| 5742 | /* X86_64_D5 */ |
| 5743 | { |
| 5744 | { "aad", { Ib } }, |
| 5745 | }, |
| 5746 | |
| 5747 | /* X86_64_EA */ |
| 5748 | { |
| 5749 | { "Jjmp{T|}", { Ap } }, |
| 5750 | }, |
| 5751 | |
| 5752 | /* X86_64_0F01_REG_0 */ |
| 5753 | { |
| 5754 | { "sgdt{Q|IQ}", { M } }, |
| 5755 | { "sgdt", { M } }, |
| 5756 | }, |
| 5757 | |
| 5758 | /* X86_64_0F01_REG_1 */ |
| 5759 | { |
| 5760 | { "sidt{Q|IQ}", { M } }, |
| 5761 | { "sidt", { M } }, |
| 5762 | }, |
| 5763 | |
| 5764 | /* X86_64_0F01_REG_2 */ |
| 5765 | { |
| 5766 | { "lgdt{Q|Q}", { M } }, |
| 5767 | { "lgdt", { M } }, |
| 5768 | }, |
| 5769 | |
| 5770 | /* X86_64_0F01_REG_3 */ |
| 5771 | { |
| 5772 | { "lidt{Q|Q}", { M } }, |
| 5773 | { "lidt", { M } }, |
| 5774 | }, |
| 5775 | }; |
| 5776 | |
| 5777 | static const struct dis386 three_byte_table[][256] = { |
| 5778 | |
| 5779 | /* THREE_BYTE_0F38 */ |
| 5780 | { |
| 5781 | /* 00 */ |
| 5782 | { "pshufb", { MX, EM } }, |
| 5783 | { "phaddw", { MX, EM } }, |
| 5784 | { "phaddd", { MX, EM } }, |
| 5785 | { "phaddsw", { MX, EM } }, |
| 5786 | { "pmaddubsw", { MX, EM } }, |
| 5787 | { "phsubw", { MX, EM } }, |
| 5788 | { "phsubd", { MX, EM } }, |
| 5789 | { "phsubsw", { MX, EM } }, |
| 5790 | /* 08 */ |
| 5791 | { "psignb", { MX, EM } }, |
| 5792 | { "psignw", { MX, EM } }, |
| 5793 | { "psignd", { MX, EM } }, |
| 5794 | { "pmulhrsw", { MX, EM } }, |
| 5795 | { Bad_Opcode }, |
| 5796 | { Bad_Opcode }, |
| 5797 | { Bad_Opcode }, |
| 5798 | { Bad_Opcode }, |
| 5799 | /* 10 */ |
| 5800 | { PREFIX_TABLE (PREFIX_0F3810) }, |
| 5801 | { Bad_Opcode }, |
| 5802 | { Bad_Opcode }, |
| 5803 | { Bad_Opcode }, |
| 5804 | { PREFIX_TABLE (PREFIX_0F3814) }, |
| 5805 | { PREFIX_TABLE (PREFIX_0F3815) }, |
| 5806 | { Bad_Opcode }, |
| 5807 | { PREFIX_TABLE (PREFIX_0F3817) }, |
| 5808 | /* 18 */ |
| 5809 | { Bad_Opcode }, |
| 5810 | { Bad_Opcode }, |
| 5811 | { Bad_Opcode }, |
| 5812 | { Bad_Opcode }, |
| 5813 | { "pabsb", { MX, EM } }, |
| 5814 | { "pabsw", { MX, EM } }, |
| 5815 | { "pabsd", { MX, EM } }, |
| 5816 | { Bad_Opcode }, |
| 5817 | /* 20 */ |
| 5818 | { PREFIX_TABLE (PREFIX_0F3820) }, |
| 5819 | { PREFIX_TABLE (PREFIX_0F3821) }, |
| 5820 | { PREFIX_TABLE (PREFIX_0F3822) }, |
| 5821 | { PREFIX_TABLE (PREFIX_0F3823) }, |
| 5822 | { PREFIX_TABLE (PREFIX_0F3824) }, |
| 5823 | { PREFIX_TABLE (PREFIX_0F3825) }, |
| 5824 | { Bad_Opcode }, |
| 5825 | { Bad_Opcode }, |
| 5826 | /* 28 */ |
| 5827 | { PREFIX_TABLE (PREFIX_0F3828) }, |
| 5828 | { PREFIX_TABLE (PREFIX_0F3829) }, |
| 5829 | { PREFIX_TABLE (PREFIX_0F382A) }, |
| 5830 | { PREFIX_TABLE (PREFIX_0F382B) }, |
| 5831 | { Bad_Opcode }, |
| 5832 | { Bad_Opcode }, |
| 5833 | { Bad_Opcode }, |
| 5834 | { Bad_Opcode }, |
| 5835 | /* 30 */ |
| 5836 | { PREFIX_TABLE (PREFIX_0F3830) }, |
| 5837 | { PREFIX_TABLE (PREFIX_0F3831) }, |
| 5838 | { PREFIX_TABLE (PREFIX_0F3832) }, |
| 5839 | { PREFIX_TABLE (PREFIX_0F3833) }, |
| 5840 | { PREFIX_TABLE (PREFIX_0F3834) }, |
| 5841 | { PREFIX_TABLE (PREFIX_0F3835) }, |
| 5842 | { Bad_Opcode }, |
| 5843 | { PREFIX_TABLE (PREFIX_0F3837) }, |
| 5844 | /* 38 */ |
| 5845 | { PREFIX_TABLE (PREFIX_0F3838) }, |
| 5846 | { PREFIX_TABLE (PREFIX_0F3839) }, |
| 5847 | { PREFIX_TABLE (PREFIX_0F383A) }, |
| 5848 | { PREFIX_TABLE (PREFIX_0F383B) }, |
| 5849 | { PREFIX_TABLE (PREFIX_0F383C) }, |
| 5850 | { PREFIX_TABLE (PREFIX_0F383D) }, |
| 5851 | { PREFIX_TABLE (PREFIX_0F383E) }, |
| 5852 | { PREFIX_TABLE (PREFIX_0F383F) }, |
| 5853 | /* 40 */ |
| 5854 | { PREFIX_TABLE (PREFIX_0F3840) }, |
| 5855 | { PREFIX_TABLE (PREFIX_0F3841) }, |
| 5856 | { Bad_Opcode }, |
| 5857 | { Bad_Opcode }, |
| 5858 | { Bad_Opcode }, |
| 5859 | { Bad_Opcode }, |
| 5860 | { Bad_Opcode }, |
| 5861 | { Bad_Opcode }, |
| 5862 | /* 48 */ |
| 5863 | { Bad_Opcode }, |
| 5864 | { Bad_Opcode }, |
| 5865 | { Bad_Opcode }, |
| 5866 | { Bad_Opcode }, |
| 5867 | { Bad_Opcode }, |
| 5868 | { Bad_Opcode }, |
| 5869 | { Bad_Opcode }, |
| 5870 | { Bad_Opcode }, |
| 5871 | /* 50 */ |
| 5872 | { Bad_Opcode }, |
| 5873 | { Bad_Opcode }, |
| 5874 | { Bad_Opcode }, |
| 5875 | { Bad_Opcode }, |
| 5876 | { Bad_Opcode }, |
| 5877 | { Bad_Opcode }, |
| 5878 | { Bad_Opcode }, |
| 5879 | { Bad_Opcode }, |
| 5880 | /* 58 */ |
| 5881 | { Bad_Opcode }, |
| 5882 | { Bad_Opcode }, |
| 5883 | { Bad_Opcode }, |
| 5884 | { Bad_Opcode }, |
| 5885 | { Bad_Opcode }, |
| 5886 | { Bad_Opcode }, |
| 5887 | { Bad_Opcode }, |
| 5888 | { Bad_Opcode }, |
| 5889 | /* 60 */ |
| 5890 | { Bad_Opcode }, |
| 5891 | { Bad_Opcode }, |
| 5892 | { Bad_Opcode }, |
| 5893 | { Bad_Opcode }, |
| 5894 | { Bad_Opcode }, |
| 5895 | { Bad_Opcode }, |
| 5896 | { Bad_Opcode }, |
| 5897 | { Bad_Opcode }, |
| 5898 | /* 68 */ |
| 5899 | { Bad_Opcode }, |
| 5900 | { Bad_Opcode }, |
| 5901 | { Bad_Opcode }, |
| 5902 | { Bad_Opcode }, |
| 5903 | { Bad_Opcode }, |
| 5904 | { Bad_Opcode }, |
| 5905 | { Bad_Opcode }, |
| 5906 | { Bad_Opcode }, |
| 5907 | /* 70 */ |
| 5908 | { Bad_Opcode }, |
| 5909 | { Bad_Opcode }, |
| 5910 | { Bad_Opcode }, |
| 5911 | { Bad_Opcode }, |
| 5912 | { Bad_Opcode }, |
| 5913 | { Bad_Opcode }, |
| 5914 | { Bad_Opcode }, |
| 5915 | { Bad_Opcode }, |
| 5916 | /* 78 */ |
| 5917 | { Bad_Opcode }, |
| 5918 | { Bad_Opcode }, |
| 5919 | { Bad_Opcode }, |
| 5920 | { Bad_Opcode }, |
| 5921 | { Bad_Opcode }, |
| 5922 | { Bad_Opcode }, |
| 5923 | { Bad_Opcode }, |
| 5924 | { Bad_Opcode }, |
| 5925 | /* 80 */ |
| 5926 | { PREFIX_TABLE (PREFIX_0F3880) }, |
| 5927 | { PREFIX_TABLE (PREFIX_0F3881) }, |
| 5928 | { PREFIX_TABLE (PREFIX_0F3882) }, |
| 5929 | { Bad_Opcode }, |
| 5930 | { Bad_Opcode }, |
| 5931 | { Bad_Opcode }, |
| 5932 | { Bad_Opcode }, |
| 5933 | { Bad_Opcode }, |
| 5934 | /* 88 */ |
| 5935 | { Bad_Opcode }, |
| 5936 | { Bad_Opcode }, |
| 5937 | { Bad_Opcode }, |
| 5938 | { Bad_Opcode }, |
| 5939 | { Bad_Opcode }, |
| 5940 | { Bad_Opcode }, |
| 5941 | { Bad_Opcode }, |
| 5942 | { Bad_Opcode }, |
| 5943 | /* 90 */ |
| 5944 | { Bad_Opcode }, |
| 5945 | { Bad_Opcode }, |
| 5946 | { Bad_Opcode }, |
| 5947 | { Bad_Opcode }, |
| 5948 | { Bad_Opcode }, |
| 5949 | { Bad_Opcode }, |
| 5950 | { Bad_Opcode }, |
| 5951 | { Bad_Opcode }, |
| 5952 | /* 98 */ |
| 5953 | { Bad_Opcode }, |
| 5954 | { Bad_Opcode }, |
| 5955 | { Bad_Opcode }, |
| 5956 | { Bad_Opcode }, |
| 5957 | { Bad_Opcode }, |
| 5958 | { Bad_Opcode }, |
| 5959 | { Bad_Opcode }, |
| 5960 | { Bad_Opcode }, |
| 5961 | /* a0 */ |
| 5962 | { Bad_Opcode }, |
| 5963 | { Bad_Opcode }, |
| 5964 | { Bad_Opcode }, |
| 5965 | { Bad_Opcode }, |
| 5966 | { Bad_Opcode }, |
| 5967 | { Bad_Opcode }, |
| 5968 | { Bad_Opcode }, |
| 5969 | { Bad_Opcode }, |
| 5970 | /* a8 */ |
| 5971 | { Bad_Opcode }, |
| 5972 | { Bad_Opcode }, |
| 5973 | { Bad_Opcode }, |
| 5974 | { Bad_Opcode }, |
| 5975 | { Bad_Opcode }, |
| 5976 | { Bad_Opcode }, |
| 5977 | { Bad_Opcode }, |
| 5978 | { Bad_Opcode }, |
| 5979 | /* b0 */ |
| 5980 | { Bad_Opcode }, |
| 5981 | { Bad_Opcode }, |
| 5982 | { Bad_Opcode }, |
| 5983 | { Bad_Opcode }, |
| 5984 | { Bad_Opcode }, |
| 5985 | { Bad_Opcode }, |
| 5986 | { Bad_Opcode }, |
| 5987 | { Bad_Opcode }, |
| 5988 | /* b8 */ |
| 5989 | { Bad_Opcode }, |
| 5990 | { Bad_Opcode }, |
| 5991 | { Bad_Opcode }, |
| 5992 | { Bad_Opcode }, |
| 5993 | { Bad_Opcode }, |
| 5994 | { Bad_Opcode }, |
| 5995 | { Bad_Opcode }, |
| 5996 | { Bad_Opcode }, |
| 5997 | /* c0 */ |
| 5998 | { Bad_Opcode }, |
| 5999 | { Bad_Opcode }, |
| 6000 | { Bad_Opcode }, |
| 6001 | { Bad_Opcode }, |
| 6002 | { Bad_Opcode }, |
| 6003 | { Bad_Opcode }, |
| 6004 | { Bad_Opcode }, |
| 6005 | { Bad_Opcode }, |
| 6006 | /* c8 */ |
| 6007 | { Bad_Opcode }, |
| 6008 | { Bad_Opcode }, |
| 6009 | { Bad_Opcode }, |
| 6010 | { Bad_Opcode }, |
| 6011 | { Bad_Opcode }, |
| 6012 | { Bad_Opcode }, |
| 6013 | { Bad_Opcode }, |
| 6014 | { Bad_Opcode }, |
| 6015 | /* d0 */ |
| 6016 | { Bad_Opcode }, |
| 6017 | { Bad_Opcode }, |
| 6018 | { Bad_Opcode }, |
| 6019 | { Bad_Opcode }, |
| 6020 | { Bad_Opcode }, |
| 6021 | { Bad_Opcode }, |
| 6022 | { Bad_Opcode }, |
| 6023 | { Bad_Opcode }, |
| 6024 | /* d8 */ |
| 6025 | { Bad_Opcode }, |
| 6026 | { Bad_Opcode }, |
| 6027 | { Bad_Opcode }, |
| 6028 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
| 6029 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
| 6030 | { PREFIX_TABLE (PREFIX_0F38DD) }, |
| 6031 | { PREFIX_TABLE (PREFIX_0F38DE) }, |
| 6032 | { PREFIX_TABLE (PREFIX_0F38DF) }, |
| 6033 | /* e0 */ |
| 6034 | { Bad_Opcode }, |
| 6035 | { Bad_Opcode }, |
| 6036 | { Bad_Opcode }, |
| 6037 | { Bad_Opcode }, |
| 6038 | { Bad_Opcode }, |
| 6039 | { Bad_Opcode }, |
| 6040 | { Bad_Opcode }, |
| 6041 | { Bad_Opcode }, |
| 6042 | /* e8 */ |
| 6043 | { Bad_Opcode }, |
| 6044 | { Bad_Opcode }, |
| 6045 | { Bad_Opcode }, |
| 6046 | { Bad_Opcode }, |
| 6047 | { Bad_Opcode }, |
| 6048 | { Bad_Opcode }, |
| 6049 | { Bad_Opcode }, |
| 6050 | { Bad_Opcode }, |
| 6051 | /* f0 */ |
| 6052 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
| 6053 | { PREFIX_TABLE (PREFIX_0F38F1) }, |
| 6054 | { Bad_Opcode }, |
| 6055 | { Bad_Opcode }, |
| 6056 | { Bad_Opcode }, |
| 6057 | { Bad_Opcode }, |
| 6058 | { Bad_Opcode }, |
| 6059 | { Bad_Opcode }, |
| 6060 | /* f8 */ |
| 6061 | { Bad_Opcode }, |
| 6062 | { Bad_Opcode }, |
| 6063 | { Bad_Opcode }, |
| 6064 | { Bad_Opcode }, |
| 6065 | { Bad_Opcode }, |
| 6066 | { Bad_Opcode }, |
| 6067 | { Bad_Opcode }, |
| 6068 | { Bad_Opcode }, |
| 6069 | }, |
| 6070 | /* THREE_BYTE_0F3A */ |
| 6071 | { |
| 6072 | /* 00 */ |
| 6073 | { Bad_Opcode }, |
| 6074 | { Bad_Opcode }, |
| 6075 | { Bad_Opcode }, |
| 6076 | { Bad_Opcode }, |
| 6077 | { Bad_Opcode }, |
| 6078 | { Bad_Opcode }, |
| 6079 | { Bad_Opcode }, |
| 6080 | { Bad_Opcode }, |
| 6081 | /* 08 */ |
| 6082 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
| 6083 | { PREFIX_TABLE (PREFIX_0F3A09) }, |
| 6084 | { PREFIX_TABLE (PREFIX_0F3A0A) }, |
| 6085 | { PREFIX_TABLE (PREFIX_0F3A0B) }, |
| 6086 | { PREFIX_TABLE (PREFIX_0F3A0C) }, |
| 6087 | { PREFIX_TABLE (PREFIX_0F3A0D) }, |
| 6088 | { PREFIX_TABLE (PREFIX_0F3A0E) }, |
| 6089 | { "palignr", { MX, EM, Ib } }, |
| 6090 | /* 10 */ |
| 6091 | { Bad_Opcode }, |
| 6092 | { Bad_Opcode }, |
| 6093 | { Bad_Opcode }, |
| 6094 | { Bad_Opcode }, |
| 6095 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
| 6096 | { PREFIX_TABLE (PREFIX_0F3A15) }, |
| 6097 | { PREFIX_TABLE (PREFIX_0F3A16) }, |
| 6098 | { PREFIX_TABLE (PREFIX_0F3A17) }, |
| 6099 | /* 18 */ |
| 6100 | { Bad_Opcode }, |
| 6101 | { Bad_Opcode }, |
| 6102 | { Bad_Opcode }, |
| 6103 | { Bad_Opcode }, |
| 6104 | { Bad_Opcode }, |
| 6105 | { Bad_Opcode }, |
| 6106 | { Bad_Opcode }, |
| 6107 | { Bad_Opcode }, |
| 6108 | /* 20 */ |
| 6109 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
| 6110 | { PREFIX_TABLE (PREFIX_0F3A21) }, |
| 6111 | { PREFIX_TABLE (PREFIX_0F3A22) }, |
| 6112 | { Bad_Opcode }, |
| 6113 | { Bad_Opcode }, |
| 6114 | { Bad_Opcode }, |
| 6115 | { Bad_Opcode }, |
| 6116 | { Bad_Opcode }, |
| 6117 | /* 28 */ |
| 6118 | { Bad_Opcode }, |
| 6119 | { Bad_Opcode }, |
| 6120 | { Bad_Opcode }, |
| 6121 | { Bad_Opcode }, |
| 6122 | { Bad_Opcode }, |
| 6123 | { Bad_Opcode }, |
| 6124 | { Bad_Opcode }, |
| 6125 | { Bad_Opcode }, |
| 6126 | /* 30 */ |
| 6127 | { Bad_Opcode }, |
| 6128 | { Bad_Opcode }, |
| 6129 | { Bad_Opcode }, |
| 6130 | { Bad_Opcode }, |
| 6131 | { Bad_Opcode }, |
| 6132 | { Bad_Opcode }, |
| 6133 | { Bad_Opcode }, |
| 6134 | { Bad_Opcode }, |
| 6135 | /* 38 */ |
| 6136 | { Bad_Opcode }, |
| 6137 | { Bad_Opcode }, |
| 6138 | { Bad_Opcode }, |
| 6139 | { Bad_Opcode }, |
| 6140 | { Bad_Opcode }, |
| 6141 | { Bad_Opcode }, |
| 6142 | { Bad_Opcode }, |
| 6143 | { Bad_Opcode }, |
| 6144 | /* 40 */ |
| 6145 | { PREFIX_TABLE (PREFIX_0F3A40) }, |
| 6146 | { PREFIX_TABLE (PREFIX_0F3A41) }, |
| 6147 | { PREFIX_TABLE (PREFIX_0F3A42) }, |
| 6148 | { Bad_Opcode }, |
| 6149 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
| 6150 | { Bad_Opcode }, |
| 6151 | { Bad_Opcode }, |
| 6152 | { Bad_Opcode }, |
| 6153 | /* 48 */ |
| 6154 | { Bad_Opcode }, |
| 6155 | { Bad_Opcode }, |
| 6156 | { Bad_Opcode }, |
| 6157 | { Bad_Opcode }, |
| 6158 | { Bad_Opcode }, |
| 6159 | { Bad_Opcode }, |
| 6160 | { Bad_Opcode }, |
| 6161 | { Bad_Opcode }, |
| 6162 | /* 50 */ |
| 6163 | { Bad_Opcode }, |
| 6164 | { Bad_Opcode }, |
| 6165 | { Bad_Opcode }, |
| 6166 | { Bad_Opcode }, |
| 6167 | { Bad_Opcode }, |
| 6168 | { Bad_Opcode }, |
| 6169 | { Bad_Opcode }, |
| 6170 | { Bad_Opcode }, |
| 6171 | /* 58 */ |
| 6172 | { Bad_Opcode }, |
| 6173 | { Bad_Opcode }, |
| 6174 | { Bad_Opcode }, |
| 6175 | { Bad_Opcode }, |
| 6176 | { Bad_Opcode }, |
| 6177 | { Bad_Opcode }, |
| 6178 | { Bad_Opcode }, |
| 6179 | { Bad_Opcode }, |
| 6180 | /* 60 */ |
| 6181 | { PREFIX_TABLE (PREFIX_0F3A60) }, |
| 6182 | { PREFIX_TABLE (PREFIX_0F3A61) }, |
| 6183 | { PREFIX_TABLE (PREFIX_0F3A62) }, |
| 6184 | { PREFIX_TABLE (PREFIX_0F3A63) }, |
| 6185 | { Bad_Opcode }, |
| 6186 | { Bad_Opcode }, |
| 6187 | { Bad_Opcode }, |
| 6188 | { Bad_Opcode }, |
| 6189 | /* 68 */ |
| 6190 | { Bad_Opcode }, |
| 6191 | { Bad_Opcode }, |
| 6192 | { Bad_Opcode }, |
| 6193 | { Bad_Opcode }, |
| 6194 | { Bad_Opcode }, |
| 6195 | { Bad_Opcode }, |
| 6196 | { Bad_Opcode }, |
| 6197 | { Bad_Opcode }, |
| 6198 | /* 70 */ |
| 6199 | { Bad_Opcode }, |
| 6200 | { Bad_Opcode }, |
| 6201 | { Bad_Opcode }, |
| 6202 | { Bad_Opcode }, |
| 6203 | { Bad_Opcode }, |
| 6204 | { Bad_Opcode }, |
| 6205 | { Bad_Opcode }, |
| 6206 | { Bad_Opcode }, |
| 6207 | /* 78 */ |
| 6208 | { Bad_Opcode }, |
| 6209 | { Bad_Opcode }, |
| 6210 | { Bad_Opcode }, |
| 6211 | { Bad_Opcode }, |
| 6212 | { Bad_Opcode }, |
| 6213 | { Bad_Opcode }, |
| 6214 | { Bad_Opcode }, |
| 6215 | { Bad_Opcode }, |
| 6216 | /* 80 */ |
| 6217 | { Bad_Opcode }, |
| 6218 | { Bad_Opcode }, |
| 6219 | { Bad_Opcode }, |
| 6220 | { Bad_Opcode }, |
| 6221 | { Bad_Opcode }, |
| 6222 | { Bad_Opcode }, |
| 6223 | { Bad_Opcode }, |
| 6224 | { Bad_Opcode }, |
| 6225 | /* 88 */ |
| 6226 | { Bad_Opcode }, |
| 6227 | { Bad_Opcode }, |
| 6228 | { Bad_Opcode }, |
| 6229 | { Bad_Opcode }, |
| 6230 | { Bad_Opcode }, |
| 6231 | { Bad_Opcode }, |
| 6232 | { Bad_Opcode }, |
| 6233 | { Bad_Opcode }, |
| 6234 | /* 90 */ |
| 6235 | { Bad_Opcode }, |
| 6236 | { Bad_Opcode }, |
| 6237 | { Bad_Opcode }, |
| 6238 | { Bad_Opcode }, |
| 6239 | { Bad_Opcode }, |
| 6240 | { Bad_Opcode }, |
| 6241 | { Bad_Opcode }, |
| 6242 | { Bad_Opcode }, |
| 6243 | /* 98 */ |
| 6244 | { Bad_Opcode }, |
| 6245 | { Bad_Opcode }, |
| 6246 | { Bad_Opcode }, |
| 6247 | { Bad_Opcode }, |
| 6248 | { Bad_Opcode }, |
| 6249 | { Bad_Opcode }, |
| 6250 | { Bad_Opcode }, |
| 6251 | { Bad_Opcode }, |
| 6252 | /* a0 */ |
| 6253 | { Bad_Opcode }, |
| 6254 | { Bad_Opcode }, |
| 6255 | { Bad_Opcode }, |
| 6256 | { Bad_Opcode }, |
| 6257 | { Bad_Opcode }, |
| 6258 | { Bad_Opcode }, |
| 6259 | { Bad_Opcode }, |
| 6260 | { Bad_Opcode }, |
| 6261 | /* a8 */ |
| 6262 | { Bad_Opcode }, |
| 6263 | { Bad_Opcode }, |
| 6264 | { Bad_Opcode }, |
| 6265 | { Bad_Opcode }, |
| 6266 | { Bad_Opcode }, |
| 6267 | { Bad_Opcode }, |
| 6268 | { Bad_Opcode }, |
| 6269 | { Bad_Opcode }, |
| 6270 | /* b0 */ |
| 6271 | { Bad_Opcode }, |
| 6272 | { Bad_Opcode }, |
| 6273 | { Bad_Opcode }, |
| 6274 | { Bad_Opcode }, |
| 6275 | { Bad_Opcode }, |
| 6276 | { Bad_Opcode }, |
| 6277 | { Bad_Opcode }, |
| 6278 | { Bad_Opcode }, |
| 6279 | /* b8 */ |
| 6280 | { Bad_Opcode }, |
| 6281 | { Bad_Opcode }, |
| 6282 | { Bad_Opcode }, |
| 6283 | { Bad_Opcode }, |
| 6284 | { Bad_Opcode }, |
| 6285 | { Bad_Opcode }, |
| 6286 | { Bad_Opcode }, |
| 6287 | { Bad_Opcode }, |
| 6288 | /* c0 */ |
| 6289 | { Bad_Opcode }, |
| 6290 | { Bad_Opcode }, |
| 6291 | { Bad_Opcode }, |
| 6292 | { Bad_Opcode }, |
| 6293 | { Bad_Opcode }, |
| 6294 | { Bad_Opcode }, |
| 6295 | { Bad_Opcode }, |
| 6296 | { Bad_Opcode }, |
| 6297 | /* c8 */ |
| 6298 | { Bad_Opcode }, |
| 6299 | { Bad_Opcode }, |
| 6300 | { Bad_Opcode }, |
| 6301 | { Bad_Opcode }, |
| 6302 | { Bad_Opcode }, |
| 6303 | { Bad_Opcode }, |
| 6304 | { Bad_Opcode }, |
| 6305 | { Bad_Opcode }, |
| 6306 | /* d0 */ |
| 6307 | { Bad_Opcode }, |
| 6308 | { Bad_Opcode }, |
| 6309 | { Bad_Opcode }, |
| 6310 | { Bad_Opcode }, |
| 6311 | { Bad_Opcode }, |
| 6312 | { Bad_Opcode }, |
| 6313 | { Bad_Opcode }, |
| 6314 | { Bad_Opcode }, |
| 6315 | /* d8 */ |
| 6316 | { Bad_Opcode }, |
| 6317 | { Bad_Opcode }, |
| 6318 | { Bad_Opcode }, |
| 6319 | { Bad_Opcode }, |
| 6320 | { Bad_Opcode }, |
| 6321 | { Bad_Opcode }, |
| 6322 | { Bad_Opcode }, |
| 6323 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
| 6324 | /* e0 */ |
| 6325 | { Bad_Opcode }, |
| 6326 | { Bad_Opcode }, |
| 6327 | { Bad_Opcode }, |
| 6328 | { Bad_Opcode }, |
| 6329 | { Bad_Opcode }, |
| 6330 | { Bad_Opcode }, |
| 6331 | { Bad_Opcode }, |
| 6332 | { Bad_Opcode }, |
| 6333 | /* e8 */ |
| 6334 | { Bad_Opcode }, |
| 6335 | { Bad_Opcode }, |
| 6336 | { Bad_Opcode }, |
| 6337 | { Bad_Opcode }, |
| 6338 | { Bad_Opcode }, |
| 6339 | { Bad_Opcode }, |
| 6340 | { Bad_Opcode }, |
| 6341 | { Bad_Opcode }, |
| 6342 | /* f0 */ |
| 6343 | { Bad_Opcode }, |
| 6344 | { Bad_Opcode }, |
| 6345 | { Bad_Opcode }, |
| 6346 | { Bad_Opcode }, |
| 6347 | { Bad_Opcode }, |
| 6348 | { Bad_Opcode }, |
| 6349 | { Bad_Opcode }, |
| 6350 | { Bad_Opcode }, |
| 6351 | /* f8 */ |
| 6352 | { Bad_Opcode }, |
| 6353 | { Bad_Opcode }, |
| 6354 | { Bad_Opcode }, |
| 6355 | { Bad_Opcode }, |
| 6356 | { Bad_Opcode }, |
| 6357 | { Bad_Opcode }, |
| 6358 | { Bad_Opcode }, |
| 6359 | { Bad_Opcode }, |
| 6360 | }, |
| 6361 | |
| 6362 | /* THREE_BYTE_0F7A */ |
| 6363 | { |
| 6364 | /* 00 */ |
| 6365 | { Bad_Opcode }, |
| 6366 | { Bad_Opcode }, |
| 6367 | { Bad_Opcode }, |
| 6368 | { Bad_Opcode }, |
| 6369 | { Bad_Opcode }, |
| 6370 | { Bad_Opcode }, |
| 6371 | { Bad_Opcode }, |
| 6372 | { Bad_Opcode }, |
| 6373 | /* 08 */ |
| 6374 | { Bad_Opcode }, |
| 6375 | { Bad_Opcode }, |
| 6376 | { Bad_Opcode }, |
| 6377 | { Bad_Opcode }, |
| 6378 | { Bad_Opcode }, |
| 6379 | { Bad_Opcode }, |
| 6380 | { Bad_Opcode }, |
| 6381 | { Bad_Opcode }, |
| 6382 | /* 10 */ |
| 6383 | { Bad_Opcode }, |
| 6384 | { Bad_Opcode }, |
| 6385 | { Bad_Opcode }, |
| 6386 | { Bad_Opcode }, |
| 6387 | { Bad_Opcode }, |
| 6388 | { Bad_Opcode }, |
| 6389 | { Bad_Opcode }, |
| 6390 | { Bad_Opcode }, |
| 6391 | /* 18 */ |
| 6392 | { Bad_Opcode }, |
| 6393 | { Bad_Opcode }, |
| 6394 | { Bad_Opcode }, |
| 6395 | { Bad_Opcode }, |
| 6396 | { Bad_Opcode }, |
| 6397 | { Bad_Opcode }, |
| 6398 | { Bad_Opcode }, |
| 6399 | { Bad_Opcode }, |
| 6400 | /* 20 */ |
| 6401 | { "ptest", { XX } }, |
| 6402 | { Bad_Opcode }, |
| 6403 | { Bad_Opcode }, |
| 6404 | { Bad_Opcode }, |
| 6405 | { Bad_Opcode }, |
| 6406 | { Bad_Opcode }, |
| 6407 | { Bad_Opcode }, |
| 6408 | { Bad_Opcode }, |
| 6409 | /* 28 */ |
| 6410 | { Bad_Opcode }, |
| 6411 | { Bad_Opcode }, |
| 6412 | { Bad_Opcode }, |
| 6413 | { Bad_Opcode }, |
| 6414 | { Bad_Opcode }, |
| 6415 | { Bad_Opcode }, |
| 6416 | { Bad_Opcode }, |
| 6417 | { Bad_Opcode }, |
| 6418 | /* 30 */ |
| 6419 | { Bad_Opcode }, |
| 6420 | { Bad_Opcode }, |
| 6421 | { Bad_Opcode }, |
| 6422 | { Bad_Opcode }, |
| 6423 | { Bad_Opcode }, |
| 6424 | { Bad_Opcode }, |
| 6425 | { Bad_Opcode }, |
| 6426 | { Bad_Opcode }, |
| 6427 | /* 38 */ |
| 6428 | { Bad_Opcode }, |
| 6429 | { Bad_Opcode }, |
| 6430 | { Bad_Opcode }, |
| 6431 | { Bad_Opcode }, |
| 6432 | { Bad_Opcode }, |
| 6433 | { Bad_Opcode }, |
| 6434 | { Bad_Opcode }, |
| 6435 | { Bad_Opcode }, |
| 6436 | /* 40 */ |
| 6437 | { Bad_Opcode }, |
| 6438 | { "phaddbw", { XM, EXq } }, |
| 6439 | { "phaddbd", { XM, EXq } }, |
| 6440 | { "phaddbq", { XM, EXq } }, |
| 6441 | { Bad_Opcode }, |
| 6442 | { Bad_Opcode }, |
| 6443 | { "phaddwd", { XM, EXq } }, |
| 6444 | { "phaddwq", { XM, EXq } }, |
| 6445 | /* 48 */ |
| 6446 | { Bad_Opcode }, |
| 6447 | { Bad_Opcode }, |
| 6448 | { Bad_Opcode }, |
| 6449 | { "phadddq", { XM, EXq } }, |
| 6450 | { Bad_Opcode }, |
| 6451 | { Bad_Opcode }, |
| 6452 | { Bad_Opcode }, |
| 6453 | { Bad_Opcode }, |
| 6454 | /* 50 */ |
| 6455 | { Bad_Opcode }, |
| 6456 | { "phaddubw", { XM, EXq } }, |
| 6457 | { "phaddubd", { XM, EXq } }, |
| 6458 | { "phaddubq", { XM, EXq } }, |
| 6459 | { Bad_Opcode }, |
| 6460 | { Bad_Opcode }, |
| 6461 | { "phadduwd", { XM, EXq } }, |
| 6462 | { "phadduwq", { XM, EXq } }, |
| 6463 | /* 58 */ |
| 6464 | { Bad_Opcode }, |
| 6465 | { Bad_Opcode }, |
| 6466 | { Bad_Opcode }, |
| 6467 | { "phaddudq", { XM, EXq } }, |
| 6468 | { Bad_Opcode }, |
| 6469 | { Bad_Opcode }, |
| 6470 | { Bad_Opcode }, |
| 6471 | { Bad_Opcode }, |
| 6472 | /* 60 */ |
| 6473 | { Bad_Opcode }, |
| 6474 | { "phsubbw", { XM, EXq } }, |
| 6475 | { "phsubbd", { XM, EXq } }, |
| 6476 | { "phsubbq", { XM, EXq } }, |
| 6477 | { Bad_Opcode }, |
| 6478 | { Bad_Opcode }, |
| 6479 | { Bad_Opcode }, |
| 6480 | { Bad_Opcode }, |
| 6481 | /* 68 */ |
| 6482 | { Bad_Opcode }, |
| 6483 | { Bad_Opcode }, |
| 6484 | { Bad_Opcode }, |
| 6485 | { Bad_Opcode }, |
| 6486 | { Bad_Opcode }, |
| 6487 | { Bad_Opcode }, |
| 6488 | { Bad_Opcode }, |
| 6489 | { Bad_Opcode }, |
| 6490 | /* 70 */ |
| 6491 | { Bad_Opcode }, |
| 6492 | { Bad_Opcode }, |
| 6493 | { Bad_Opcode }, |
| 6494 | { Bad_Opcode }, |
| 6495 | { Bad_Opcode }, |
| 6496 | { Bad_Opcode }, |
| 6497 | { Bad_Opcode }, |
| 6498 | { Bad_Opcode }, |
| 6499 | /* 78 */ |
| 6500 | { Bad_Opcode }, |
| 6501 | { Bad_Opcode }, |
| 6502 | { Bad_Opcode }, |
| 6503 | { Bad_Opcode }, |
| 6504 | { Bad_Opcode }, |
| 6505 | { Bad_Opcode }, |
| 6506 | { Bad_Opcode }, |
| 6507 | { Bad_Opcode }, |
| 6508 | /* 80 */ |
| 6509 | { Bad_Opcode }, |
| 6510 | { Bad_Opcode }, |
| 6511 | { Bad_Opcode }, |
| 6512 | { Bad_Opcode }, |
| 6513 | { Bad_Opcode }, |
| 6514 | { Bad_Opcode }, |
| 6515 | { Bad_Opcode }, |
| 6516 | { Bad_Opcode }, |
| 6517 | /* 88 */ |
| 6518 | { Bad_Opcode }, |
| 6519 | { Bad_Opcode }, |
| 6520 | { Bad_Opcode }, |
| 6521 | { Bad_Opcode }, |
| 6522 | { Bad_Opcode }, |
| 6523 | { Bad_Opcode }, |
| 6524 | { Bad_Opcode }, |
| 6525 | { Bad_Opcode }, |
| 6526 | /* 90 */ |
| 6527 | { Bad_Opcode }, |
| 6528 | { Bad_Opcode }, |
| 6529 | { Bad_Opcode }, |
| 6530 | { Bad_Opcode }, |
| 6531 | { Bad_Opcode }, |
| 6532 | { Bad_Opcode }, |
| 6533 | { Bad_Opcode }, |
| 6534 | { Bad_Opcode }, |
| 6535 | /* 98 */ |
| 6536 | { Bad_Opcode }, |
| 6537 | { Bad_Opcode }, |
| 6538 | { Bad_Opcode }, |
| 6539 | { Bad_Opcode }, |
| 6540 | { Bad_Opcode }, |
| 6541 | { Bad_Opcode }, |
| 6542 | { Bad_Opcode }, |
| 6543 | { Bad_Opcode }, |
| 6544 | /* a0 */ |
| 6545 | { Bad_Opcode }, |
| 6546 | { Bad_Opcode }, |
| 6547 | { Bad_Opcode }, |
| 6548 | { Bad_Opcode }, |
| 6549 | { Bad_Opcode }, |
| 6550 | { Bad_Opcode }, |
| 6551 | { Bad_Opcode }, |
| 6552 | { Bad_Opcode }, |
| 6553 | /* a8 */ |
| 6554 | { Bad_Opcode }, |
| 6555 | { Bad_Opcode }, |
| 6556 | { Bad_Opcode }, |
| 6557 | { Bad_Opcode }, |
| 6558 | { Bad_Opcode }, |
| 6559 | { Bad_Opcode }, |
| 6560 | { Bad_Opcode }, |
| 6561 | { Bad_Opcode }, |
| 6562 | /* b0 */ |
| 6563 | { Bad_Opcode }, |
| 6564 | { Bad_Opcode }, |
| 6565 | { Bad_Opcode }, |
| 6566 | { Bad_Opcode }, |
| 6567 | { Bad_Opcode }, |
| 6568 | { Bad_Opcode }, |
| 6569 | { Bad_Opcode }, |
| 6570 | { Bad_Opcode }, |
| 6571 | /* b8 */ |
| 6572 | { Bad_Opcode }, |
| 6573 | { Bad_Opcode }, |
| 6574 | { Bad_Opcode }, |
| 6575 | { Bad_Opcode }, |
| 6576 | { Bad_Opcode }, |
| 6577 | { Bad_Opcode }, |
| 6578 | { Bad_Opcode }, |
| 6579 | { Bad_Opcode }, |
| 6580 | /* c0 */ |
| 6581 | { Bad_Opcode }, |
| 6582 | { Bad_Opcode }, |
| 6583 | { Bad_Opcode }, |
| 6584 | { Bad_Opcode }, |
| 6585 | { Bad_Opcode }, |
| 6586 | { Bad_Opcode }, |
| 6587 | { Bad_Opcode }, |
| 6588 | { Bad_Opcode }, |
| 6589 | /* c8 */ |
| 6590 | { Bad_Opcode }, |
| 6591 | { Bad_Opcode }, |
| 6592 | { Bad_Opcode }, |
| 6593 | { Bad_Opcode }, |
| 6594 | { Bad_Opcode }, |
| 6595 | { Bad_Opcode }, |
| 6596 | { Bad_Opcode }, |
| 6597 | { Bad_Opcode }, |
| 6598 | /* d0 */ |
| 6599 | { Bad_Opcode }, |
| 6600 | { Bad_Opcode }, |
| 6601 | { Bad_Opcode }, |
| 6602 | { Bad_Opcode }, |
| 6603 | { Bad_Opcode }, |
| 6604 | { Bad_Opcode }, |
| 6605 | { Bad_Opcode }, |
| 6606 | { Bad_Opcode }, |
| 6607 | /* d8 */ |
| 6608 | { Bad_Opcode }, |
| 6609 | { Bad_Opcode }, |
| 6610 | { Bad_Opcode }, |
| 6611 | { Bad_Opcode }, |
| 6612 | { Bad_Opcode }, |
| 6613 | { Bad_Opcode }, |
| 6614 | { Bad_Opcode }, |
| 6615 | { Bad_Opcode }, |
| 6616 | /* e0 */ |
| 6617 | { Bad_Opcode }, |
| 6618 | { Bad_Opcode }, |
| 6619 | { Bad_Opcode }, |
| 6620 | { Bad_Opcode }, |
| 6621 | { Bad_Opcode }, |
| 6622 | { Bad_Opcode }, |
| 6623 | { Bad_Opcode }, |
| 6624 | { Bad_Opcode }, |
| 6625 | /* e8 */ |
| 6626 | { Bad_Opcode }, |
| 6627 | { Bad_Opcode }, |
| 6628 | { Bad_Opcode }, |
| 6629 | { Bad_Opcode }, |
| 6630 | { Bad_Opcode }, |
| 6631 | { Bad_Opcode }, |
| 6632 | { Bad_Opcode }, |
| 6633 | { Bad_Opcode }, |
| 6634 | /* f0 */ |
| 6635 | { Bad_Opcode }, |
| 6636 | { Bad_Opcode }, |
| 6637 | { Bad_Opcode }, |
| 6638 | { Bad_Opcode }, |
| 6639 | { Bad_Opcode }, |
| 6640 | { Bad_Opcode }, |
| 6641 | { Bad_Opcode }, |
| 6642 | { Bad_Opcode }, |
| 6643 | /* f8 */ |
| 6644 | { Bad_Opcode }, |
| 6645 | { Bad_Opcode }, |
| 6646 | { Bad_Opcode }, |
| 6647 | { Bad_Opcode }, |
| 6648 | { Bad_Opcode }, |
| 6649 | { Bad_Opcode }, |
| 6650 | { Bad_Opcode }, |
| 6651 | { Bad_Opcode }, |
| 6652 | }, |
| 6653 | }; |
| 6654 | |
| 6655 | static const struct dis386 xop_table[][256] = { |
| 6656 | /* XOP_08 */ |
| 6657 | { |
| 6658 | /* 00 */ |
| 6659 | { Bad_Opcode }, |
| 6660 | { Bad_Opcode }, |
| 6661 | { Bad_Opcode }, |
| 6662 | { Bad_Opcode }, |
| 6663 | { Bad_Opcode }, |
| 6664 | { Bad_Opcode }, |
| 6665 | { Bad_Opcode }, |
| 6666 | { Bad_Opcode }, |
| 6667 | /* 08 */ |
| 6668 | { Bad_Opcode }, |
| 6669 | { Bad_Opcode }, |
| 6670 | { Bad_Opcode }, |
| 6671 | { Bad_Opcode }, |
| 6672 | { Bad_Opcode }, |
| 6673 | { Bad_Opcode }, |
| 6674 | { Bad_Opcode }, |
| 6675 | { Bad_Opcode }, |
| 6676 | /* 10 */ |
| 6677 | { Bad_Opcode }, |
| 6678 | { Bad_Opcode }, |
| 6679 | { Bad_Opcode }, |
| 6680 | { Bad_Opcode }, |
| 6681 | { Bad_Opcode }, |
| 6682 | { Bad_Opcode }, |
| 6683 | { Bad_Opcode }, |
| 6684 | { Bad_Opcode }, |
| 6685 | /* 18 */ |
| 6686 | { Bad_Opcode }, |
| 6687 | { Bad_Opcode }, |
| 6688 | { Bad_Opcode }, |
| 6689 | { Bad_Opcode }, |
| 6690 | { Bad_Opcode }, |
| 6691 | { Bad_Opcode }, |
| 6692 | { Bad_Opcode }, |
| 6693 | { Bad_Opcode }, |
| 6694 | /* 20 */ |
| 6695 | { Bad_Opcode }, |
| 6696 | { Bad_Opcode }, |
| 6697 | { Bad_Opcode }, |
| 6698 | { Bad_Opcode }, |
| 6699 | { Bad_Opcode }, |
| 6700 | { Bad_Opcode }, |
| 6701 | { Bad_Opcode }, |
| 6702 | { Bad_Opcode }, |
| 6703 | /* 28 */ |
| 6704 | { Bad_Opcode }, |
| 6705 | { Bad_Opcode }, |
| 6706 | { Bad_Opcode }, |
| 6707 | { Bad_Opcode }, |
| 6708 | { Bad_Opcode }, |
| 6709 | { Bad_Opcode }, |
| 6710 | { Bad_Opcode }, |
| 6711 | { Bad_Opcode }, |
| 6712 | /* 30 */ |
| 6713 | { Bad_Opcode }, |
| 6714 | { Bad_Opcode }, |
| 6715 | { Bad_Opcode }, |
| 6716 | { Bad_Opcode }, |
| 6717 | { Bad_Opcode }, |
| 6718 | { Bad_Opcode }, |
| 6719 | { Bad_Opcode }, |
| 6720 | { Bad_Opcode }, |
| 6721 | /* 38 */ |
| 6722 | { Bad_Opcode }, |
| 6723 | { Bad_Opcode }, |
| 6724 | { Bad_Opcode }, |
| 6725 | { Bad_Opcode }, |
| 6726 | { Bad_Opcode }, |
| 6727 | { Bad_Opcode }, |
| 6728 | { Bad_Opcode }, |
| 6729 | { Bad_Opcode }, |
| 6730 | /* 40 */ |
| 6731 | { Bad_Opcode }, |
| 6732 | { Bad_Opcode }, |
| 6733 | { Bad_Opcode }, |
| 6734 | { Bad_Opcode }, |
| 6735 | { Bad_Opcode }, |
| 6736 | { Bad_Opcode }, |
| 6737 | { Bad_Opcode }, |
| 6738 | { Bad_Opcode }, |
| 6739 | /* 48 */ |
| 6740 | { Bad_Opcode }, |
| 6741 | { Bad_Opcode }, |
| 6742 | { Bad_Opcode }, |
| 6743 | { Bad_Opcode }, |
| 6744 | { Bad_Opcode }, |
| 6745 | { Bad_Opcode }, |
| 6746 | { Bad_Opcode }, |
| 6747 | { Bad_Opcode }, |
| 6748 | /* 50 */ |
| 6749 | { Bad_Opcode }, |
| 6750 | { Bad_Opcode }, |
| 6751 | { Bad_Opcode }, |
| 6752 | { Bad_Opcode }, |
| 6753 | { Bad_Opcode }, |
| 6754 | { Bad_Opcode }, |
| 6755 | { Bad_Opcode }, |
| 6756 | { Bad_Opcode }, |
| 6757 | /* 58 */ |
| 6758 | { Bad_Opcode }, |
| 6759 | { Bad_Opcode }, |
| 6760 | { Bad_Opcode }, |
| 6761 | { Bad_Opcode }, |
| 6762 | { Bad_Opcode }, |
| 6763 | { Bad_Opcode }, |
| 6764 | { Bad_Opcode }, |
| 6765 | { Bad_Opcode }, |
| 6766 | /* 60 */ |
| 6767 | { Bad_Opcode }, |
| 6768 | { Bad_Opcode }, |
| 6769 | { Bad_Opcode }, |
| 6770 | { Bad_Opcode }, |
| 6771 | { Bad_Opcode }, |
| 6772 | { Bad_Opcode }, |
| 6773 | { Bad_Opcode }, |
| 6774 | { Bad_Opcode }, |
| 6775 | /* 68 */ |
| 6776 | { Bad_Opcode }, |
| 6777 | { Bad_Opcode }, |
| 6778 | { Bad_Opcode }, |
| 6779 | { Bad_Opcode }, |
| 6780 | { Bad_Opcode }, |
| 6781 | { Bad_Opcode }, |
| 6782 | { Bad_Opcode }, |
| 6783 | { Bad_Opcode }, |
| 6784 | /* 70 */ |
| 6785 | { Bad_Opcode }, |
| 6786 | { Bad_Opcode }, |
| 6787 | { Bad_Opcode }, |
| 6788 | { Bad_Opcode }, |
| 6789 | { Bad_Opcode }, |
| 6790 | { Bad_Opcode }, |
| 6791 | { Bad_Opcode }, |
| 6792 | { Bad_Opcode }, |
| 6793 | /* 78 */ |
| 6794 | { Bad_Opcode }, |
| 6795 | { Bad_Opcode }, |
| 6796 | { Bad_Opcode }, |
| 6797 | { Bad_Opcode }, |
| 6798 | { Bad_Opcode }, |
| 6799 | { Bad_Opcode }, |
| 6800 | { Bad_Opcode }, |
| 6801 | { Bad_Opcode }, |
| 6802 | /* 80 */ |
| 6803 | { Bad_Opcode }, |
| 6804 | { Bad_Opcode }, |
| 6805 | { Bad_Opcode }, |
| 6806 | { Bad_Opcode }, |
| 6807 | { Bad_Opcode }, |
| 6808 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6809 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6810 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6811 | /* 88 */ |
| 6812 | { Bad_Opcode }, |
| 6813 | { Bad_Opcode }, |
| 6814 | { Bad_Opcode }, |
| 6815 | { Bad_Opcode }, |
| 6816 | { Bad_Opcode }, |
| 6817 | { Bad_Opcode }, |
| 6818 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6819 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6820 | /* 90 */ |
| 6821 | { Bad_Opcode }, |
| 6822 | { Bad_Opcode }, |
| 6823 | { Bad_Opcode }, |
| 6824 | { Bad_Opcode }, |
| 6825 | { Bad_Opcode }, |
| 6826 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6827 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6828 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6829 | /* 98 */ |
| 6830 | { Bad_Opcode }, |
| 6831 | { Bad_Opcode }, |
| 6832 | { Bad_Opcode }, |
| 6833 | { Bad_Opcode }, |
| 6834 | { Bad_Opcode }, |
| 6835 | { Bad_Opcode }, |
| 6836 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6837 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6838 | /* a0 */ |
| 6839 | { Bad_Opcode }, |
| 6840 | { Bad_Opcode }, |
| 6841 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6842 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6843 | { Bad_Opcode }, |
| 6844 | { Bad_Opcode }, |
| 6845 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6846 | { Bad_Opcode }, |
| 6847 | /* a8 */ |
| 6848 | { Bad_Opcode }, |
| 6849 | { Bad_Opcode }, |
| 6850 | { Bad_Opcode }, |
| 6851 | { Bad_Opcode }, |
| 6852 | { Bad_Opcode }, |
| 6853 | { Bad_Opcode }, |
| 6854 | { Bad_Opcode }, |
| 6855 | { Bad_Opcode }, |
| 6856 | /* b0 */ |
| 6857 | { Bad_Opcode }, |
| 6858 | { Bad_Opcode }, |
| 6859 | { Bad_Opcode }, |
| 6860 | { Bad_Opcode }, |
| 6861 | { Bad_Opcode }, |
| 6862 | { Bad_Opcode }, |
| 6863 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
| 6864 | { Bad_Opcode }, |
| 6865 | /* b8 */ |
| 6866 | { Bad_Opcode }, |
| 6867 | { Bad_Opcode }, |
| 6868 | { Bad_Opcode }, |
| 6869 | { Bad_Opcode }, |
| 6870 | { Bad_Opcode }, |
| 6871 | { Bad_Opcode }, |
| 6872 | { Bad_Opcode }, |
| 6873 | { Bad_Opcode }, |
| 6874 | /* c0 */ |
| 6875 | { "vprotb", { XM, Vex_2src_1, Ib } }, |
| 6876 | { "vprotw", { XM, Vex_2src_1, Ib } }, |
| 6877 | { "vprotd", { XM, Vex_2src_1, Ib } }, |
| 6878 | { "vprotq", { XM, Vex_2src_1, Ib } }, |
| 6879 | { Bad_Opcode }, |
| 6880 | { Bad_Opcode }, |
| 6881 | { Bad_Opcode }, |
| 6882 | { Bad_Opcode }, |
| 6883 | /* c8 */ |
| 6884 | { Bad_Opcode }, |
| 6885 | { Bad_Opcode }, |
| 6886 | { Bad_Opcode }, |
| 6887 | { Bad_Opcode }, |
| 6888 | { "vpcomb", { XM, Vex128, EXx, Ib } }, |
| 6889 | { "vpcomw", { XM, Vex128, EXx, Ib } }, |
| 6890 | { "vpcomd", { XM, Vex128, EXx, Ib } }, |
| 6891 | { "vpcomq", { XM, Vex128, EXx, Ib } }, |
| 6892 | /* d0 */ |
| 6893 | { Bad_Opcode }, |
| 6894 | { Bad_Opcode }, |
| 6895 | { Bad_Opcode }, |
| 6896 | { Bad_Opcode }, |
| 6897 | { Bad_Opcode }, |
| 6898 | { Bad_Opcode }, |
| 6899 | { Bad_Opcode }, |
| 6900 | { Bad_Opcode }, |
| 6901 | /* d8 */ |
| 6902 | { Bad_Opcode }, |
| 6903 | { Bad_Opcode }, |
| 6904 | { Bad_Opcode }, |
| 6905 | { Bad_Opcode }, |
| 6906 | { Bad_Opcode }, |
| 6907 | { Bad_Opcode }, |
| 6908 | { Bad_Opcode }, |
| 6909 | { Bad_Opcode }, |
| 6910 | /* e0 */ |
| 6911 | { Bad_Opcode }, |
| 6912 | { Bad_Opcode }, |
| 6913 | { Bad_Opcode }, |
| 6914 | { Bad_Opcode }, |
| 6915 | { Bad_Opcode }, |
| 6916 | { Bad_Opcode }, |
| 6917 | { Bad_Opcode }, |
| 6918 | { Bad_Opcode }, |
| 6919 | /* e8 */ |
| 6920 | { Bad_Opcode }, |
| 6921 | { Bad_Opcode }, |
| 6922 | { Bad_Opcode }, |
| 6923 | { Bad_Opcode }, |
| 6924 | { "vpcomub", { XM, Vex128, EXx, Ib } }, |
| 6925 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, |
| 6926 | { "vpcomud", { XM, Vex128, EXx, Ib } }, |
| 6927 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, |
| 6928 | /* f0 */ |
| 6929 | { Bad_Opcode }, |
| 6930 | { Bad_Opcode }, |
| 6931 | { Bad_Opcode }, |
| 6932 | { Bad_Opcode }, |
| 6933 | { Bad_Opcode }, |
| 6934 | { Bad_Opcode }, |
| 6935 | { Bad_Opcode }, |
| 6936 | { Bad_Opcode }, |
| 6937 | /* f8 */ |
| 6938 | { Bad_Opcode }, |
| 6939 | { Bad_Opcode }, |
| 6940 | { Bad_Opcode }, |
| 6941 | { Bad_Opcode }, |
| 6942 | { Bad_Opcode }, |
| 6943 | { Bad_Opcode }, |
| 6944 | { Bad_Opcode }, |
| 6945 | { Bad_Opcode }, |
| 6946 | }, |
| 6947 | /* XOP_09 */ |
| 6948 | { |
| 6949 | /* 00 */ |
| 6950 | { Bad_Opcode }, |
| 6951 | { REG_TABLE (REG_XOP_TBM_01) }, |
| 6952 | { REG_TABLE (REG_XOP_TBM_02) }, |
| 6953 | { Bad_Opcode }, |
| 6954 | { Bad_Opcode }, |
| 6955 | { Bad_Opcode }, |
| 6956 | { Bad_Opcode }, |
| 6957 | { Bad_Opcode }, |
| 6958 | /* 08 */ |
| 6959 | { Bad_Opcode }, |
| 6960 | { Bad_Opcode }, |
| 6961 | { Bad_Opcode }, |
| 6962 | { Bad_Opcode }, |
| 6963 | { Bad_Opcode }, |
| 6964 | { Bad_Opcode }, |
| 6965 | { Bad_Opcode }, |
| 6966 | { Bad_Opcode }, |
| 6967 | /* 10 */ |
| 6968 | { Bad_Opcode }, |
| 6969 | { Bad_Opcode }, |
| 6970 | { REG_TABLE (REG_XOP_LWPCB) }, |
| 6971 | { Bad_Opcode }, |
| 6972 | { Bad_Opcode }, |
| 6973 | { Bad_Opcode }, |
| 6974 | { Bad_Opcode }, |
| 6975 | { Bad_Opcode }, |
| 6976 | /* 18 */ |
| 6977 | { Bad_Opcode }, |
| 6978 | { Bad_Opcode }, |
| 6979 | { Bad_Opcode }, |
| 6980 | { Bad_Opcode }, |
| 6981 | { Bad_Opcode }, |
| 6982 | { Bad_Opcode }, |
| 6983 | { Bad_Opcode }, |
| 6984 | { Bad_Opcode }, |
| 6985 | /* 20 */ |
| 6986 | { Bad_Opcode }, |
| 6987 | { Bad_Opcode }, |
| 6988 | { Bad_Opcode }, |
| 6989 | { Bad_Opcode }, |
| 6990 | { Bad_Opcode }, |
| 6991 | { Bad_Opcode }, |
| 6992 | { Bad_Opcode }, |
| 6993 | { Bad_Opcode }, |
| 6994 | /* 28 */ |
| 6995 | { Bad_Opcode }, |
| 6996 | { Bad_Opcode }, |
| 6997 | { Bad_Opcode }, |
| 6998 | { Bad_Opcode }, |
| 6999 | { Bad_Opcode }, |
| 7000 | { Bad_Opcode }, |
| 7001 | { Bad_Opcode }, |
| 7002 | { Bad_Opcode }, |
| 7003 | /* 30 */ |
| 7004 | { Bad_Opcode }, |
| 7005 | { Bad_Opcode }, |
| 7006 | { Bad_Opcode }, |
| 7007 | { Bad_Opcode }, |
| 7008 | { Bad_Opcode }, |
| 7009 | { Bad_Opcode }, |
| 7010 | { Bad_Opcode }, |
| 7011 | { Bad_Opcode }, |
| 7012 | /* 38 */ |
| 7013 | { Bad_Opcode }, |
| 7014 | { Bad_Opcode }, |
| 7015 | { Bad_Opcode }, |
| 7016 | { Bad_Opcode }, |
| 7017 | { Bad_Opcode }, |
| 7018 | { Bad_Opcode }, |
| 7019 | { Bad_Opcode }, |
| 7020 | { Bad_Opcode }, |
| 7021 | /* 40 */ |
| 7022 | { Bad_Opcode }, |
| 7023 | { Bad_Opcode }, |
| 7024 | { Bad_Opcode }, |
| 7025 | { Bad_Opcode }, |
| 7026 | { Bad_Opcode }, |
| 7027 | { Bad_Opcode }, |
| 7028 | { Bad_Opcode }, |
| 7029 | { Bad_Opcode }, |
| 7030 | /* 48 */ |
| 7031 | { Bad_Opcode }, |
| 7032 | { Bad_Opcode }, |
| 7033 | { Bad_Opcode }, |
| 7034 | { Bad_Opcode }, |
| 7035 | { Bad_Opcode }, |
| 7036 | { Bad_Opcode }, |
| 7037 | { Bad_Opcode }, |
| 7038 | { Bad_Opcode }, |
| 7039 | /* 50 */ |
| 7040 | { Bad_Opcode }, |
| 7041 | { Bad_Opcode }, |
| 7042 | { Bad_Opcode }, |
| 7043 | { Bad_Opcode }, |
| 7044 | { Bad_Opcode }, |
| 7045 | { Bad_Opcode }, |
| 7046 | { Bad_Opcode }, |
| 7047 | { Bad_Opcode }, |
| 7048 | /* 58 */ |
| 7049 | { Bad_Opcode }, |
| 7050 | { Bad_Opcode }, |
| 7051 | { Bad_Opcode }, |
| 7052 | { Bad_Opcode }, |
| 7053 | { Bad_Opcode }, |
| 7054 | { Bad_Opcode }, |
| 7055 | { Bad_Opcode }, |
| 7056 | { Bad_Opcode }, |
| 7057 | /* 60 */ |
| 7058 | { Bad_Opcode }, |
| 7059 | { Bad_Opcode }, |
| 7060 | { Bad_Opcode }, |
| 7061 | { Bad_Opcode }, |
| 7062 | { Bad_Opcode }, |
| 7063 | { Bad_Opcode }, |
| 7064 | { Bad_Opcode }, |
| 7065 | { Bad_Opcode }, |
| 7066 | /* 68 */ |
| 7067 | { Bad_Opcode }, |
| 7068 | { Bad_Opcode }, |
| 7069 | { Bad_Opcode }, |
| 7070 | { Bad_Opcode }, |
| 7071 | { Bad_Opcode }, |
| 7072 | { Bad_Opcode }, |
| 7073 | { Bad_Opcode }, |
| 7074 | { Bad_Opcode }, |
| 7075 | /* 70 */ |
| 7076 | { Bad_Opcode }, |
| 7077 | { Bad_Opcode }, |
| 7078 | { Bad_Opcode }, |
| 7079 | { Bad_Opcode }, |
| 7080 | { Bad_Opcode }, |
| 7081 | { Bad_Opcode }, |
| 7082 | { Bad_Opcode }, |
| 7083 | { Bad_Opcode }, |
| 7084 | /* 78 */ |
| 7085 | { Bad_Opcode }, |
| 7086 | { Bad_Opcode }, |
| 7087 | { Bad_Opcode }, |
| 7088 | { Bad_Opcode }, |
| 7089 | { Bad_Opcode }, |
| 7090 | { Bad_Opcode }, |
| 7091 | { Bad_Opcode }, |
| 7092 | { Bad_Opcode }, |
| 7093 | /* 80 */ |
| 7094 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
| 7095 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, |
| 7096 | { "vfrczss", { XM, EXd } }, |
| 7097 | { "vfrczsd", { XM, EXq } }, |
| 7098 | { Bad_Opcode }, |
| 7099 | { Bad_Opcode }, |
| 7100 | { Bad_Opcode }, |
| 7101 | { Bad_Opcode }, |
| 7102 | /* 88 */ |
| 7103 | { Bad_Opcode }, |
| 7104 | { Bad_Opcode }, |
| 7105 | { Bad_Opcode }, |
| 7106 | { Bad_Opcode }, |
| 7107 | { Bad_Opcode }, |
| 7108 | { Bad_Opcode }, |
| 7109 | { Bad_Opcode }, |
| 7110 | { Bad_Opcode }, |
| 7111 | /* 90 */ |
| 7112 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7113 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7114 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7115 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7116 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7117 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7118 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7119 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7120 | /* 98 */ |
| 7121 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7122 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7123 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7124 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, |
| 7125 | { Bad_Opcode }, |
| 7126 | { Bad_Opcode }, |
| 7127 | { Bad_Opcode }, |
| 7128 | { Bad_Opcode }, |
| 7129 | /* a0 */ |
| 7130 | { Bad_Opcode }, |
| 7131 | { Bad_Opcode }, |
| 7132 | { Bad_Opcode }, |
| 7133 | { Bad_Opcode }, |
| 7134 | { Bad_Opcode }, |
| 7135 | { Bad_Opcode }, |
| 7136 | { Bad_Opcode }, |
| 7137 | { Bad_Opcode }, |
| 7138 | /* a8 */ |
| 7139 | { Bad_Opcode }, |
| 7140 | { Bad_Opcode }, |
| 7141 | { Bad_Opcode }, |
| 7142 | { Bad_Opcode }, |
| 7143 | { Bad_Opcode }, |
| 7144 | { Bad_Opcode }, |
| 7145 | { Bad_Opcode }, |
| 7146 | { Bad_Opcode }, |
| 7147 | /* b0 */ |
| 7148 | { Bad_Opcode }, |
| 7149 | { Bad_Opcode }, |
| 7150 | { Bad_Opcode }, |
| 7151 | { Bad_Opcode }, |
| 7152 | { Bad_Opcode }, |
| 7153 | { Bad_Opcode }, |
| 7154 | { Bad_Opcode }, |
| 7155 | { Bad_Opcode }, |
| 7156 | /* b8 */ |
| 7157 | { Bad_Opcode }, |
| 7158 | { Bad_Opcode }, |
| 7159 | { Bad_Opcode }, |
| 7160 | { Bad_Opcode }, |
| 7161 | { Bad_Opcode }, |
| 7162 | { Bad_Opcode }, |
| 7163 | { Bad_Opcode }, |
| 7164 | { Bad_Opcode }, |
| 7165 | /* c0 */ |
| 7166 | { Bad_Opcode }, |
| 7167 | { "vphaddbw", { XM, EXxmm } }, |
| 7168 | { "vphaddbd", { XM, EXxmm } }, |
| 7169 | { "vphaddbq", { XM, EXxmm } }, |
| 7170 | { Bad_Opcode }, |
| 7171 | { Bad_Opcode }, |
| 7172 | { "vphaddwd", { XM, EXxmm } }, |
| 7173 | { "vphaddwq", { XM, EXxmm } }, |
| 7174 | /* c8 */ |
| 7175 | { Bad_Opcode }, |
| 7176 | { Bad_Opcode }, |
| 7177 | { Bad_Opcode }, |
| 7178 | { "vphadddq", { XM, EXxmm } }, |
| 7179 | { Bad_Opcode }, |
| 7180 | { Bad_Opcode }, |
| 7181 | { Bad_Opcode }, |
| 7182 | { Bad_Opcode }, |
| 7183 | /* d0 */ |
| 7184 | { Bad_Opcode }, |
| 7185 | { "vphaddubw", { XM, EXxmm } }, |
| 7186 | { "vphaddubd", { XM, EXxmm } }, |
| 7187 | { "vphaddubq", { XM, EXxmm } }, |
| 7188 | { Bad_Opcode }, |
| 7189 | { Bad_Opcode }, |
| 7190 | { "vphadduwd", { XM, EXxmm } }, |
| 7191 | { "vphadduwq", { XM, EXxmm } }, |
| 7192 | /* d8 */ |
| 7193 | { Bad_Opcode }, |
| 7194 | { Bad_Opcode }, |
| 7195 | { Bad_Opcode }, |
| 7196 | { "vphaddudq", { XM, EXxmm } }, |
| 7197 | { Bad_Opcode }, |
| 7198 | { Bad_Opcode }, |
| 7199 | { Bad_Opcode }, |
| 7200 | { Bad_Opcode }, |
| 7201 | /* e0 */ |
| 7202 | { Bad_Opcode }, |
| 7203 | { "vphsubbw", { XM, EXxmm } }, |
| 7204 | { "vphsubwd", { XM, EXxmm } }, |
| 7205 | { "vphsubdq", { XM, EXxmm } }, |
| 7206 | { Bad_Opcode }, |
| 7207 | { Bad_Opcode }, |
| 7208 | { Bad_Opcode }, |
| 7209 | { Bad_Opcode }, |
| 7210 | /* e8 */ |
| 7211 | { Bad_Opcode }, |
| 7212 | { Bad_Opcode }, |
| 7213 | { Bad_Opcode }, |
| 7214 | { Bad_Opcode }, |
| 7215 | { Bad_Opcode }, |
| 7216 | { Bad_Opcode }, |
| 7217 | { Bad_Opcode }, |
| 7218 | { Bad_Opcode }, |
| 7219 | /* f0 */ |
| 7220 | { Bad_Opcode }, |
| 7221 | { Bad_Opcode }, |
| 7222 | { Bad_Opcode }, |
| 7223 | { Bad_Opcode }, |
| 7224 | { Bad_Opcode }, |
| 7225 | { Bad_Opcode }, |
| 7226 | { Bad_Opcode }, |
| 7227 | { Bad_Opcode }, |
| 7228 | /* f8 */ |
| 7229 | { Bad_Opcode }, |
| 7230 | { Bad_Opcode }, |
| 7231 | { Bad_Opcode }, |
| 7232 | { Bad_Opcode }, |
| 7233 | { Bad_Opcode }, |
| 7234 | { Bad_Opcode }, |
| 7235 | { Bad_Opcode }, |
| 7236 | { Bad_Opcode }, |
| 7237 | }, |
| 7238 | /* XOP_0A */ |
| 7239 | { |
| 7240 | /* 00 */ |
| 7241 | { Bad_Opcode }, |
| 7242 | { Bad_Opcode }, |
| 7243 | { Bad_Opcode }, |
| 7244 | { Bad_Opcode }, |
| 7245 | { Bad_Opcode }, |
| 7246 | { Bad_Opcode }, |
| 7247 | { Bad_Opcode }, |
| 7248 | { Bad_Opcode }, |
| 7249 | /* 08 */ |
| 7250 | { Bad_Opcode }, |
| 7251 | { Bad_Opcode }, |
| 7252 | { Bad_Opcode }, |
| 7253 | { Bad_Opcode }, |
| 7254 | { Bad_Opcode }, |
| 7255 | { Bad_Opcode }, |
| 7256 | { Bad_Opcode }, |
| 7257 | { Bad_Opcode }, |
| 7258 | /* 10 */ |
| 7259 | { "bextr", { Gv, Ev, Iq } }, |
| 7260 | { Bad_Opcode }, |
| 7261 | { REG_TABLE (REG_XOP_LWP) }, |
| 7262 | { Bad_Opcode }, |
| 7263 | { Bad_Opcode }, |
| 7264 | { Bad_Opcode }, |
| 7265 | { Bad_Opcode }, |
| 7266 | { Bad_Opcode }, |
| 7267 | /* 18 */ |
| 7268 | { Bad_Opcode }, |
| 7269 | { Bad_Opcode }, |
| 7270 | { Bad_Opcode }, |
| 7271 | { Bad_Opcode }, |
| 7272 | { Bad_Opcode }, |
| 7273 | { Bad_Opcode }, |
| 7274 | { Bad_Opcode }, |
| 7275 | { Bad_Opcode }, |
| 7276 | /* 20 */ |
| 7277 | { Bad_Opcode }, |
| 7278 | { Bad_Opcode }, |
| 7279 | { Bad_Opcode }, |
| 7280 | { Bad_Opcode }, |
| 7281 | { Bad_Opcode }, |
| 7282 | { Bad_Opcode }, |
| 7283 | { Bad_Opcode }, |
| 7284 | { Bad_Opcode }, |
| 7285 | /* 28 */ |
| 7286 | { Bad_Opcode }, |
| 7287 | { Bad_Opcode }, |
| 7288 | { Bad_Opcode }, |
| 7289 | { Bad_Opcode }, |
| 7290 | { Bad_Opcode }, |
| 7291 | { Bad_Opcode }, |
| 7292 | { Bad_Opcode }, |
| 7293 | { Bad_Opcode }, |
| 7294 | /* 30 */ |
| 7295 | { Bad_Opcode }, |
| 7296 | { Bad_Opcode }, |
| 7297 | { Bad_Opcode }, |
| 7298 | { Bad_Opcode }, |
| 7299 | { Bad_Opcode }, |
| 7300 | { Bad_Opcode }, |
| 7301 | { Bad_Opcode }, |
| 7302 | { Bad_Opcode }, |
| 7303 | /* 38 */ |
| 7304 | { Bad_Opcode }, |
| 7305 | { Bad_Opcode }, |
| 7306 | { Bad_Opcode }, |
| 7307 | { Bad_Opcode }, |
| 7308 | { Bad_Opcode }, |
| 7309 | { Bad_Opcode }, |
| 7310 | { Bad_Opcode }, |
| 7311 | { Bad_Opcode }, |
| 7312 | /* 40 */ |
| 7313 | { Bad_Opcode }, |
| 7314 | { Bad_Opcode }, |
| 7315 | { Bad_Opcode }, |
| 7316 | { Bad_Opcode }, |
| 7317 | { Bad_Opcode }, |
| 7318 | { Bad_Opcode }, |
| 7319 | { Bad_Opcode }, |
| 7320 | { Bad_Opcode }, |
| 7321 | /* 48 */ |
| 7322 | { Bad_Opcode }, |
| 7323 | { Bad_Opcode }, |
| 7324 | { Bad_Opcode }, |
| 7325 | { Bad_Opcode }, |
| 7326 | { Bad_Opcode }, |
| 7327 | { Bad_Opcode }, |
| 7328 | { Bad_Opcode }, |
| 7329 | { Bad_Opcode }, |
| 7330 | /* 50 */ |
| 7331 | { Bad_Opcode }, |
| 7332 | { Bad_Opcode }, |
| 7333 | { Bad_Opcode }, |
| 7334 | { Bad_Opcode }, |
| 7335 | { Bad_Opcode }, |
| 7336 | { Bad_Opcode }, |
| 7337 | { Bad_Opcode }, |
| 7338 | { Bad_Opcode }, |
| 7339 | /* 58 */ |
| 7340 | { Bad_Opcode }, |
| 7341 | { Bad_Opcode }, |
| 7342 | { Bad_Opcode }, |
| 7343 | { Bad_Opcode }, |
| 7344 | { Bad_Opcode }, |
| 7345 | { Bad_Opcode }, |
| 7346 | { Bad_Opcode }, |
| 7347 | { Bad_Opcode }, |
| 7348 | /* 60 */ |
| 7349 | { Bad_Opcode }, |
| 7350 | { Bad_Opcode }, |
| 7351 | { Bad_Opcode }, |
| 7352 | { Bad_Opcode }, |
| 7353 | { Bad_Opcode }, |
| 7354 | { Bad_Opcode }, |
| 7355 | { Bad_Opcode }, |
| 7356 | { Bad_Opcode }, |
| 7357 | /* 68 */ |
| 7358 | { Bad_Opcode }, |
| 7359 | { Bad_Opcode }, |
| 7360 | { Bad_Opcode }, |
| 7361 | { Bad_Opcode }, |
| 7362 | { Bad_Opcode }, |
| 7363 | { Bad_Opcode }, |
| 7364 | { Bad_Opcode }, |
| 7365 | { Bad_Opcode }, |
| 7366 | /* 70 */ |
| 7367 | { Bad_Opcode }, |
| 7368 | { Bad_Opcode }, |
| 7369 | { Bad_Opcode }, |
| 7370 | { Bad_Opcode }, |
| 7371 | { Bad_Opcode }, |
| 7372 | { Bad_Opcode }, |
| 7373 | { Bad_Opcode }, |
| 7374 | { Bad_Opcode }, |
| 7375 | /* 78 */ |
| 7376 | { Bad_Opcode }, |
| 7377 | { Bad_Opcode }, |
| 7378 | { Bad_Opcode }, |
| 7379 | { Bad_Opcode }, |
| 7380 | { Bad_Opcode }, |
| 7381 | { Bad_Opcode }, |
| 7382 | { Bad_Opcode }, |
| 7383 | { Bad_Opcode }, |
| 7384 | /* 80 */ |
| 7385 | { Bad_Opcode }, |
| 7386 | { Bad_Opcode }, |
| 7387 | { Bad_Opcode }, |
| 7388 | { Bad_Opcode }, |
| 7389 | { Bad_Opcode }, |
| 7390 | { Bad_Opcode }, |
| 7391 | { Bad_Opcode }, |
| 7392 | { Bad_Opcode }, |
| 7393 | /* 88 */ |
| 7394 | { Bad_Opcode }, |
| 7395 | { Bad_Opcode }, |
| 7396 | { Bad_Opcode }, |
| 7397 | { Bad_Opcode }, |
| 7398 | { Bad_Opcode }, |
| 7399 | { Bad_Opcode }, |
| 7400 | { Bad_Opcode }, |
| 7401 | { Bad_Opcode }, |
| 7402 | /* 90 */ |
| 7403 | { Bad_Opcode }, |
| 7404 | { Bad_Opcode }, |
| 7405 | { Bad_Opcode }, |
| 7406 | { Bad_Opcode }, |
| 7407 | { Bad_Opcode }, |
| 7408 | { Bad_Opcode }, |
| 7409 | { Bad_Opcode }, |
| 7410 | { Bad_Opcode }, |
| 7411 | /* 98 */ |
| 7412 | { Bad_Opcode }, |
| 7413 | { Bad_Opcode }, |
| 7414 | { Bad_Opcode }, |
| 7415 | { Bad_Opcode }, |
| 7416 | { Bad_Opcode }, |
| 7417 | { Bad_Opcode }, |
| 7418 | { Bad_Opcode }, |
| 7419 | { Bad_Opcode }, |
| 7420 | /* a0 */ |
| 7421 | { Bad_Opcode }, |
| 7422 | { Bad_Opcode }, |
| 7423 | { Bad_Opcode }, |
| 7424 | { Bad_Opcode }, |
| 7425 | { Bad_Opcode }, |
| 7426 | { Bad_Opcode }, |
| 7427 | { Bad_Opcode }, |
| 7428 | { Bad_Opcode }, |
| 7429 | /* a8 */ |
| 7430 | { Bad_Opcode }, |
| 7431 | { Bad_Opcode }, |
| 7432 | { Bad_Opcode }, |
| 7433 | { Bad_Opcode }, |
| 7434 | { Bad_Opcode }, |
| 7435 | { Bad_Opcode }, |
| 7436 | { Bad_Opcode }, |
| 7437 | { Bad_Opcode }, |
| 7438 | /* b0 */ |
| 7439 | { Bad_Opcode }, |
| 7440 | { Bad_Opcode }, |
| 7441 | { Bad_Opcode }, |
| 7442 | { Bad_Opcode }, |
| 7443 | { Bad_Opcode }, |
| 7444 | { Bad_Opcode }, |
| 7445 | { Bad_Opcode }, |
| 7446 | { Bad_Opcode }, |
| 7447 | /* b8 */ |
| 7448 | { Bad_Opcode }, |
| 7449 | { Bad_Opcode }, |
| 7450 | { Bad_Opcode }, |
| 7451 | { Bad_Opcode }, |
| 7452 | { Bad_Opcode }, |
| 7453 | { Bad_Opcode }, |
| 7454 | { Bad_Opcode }, |
| 7455 | { Bad_Opcode }, |
| 7456 | /* c0 */ |
| 7457 | { Bad_Opcode }, |
| 7458 | { Bad_Opcode }, |
| 7459 | { Bad_Opcode }, |
| 7460 | { Bad_Opcode }, |
| 7461 | { Bad_Opcode }, |
| 7462 | { Bad_Opcode }, |
| 7463 | { Bad_Opcode }, |
| 7464 | { Bad_Opcode }, |
| 7465 | /* c8 */ |
| 7466 | { Bad_Opcode }, |
| 7467 | { Bad_Opcode }, |
| 7468 | { Bad_Opcode }, |
| 7469 | { Bad_Opcode }, |
| 7470 | { Bad_Opcode }, |
| 7471 | { Bad_Opcode }, |
| 7472 | { Bad_Opcode }, |
| 7473 | { Bad_Opcode }, |
| 7474 | /* d0 */ |
| 7475 | { Bad_Opcode }, |
| 7476 | { Bad_Opcode }, |
| 7477 | { Bad_Opcode }, |
| 7478 | { Bad_Opcode }, |
| 7479 | { Bad_Opcode }, |
| 7480 | { Bad_Opcode }, |
| 7481 | { Bad_Opcode }, |
| 7482 | { Bad_Opcode }, |
| 7483 | /* d8 */ |
| 7484 | { Bad_Opcode }, |
| 7485 | { Bad_Opcode }, |
| 7486 | { Bad_Opcode }, |
| 7487 | { Bad_Opcode }, |
| 7488 | { Bad_Opcode }, |
| 7489 | { Bad_Opcode }, |
| 7490 | { Bad_Opcode }, |
| 7491 | { Bad_Opcode }, |
| 7492 | /* e0 */ |
| 7493 | { Bad_Opcode }, |
| 7494 | { Bad_Opcode }, |
| 7495 | { Bad_Opcode }, |
| 7496 | { Bad_Opcode }, |
| 7497 | { Bad_Opcode }, |
| 7498 | { Bad_Opcode }, |
| 7499 | { Bad_Opcode }, |
| 7500 | { Bad_Opcode }, |
| 7501 | /* e8 */ |
| 7502 | { Bad_Opcode }, |
| 7503 | { Bad_Opcode }, |
| 7504 | { Bad_Opcode }, |
| 7505 | { Bad_Opcode }, |
| 7506 | { Bad_Opcode }, |
| 7507 | { Bad_Opcode }, |
| 7508 | { Bad_Opcode }, |
| 7509 | { Bad_Opcode }, |
| 7510 | /* f0 */ |
| 7511 | { Bad_Opcode }, |
| 7512 | { Bad_Opcode }, |
| 7513 | { Bad_Opcode }, |
| 7514 | { Bad_Opcode }, |
| 7515 | { Bad_Opcode }, |
| 7516 | { Bad_Opcode }, |
| 7517 | { Bad_Opcode }, |
| 7518 | { Bad_Opcode }, |
| 7519 | /* f8 */ |
| 7520 | { Bad_Opcode }, |
| 7521 | { Bad_Opcode }, |
| 7522 | { Bad_Opcode }, |
| 7523 | { Bad_Opcode }, |
| 7524 | { Bad_Opcode }, |
| 7525 | { Bad_Opcode }, |
| 7526 | { Bad_Opcode }, |
| 7527 | { Bad_Opcode }, |
| 7528 | }, |
| 7529 | }; |
| 7530 | |
| 7531 | static const struct dis386 vex_table[][256] = { |
| 7532 | /* VEX_0F */ |
| 7533 | { |
| 7534 | /* 00 */ |
| 7535 | { Bad_Opcode }, |
| 7536 | { Bad_Opcode }, |
| 7537 | { Bad_Opcode }, |
| 7538 | { Bad_Opcode }, |
| 7539 | { Bad_Opcode }, |
| 7540 | { Bad_Opcode }, |
| 7541 | { Bad_Opcode }, |
| 7542 | { Bad_Opcode }, |
| 7543 | /* 08 */ |
| 7544 | { Bad_Opcode }, |
| 7545 | { Bad_Opcode }, |
| 7546 | { Bad_Opcode }, |
| 7547 | { Bad_Opcode }, |
| 7548 | { Bad_Opcode }, |
| 7549 | { Bad_Opcode }, |
| 7550 | { Bad_Opcode }, |
| 7551 | { Bad_Opcode }, |
| 7552 | /* 10 */ |
| 7553 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
| 7554 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, |
| 7555 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, |
| 7556 | { MOD_TABLE (MOD_VEX_0F13) }, |
| 7557 | { VEX_W_TABLE (VEX_W_0F14) }, |
| 7558 | { VEX_W_TABLE (VEX_W_0F15) }, |
| 7559 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
| 7560 | { MOD_TABLE (MOD_VEX_0F17) }, |
| 7561 | /* 18 */ |
| 7562 | { Bad_Opcode }, |
| 7563 | { Bad_Opcode }, |
| 7564 | { Bad_Opcode }, |
| 7565 | { Bad_Opcode }, |
| 7566 | { Bad_Opcode }, |
| 7567 | { Bad_Opcode }, |
| 7568 | { Bad_Opcode }, |
| 7569 | { Bad_Opcode }, |
| 7570 | /* 20 */ |
| 7571 | { Bad_Opcode }, |
| 7572 | { Bad_Opcode }, |
| 7573 | { Bad_Opcode }, |
| 7574 | { Bad_Opcode }, |
| 7575 | { Bad_Opcode }, |
| 7576 | { Bad_Opcode }, |
| 7577 | { Bad_Opcode }, |
| 7578 | { Bad_Opcode }, |
| 7579 | /* 28 */ |
| 7580 | { VEX_W_TABLE (VEX_W_0F28) }, |
| 7581 | { VEX_W_TABLE (VEX_W_0F29) }, |
| 7582 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
| 7583 | { MOD_TABLE (MOD_VEX_0F2B) }, |
| 7584 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, |
| 7585 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, |
| 7586 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, |
| 7587 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, |
| 7588 | /* 30 */ |
| 7589 | { Bad_Opcode }, |
| 7590 | { Bad_Opcode }, |
| 7591 | { Bad_Opcode }, |
| 7592 | { Bad_Opcode }, |
| 7593 | { Bad_Opcode }, |
| 7594 | { Bad_Opcode }, |
| 7595 | { Bad_Opcode }, |
| 7596 | { Bad_Opcode }, |
| 7597 | /* 38 */ |
| 7598 | { Bad_Opcode }, |
| 7599 | { Bad_Opcode }, |
| 7600 | { Bad_Opcode }, |
| 7601 | { Bad_Opcode }, |
| 7602 | { Bad_Opcode }, |
| 7603 | { Bad_Opcode }, |
| 7604 | { Bad_Opcode }, |
| 7605 | { Bad_Opcode }, |
| 7606 | /* 40 */ |
| 7607 | { Bad_Opcode }, |
| 7608 | { Bad_Opcode }, |
| 7609 | { Bad_Opcode }, |
| 7610 | { Bad_Opcode }, |
| 7611 | { Bad_Opcode }, |
| 7612 | { Bad_Opcode }, |
| 7613 | { Bad_Opcode }, |
| 7614 | { Bad_Opcode }, |
| 7615 | /* 48 */ |
| 7616 | { Bad_Opcode }, |
| 7617 | { Bad_Opcode }, |
| 7618 | { Bad_Opcode }, |
| 7619 | { Bad_Opcode }, |
| 7620 | { Bad_Opcode }, |
| 7621 | { Bad_Opcode }, |
| 7622 | { Bad_Opcode }, |
| 7623 | { Bad_Opcode }, |
| 7624 | /* 50 */ |
| 7625 | { MOD_TABLE (MOD_VEX_0F50) }, |
| 7626 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, |
| 7627 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, |
| 7628 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, |
| 7629 | { "vandpX", { XM, Vex, EXx } }, |
| 7630 | { "vandnpX", { XM, Vex, EXx } }, |
| 7631 | { "vorpX", { XM, Vex, EXx } }, |
| 7632 | { "vxorpX", { XM, Vex, EXx } }, |
| 7633 | /* 58 */ |
| 7634 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
| 7635 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, |
| 7636 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, |
| 7637 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, |
| 7638 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, |
| 7639 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, |
| 7640 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, |
| 7641 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, |
| 7642 | /* 60 */ |
| 7643 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
| 7644 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, |
| 7645 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, |
| 7646 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, |
| 7647 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, |
| 7648 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, |
| 7649 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, |
| 7650 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, |
| 7651 | /* 68 */ |
| 7652 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
| 7653 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, |
| 7654 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, |
| 7655 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, |
| 7656 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, |
| 7657 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, |
| 7658 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, |
| 7659 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
| 7660 | /* 70 */ |
| 7661 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
| 7662 | { REG_TABLE (REG_VEX_0F71) }, |
| 7663 | { REG_TABLE (REG_VEX_0F72) }, |
| 7664 | { REG_TABLE (REG_VEX_0F73) }, |
| 7665 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, |
| 7666 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, |
| 7667 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, |
| 7668 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, |
| 7669 | /* 78 */ |
| 7670 | { Bad_Opcode }, |
| 7671 | { Bad_Opcode }, |
| 7672 | { Bad_Opcode }, |
| 7673 | { Bad_Opcode }, |
| 7674 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
| 7675 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, |
| 7676 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, |
| 7677 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, |
| 7678 | /* 80 */ |
| 7679 | { Bad_Opcode }, |
| 7680 | { Bad_Opcode }, |
| 7681 | { Bad_Opcode }, |
| 7682 | { Bad_Opcode }, |
| 7683 | { Bad_Opcode }, |
| 7684 | { Bad_Opcode }, |
| 7685 | { Bad_Opcode }, |
| 7686 | { Bad_Opcode }, |
| 7687 | /* 88 */ |
| 7688 | { Bad_Opcode }, |
| 7689 | { Bad_Opcode }, |
| 7690 | { Bad_Opcode }, |
| 7691 | { Bad_Opcode }, |
| 7692 | { Bad_Opcode }, |
| 7693 | { Bad_Opcode }, |
| 7694 | { Bad_Opcode }, |
| 7695 | { Bad_Opcode }, |
| 7696 | /* 90 */ |
| 7697 | { Bad_Opcode }, |
| 7698 | { Bad_Opcode }, |
| 7699 | { Bad_Opcode }, |
| 7700 | { Bad_Opcode }, |
| 7701 | { Bad_Opcode }, |
| 7702 | { Bad_Opcode }, |
| 7703 | { Bad_Opcode }, |
| 7704 | { Bad_Opcode }, |
| 7705 | /* 98 */ |
| 7706 | { Bad_Opcode }, |
| 7707 | { Bad_Opcode }, |
| 7708 | { Bad_Opcode }, |
| 7709 | { Bad_Opcode }, |
| 7710 | { Bad_Opcode }, |
| 7711 | { Bad_Opcode }, |
| 7712 | { Bad_Opcode }, |
| 7713 | { Bad_Opcode }, |
| 7714 | /* a0 */ |
| 7715 | { Bad_Opcode }, |
| 7716 | { Bad_Opcode }, |
| 7717 | { Bad_Opcode }, |
| 7718 | { Bad_Opcode }, |
| 7719 | { Bad_Opcode }, |
| 7720 | { Bad_Opcode }, |
| 7721 | { Bad_Opcode }, |
| 7722 | { Bad_Opcode }, |
| 7723 | /* a8 */ |
| 7724 | { Bad_Opcode }, |
| 7725 | { Bad_Opcode }, |
| 7726 | { Bad_Opcode }, |
| 7727 | { Bad_Opcode }, |
| 7728 | { Bad_Opcode }, |
| 7729 | { Bad_Opcode }, |
| 7730 | { REG_TABLE (REG_VEX_0FAE) }, |
| 7731 | { Bad_Opcode }, |
| 7732 | /* b0 */ |
| 7733 | { Bad_Opcode }, |
| 7734 | { Bad_Opcode }, |
| 7735 | { Bad_Opcode }, |
| 7736 | { Bad_Opcode }, |
| 7737 | { Bad_Opcode }, |
| 7738 | { Bad_Opcode }, |
| 7739 | { Bad_Opcode }, |
| 7740 | { Bad_Opcode }, |
| 7741 | /* b8 */ |
| 7742 | { Bad_Opcode }, |
| 7743 | { Bad_Opcode }, |
| 7744 | { Bad_Opcode }, |
| 7745 | { Bad_Opcode }, |
| 7746 | { Bad_Opcode }, |
| 7747 | { Bad_Opcode }, |
| 7748 | { Bad_Opcode }, |
| 7749 | { Bad_Opcode }, |
| 7750 | /* c0 */ |
| 7751 | { Bad_Opcode }, |
| 7752 | { Bad_Opcode }, |
| 7753 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
| 7754 | { Bad_Opcode }, |
| 7755 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
| 7756 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, |
| 7757 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
| 7758 | { Bad_Opcode }, |
| 7759 | /* c8 */ |
| 7760 | { Bad_Opcode }, |
| 7761 | { Bad_Opcode }, |
| 7762 | { Bad_Opcode }, |
| 7763 | { Bad_Opcode }, |
| 7764 | { Bad_Opcode }, |
| 7765 | { Bad_Opcode }, |
| 7766 | { Bad_Opcode }, |
| 7767 | { Bad_Opcode }, |
| 7768 | /* d0 */ |
| 7769 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
| 7770 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, |
| 7771 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, |
| 7772 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, |
| 7773 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, |
| 7774 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, |
| 7775 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, |
| 7776 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, |
| 7777 | /* d8 */ |
| 7778 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
| 7779 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, |
| 7780 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, |
| 7781 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, |
| 7782 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, |
| 7783 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, |
| 7784 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, |
| 7785 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, |
| 7786 | /* e0 */ |
| 7787 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
| 7788 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, |
| 7789 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, |
| 7790 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, |
| 7791 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, |
| 7792 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, |
| 7793 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
| 7794 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, |
| 7795 | /* e8 */ |
| 7796 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
| 7797 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, |
| 7798 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, |
| 7799 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, |
| 7800 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, |
| 7801 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, |
| 7802 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, |
| 7803 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, |
| 7804 | /* f0 */ |
| 7805 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
| 7806 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, |
| 7807 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, |
| 7808 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, |
| 7809 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, |
| 7810 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, |
| 7811 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, |
| 7812 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, |
| 7813 | /* f8 */ |
| 7814 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
| 7815 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, |
| 7816 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, |
| 7817 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, |
| 7818 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, |
| 7819 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, |
| 7820 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, |
| 7821 | { Bad_Opcode }, |
| 7822 | }, |
| 7823 | /* VEX_0F38 */ |
| 7824 | { |
| 7825 | /* 00 */ |
| 7826 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
| 7827 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, |
| 7828 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, |
| 7829 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, |
| 7830 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, |
| 7831 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, |
| 7832 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, |
| 7833 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, |
| 7834 | /* 08 */ |
| 7835 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
| 7836 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, |
| 7837 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, |
| 7838 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, |
| 7839 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, |
| 7840 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, |
| 7841 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, |
| 7842 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, |
| 7843 | /* 10 */ |
| 7844 | { Bad_Opcode }, |
| 7845 | { Bad_Opcode }, |
| 7846 | { Bad_Opcode }, |
| 7847 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
| 7848 | { Bad_Opcode }, |
| 7849 | { Bad_Opcode }, |
| 7850 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
| 7851 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
| 7852 | /* 18 */ |
| 7853 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
| 7854 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, |
| 7855 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, |
| 7856 | { Bad_Opcode }, |
| 7857 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
| 7858 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, |
| 7859 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, |
| 7860 | { Bad_Opcode }, |
| 7861 | /* 20 */ |
| 7862 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
| 7863 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, |
| 7864 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, |
| 7865 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, |
| 7866 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, |
| 7867 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, |
| 7868 | { Bad_Opcode }, |
| 7869 | { Bad_Opcode }, |
| 7870 | /* 28 */ |
| 7871 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
| 7872 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, |
| 7873 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, |
| 7874 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, |
| 7875 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, |
| 7876 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, |
| 7877 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, |
| 7878 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, |
| 7879 | /* 30 */ |
| 7880 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
| 7881 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, |
| 7882 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, |
| 7883 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, |
| 7884 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, |
| 7885 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, |
| 7886 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
| 7887 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
| 7888 | /* 38 */ |
| 7889 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
| 7890 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, |
| 7891 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, |
| 7892 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, |
| 7893 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, |
| 7894 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, |
| 7895 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, |
| 7896 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, |
| 7897 | /* 40 */ |
| 7898 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
| 7899 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, |
| 7900 | { Bad_Opcode }, |
| 7901 | { Bad_Opcode }, |
| 7902 | { Bad_Opcode }, |
| 7903 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
| 7904 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, |
| 7905 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, |
| 7906 | /* 48 */ |
| 7907 | { Bad_Opcode }, |
| 7908 | { Bad_Opcode }, |
| 7909 | { Bad_Opcode }, |
| 7910 | { Bad_Opcode }, |
| 7911 | { Bad_Opcode }, |
| 7912 | { Bad_Opcode }, |
| 7913 | { Bad_Opcode }, |
| 7914 | { Bad_Opcode }, |
| 7915 | /* 50 */ |
| 7916 | { Bad_Opcode }, |
| 7917 | { Bad_Opcode }, |
| 7918 | { Bad_Opcode }, |
| 7919 | { Bad_Opcode }, |
| 7920 | { Bad_Opcode }, |
| 7921 | { Bad_Opcode }, |
| 7922 | { Bad_Opcode }, |
| 7923 | { Bad_Opcode }, |
| 7924 | /* 58 */ |
| 7925 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
| 7926 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, |
| 7927 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, |
| 7928 | { Bad_Opcode }, |
| 7929 | { Bad_Opcode }, |
| 7930 | { Bad_Opcode }, |
| 7931 | { Bad_Opcode }, |
| 7932 | { Bad_Opcode }, |
| 7933 | /* 60 */ |
| 7934 | { Bad_Opcode }, |
| 7935 | { Bad_Opcode }, |
| 7936 | { Bad_Opcode }, |
| 7937 | { Bad_Opcode }, |
| 7938 | { Bad_Opcode }, |
| 7939 | { Bad_Opcode }, |
| 7940 | { Bad_Opcode }, |
| 7941 | { Bad_Opcode }, |
| 7942 | /* 68 */ |
| 7943 | { Bad_Opcode }, |
| 7944 | { Bad_Opcode }, |
| 7945 | { Bad_Opcode }, |
| 7946 | { Bad_Opcode }, |
| 7947 | { Bad_Opcode }, |
| 7948 | { Bad_Opcode }, |
| 7949 | { Bad_Opcode }, |
| 7950 | { Bad_Opcode }, |
| 7951 | /* 70 */ |
| 7952 | { Bad_Opcode }, |
| 7953 | { Bad_Opcode }, |
| 7954 | { Bad_Opcode }, |
| 7955 | { Bad_Opcode }, |
| 7956 | { Bad_Opcode }, |
| 7957 | { Bad_Opcode }, |
| 7958 | { Bad_Opcode }, |
| 7959 | { Bad_Opcode }, |
| 7960 | /* 78 */ |
| 7961 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
| 7962 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, |
| 7963 | { Bad_Opcode }, |
| 7964 | { Bad_Opcode }, |
| 7965 | { Bad_Opcode }, |
| 7966 | { Bad_Opcode }, |
| 7967 | { Bad_Opcode }, |
| 7968 | { Bad_Opcode }, |
| 7969 | /* 80 */ |
| 7970 | { Bad_Opcode }, |
| 7971 | { Bad_Opcode }, |
| 7972 | { Bad_Opcode }, |
| 7973 | { Bad_Opcode }, |
| 7974 | { Bad_Opcode }, |
| 7975 | { Bad_Opcode }, |
| 7976 | { Bad_Opcode }, |
| 7977 | { Bad_Opcode }, |
| 7978 | /* 88 */ |
| 7979 | { Bad_Opcode }, |
| 7980 | { Bad_Opcode }, |
| 7981 | { Bad_Opcode }, |
| 7982 | { Bad_Opcode }, |
| 7983 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
| 7984 | { Bad_Opcode }, |
| 7985 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
| 7986 | { Bad_Opcode }, |
| 7987 | /* 90 */ |
| 7988 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
| 7989 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, |
| 7990 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, |
| 7991 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, |
| 7992 | { Bad_Opcode }, |
| 7993 | { Bad_Opcode }, |
| 7994 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
| 7995 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, |
| 7996 | /* 98 */ |
| 7997 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
| 7998 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, |
| 7999 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, |
| 8000 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, |
| 8001 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, |
| 8002 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, |
| 8003 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, |
| 8004 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, |
| 8005 | /* a0 */ |
| 8006 | { Bad_Opcode }, |
| 8007 | { Bad_Opcode }, |
| 8008 | { Bad_Opcode }, |
| 8009 | { Bad_Opcode }, |
| 8010 | { Bad_Opcode }, |
| 8011 | { Bad_Opcode }, |
| 8012 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
| 8013 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, |
| 8014 | /* a8 */ |
| 8015 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
| 8016 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, |
| 8017 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, |
| 8018 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, |
| 8019 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, |
| 8020 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, |
| 8021 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, |
| 8022 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, |
| 8023 | /* b0 */ |
| 8024 | { Bad_Opcode }, |
| 8025 | { Bad_Opcode }, |
| 8026 | { Bad_Opcode }, |
| 8027 | { Bad_Opcode }, |
| 8028 | { Bad_Opcode }, |
| 8029 | { Bad_Opcode }, |
| 8030 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
| 8031 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, |
| 8032 | /* b8 */ |
| 8033 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
| 8034 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, |
| 8035 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, |
| 8036 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, |
| 8037 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, |
| 8038 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, |
| 8039 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, |
| 8040 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, |
| 8041 | /* c0 */ |
| 8042 | { Bad_Opcode }, |
| 8043 | { Bad_Opcode }, |
| 8044 | { Bad_Opcode }, |
| 8045 | { Bad_Opcode }, |
| 8046 | { Bad_Opcode }, |
| 8047 | { Bad_Opcode }, |
| 8048 | { Bad_Opcode }, |
| 8049 | { Bad_Opcode }, |
| 8050 | /* c8 */ |
| 8051 | { Bad_Opcode }, |
| 8052 | { Bad_Opcode }, |
| 8053 | { Bad_Opcode }, |
| 8054 | { Bad_Opcode }, |
| 8055 | { Bad_Opcode }, |
| 8056 | { Bad_Opcode }, |
| 8057 | { Bad_Opcode }, |
| 8058 | { Bad_Opcode }, |
| 8059 | /* d0 */ |
| 8060 | { Bad_Opcode }, |
| 8061 | { Bad_Opcode }, |
| 8062 | { Bad_Opcode }, |
| 8063 | { Bad_Opcode }, |
| 8064 | { Bad_Opcode }, |
| 8065 | { Bad_Opcode }, |
| 8066 | { Bad_Opcode }, |
| 8067 | { Bad_Opcode }, |
| 8068 | /* d8 */ |
| 8069 | { Bad_Opcode }, |
| 8070 | { Bad_Opcode }, |
| 8071 | { Bad_Opcode }, |
| 8072 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
| 8073 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, |
| 8074 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, |
| 8075 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, |
| 8076 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, |
| 8077 | /* e0 */ |
| 8078 | { Bad_Opcode }, |
| 8079 | { Bad_Opcode }, |
| 8080 | { Bad_Opcode }, |
| 8081 | { Bad_Opcode }, |
| 8082 | { Bad_Opcode }, |
| 8083 | { Bad_Opcode }, |
| 8084 | { Bad_Opcode }, |
| 8085 | { Bad_Opcode }, |
| 8086 | /* e8 */ |
| 8087 | { Bad_Opcode }, |
| 8088 | { Bad_Opcode }, |
| 8089 | { Bad_Opcode }, |
| 8090 | { Bad_Opcode }, |
| 8091 | { Bad_Opcode }, |
| 8092 | { Bad_Opcode }, |
| 8093 | { Bad_Opcode }, |
| 8094 | { Bad_Opcode }, |
| 8095 | /* f0 */ |
| 8096 | { Bad_Opcode }, |
| 8097 | { Bad_Opcode }, |
| 8098 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
| 8099 | { REG_TABLE (REG_VEX_0F38F3) }, |
| 8100 | { Bad_Opcode }, |
| 8101 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
| 8102 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, |
| 8103 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
| 8104 | /* f8 */ |
| 8105 | { Bad_Opcode }, |
| 8106 | { Bad_Opcode }, |
| 8107 | { Bad_Opcode }, |
| 8108 | { Bad_Opcode }, |
| 8109 | { Bad_Opcode }, |
| 8110 | { Bad_Opcode }, |
| 8111 | { Bad_Opcode }, |
| 8112 | { Bad_Opcode }, |
| 8113 | }, |
| 8114 | /* VEX_0F3A */ |
| 8115 | { |
| 8116 | /* 00 */ |
| 8117 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
| 8118 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, |
| 8119 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, |
| 8120 | { Bad_Opcode }, |
| 8121 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
| 8122 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, |
| 8123 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, |
| 8124 | { Bad_Opcode }, |
| 8125 | /* 08 */ |
| 8126 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
| 8127 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, |
| 8128 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, |
| 8129 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, |
| 8130 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, |
| 8131 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, |
| 8132 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, |
| 8133 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, |
| 8134 | /* 10 */ |
| 8135 | { Bad_Opcode }, |
| 8136 | { Bad_Opcode }, |
| 8137 | { Bad_Opcode }, |
| 8138 | { Bad_Opcode }, |
| 8139 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
| 8140 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, |
| 8141 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, |
| 8142 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, |
| 8143 | /* 18 */ |
| 8144 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
| 8145 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, |
| 8146 | { Bad_Opcode }, |
| 8147 | { Bad_Opcode }, |
| 8148 | { Bad_Opcode }, |
| 8149 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
| 8150 | { Bad_Opcode }, |
| 8151 | { Bad_Opcode }, |
| 8152 | /* 20 */ |
| 8153 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
| 8154 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, |
| 8155 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, |
| 8156 | { Bad_Opcode }, |
| 8157 | { Bad_Opcode }, |
| 8158 | { Bad_Opcode }, |
| 8159 | { Bad_Opcode }, |
| 8160 | { Bad_Opcode }, |
| 8161 | /* 28 */ |
| 8162 | { Bad_Opcode }, |
| 8163 | { Bad_Opcode }, |
| 8164 | { Bad_Opcode }, |
| 8165 | { Bad_Opcode }, |
| 8166 | { Bad_Opcode }, |
| 8167 | { Bad_Opcode }, |
| 8168 | { Bad_Opcode }, |
| 8169 | { Bad_Opcode }, |
| 8170 | /* 30 */ |
| 8171 | { Bad_Opcode }, |
| 8172 | { Bad_Opcode }, |
| 8173 | { Bad_Opcode }, |
| 8174 | { Bad_Opcode }, |
| 8175 | { Bad_Opcode }, |
| 8176 | { Bad_Opcode }, |
| 8177 | { Bad_Opcode }, |
| 8178 | { Bad_Opcode }, |
| 8179 | /* 38 */ |
| 8180 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
| 8181 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, |
| 8182 | { Bad_Opcode }, |
| 8183 | { Bad_Opcode }, |
| 8184 | { Bad_Opcode }, |
| 8185 | { Bad_Opcode }, |
| 8186 | { Bad_Opcode }, |
| 8187 | { Bad_Opcode }, |
| 8188 | /* 40 */ |
| 8189 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
| 8190 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, |
| 8191 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, |
| 8192 | { Bad_Opcode }, |
| 8193 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
| 8194 | { Bad_Opcode }, |
| 8195 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
| 8196 | { Bad_Opcode }, |
| 8197 | /* 48 */ |
| 8198 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
| 8199 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, |
| 8200 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, |
| 8201 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, |
| 8202 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, |
| 8203 | { Bad_Opcode }, |
| 8204 | { Bad_Opcode }, |
| 8205 | { Bad_Opcode }, |
| 8206 | /* 50 */ |
| 8207 | { Bad_Opcode }, |
| 8208 | { Bad_Opcode }, |
| 8209 | { Bad_Opcode }, |
| 8210 | { Bad_Opcode }, |
| 8211 | { Bad_Opcode }, |
| 8212 | { Bad_Opcode }, |
| 8213 | { Bad_Opcode }, |
| 8214 | { Bad_Opcode }, |
| 8215 | /* 58 */ |
| 8216 | { Bad_Opcode }, |
| 8217 | { Bad_Opcode }, |
| 8218 | { Bad_Opcode }, |
| 8219 | { Bad_Opcode }, |
| 8220 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
| 8221 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, |
| 8222 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, |
| 8223 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, |
| 8224 | /* 60 */ |
| 8225 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
| 8226 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, |
| 8227 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, |
| 8228 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, |
| 8229 | { Bad_Opcode }, |
| 8230 | { Bad_Opcode }, |
| 8231 | { Bad_Opcode }, |
| 8232 | { Bad_Opcode }, |
| 8233 | /* 68 */ |
| 8234 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
| 8235 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, |
| 8236 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, |
| 8237 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, |
| 8238 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, |
| 8239 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, |
| 8240 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, |
| 8241 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, |
| 8242 | /* 70 */ |
| 8243 | { Bad_Opcode }, |
| 8244 | { Bad_Opcode }, |
| 8245 | { Bad_Opcode }, |
| 8246 | { Bad_Opcode }, |
| 8247 | { Bad_Opcode }, |
| 8248 | { Bad_Opcode }, |
| 8249 | { Bad_Opcode }, |
| 8250 | { Bad_Opcode }, |
| 8251 | /* 78 */ |
| 8252 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
| 8253 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, |
| 8254 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, |
| 8255 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, |
| 8256 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, |
| 8257 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, |
| 8258 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, |
| 8259 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, |
| 8260 | /* 80 */ |
| 8261 | { Bad_Opcode }, |
| 8262 | { Bad_Opcode }, |
| 8263 | { Bad_Opcode }, |
| 8264 | { Bad_Opcode }, |
| 8265 | { Bad_Opcode }, |
| 8266 | { Bad_Opcode }, |
| 8267 | { Bad_Opcode }, |
| 8268 | { Bad_Opcode }, |
| 8269 | /* 88 */ |
| 8270 | { Bad_Opcode }, |
| 8271 | { Bad_Opcode }, |
| 8272 | { Bad_Opcode }, |
| 8273 | { Bad_Opcode }, |
| 8274 | { Bad_Opcode }, |
| 8275 | { Bad_Opcode }, |
| 8276 | { Bad_Opcode }, |
| 8277 | { Bad_Opcode }, |
| 8278 | /* 90 */ |
| 8279 | { Bad_Opcode }, |
| 8280 | { Bad_Opcode }, |
| 8281 | { Bad_Opcode }, |
| 8282 | { Bad_Opcode }, |
| 8283 | { Bad_Opcode }, |
| 8284 | { Bad_Opcode }, |
| 8285 | { Bad_Opcode }, |
| 8286 | { Bad_Opcode }, |
| 8287 | /* 98 */ |
| 8288 | { Bad_Opcode }, |
| 8289 | { Bad_Opcode }, |
| 8290 | { Bad_Opcode }, |
| 8291 | { Bad_Opcode }, |
| 8292 | { Bad_Opcode }, |
| 8293 | { Bad_Opcode }, |
| 8294 | { Bad_Opcode }, |
| 8295 | { Bad_Opcode }, |
| 8296 | /* a0 */ |
| 8297 | { Bad_Opcode }, |
| 8298 | { Bad_Opcode }, |
| 8299 | { Bad_Opcode }, |
| 8300 | { Bad_Opcode }, |
| 8301 | { Bad_Opcode }, |
| 8302 | { Bad_Opcode }, |
| 8303 | { Bad_Opcode }, |
| 8304 | { Bad_Opcode }, |
| 8305 | /* a8 */ |
| 8306 | { Bad_Opcode }, |
| 8307 | { Bad_Opcode }, |
| 8308 | { Bad_Opcode }, |
| 8309 | { Bad_Opcode }, |
| 8310 | { Bad_Opcode }, |
| 8311 | { Bad_Opcode }, |
| 8312 | { Bad_Opcode }, |
| 8313 | { Bad_Opcode }, |
| 8314 | /* b0 */ |
| 8315 | { Bad_Opcode }, |
| 8316 | { Bad_Opcode }, |
| 8317 | { Bad_Opcode }, |
| 8318 | { Bad_Opcode }, |
| 8319 | { Bad_Opcode }, |
| 8320 | { Bad_Opcode }, |
| 8321 | { Bad_Opcode }, |
| 8322 | { Bad_Opcode }, |
| 8323 | /* b8 */ |
| 8324 | { Bad_Opcode }, |
| 8325 | { Bad_Opcode }, |
| 8326 | { Bad_Opcode }, |
| 8327 | { Bad_Opcode }, |
| 8328 | { Bad_Opcode }, |
| 8329 | { Bad_Opcode }, |
| 8330 | { Bad_Opcode }, |
| 8331 | { Bad_Opcode }, |
| 8332 | /* c0 */ |
| 8333 | { Bad_Opcode }, |
| 8334 | { Bad_Opcode }, |
| 8335 | { Bad_Opcode }, |
| 8336 | { Bad_Opcode }, |
| 8337 | { Bad_Opcode }, |
| 8338 | { Bad_Opcode }, |
| 8339 | { Bad_Opcode }, |
| 8340 | { Bad_Opcode }, |
| 8341 | /* c8 */ |
| 8342 | { Bad_Opcode }, |
| 8343 | { Bad_Opcode }, |
| 8344 | { Bad_Opcode }, |
| 8345 | { Bad_Opcode }, |
| 8346 | { Bad_Opcode }, |
| 8347 | { Bad_Opcode }, |
| 8348 | { Bad_Opcode }, |
| 8349 | { Bad_Opcode }, |
| 8350 | /* d0 */ |
| 8351 | { Bad_Opcode }, |
| 8352 | { Bad_Opcode }, |
| 8353 | { Bad_Opcode }, |
| 8354 | { Bad_Opcode }, |
| 8355 | { Bad_Opcode }, |
| 8356 | { Bad_Opcode }, |
| 8357 | { Bad_Opcode }, |
| 8358 | { Bad_Opcode }, |
| 8359 | /* d8 */ |
| 8360 | { Bad_Opcode }, |
| 8361 | { Bad_Opcode }, |
| 8362 | { Bad_Opcode }, |
| 8363 | { Bad_Opcode }, |
| 8364 | { Bad_Opcode }, |
| 8365 | { Bad_Opcode }, |
| 8366 | { Bad_Opcode }, |
| 8367 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
| 8368 | /* e0 */ |
| 8369 | { Bad_Opcode }, |
| 8370 | { Bad_Opcode }, |
| 8371 | { Bad_Opcode }, |
| 8372 | { Bad_Opcode }, |
| 8373 | { Bad_Opcode }, |
| 8374 | { Bad_Opcode }, |
| 8375 | { Bad_Opcode }, |
| 8376 | { Bad_Opcode }, |
| 8377 | /* e8 */ |
| 8378 | { Bad_Opcode }, |
| 8379 | { Bad_Opcode }, |
| 8380 | { Bad_Opcode }, |
| 8381 | { Bad_Opcode }, |
| 8382 | { Bad_Opcode }, |
| 8383 | { Bad_Opcode }, |
| 8384 | { Bad_Opcode }, |
| 8385 | { Bad_Opcode }, |
| 8386 | /* f0 */ |
| 8387 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
| 8388 | { Bad_Opcode }, |
| 8389 | { Bad_Opcode }, |
| 8390 | { Bad_Opcode }, |
| 8391 | { Bad_Opcode }, |
| 8392 | { Bad_Opcode }, |
| 8393 | { Bad_Opcode }, |
| 8394 | { Bad_Opcode }, |
| 8395 | /* f8 */ |
| 8396 | { Bad_Opcode }, |
| 8397 | { Bad_Opcode }, |
| 8398 | { Bad_Opcode }, |
| 8399 | { Bad_Opcode }, |
| 8400 | { Bad_Opcode }, |
| 8401 | { Bad_Opcode }, |
| 8402 | { Bad_Opcode }, |
| 8403 | { Bad_Opcode }, |
| 8404 | }, |
| 8405 | }; |
| 8406 | |
| 8407 | static const struct dis386 vex_len_table[][2] = { |
| 8408 | /* VEX_LEN_0F10_P_1 */ |
| 8409 | { |
| 8410 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
| 8411 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
| 8412 | }, |
| 8413 | |
| 8414 | /* VEX_LEN_0F10_P_3 */ |
| 8415 | { |
| 8416 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
| 8417 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
| 8418 | }, |
| 8419 | |
| 8420 | /* VEX_LEN_0F11_P_1 */ |
| 8421 | { |
| 8422 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
| 8423 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
| 8424 | }, |
| 8425 | |
| 8426 | /* VEX_LEN_0F11_P_3 */ |
| 8427 | { |
| 8428 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
| 8429 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
| 8430 | }, |
| 8431 | |
| 8432 | /* VEX_LEN_0F12_P_0_M_0 */ |
| 8433 | { |
| 8434 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
| 8435 | }, |
| 8436 | |
| 8437 | /* VEX_LEN_0F12_P_0_M_1 */ |
| 8438 | { |
| 8439 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
| 8440 | }, |
| 8441 | |
| 8442 | /* VEX_LEN_0F12_P_2 */ |
| 8443 | { |
| 8444 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
| 8445 | }, |
| 8446 | |
| 8447 | /* VEX_LEN_0F13_M_0 */ |
| 8448 | { |
| 8449 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
| 8450 | }, |
| 8451 | |
| 8452 | /* VEX_LEN_0F16_P_0_M_0 */ |
| 8453 | { |
| 8454 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
| 8455 | }, |
| 8456 | |
| 8457 | /* VEX_LEN_0F16_P_0_M_1 */ |
| 8458 | { |
| 8459 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
| 8460 | }, |
| 8461 | |
| 8462 | /* VEX_LEN_0F16_P_2 */ |
| 8463 | { |
| 8464 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
| 8465 | }, |
| 8466 | |
| 8467 | /* VEX_LEN_0F17_M_0 */ |
| 8468 | { |
| 8469 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
| 8470 | }, |
| 8471 | |
| 8472 | /* VEX_LEN_0F2A_P_1 */ |
| 8473 | { |
| 8474 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
| 8475 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
| 8476 | }, |
| 8477 | |
| 8478 | /* VEX_LEN_0F2A_P_3 */ |
| 8479 | { |
| 8480 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
| 8481 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
| 8482 | }, |
| 8483 | |
| 8484 | /* VEX_LEN_0F2C_P_1 */ |
| 8485 | { |
| 8486 | { "vcvttss2siY", { Gv, EXdScalar } }, |
| 8487 | { "vcvttss2siY", { Gv, EXdScalar } }, |
| 8488 | }, |
| 8489 | |
| 8490 | /* VEX_LEN_0F2C_P_3 */ |
| 8491 | { |
| 8492 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
| 8493 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
| 8494 | }, |
| 8495 | |
| 8496 | /* VEX_LEN_0F2D_P_1 */ |
| 8497 | { |
| 8498 | { "vcvtss2siY", { Gv, EXdScalar } }, |
| 8499 | { "vcvtss2siY", { Gv, EXdScalar } }, |
| 8500 | }, |
| 8501 | |
| 8502 | /* VEX_LEN_0F2D_P_3 */ |
| 8503 | { |
| 8504 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
| 8505 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
| 8506 | }, |
| 8507 | |
| 8508 | /* VEX_LEN_0F2E_P_0 */ |
| 8509 | { |
| 8510 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
| 8511 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
| 8512 | }, |
| 8513 | |
| 8514 | /* VEX_LEN_0F2E_P_2 */ |
| 8515 | { |
| 8516 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
| 8517 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
| 8518 | }, |
| 8519 | |
| 8520 | /* VEX_LEN_0F2F_P_0 */ |
| 8521 | { |
| 8522 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
| 8523 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
| 8524 | }, |
| 8525 | |
| 8526 | /* VEX_LEN_0F2F_P_2 */ |
| 8527 | { |
| 8528 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
| 8529 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
| 8530 | }, |
| 8531 | |
| 8532 | /* VEX_LEN_0F51_P_1 */ |
| 8533 | { |
| 8534 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
| 8535 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
| 8536 | }, |
| 8537 | |
| 8538 | /* VEX_LEN_0F51_P_3 */ |
| 8539 | { |
| 8540 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
| 8541 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
| 8542 | }, |
| 8543 | |
| 8544 | /* VEX_LEN_0F52_P_1 */ |
| 8545 | { |
| 8546 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
| 8547 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
| 8548 | }, |
| 8549 | |
| 8550 | /* VEX_LEN_0F53_P_1 */ |
| 8551 | { |
| 8552 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
| 8553 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
| 8554 | }, |
| 8555 | |
| 8556 | /* VEX_LEN_0F58_P_1 */ |
| 8557 | { |
| 8558 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
| 8559 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
| 8560 | }, |
| 8561 | |
| 8562 | /* VEX_LEN_0F58_P_3 */ |
| 8563 | { |
| 8564 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
| 8565 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
| 8566 | }, |
| 8567 | |
| 8568 | /* VEX_LEN_0F59_P_1 */ |
| 8569 | { |
| 8570 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
| 8571 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
| 8572 | }, |
| 8573 | |
| 8574 | /* VEX_LEN_0F59_P_3 */ |
| 8575 | { |
| 8576 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
| 8577 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
| 8578 | }, |
| 8579 | |
| 8580 | /* VEX_LEN_0F5A_P_1 */ |
| 8581 | { |
| 8582 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
| 8583 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
| 8584 | }, |
| 8585 | |
| 8586 | /* VEX_LEN_0F5A_P_3 */ |
| 8587 | { |
| 8588 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
| 8589 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
| 8590 | }, |
| 8591 | |
| 8592 | /* VEX_LEN_0F5C_P_1 */ |
| 8593 | { |
| 8594 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
| 8595 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
| 8596 | }, |
| 8597 | |
| 8598 | /* VEX_LEN_0F5C_P_3 */ |
| 8599 | { |
| 8600 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
| 8601 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
| 8602 | }, |
| 8603 | |
| 8604 | /* VEX_LEN_0F5D_P_1 */ |
| 8605 | { |
| 8606 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
| 8607 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
| 8608 | }, |
| 8609 | |
| 8610 | /* VEX_LEN_0F5D_P_3 */ |
| 8611 | { |
| 8612 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
| 8613 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
| 8614 | }, |
| 8615 | |
| 8616 | /* VEX_LEN_0F5E_P_1 */ |
| 8617 | { |
| 8618 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
| 8619 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
| 8620 | }, |
| 8621 | |
| 8622 | /* VEX_LEN_0F5E_P_3 */ |
| 8623 | { |
| 8624 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
| 8625 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
| 8626 | }, |
| 8627 | |
| 8628 | /* VEX_LEN_0F5F_P_1 */ |
| 8629 | { |
| 8630 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
| 8631 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
| 8632 | }, |
| 8633 | |
| 8634 | /* VEX_LEN_0F5F_P_3 */ |
| 8635 | { |
| 8636 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
| 8637 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
| 8638 | }, |
| 8639 | |
| 8640 | /* VEX_LEN_0F6E_P_2 */ |
| 8641 | { |
| 8642 | { "vmovK", { XMScalar, Edq } }, |
| 8643 | { "vmovK", { XMScalar, Edq } }, |
| 8644 | }, |
| 8645 | |
| 8646 | /* VEX_LEN_0F7E_P_1 */ |
| 8647 | { |
| 8648 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
| 8649 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
| 8650 | }, |
| 8651 | |
| 8652 | /* VEX_LEN_0F7E_P_2 */ |
| 8653 | { |
| 8654 | { "vmovK", { Edq, XMScalar } }, |
| 8655 | { "vmovK", { Edq, XMScalar } }, |
| 8656 | }, |
| 8657 | |
| 8658 | /* VEX_LEN_0FAE_R_2_M_0 */ |
| 8659 | { |
| 8660 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
| 8661 | }, |
| 8662 | |
| 8663 | /* VEX_LEN_0FAE_R_3_M_0 */ |
| 8664 | { |
| 8665 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
| 8666 | }, |
| 8667 | |
| 8668 | /* VEX_LEN_0FC2_P_1 */ |
| 8669 | { |
| 8670 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
| 8671 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
| 8672 | }, |
| 8673 | |
| 8674 | /* VEX_LEN_0FC2_P_3 */ |
| 8675 | { |
| 8676 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
| 8677 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
| 8678 | }, |
| 8679 | |
| 8680 | /* VEX_LEN_0FC4_P_2 */ |
| 8681 | { |
| 8682 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
| 8683 | }, |
| 8684 | |
| 8685 | /* VEX_LEN_0FC5_P_2 */ |
| 8686 | { |
| 8687 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
| 8688 | }, |
| 8689 | |
| 8690 | /* VEX_LEN_0FD6_P_2 */ |
| 8691 | { |
| 8692 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
| 8693 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
| 8694 | }, |
| 8695 | |
| 8696 | /* VEX_LEN_0FF7_P_2 */ |
| 8697 | { |
| 8698 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
| 8699 | }, |
| 8700 | |
| 8701 | /* VEX_LEN_0F3816_P_2 */ |
| 8702 | { |
| 8703 | { Bad_Opcode }, |
| 8704 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, |
| 8705 | }, |
| 8706 | |
| 8707 | /* VEX_LEN_0F3819_P_2 */ |
| 8708 | { |
| 8709 | { Bad_Opcode }, |
| 8710 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, |
| 8711 | }, |
| 8712 | |
| 8713 | /* VEX_LEN_0F381A_P_2_M_0 */ |
| 8714 | { |
| 8715 | { Bad_Opcode }, |
| 8716 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, |
| 8717 | }, |
| 8718 | |
| 8719 | /* VEX_LEN_0F3836_P_2 */ |
| 8720 | { |
| 8721 | { Bad_Opcode }, |
| 8722 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, |
| 8723 | }, |
| 8724 | |
| 8725 | /* VEX_LEN_0F3841_P_2 */ |
| 8726 | { |
| 8727 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
| 8728 | }, |
| 8729 | |
| 8730 | /* VEX_LEN_0F385A_P_2_M_0 */ |
| 8731 | { |
| 8732 | { Bad_Opcode }, |
| 8733 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, |
| 8734 | }, |
| 8735 | |
| 8736 | /* VEX_LEN_0F38DB_P_2 */ |
| 8737 | { |
| 8738 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
| 8739 | }, |
| 8740 | |
| 8741 | /* VEX_LEN_0F38DC_P_2 */ |
| 8742 | { |
| 8743 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
| 8744 | }, |
| 8745 | |
| 8746 | /* VEX_LEN_0F38DD_P_2 */ |
| 8747 | { |
| 8748 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
| 8749 | }, |
| 8750 | |
| 8751 | /* VEX_LEN_0F38DE_P_2 */ |
| 8752 | { |
| 8753 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
| 8754 | }, |
| 8755 | |
| 8756 | /* VEX_LEN_0F38DF_P_2 */ |
| 8757 | { |
| 8758 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
| 8759 | }, |
| 8760 | |
| 8761 | /* VEX_LEN_0F38F2_P_0 */ |
| 8762 | { |
| 8763 | { "andnS", { Gdq, VexGdq, Edq } }, |
| 8764 | }, |
| 8765 | |
| 8766 | /* VEX_LEN_0F38F3_R_1_P_0 */ |
| 8767 | { |
| 8768 | { "blsrS", { VexGdq, Edq } }, |
| 8769 | }, |
| 8770 | |
| 8771 | /* VEX_LEN_0F38F3_R_2_P_0 */ |
| 8772 | { |
| 8773 | { "blsmskS", { VexGdq, Edq } }, |
| 8774 | }, |
| 8775 | |
| 8776 | /* VEX_LEN_0F38F3_R_3_P_0 */ |
| 8777 | { |
| 8778 | { "blsiS", { VexGdq, Edq } }, |
| 8779 | }, |
| 8780 | |
| 8781 | /* VEX_LEN_0F38F5_P_0 */ |
| 8782 | { |
| 8783 | { "bzhiS", { Gdq, Edq, VexGdq } }, |
| 8784 | }, |
| 8785 | |
| 8786 | /* VEX_LEN_0F38F5_P_1 */ |
| 8787 | { |
| 8788 | { "pextS", { Gdq, VexGdq, Edq } }, |
| 8789 | }, |
| 8790 | |
| 8791 | /* VEX_LEN_0F38F5_P_3 */ |
| 8792 | { |
| 8793 | { "pdepS", { Gdq, VexGdq, Edq } }, |
| 8794 | }, |
| 8795 | |
| 8796 | /* VEX_LEN_0F38F6_P_3 */ |
| 8797 | { |
| 8798 | { "mulxS", { Gdq, VexGdq, Edq } }, |
| 8799 | }, |
| 8800 | |
| 8801 | /* VEX_LEN_0F38F7_P_0 */ |
| 8802 | { |
| 8803 | { "bextrS", { Gdq, Edq, VexGdq } }, |
| 8804 | }, |
| 8805 | |
| 8806 | /* VEX_LEN_0F38F7_P_1 */ |
| 8807 | { |
| 8808 | { "sarxS", { Gdq, Edq, VexGdq } }, |
| 8809 | }, |
| 8810 | |
| 8811 | /* VEX_LEN_0F38F7_P_2 */ |
| 8812 | { |
| 8813 | { "shlxS", { Gdq, Edq, VexGdq } }, |
| 8814 | }, |
| 8815 | |
| 8816 | /* VEX_LEN_0F38F7_P_3 */ |
| 8817 | { |
| 8818 | { "shrxS", { Gdq, Edq, VexGdq } }, |
| 8819 | }, |
| 8820 | |
| 8821 | /* VEX_LEN_0F3A00_P_2 */ |
| 8822 | { |
| 8823 | { Bad_Opcode }, |
| 8824 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, |
| 8825 | }, |
| 8826 | |
| 8827 | /* VEX_LEN_0F3A01_P_2 */ |
| 8828 | { |
| 8829 | { Bad_Opcode }, |
| 8830 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, |
| 8831 | }, |
| 8832 | |
| 8833 | /* VEX_LEN_0F3A06_P_2 */ |
| 8834 | { |
| 8835 | { Bad_Opcode }, |
| 8836 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
| 8837 | }, |
| 8838 | |
| 8839 | /* VEX_LEN_0F3A0A_P_2 */ |
| 8840 | { |
| 8841 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
| 8842 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
| 8843 | }, |
| 8844 | |
| 8845 | /* VEX_LEN_0F3A0B_P_2 */ |
| 8846 | { |
| 8847 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
| 8848 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
| 8849 | }, |
| 8850 | |
| 8851 | /* VEX_LEN_0F3A14_P_2 */ |
| 8852 | { |
| 8853 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
| 8854 | }, |
| 8855 | |
| 8856 | /* VEX_LEN_0F3A15_P_2 */ |
| 8857 | { |
| 8858 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
| 8859 | }, |
| 8860 | |
| 8861 | /* VEX_LEN_0F3A16_P_2 */ |
| 8862 | { |
| 8863 | { "vpextrK", { Edq, XM, Ib } }, |
| 8864 | }, |
| 8865 | |
| 8866 | /* VEX_LEN_0F3A17_P_2 */ |
| 8867 | { |
| 8868 | { "vextractps", { Edqd, XM, Ib } }, |
| 8869 | }, |
| 8870 | |
| 8871 | /* VEX_LEN_0F3A18_P_2 */ |
| 8872 | { |
| 8873 | { Bad_Opcode }, |
| 8874 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
| 8875 | }, |
| 8876 | |
| 8877 | /* VEX_LEN_0F3A19_P_2 */ |
| 8878 | { |
| 8879 | { Bad_Opcode }, |
| 8880 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
| 8881 | }, |
| 8882 | |
| 8883 | /* VEX_LEN_0F3A20_P_2 */ |
| 8884 | { |
| 8885 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
| 8886 | }, |
| 8887 | |
| 8888 | /* VEX_LEN_0F3A21_P_2 */ |
| 8889 | { |
| 8890 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
| 8891 | }, |
| 8892 | |
| 8893 | /* VEX_LEN_0F3A22_P_2 */ |
| 8894 | { |
| 8895 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, |
| 8896 | }, |
| 8897 | |
| 8898 | /* VEX_LEN_0F3A38_P_2 */ |
| 8899 | { |
| 8900 | { Bad_Opcode }, |
| 8901 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, |
| 8902 | }, |
| 8903 | |
| 8904 | /* VEX_LEN_0F3A39_P_2 */ |
| 8905 | { |
| 8906 | { Bad_Opcode }, |
| 8907 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, |
| 8908 | }, |
| 8909 | |
| 8910 | /* VEX_LEN_0F3A41_P_2 */ |
| 8911 | { |
| 8912 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, |
| 8913 | }, |
| 8914 | |
| 8915 | /* VEX_LEN_0F3A44_P_2 */ |
| 8916 | { |
| 8917 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
| 8918 | }, |
| 8919 | |
| 8920 | /* VEX_LEN_0F3A46_P_2 */ |
| 8921 | { |
| 8922 | { Bad_Opcode }, |
| 8923 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, |
| 8924 | }, |
| 8925 | |
| 8926 | /* VEX_LEN_0F3A60_P_2 */ |
| 8927 | { |
| 8928 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
| 8929 | }, |
| 8930 | |
| 8931 | /* VEX_LEN_0F3A61_P_2 */ |
| 8932 | { |
| 8933 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
| 8934 | }, |
| 8935 | |
| 8936 | /* VEX_LEN_0F3A62_P_2 */ |
| 8937 | { |
| 8938 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
| 8939 | }, |
| 8940 | |
| 8941 | /* VEX_LEN_0F3A63_P_2 */ |
| 8942 | { |
| 8943 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
| 8944 | }, |
| 8945 | |
| 8946 | /* VEX_LEN_0F3A6A_P_2 */ |
| 8947 | { |
| 8948 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
| 8949 | }, |
| 8950 | |
| 8951 | /* VEX_LEN_0F3A6B_P_2 */ |
| 8952 | { |
| 8953 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
| 8954 | }, |
| 8955 | |
| 8956 | /* VEX_LEN_0F3A6E_P_2 */ |
| 8957 | { |
| 8958 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
| 8959 | }, |
| 8960 | |
| 8961 | /* VEX_LEN_0F3A6F_P_2 */ |
| 8962 | { |
| 8963 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
| 8964 | }, |
| 8965 | |
| 8966 | /* VEX_LEN_0F3A7A_P_2 */ |
| 8967 | { |
| 8968 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
| 8969 | }, |
| 8970 | |
| 8971 | /* VEX_LEN_0F3A7B_P_2 */ |
| 8972 | { |
| 8973 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
| 8974 | }, |
| 8975 | |
| 8976 | /* VEX_LEN_0F3A7E_P_2 */ |
| 8977 | { |
| 8978 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
| 8979 | }, |
| 8980 | |
| 8981 | /* VEX_LEN_0F3A7F_P_2 */ |
| 8982 | { |
| 8983 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
| 8984 | }, |
| 8985 | |
| 8986 | /* VEX_LEN_0F3ADF_P_2 */ |
| 8987 | { |
| 8988 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
| 8989 | }, |
| 8990 | |
| 8991 | /* VEX_LEN_0F3AF0_P_3 */ |
| 8992 | { |
| 8993 | { "rorxS", { Gdq, Edq, Ib } }, |
| 8994 | }, |
| 8995 | |
| 8996 | /* VEX_LEN_0FXOP_09_80 */ |
| 8997 | { |
| 8998 | { "vfrczps", { XM, EXxmm } }, |
| 8999 | { "vfrczps", { XM, EXymmq } }, |
| 9000 | }, |
| 9001 | |
| 9002 | /* VEX_LEN_0FXOP_09_81 */ |
| 9003 | { |
| 9004 | { "vfrczpd", { XM, EXxmm } }, |
| 9005 | { "vfrczpd", { XM, EXymmq } }, |
| 9006 | }, |
| 9007 | }; |
| 9008 | |
| 9009 | static const struct dis386 vex_w_table[][2] = { |
| 9010 | { |
| 9011 | /* VEX_W_0F10_P_0 */ |
| 9012 | { "vmovups", { XM, EXx } }, |
| 9013 | }, |
| 9014 | { |
| 9015 | /* VEX_W_0F10_P_1 */ |
| 9016 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
| 9017 | }, |
| 9018 | { |
| 9019 | /* VEX_W_0F10_P_2 */ |
| 9020 | { "vmovupd", { XM, EXx } }, |
| 9021 | }, |
| 9022 | { |
| 9023 | /* VEX_W_0F10_P_3 */ |
| 9024 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
| 9025 | }, |
| 9026 | { |
| 9027 | /* VEX_W_0F11_P_0 */ |
| 9028 | { "vmovups", { EXxS, XM } }, |
| 9029 | }, |
| 9030 | { |
| 9031 | /* VEX_W_0F11_P_1 */ |
| 9032 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
| 9033 | }, |
| 9034 | { |
| 9035 | /* VEX_W_0F11_P_2 */ |
| 9036 | { "vmovupd", { EXxS, XM } }, |
| 9037 | }, |
| 9038 | { |
| 9039 | /* VEX_W_0F11_P_3 */ |
| 9040 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
| 9041 | }, |
| 9042 | { |
| 9043 | /* VEX_W_0F12_P_0_M_0 */ |
| 9044 | { "vmovlps", { XM, Vex128, EXq } }, |
| 9045 | }, |
| 9046 | { |
| 9047 | /* VEX_W_0F12_P_0_M_1 */ |
| 9048 | { "vmovhlps", { XM, Vex128, EXq } }, |
| 9049 | }, |
| 9050 | { |
| 9051 | /* VEX_W_0F12_P_1 */ |
| 9052 | { "vmovsldup", { XM, EXx } }, |
| 9053 | }, |
| 9054 | { |
| 9055 | /* VEX_W_0F12_P_2 */ |
| 9056 | { "vmovlpd", { XM, Vex128, EXq } }, |
| 9057 | }, |
| 9058 | { |
| 9059 | /* VEX_W_0F12_P_3 */ |
| 9060 | { "vmovddup", { XM, EXymmq } }, |
| 9061 | }, |
| 9062 | { |
| 9063 | /* VEX_W_0F13_M_0 */ |
| 9064 | { "vmovlpX", { EXq, XM } }, |
| 9065 | }, |
| 9066 | { |
| 9067 | /* VEX_W_0F14 */ |
| 9068 | { "vunpcklpX", { XM, Vex, EXx } }, |
| 9069 | }, |
| 9070 | { |
| 9071 | /* VEX_W_0F15 */ |
| 9072 | { "vunpckhpX", { XM, Vex, EXx } }, |
| 9073 | }, |
| 9074 | { |
| 9075 | /* VEX_W_0F16_P_0_M_0 */ |
| 9076 | { "vmovhps", { XM, Vex128, EXq } }, |
| 9077 | }, |
| 9078 | { |
| 9079 | /* VEX_W_0F16_P_0_M_1 */ |
| 9080 | { "vmovlhps", { XM, Vex128, EXq } }, |
| 9081 | }, |
| 9082 | { |
| 9083 | /* VEX_W_0F16_P_1 */ |
| 9084 | { "vmovshdup", { XM, EXx } }, |
| 9085 | }, |
| 9086 | { |
| 9087 | /* VEX_W_0F16_P_2 */ |
| 9088 | { "vmovhpd", { XM, Vex128, EXq } }, |
| 9089 | }, |
| 9090 | { |
| 9091 | /* VEX_W_0F17_M_0 */ |
| 9092 | { "vmovhpX", { EXq, XM } }, |
| 9093 | }, |
| 9094 | { |
| 9095 | /* VEX_W_0F28 */ |
| 9096 | { "vmovapX", { XM, EXx } }, |
| 9097 | }, |
| 9098 | { |
| 9099 | /* VEX_W_0F29 */ |
| 9100 | { "vmovapX", { EXxS, XM } }, |
| 9101 | }, |
| 9102 | { |
| 9103 | /* VEX_W_0F2B_M_0 */ |
| 9104 | { "vmovntpX", { Mx, XM } }, |
| 9105 | }, |
| 9106 | { |
| 9107 | /* VEX_W_0F2E_P_0 */ |
| 9108 | { "vucomiss", { XMScalar, EXdScalar } }, |
| 9109 | }, |
| 9110 | { |
| 9111 | /* VEX_W_0F2E_P_2 */ |
| 9112 | { "vucomisd", { XMScalar, EXqScalar } }, |
| 9113 | }, |
| 9114 | { |
| 9115 | /* VEX_W_0F2F_P_0 */ |
| 9116 | { "vcomiss", { XMScalar, EXdScalar } }, |
| 9117 | }, |
| 9118 | { |
| 9119 | /* VEX_W_0F2F_P_2 */ |
| 9120 | { "vcomisd", { XMScalar, EXqScalar } }, |
| 9121 | }, |
| 9122 | { |
| 9123 | /* VEX_W_0F50_M_0 */ |
| 9124 | { "vmovmskpX", { Gdq, XS } }, |
| 9125 | }, |
| 9126 | { |
| 9127 | /* VEX_W_0F51_P_0 */ |
| 9128 | { "vsqrtps", { XM, EXx } }, |
| 9129 | }, |
| 9130 | { |
| 9131 | /* VEX_W_0F51_P_1 */ |
| 9132 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
| 9133 | }, |
| 9134 | { |
| 9135 | /* VEX_W_0F51_P_2 */ |
| 9136 | { "vsqrtpd", { XM, EXx } }, |
| 9137 | }, |
| 9138 | { |
| 9139 | /* VEX_W_0F51_P_3 */ |
| 9140 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9141 | }, |
| 9142 | { |
| 9143 | /* VEX_W_0F52_P_0 */ |
| 9144 | { "vrsqrtps", { XM, EXx } }, |
| 9145 | }, |
| 9146 | { |
| 9147 | /* VEX_W_0F52_P_1 */ |
| 9148 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
| 9149 | }, |
| 9150 | { |
| 9151 | /* VEX_W_0F53_P_0 */ |
| 9152 | { "vrcpps", { XM, EXx } }, |
| 9153 | }, |
| 9154 | { |
| 9155 | /* VEX_W_0F53_P_1 */ |
| 9156 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
| 9157 | }, |
| 9158 | { |
| 9159 | /* VEX_W_0F58_P_0 */ |
| 9160 | { "vaddps", { XM, Vex, EXx } }, |
| 9161 | }, |
| 9162 | { |
| 9163 | /* VEX_W_0F58_P_1 */ |
| 9164 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
| 9165 | }, |
| 9166 | { |
| 9167 | /* VEX_W_0F58_P_2 */ |
| 9168 | { "vaddpd", { XM, Vex, EXx } }, |
| 9169 | }, |
| 9170 | { |
| 9171 | /* VEX_W_0F58_P_3 */ |
| 9172 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9173 | }, |
| 9174 | { |
| 9175 | /* VEX_W_0F59_P_0 */ |
| 9176 | { "vmulps", { XM, Vex, EXx } }, |
| 9177 | }, |
| 9178 | { |
| 9179 | /* VEX_W_0F59_P_1 */ |
| 9180 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
| 9181 | }, |
| 9182 | { |
| 9183 | /* VEX_W_0F59_P_2 */ |
| 9184 | { "vmulpd", { XM, Vex, EXx } }, |
| 9185 | }, |
| 9186 | { |
| 9187 | /* VEX_W_0F59_P_3 */ |
| 9188 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9189 | }, |
| 9190 | { |
| 9191 | /* VEX_W_0F5A_P_0 */ |
| 9192 | { "vcvtps2pd", { XM, EXxmmq } }, |
| 9193 | }, |
| 9194 | { |
| 9195 | /* VEX_W_0F5A_P_1 */ |
| 9196 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
| 9197 | }, |
| 9198 | { |
| 9199 | /* VEX_W_0F5A_P_3 */ |
| 9200 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
| 9201 | }, |
| 9202 | { |
| 9203 | /* VEX_W_0F5B_P_0 */ |
| 9204 | { "vcvtdq2ps", { XM, EXx } }, |
| 9205 | }, |
| 9206 | { |
| 9207 | /* VEX_W_0F5B_P_1 */ |
| 9208 | { "vcvttps2dq", { XM, EXx } }, |
| 9209 | }, |
| 9210 | { |
| 9211 | /* VEX_W_0F5B_P_2 */ |
| 9212 | { "vcvtps2dq", { XM, EXx } }, |
| 9213 | }, |
| 9214 | { |
| 9215 | /* VEX_W_0F5C_P_0 */ |
| 9216 | { "vsubps", { XM, Vex, EXx } }, |
| 9217 | }, |
| 9218 | { |
| 9219 | /* VEX_W_0F5C_P_1 */ |
| 9220 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
| 9221 | }, |
| 9222 | { |
| 9223 | /* VEX_W_0F5C_P_2 */ |
| 9224 | { "vsubpd", { XM, Vex, EXx } }, |
| 9225 | }, |
| 9226 | { |
| 9227 | /* VEX_W_0F5C_P_3 */ |
| 9228 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9229 | }, |
| 9230 | { |
| 9231 | /* VEX_W_0F5D_P_0 */ |
| 9232 | { "vminps", { XM, Vex, EXx } }, |
| 9233 | }, |
| 9234 | { |
| 9235 | /* VEX_W_0F5D_P_1 */ |
| 9236 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
| 9237 | }, |
| 9238 | { |
| 9239 | /* VEX_W_0F5D_P_2 */ |
| 9240 | { "vminpd", { XM, Vex, EXx } }, |
| 9241 | }, |
| 9242 | { |
| 9243 | /* VEX_W_0F5D_P_3 */ |
| 9244 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9245 | }, |
| 9246 | { |
| 9247 | /* VEX_W_0F5E_P_0 */ |
| 9248 | { "vdivps", { XM, Vex, EXx } }, |
| 9249 | }, |
| 9250 | { |
| 9251 | /* VEX_W_0F5E_P_1 */ |
| 9252 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
| 9253 | }, |
| 9254 | { |
| 9255 | /* VEX_W_0F5E_P_2 */ |
| 9256 | { "vdivpd", { XM, Vex, EXx } }, |
| 9257 | }, |
| 9258 | { |
| 9259 | /* VEX_W_0F5E_P_3 */ |
| 9260 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9261 | }, |
| 9262 | { |
| 9263 | /* VEX_W_0F5F_P_0 */ |
| 9264 | { "vmaxps", { XM, Vex, EXx } }, |
| 9265 | }, |
| 9266 | { |
| 9267 | /* VEX_W_0F5F_P_1 */ |
| 9268 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
| 9269 | }, |
| 9270 | { |
| 9271 | /* VEX_W_0F5F_P_2 */ |
| 9272 | { "vmaxpd", { XM, Vex, EXx } }, |
| 9273 | }, |
| 9274 | { |
| 9275 | /* VEX_W_0F5F_P_3 */ |
| 9276 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
| 9277 | }, |
| 9278 | { |
| 9279 | /* VEX_W_0F60_P_2 */ |
| 9280 | { "vpunpcklbw", { XM, Vex, EXx } }, |
| 9281 | }, |
| 9282 | { |
| 9283 | /* VEX_W_0F61_P_2 */ |
| 9284 | { "vpunpcklwd", { XM, Vex, EXx } }, |
| 9285 | }, |
| 9286 | { |
| 9287 | /* VEX_W_0F62_P_2 */ |
| 9288 | { "vpunpckldq", { XM, Vex, EXx } }, |
| 9289 | }, |
| 9290 | { |
| 9291 | /* VEX_W_0F63_P_2 */ |
| 9292 | { "vpacksswb", { XM, Vex, EXx } }, |
| 9293 | }, |
| 9294 | { |
| 9295 | /* VEX_W_0F64_P_2 */ |
| 9296 | { "vpcmpgtb", { XM, Vex, EXx } }, |
| 9297 | }, |
| 9298 | { |
| 9299 | /* VEX_W_0F65_P_2 */ |
| 9300 | { "vpcmpgtw", { XM, Vex, EXx } }, |
| 9301 | }, |
| 9302 | { |
| 9303 | /* VEX_W_0F66_P_2 */ |
| 9304 | { "vpcmpgtd", { XM, Vex, EXx } }, |
| 9305 | }, |
| 9306 | { |
| 9307 | /* VEX_W_0F67_P_2 */ |
| 9308 | { "vpackuswb", { XM, Vex, EXx } }, |
| 9309 | }, |
| 9310 | { |
| 9311 | /* VEX_W_0F68_P_2 */ |
| 9312 | { "vpunpckhbw", { XM, Vex, EXx } }, |
| 9313 | }, |
| 9314 | { |
| 9315 | /* VEX_W_0F69_P_2 */ |
| 9316 | { "vpunpckhwd", { XM, Vex, EXx } }, |
| 9317 | }, |
| 9318 | { |
| 9319 | /* VEX_W_0F6A_P_2 */ |
| 9320 | { "vpunpckhdq", { XM, Vex, EXx } }, |
| 9321 | }, |
| 9322 | { |
| 9323 | /* VEX_W_0F6B_P_2 */ |
| 9324 | { "vpackssdw", { XM, Vex, EXx } }, |
| 9325 | }, |
| 9326 | { |
| 9327 | /* VEX_W_0F6C_P_2 */ |
| 9328 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
| 9329 | }, |
| 9330 | { |
| 9331 | /* VEX_W_0F6D_P_2 */ |
| 9332 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
| 9333 | }, |
| 9334 | { |
| 9335 | /* VEX_W_0F6F_P_1 */ |
| 9336 | { "vmovdqu", { XM, EXx } }, |
| 9337 | }, |
| 9338 | { |
| 9339 | /* VEX_W_0F6F_P_2 */ |
| 9340 | { "vmovdqa", { XM, EXx } }, |
| 9341 | }, |
| 9342 | { |
| 9343 | /* VEX_W_0F70_P_1 */ |
| 9344 | { "vpshufhw", { XM, EXx, Ib } }, |
| 9345 | }, |
| 9346 | { |
| 9347 | /* VEX_W_0F70_P_2 */ |
| 9348 | { "vpshufd", { XM, EXx, Ib } }, |
| 9349 | }, |
| 9350 | { |
| 9351 | /* VEX_W_0F70_P_3 */ |
| 9352 | { "vpshuflw", { XM, EXx, Ib } }, |
| 9353 | }, |
| 9354 | { |
| 9355 | /* VEX_W_0F71_R_2_P_2 */ |
| 9356 | { "vpsrlw", { Vex, XS, Ib } }, |
| 9357 | }, |
| 9358 | { |
| 9359 | /* VEX_W_0F71_R_4_P_2 */ |
| 9360 | { "vpsraw", { Vex, XS, Ib } }, |
| 9361 | }, |
| 9362 | { |
| 9363 | /* VEX_W_0F71_R_6_P_2 */ |
| 9364 | { "vpsllw", { Vex, XS, Ib } }, |
| 9365 | }, |
| 9366 | { |
| 9367 | /* VEX_W_0F72_R_2_P_2 */ |
| 9368 | { "vpsrld", { Vex, XS, Ib } }, |
| 9369 | }, |
| 9370 | { |
| 9371 | /* VEX_W_0F72_R_4_P_2 */ |
| 9372 | { "vpsrad", { Vex, XS, Ib } }, |
| 9373 | }, |
| 9374 | { |
| 9375 | /* VEX_W_0F72_R_6_P_2 */ |
| 9376 | { "vpslld", { Vex, XS, Ib } }, |
| 9377 | }, |
| 9378 | { |
| 9379 | /* VEX_W_0F73_R_2_P_2 */ |
| 9380 | { "vpsrlq", { Vex, XS, Ib } }, |
| 9381 | }, |
| 9382 | { |
| 9383 | /* VEX_W_0F73_R_3_P_2 */ |
| 9384 | { "vpsrldq", { Vex, XS, Ib } }, |
| 9385 | }, |
| 9386 | { |
| 9387 | /* VEX_W_0F73_R_6_P_2 */ |
| 9388 | { "vpsllq", { Vex, XS, Ib } }, |
| 9389 | }, |
| 9390 | { |
| 9391 | /* VEX_W_0F73_R_7_P_2 */ |
| 9392 | { "vpslldq", { Vex, XS, Ib } }, |
| 9393 | }, |
| 9394 | { |
| 9395 | /* VEX_W_0F74_P_2 */ |
| 9396 | { "vpcmpeqb", { XM, Vex, EXx } }, |
| 9397 | }, |
| 9398 | { |
| 9399 | /* VEX_W_0F75_P_2 */ |
| 9400 | { "vpcmpeqw", { XM, Vex, EXx } }, |
| 9401 | }, |
| 9402 | { |
| 9403 | /* VEX_W_0F76_P_2 */ |
| 9404 | { "vpcmpeqd", { XM, Vex, EXx } }, |
| 9405 | }, |
| 9406 | { |
| 9407 | /* VEX_W_0F77_P_0 */ |
| 9408 | { "", { VZERO } }, |
| 9409 | }, |
| 9410 | { |
| 9411 | /* VEX_W_0F7C_P_2 */ |
| 9412 | { "vhaddpd", { XM, Vex, EXx } }, |
| 9413 | }, |
| 9414 | { |
| 9415 | /* VEX_W_0F7C_P_3 */ |
| 9416 | { "vhaddps", { XM, Vex, EXx } }, |
| 9417 | }, |
| 9418 | { |
| 9419 | /* VEX_W_0F7D_P_2 */ |
| 9420 | { "vhsubpd", { XM, Vex, EXx } }, |
| 9421 | }, |
| 9422 | { |
| 9423 | /* VEX_W_0F7D_P_3 */ |
| 9424 | { "vhsubps", { XM, Vex, EXx } }, |
| 9425 | }, |
| 9426 | { |
| 9427 | /* VEX_W_0F7E_P_1 */ |
| 9428 | { "vmovq", { XMScalar, EXqScalar } }, |
| 9429 | }, |
| 9430 | { |
| 9431 | /* VEX_W_0F7F_P_1 */ |
| 9432 | { "vmovdqu", { EXxS, XM } }, |
| 9433 | }, |
| 9434 | { |
| 9435 | /* VEX_W_0F7F_P_2 */ |
| 9436 | { "vmovdqa", { EXxS, XM } }, |
| 9437 | }, |
| 9438 | { |
| 9439 | /* VEX_W_0FAE_R_2_M_0 */ |
| 9440 | { "vldmxcsr", { Md } }, |
| 9441 | }, |
| 9442 | { |
| 9443 | /* VEX_W_0FAE_R_3_M_0 */ |
| 9444 | { "vstmxcsr", { Md } }, |
| 9445 | }, |
| 9446 | { |
| 9447 | /* VEX_W_0FC2_P_0 */ |
| 9448 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
| 9449 | }, |
| 9450 | { |
| 9451 | /* VEX_W_0FC2_P_1 */ |
| 9452 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
| 9453 | }, |
| 9454 | { |
| 9455 | /* VEX_W_0FC2_P_2 */ |
| 9456 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
| 9457 | }, |
| 9458 | { |
| 9459 | /* VEX_W_0FC2_P_3 */ |
| 9460 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
| 9461 | }, |
| 9462 | { |
| 9463 | /* VEX_W_0FC4_P_2 */ |
| 9464 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
| 9465 | }, |
| 9466 | { |
| 9467 | /* VEX_W_0FC5_P_2 */ |
| 9468 | { "vpextrw", { Gdq, XS, Ib } }, |
| 9469 | }, |
| 9470 | { |
| 9471 | /* VEX_W_0FD0_P_2 */ |
| 9472 | { "vaddsubpd", { XM, Vex, EXx } }, |
| 9473 | }, |
| 9474 | { |
| 9475 | /* VEX_W_0FD0_P_3 */ |
| 9476 | { "vaddsubps", { XM, Vex, EXx } }, |
| 9477 | }, |
| 9478 | { |
| 9479 | /* VEX_W_0FD1_P_2 */ |
| 9480 | { "vpsrlw", { XM, Vex, EXxmm } }, |
| 9481 | }, |
| 9482 | { |
| 9483 | /* VEX_W_0FD2_P_2 */ |
| 9484 | { "vpsrld", { XM, Vex, EXxmm } }, |
| 9485 | }, |
| 9486 | { |
| 9487 | /* VEX_W_0FD3_P_2 */ |
| 9488 | { "vpsrlq", { XM, Vex, EXxmm } }, |
| 9489 | }, |
| 9490 | { |
| 9491 | /* VEX_W_0FD4_P_2 */ |
| 9492 | { "vpaddq", { XM, Vex, EXx } }, |
| 9493 | }, |
| 9494 | { |
| 9495 | /* VEX_W_0FD5_P_2 */ |
| 9496 | { "vpmullw", { XM, Vex, EXx } }, |
| 9497 | }, |
| 9498 | { |
| 9499 | /* VEX_W_0FD6_P_2 */ |
| 9500 | { "vmovq", { EXqScalarS, XMScalar } }, |
| 9501 | }, |
| 9502 | { |
| 9503 | /* VEX_W_0FD7_P_2_M_1 */ |
| 9504 | { "vpmovmskb", { Gdq, XS } }, |
| 9505 | }, |
| 9506 | { |
| 9507 | /* VEX_W_0FD8_P_2 */ |
| 9508 | { "vpsubusb", { XM, Vex, EXx } }, |
| 9509 | }, |
| 9510 | { |
| 9511 | /* VEX_W_0FD9_P_2 */ |
| 9512 | { "vpsubusw", { XM, Vex, EXx } }, |
| 9513 | }, |
| 9514 | { |
| 9515 | /* VEX_W_0FDA_P_2 */ |
| 9516 | { "vpminub", { XM, Vex, EXx } }, |
| 9517 | }, |
| 9518 | { |
| 9519 | /* VEX_W_0FDB_P_2 */ |
| 9520 | { "vpand", { XM, Vex, EXx } }, |
| 9521 | }, |
| 9522 | { |
| 9523 | /* VEX_W_0FDC_P_2 */ |
| 9524 | { "vpaddusb", { XM, Vex, EXx } }, |
| 9525 | }, |
| 9526 | { |
| 9527 | /* VEX_W_0FDD_P_2 */ |
| 9528 | { "vpaddusw", { XM, Vex, EXx } }, |
| 9529 | }, |
| 9530 | { |
| 9531 | /* VEX_W_0FDE_P_2 */ |
| 9532 | { "vpmaxub", { XM, Vex, EXx } }, |
| 9533 | }, |
| 9534 | { |
| 9535 | /* VEX_W_0FDF_P_2 */ |
| 9536 | { "vpandn", { XM, Vex, EXx } }, |
| 9537 | }, |
| 9538 | { |
| 9539 | /* VEX_W_0FE0_P_2 */ |
| 9540 | { "vpavgb", { XM, Vex, EXx } }, |
| 9541 | }, |
| 9542 | { |
| 9543 | /* VEX_W_0FE1_P_2 */ |
| 9544 | { "vpsraw", { XM, Vex, EXxmm } }, |
| 9545 | }, |
| 9546 | { |
| 9547 | /* VEX_W_0FE2_P_2 */ |
| 9548 | { "vpsrad", { XM, Vex, EXxmm } }, |
| 9549 | }, |
| 9550 | { |
| 9551 | /* VEX_W_0FE3_P_2 */ |
| 9552 | { "vpavgw", { XM, Vex, EXx } }, |
| 9553 | }, |
| 9554 | { |
| 9555 | /* VEX_W_0FE4_P_2 */ |
| 9556 | { "vpmulhuw", { XM, Vex, EXx } }, |
| 9557 | }, |
| 9558 | { |
| 9559 | /* VEX_W_0FE5_P_2 */ |
| 9560 | { "vpmulhw", { XM, Vex, EXx } }, |
| 9561 | }, |
| 9562 | { |
| 9563 | /* VEX_W_0FE6_P_1 */ |
| 9564 | { "vcvtdq2pd", { XM, EXxmmq } }, |
| 9565 | }, |
| 9566 | { |
| 9567 | /* VEX_W_0FE6_P_2 */ |
| 9568 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
| 9569 | }, |
| 9570 | { |
| 9571 | /* VEX_W_0FE6_P_3 */ |
| 9572 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
| 9573 | }, |
| 9574 | { |
| 9575 | /* VEX_W_0FE7_P_2_M_0 */ |
| 9576 | { "vmovntdq", { Mx, XM } }, |
| 9577 | }, |
| 9578 | { |
| 9579 | /* VEX_W_0FE8_P_2 */ |
| 9580 | { "vpsubsb", { XM, Vex, EXx } }, |
| 9581 | }, |
| 9582 | { |
| 9583 | /* VEX_W_0FE9_P_2 */ |
| 9584 | { "vpsubsw", { XM, Vex, EXx } }, |
| 9585 | }, |
| 9586 | { |
| 9587 | /* VEX_W_0FEA_P_2 */ |
| 9588 | { "vpminsw", { XM, Vex, EXx } }, |
| 9589 | }, |
| 9590 | { |
| 9591 | /* VEX_W_0FEB_P_2 */ |
| 9592 | { "vpor", { XM, Vex, EXx } }, |
| 9593 | }, |
| 9594 | { |
| 9595 | /* VEX_W_0FEC_P_2 */ |
| 9596 | { "vpaddsb", { XM, Vex, EXx } }, |
| 9597 | }, |
| 9598 | { |
| 9599 | /* VEX_W_0FED_P_2 */ |
| 9600 | { "vpaddsw", { XM, Vex, EXx } }, |
| 9601 | }, |
| 9602 | { |
| 9603 | /* VEX_W_0FEE_P_2 */ |
| 9604 | { "vpmaxsw", { XM, Vex, EXx } }, |
| 9605 | }, |
| 9606 | { |
| 9607 | /* VEX_W_0FEF_P_2 */ |
| 9608 | { "vpxor", { XM, Vex, EXx } }, |
| 9609 | }, |
| 9610 | { |
| 9611 | /* VEX_W_0FF0_P_3_M_0 */ |
| 9612 | { "vlddqu", { XM, M } }, |
| 9613 | }, |
| 9614 | { |
| 9615 | /* VEX_W_0FF1_P_2 */ |
| 9616 | { "vpsllw", { XM, Vex, EXxmm } }, |
| 9617 | }, |
| 9618 | { |
| 9619 | /* VEX_W_0FF2_P_2 */ |
| 9620 | { "vpslld", { XM, Vex, EXxmm } }, |
| 9621 | }, |
| 9622 | { |
| 9623 | /* VEX_W_0FF3_P_2 */ |
| 9624 | { "vpsllq", { XM, Vex, EXxmm } }, |
| 9625 | }, |
| 9626 | { |
| 9627 | /* VEX_W_0FF4_P_2 */ |
| 9628 | { "vpmuludq", { XM, Vex, EXx } }, |
| 9629 | }, |
| 9630 | { |
| 9631 | /* VEX_W_0FF5_P_2 */ |
| 9632 | { "vpmaddwd", { XM, Vex, EXx } }, |
| 9633 | }, |
| 9634 | { |
| 9635 | /* VEX_W_0FF6_P_2 */ |
| 9636 | { "vpsadbw", { XM, Vex, EXx } }, |
| 9637 | }, |
| 9638 | { |
| 9639 | /* VEX_W_0FF7_P_2 */ |
| 9640 | { "vmaskmovdqu", { XM, XS } }, |
| 9641 | }, |
| 9642 | { |
| 9643 | /* VEX_W_0FF8_P_2 */ |
| 9644 | { "vpsubb", { XM, Vex, EXx } }, |
| 9645 | }, |
| 9646 | { |
| 9647 | /* VEX_W_0FF9_P_2 */ |
| 9648 | { "vpsubw", { XM, Vex, EXx } }, |
| 9649 | }, |
| 9650 | { |
| 9651 | /* VEX_W_0FFA_P_2 */ |
| 9652 | { "vpsubd", { XM, Vex, EXx } }, |
| 9653 | }, |
| 9654 | { |
| 9655 | /* VEX_W_0FFB_P_2 */ |
| 9656 | { "vpsubq", { XM, Vex, EXx } }, |
| 9657 | }, |
| 9658 | { |
| 9659 | /* VEX_W_0FFC_P_2 */ |
| 9660 | { "vpaddb", { XM, Vex, EXx } }, |
| 9661 | }, |
| 9662 | { |
| 9663 | /* VEX_W_0FFD_P_2 */ |
| 9664 | { "vpaddw", { XM, Vex, EXx } }, |
| 9665 | }, |
| 9666 | { |
| 9667 | /* VEX_W_0FFE_P_2 */ |
| 9668 | { "vpaddd", { XM, Vex, EXx } }, |
| 9669 | }, |
| 9670 | { |
| 9671 | /* VEX_W_0F3800_P_2 */ |
| 9672 | { "vpshufb", { XM, Vex, EXx } }, |
| 9673 | }, |
| 9674 | { |
| 9675 | /* VEX_W_0F3801_P_2 */ |
| 9676 | { "vphaddw", { XM, Vex, EXx } }, |
| 9677 | }, |
| 9678 | { |
| 9679 | /* VEX_W_0F3802_P_2 */ |
| 9680 | { "vphaddd", { XM, Vex, EXx } }, |
| 9681 | }, |
| 9682 | { |
| 9683 | /* VEX_W_0F3803_P_2 */ |
| 9684 | { "vphaddsw", { XM, Vex, EXx } }, |
| 9685 | }, |
| 9686 | { |
| 9687 | /* VEX_W_0F3804_P_2 */ |
| 9688 | { "vpmaddubsw", { XM, Vex, EXx } }, |
| 9689 | }, |
| 9690 | { |
| 9691 | /* VEX_W_0F3805_P_2 */ |
| 9692 | { "vphsubw", { XM, Vex, EXx } }, |
| 9693 | }, |
| 9694 | { |
| 9695 | /* VEX_W_0F3806_P_2 */ |
| 9696 | { "vphsubd", { XM, Vex, EXx } }, |
| 9697 | }, |
| 9698 | { |
| 9699 | /* VEX_W_0F3807_P_2 */ |
| 9700 | { "vphsubsw", { XM, Vex, EXx } }, |
| 9701 | }, |
| 9702 | { |
| 9703 | /* VEX_W_0F3808_P_2 */ |
| 9704 | { "vpsignb", { XM, Vex, EXx } }, |
| 9705 | }, |
| 9706 | { |
| 9707 | /* VEX_W_0F3809_P_2 */ |
| 9708 | { "vpsignw", { XM, Vex, EXx } }, |
| 9709 | }, |
| 9710 | { |
| 9711 | /* VEX_W_0F380A_P_2 */ |
| 9712 | { "vpsignd", { XM, Vex, EXx } }, |
| 9713 | }, |
| 9714 | { |
| 9715 | /* VEX_W_0F380B_P_2 */ |
| 9716 | { "vpmulhrsw", { XM, Vex, EXx } }, |
| 9717 | }, |
| 9718 | { |
| 9719 | /* VEX_W_0F380C_P_2 */ |
| 9720 | { "vpermilps", { XM, Vex, EXx } }, |
| 9721 | }, |
| 9722 | { |
| 9723 | /* VEX_W_0F380D_P_2 */ |
| 9724 | { "vpermilpd", { XM, Vex, EXx } }, |
| 9725 | }, |
| 9726 | { |
| 9727 | /* VEX_W_0F380E_P_2 */ |
| 9728 | { "vtestps", { XM, EXx } }, |
| 9729 | }, |
| 9730 | { |
| 9731 | /* VEX_W_0F380F_P_2 */ |
| 9732 | { "vtestpd", { XM, EXx } }, |
| 9733 | }, |
| 9734 | { |
| 9735 | /* VEX_W_0F3816_P_2 */ |
| 9736 | { "vpermps", { XM, Vex, EXx } }, |
| 9737 | }, |
| 9738 | { |
| 9739 | /* VEX_W_0F3817_P_2 */ |
| 9740 | { "vptest", { XM, EXx } }, |
| 9741 | }, |
| 9742 | { |
| 9743 | /* VEX_W_0F3818_P_2 */ |
| 9744 | { "vbroadcastss", { XM, EXxmm_md } }, |
| 9745 | }, |
| 9746 | { |
| 9747 | /* VEX_W_0F3819_P_2 */ |
| 9748 | { "vbroadcastsd", { XM, EXxmm_mq } }, |
| 9749 | }, |
| 9750 | { |
| 9751 | /* VEX_W_0F381A_P_2_M_0 */ |
| 9752 | { "vbroadcastf128", { XM, Mxmm } }, |
| 9753 | }, |
| 9754 | { |
| 9755 | /* VEX_W_0F381C_P_2 */ |
| 9756 | { "vpabsb", { XM, EXx } }, |
| 9757 | }, |
| 9758 | { |
| 9759 | /* VEX_W_0F381D_P_2 */ |
| 9760 | { "vpabsw", { XM, EXx } }, |
| 9761 | }, |
| 9762 | { |
| 9763 | /* VEX_W_0F381E_P_2 */ |
| 9764 | { "vpabsd", { XM, EXx } }, |
| 9765 | }, |
| 9766 | { |
| 9767 | /* VEX_W_0F3820_P_2 */ |
| 9768 | { "vpmovsxbw", { XM, EXxmmq } }, |
| 9769 | }, |
| 9770 | { |
| 9771 | /* VEX_W_0F3821_P_2 */ |
| 9772 | { "vpmovsxbd", { XM, EXxmmqd } }, |
| 9773 | }, |
| 9774 | { |
| 9775 | /* VEX_W_0F3822_P_2 */ |
| 9776 | { "vpmovsxbq", { XM, EXxmmdw } }, |
| 9777 | }, |
| 9778 | { |
| 9779 | /* VEX_W_0F3823_P_2 */ |
| 9780 | { "vpmovsxwd", { XM, EXxmmq } }, |
| 9781 | }, |
| 9782 | { |
| 9783 | /* VEX_W_0F3824_P_2 */ |
| 9784 | { "vpmovsxwq", { XM, EXxmmqd } }, |
| 9785 | }, |
| 9786 | { |
| 9787 | /* VEX_W_0F3825_P_2 */ |
| 9788 | { "vpmovsxdq", { XM, EXxmmq } }, |
| 9789 | }, |
| 9790 | { |
| 9791 | /* VEX_W_0F3828_P_2 */ |
| 9792 | { "vpmuldq", { XM, Vex, EXx } }, |
| 9793 | }, |
| 9794 | { |
| 9795 | /* VEX_W_0F3829_P_2 */ |
| 9796 | { "vpcmpeqq", { XM, Vex, EXx } }, |
| 9797 | }, |
| 9798 | { |
| 9799 | /* VEX_W_0F382A_P_2_M_0 */ |
| 9800 | { "vmovntdqa", { XM, Mx } }, |
| 9801 | }, |
| 9802 | { |
| 9803 | /* VEX_W_0F382B_P_2 */ |
| 9804 | { "vpackusdw", { XM, Vex, EXx } }, |
| 9805 | }, |
| 9806 | { |
| 9807 | /* VEX_W_0F382C_P_2_M_0 */ |
| 9808 | { "vmaskmovps", { XM, Vex, Mx } }, |
| 9809 | }, |
| 9810 | { |
| 9811 | /* VEX_W_0F382D_P_2_M_0 */ |
| 9812 | { "vmaskmovpd", { XM, Vex, Mx } }, |
| 9813 | }, |
| 9814 | { |
| 9815 | /* VEX_W_0F382E_P_2_M_0 */ |
| 9816 | { "vmaskmovps", { Mx, Vex, XM } }, |
| 9817 | }, |
| 9818 | { |
| 9819 | /* VEX_W_0F382F_P_2_M_0 */ |
| 9820 | { "vmaskmovpd", { Mx, Vex, XM } }, |
| 9821 | }, |
| 9822 | { |
| 9823 | /* VEX_W_0F3830_P_2 */ |
| 9824 | { "vpmovzxbw", { XM, EXxmmq } }, |
| 9825 | }, |
| 9826 | { |
| 9827 | /* VEX_W_0F3831_P_2 */ |
| 9828 | { "vpmovzxbd", { XM, EXxmmqd } }, |
| 9829 | }, |
| 9830 | { |
| 9831 | /* VEX_W_0F3832_P_2 */ |
| 9832 | { "vpmovzxbq", { XM, EXxmmdw } }, |
| 9833 | }, |
| 9834 | { |
| 9835 | /* VEX_W_0F3833_P_2 */ |
| 9836 | { "vpmovzxwd", { XM, EXxmmq } }, |
| 9837 | }, |
| 9838 | { |
| 9839 | /* VEX_W_0F3834_P_2 */ |
| 9840 | { "vpmovzxwq", { XM, EXxmmqd } }, |
| 9841 | }, |
| 9842 | { |
| 9843 | /* VEX_W_0F3835_P_2 */ |
| 9844 | { "vpmovzxdq", { XM, EXxmmq } }, |
| 9845 | }, |
| 9846 | { |
| 9847 | /* VEX_W_0F3836_P_2 */ |
| 9848 | { "vpermd", { XM, Vex, EXx } }, |
| 9849 | }, |
| 9850 | { |
| 9851 | /* VEX_W_0F3837_P_2 */ |
| 9852 | { "vpcmpgtq", { XM, Vex, EXx } }, |
| 9853 | }, |
| 9854 | { |
| 9855 | /* VEX_W_0F3838_P_2 */ |
| 9856 | { "vpminsb", { XM, Vex, EXx } }, |
| 9857 | }, |
| 9858 | { |
| 9859 | /* VEX_W_0F3839_P_2 */ |
| 9860 | { "vpminsd", { XM, Vex, EXx } }, |
| 9861 | }, |
| 9862 | { |
| 9863 | /* VEX_W_0F383A_P_2 */ |
| 9864 | { "vpminuw", { XM, Vex, EXx } }, |
| 9865 | }, |
| 9866 | { |
| 9867 | /* VEX_W_0F383B_P_2 */ |
| 9868 | { "vpminud", { XM, Vex, EXx } }, |
| 9869 | }, |
| 9870 | { |
| 9871 | /* VEX_W_0F383C_P_2 */ |
| 9872 | { "vpmaxsb", { XM, Vex, EXx } }, |
| 9873 | }, |
| 9874 | { |
| 9875 | /* VEX_W_0F383D_P_2 */ |
| 9876 | { "vpmaxsd", { XM, Vex, EXx } }, |
| 9877 | }, |
| 9878 | { |
| 9879 | /* VEX_W_0F383E_P_2 */ |
| 9880 | { "vpmaxuw", { XM, Vex, EXx } }, |
| 9881 | }, |
| 9882 | { |
| 9883 | /* VEX_W_0F383F_P_2 */ |
| 9884 | { "vpmaxud", { XM, Vex, EXx } }, |
| 9885 | }, |
| 9886 | { |
| 9887 | /* VEX_W_0F3840_P_2 */ |
| 9888 | { "vpmulld", { XM, Vex, EXx } }, |
| 9889 | }, |
| 9890 | { |
| 9891 | /* VEX_W_0F3841_P_2 */ |
| 9892 | { "vphminposuw", { XM, EXx } }, |
| 9893 | }, |
| 9894 | { |
| 9895 | /* VEX_W_0F3846_P_2 */ |
| 9896 | { "vpsravd", { XM, Vex, EXx } }, |
| 9897 | }, |
| 9898 | { |
| 9899 | /* VEX_W_0F3858_P_2 */ |
| 9900 | { "vpbroadcastd", { XM, EXxmm_md } }, |
| 9901 | }, |
| 9902 | { |
| 9903 | /* VEX_W_0F3859_P_2 */ |
| 9904 | { "vpbroadcastq", { XM, EXxmm_mq } }, |
| 9905 | }, |
| 9906 | { |
| 9907 | /* VEX_W_0F385A_P_2_M_0 */ |
| 9908 | { "vbroadcasti128", { XM, Mxmm } }, |
| 9909 | }, |
| 9910 | { |
| 9911 | /* VEX_W_0F3878_P_2 */ |
| 9912 | { "vpbroadcastb", { XM, EXxmm_mb } }, |
| 9913 | }, |
| 9914 | { |
| 9915 | /* VEX_W_0F3879_P_2 */ |
| 9916 | { "vpbroadcastw", { XM, EXxmm_mw } }, |
| 9917 | }, |
| 9918 | { |
| 9919 | /* VEX_W_0F38DB_P_2 */ |
| 9920 | { "vaesimc", { XM, EXx } }, |
| 9921 | }, |
| 9922 | { |
| 9923 | /* VEX_W_0F38DC_P_2 */ |
| 9924 | { "vaesenc", { XM, Vex128, EXx } }, |
| 9925 | }, |
| 9926 | { |
| 9927 | /* VEX_W_0F38DD_P_2 */ |
| 9928 | { "vaesenclast", { XM, Vex128, EXx } }, |
| 9929 | }, |
| 9930 | { |
| 9931 | /* VEX_W_0F38DE_P_2 */ |
| 9932 | { "vaesdec", { XM, Vex128, EXx } }, |
| 9933 | }, |
| 9934 | { |
| 9935 | /* VEX_W_0F38DF_P_2 */ |
| 9936 | { "vaesdeclast", { XM, Vex128, EXx } }, |
| 9937 | }, |
| 9938 | { |
| 9939 | /* VEX_W_0F3A00_P_2 */ |
| 9940 | { Bad_Opcode }, |
| 9941 | { "vpermq", { XM, EXx, Ib } }, |
| 9942 | }, |
| 9943 | { |
| 9944 | /* VEX_W_0F3A01_P_2 */ |
| 9945 | { Bad_Opcode }, |
| 9946 | { "vpermpd", { XM, EXx, Ib } }, |
| 9947 | }, |
| 9948 | { |
| 9949 | /* VEX_W_0F3A02_P_2 */ |
| 9950 | { "vpblendd", { XM, Vex, EXx, Ib } }, |
| 9951 | }, |
| 9952 | { |
| 9953 | /* VEX_W_0F3A04_P_2 */ |
| 9954 | { "vpermilps", { XM, EXx, Ib } }, |
| 9955 | }, |
| 9956 | { |
| 9957 | /* VEX_W_0F3A05_P_2 */ |
| 9958 | { "vpermilpd", { XM, EXx, Ib } }, |
| 9959 | }, |
| 9960 | { |
| 9961 | /* VEX_W_0F3A06_P_2 */ |
| 9962 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
| 9963 | }, |
| 9964 | { |
| 9965 | /* VEX_W_0F3A08_P_2 */ |
| 9966 | { "vroundps", { XM, EXx, Ib } }, |
| 9967 | }, |
| 9968 | { |
| 9969 | /* VEX_W_0F3A09_P_2 */ |
| 9970 | { "vroundpd", { XM, EXx, Ib } }, |
| 9971 | }, |
| 9972 | { |
| 9973 | /* VEX_W_0F3A0A_P_2 */ |
| 9974 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
| 9975 | }, |
| 9976 | { |
| 9977 | /* VEX_W_0F3A0B_P_2 */ |
| 9978 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
| 9979 | }, |
| 9980 | { |
| 9981 | /* VEX_W_0F3A0C_P_2 */ |
| 9982 | { "vblendps", { XM, Vex, EXx, Ib } }, |
| 9983 | }, |
| 9984 | { |
| 9985 | /* VEX_W_0F3A0D_P_2 */ |
| 9986 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
| 9987 | }, |
| 9988 | { |
| 9989 | /* VEX_W_0F3A0E_P_2 */ |
| 9990 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
| 9991 | }, |
| 9992 | { |
| 9993 | /* VEX_W_0F3A0F_P_2 */ |
| 9994 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
| 9995 | }, |
| 9996 | { |
| 9997 | /* VEX_W_0F3A14_P_2 */ |
| 9998 | { "vpextrb", { Edqb, XM, Ib } }, |
| 9999 | }, |
| 10000 | { |
| 10001 | /* VEX_W_0F3A15_P_2 */ |
| 10002 | { "vpextrw", { Edqw, XM, Ib } }, |
| 10003 | }, |
| 10004 | { |
| 10005 | /* VEX_W_0F3A18_P_2 */ |
| 10006 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
| 10007 | }, |
| 10008 | { |
| 10009 | /* VEX_W_0F3A19_P_2 */ |
| 10010 | { "vextractf128", { EXxmm, XM, Ib } }, |
| 10011 | }, |
| 10012 | { |
| 10013 | /* VEX_W_0F3A20_P_2 */ |
| 10014 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
| 10015 | }, |
| 10016 | { |
| 10017 | /* VEX_W_0F3A21_P_2 */ |
| 10018 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
| 10019 | }, |
| 10020 | { |
| 10021 | /* VEX_W_0F3A38_P_2 */ |
| 10022 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, |
| 10023 | }, |
| 10024 | { |
| 10025 | /* VEX_W_0F3A39_P_2 */ |
| 10026 | { "vextracti128", { EXxmm, XM, Ib } }, |
| 10027 | }, |
| 10028 | { |
| 10029 | /* VEX_W_0F3A40_P_2 */ |
| 10030 | { "vdpps", { XM, Vex, EXx, Ib } }, |
| 10031 | }, |
| 10032 | { |
| 10033 | /* VEX_W_0F3A41_P_2 */ |
| 10034 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
| 10035 | }, |
| 10036 | { |
| 10037 | /* VEX_W_0F3A42_P_2 */ |
| 10038 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
| 10039 | }, |
| 10040 | { |
| 10041 | /* VEX_W_0F3A44_P_2 */ |
| 10042 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
| 10043 | }, |
| 10044 | { |
| 10045 | /* VEX_W_0F3A46_P_2 */ |
| 10046 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, |
| 10047 | }, |
| 10048 | { |
| 10049 | /* VEX_W_0F3A48_P_2 */ |
| 10050 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
| 10051 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
| 10052 | }, |
| 10053 | { |
| 10054 | /* VEX_W_0F3A49_P_2 */ |
| 10055 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
| 10056 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
| 10057 | }, |
| 10058 | { |
| 10059 | /* VEX_W_0F3A4A_P_2 */ |
| 10060 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
| 10061 | }, |
| 10062 | { |
| 10063 | /* VEX_W_0F3A4B_P_2 */ |
| 10064 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
| 10065 | }, |
| 10066 | { |
| 10067 | /* VEX_W_0F3A4C_P_2 */ |
| 10068 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
| 10069 | }, |
| 10070 | { |
| 10071 | /* VEX_W_0F3A60_P_2 */ |
| 10072 | { "vpcmpestrm", { XM, EXx, Ib } }, |
| 10073 | }, |
| 10074 | { |
| 10075 | /* VEX_W_0F3A61_P_2 */ |
| 10076 | { "vpcmpestri", { XM, EXx, Ib } }, |
| 10077 | }, |
| 10078 | { |
| 10079 | /* VEX_W_0F3A62_P_2 */ |
| 10080 | { "vpcmpistrm", { XM, EXx, Ib } }, |
| 10081 | }, |
| 10082 | { |
| 10083 | /* VEX_W_0F3A63_P_2 */ |
| 10084 | { "vpcmpistri", { XM, EXx, Ib } }, |
| 10085 | }, |
| 10086 | { |
| 10087 | /* VEX_W_0F3ADF_P_2 */ |
| 10088 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
| 10089 | }, |
| 10090 | }; |
| 10091 | |
| 10092 | static const struct dis386 mod_table[][2] = { |
| 10093 | { |
| 10094 | /* MOD_8D */ |
| 10095 | { "leaS", { Gv, M } }, |
| 10096 | }, |
| 10097 | { |
| 10098 | /* MOD_C6_REG_7 */ |
| 10099 | { Bad_Opcode }, |
| 10100 | { RM_TABLE (RM_C6_REG_7) }, |
| 10101 | }, |
| 10102 | { |
| 10103 | /* MOD_C7_REG_7 */ |
| 10104 | { Bad_Opcode }, |
| 10105 | { RM_TABLE (RM_C7_REG_7) }, |
| 10106 | }, |
| 10107 | { |
| 10108 | /* MOD_0F01_REG_0 */ |
| 10109 | { X86_64_TABLE (X86_64_0F01_REG_0) }, |
| 10110 | { RM_TABLE (RM_0F01_REG_0) }, |
| 10111 | }, |
| 10112 | { |
| 10113 | /* MOD_0F01_REG_1 */ |
| 10114 | { X86_64_TABLE (X86_64_0F01_REG_1) }, |
| 10115 | { RM_TABLE (RM_0F01_REG_1) }, |
| 10116 | }, |
| 10117 | { |
| 10118 | /* MOD_0F01_REG_2 */ |
| 10119 | { X86_64_TABLE (X86_64_0F01_REG_2) }, |
| 10120 | { RM_TABLE (RM_0F01_REG_2) }, |
| 10121 | }, |
| 10122 | { |
| 10123 | /* MOD_0F01_REG_3 */ |
| 10124 | { X86_64_TABLE (X86_64_0F01_REG_3) }, |
| 10125 | { RM_TABLE (RM_0F01_REG_3) }, |
| 10126 | }, |
| 10127 | { |
| 10128 | /* MOD_0F01_REG_7 */ |
| 10129 | { "invlpg", { Mb } }, |
| 10130 | { RM_TABLE (RM_0F01_REG_7) }, |
| 10131 | }, |
| 10132 | { |
| 10133 | /* MOD_0F12_PREFIX_0 */ |
| 10134 | { "movlps", { XM, EXq } }, |
| 10135 | { "movhlps", { XM, EXq } }, |
| 10136 | }, |
| 10137 | { |
| 10138 | /* MOD_0F13 */ |
| 10139 | { "movlpX", { EXq, XM } }, |
| 10140 | }, |
| 10141 | { |
| 10142 | /* MOD_0F16_PREFIX_0 */ |
| 10143 | { "movhps", { XM, EXq } }, |
| 10144 | { "movlhps", { XM, EXq } }, |
| 10145 | }, |
| 10146 | { |
| 10147 | /* MOD_0F17 */ |
| 10148 | { "movhpX", { EXq, XM } }, |
| 10149 | }, |
| 10150 | { |
| 10151 | /* MOD_0F18_REG_0 */ |
| 10152 | { "prefetchnta", { Mb } }, |
| 10153 | }, |
| 10154 | { |
| 10155 | /* MOD_0F18_REG_1 */ |
| 10156 | { "prefetcht0", { Mb } }, |
| 10157 | }, |
| 10158 | { |
| 10159 | /* MOD_0F18_REG_2 */ |
| 10160 | { "prefetcht1", { Mb } }, |
| 10161 | }, |
| 10162 | { |
| 10163 | /* MOD_0F18_REG_3 */ |
| 10164 | { "prefetcht2", { Mb } }, |
| 10165 | }, |
| 10166 | { |
| 10167 | /* MOD_0F20 */ |
| 10168 | { Bad_Opcode }, |
| 10169 | { "movZ", { Rm, Cm } }, |
| 10170 | }, |
| 10171 | { |
| 10172 | /* MOD_0F21 */ |
| 10173 | { Bad_Opcode }, |
| 10174 | { "movZ", { Rm, Dm } }, |
| 10175 | }, |
| 10176 | { |
| 10177 | /* MOD_0F22 */ |
| 10178 | { Bad_Opcode }, |
| 10179 | { "movZ", { Cm, Rm } }, |
| 10180 | }, |
| 10181 | { |
| 10182 | /* MOD_0F23 */ |
| 10183 | { Bad_Opcode }, |
| 10184 | { "movZ", { Dm, Rm } }, |
| 10185 | }, |
| 10186 | { |
| 10187 | /* MOD_0F24 */ |
| 10188 | { Bad_Opcode }, |
| 10189 | { "movL", { Rd, Td } }, |
| 10190 | }, |
| 10191 | { |
| 10192 | /* MOD_0F26 */ |
| 10193 | { Bad_Opcode }, |
| 10194 | { "movL", { Td, Rd } }, |
| 10195 | }, |
| 10196 | { |
| 10197 | /* MOD_0F2B_PREFIX_0 */ |
| 10198 | {"movntps", { Mx, XM } }, |
| 10199 | }, |
| 10200 | { |
| 10201 | /* MOD_0F2B_PREFIX_1 */ |
| 10202 | {"movntss", { Md, XM } }, |
| 10203 | }, |
| 10204 | { |
| 10205 | /* MOD_0F2B_PREFIX_2 */ |
| 10206 | {"movntpd", { Mx, XM } }, |
| 10207 | }, |
| 10208 | { |
| 10209 | /* MOD_0F2B_PREFIX_3 */ |
| 10210 | {"movntsd", { Mq, XM } }, |
| 10211 | }, |
| 10212 | { |
| 10213 | /* MOD_0F51 */ |
| 10214 | { Bad_Opcode }, |
| 10215 | { "movmskpX", { Gdq, XS } }, |
| 10216 | }, |
| 10217 | { |
| 10218 | /* MOD_0F71_REG_2 */ |
| 10219 | { Bad_Opcode }, |
| 10220 | { "psrlw", { MS, Ib } }, |
| 10221 | }, |
| 10222 | { |
| 10223 | /* MOD_0F71_REG_4 */ |
| 10224 | { Bad_Opcode }, |
| 10225 | { "psraw", { MS, Ib } }, |
| 10226 | }, |
| 10227 | { |
| 10228 | /* MOD_0F71_REG_6 */ |
| 10229 | { Bad_Opcode }, |
| 10230 | { "psllw", { MS, Ib } }, |
| 10231 | }, |
| 10232 | { |
| 10233 | /* MOD_0F72_REG_2 */ |
| 10234 | { Bad_Opcode }, |
| 10235 | { "psrld", { MS, Ib } }, |
| 10236 | }, |
| 10237 | { |
| 10238 | /* MOD_0F72_REG_4 */ |
| 10239 | { Bad_Opcode }, |
| 10240 | { "psrad", { MS, Ib } }, |
| 10241 | }, |
| 10242 | { |
| 10243 | /* MOD_0F72_REG_6 */ |
| 10244 | { Bad_Opcode }, |
| 10245 | { "pslld", { MS, Ib } }, |
| 10246 | }, |
| 10247 | { |
| 10248 | /* MOD_0F73_REG_2 */ |
| 10249 | { Bad_Opcode }, |
| 10250 | { "psrlq", { MS, Ib } }, |
| 10251 | }, |
| 10252 | { |
| 10253 | /* MOD_0F73_REG_3 */ |
| 10254 | { Bad_Opcode }, |
| 10255 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
| 10256 | }, |
| 10257 | { |
| 10258 | /* MOD_0F73_REG_6 */ |
| 10259 | { Bad_Opcode }, |
| 10260 | { "psllq", { MS, Ib } }, |
| 10261 | }, |
| 10262 | { |
| 10263 | /* MOD_0F73_REG_7 */ |
| 10264 | { Bad_Opcode }, |
| 10265 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
| 10266 | }, |
| 10267 | { |
| 10268 | /* MOD_0FAE_REG_0 */ |
| 10269 | { "fxsave", { FXSAVE } }, |
| 10270 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
| 10271 | }, |
| 10272 | { |
| 10273 | /* MOD_0FAE_REG_1 */ |
| 10274 | { "fxrstor", { FXSAVE } }, |
| 10275 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
| 10276 | }, |
| 10277 | { |
| 10278 | /* MOD_0FAE_REG_2 */ |
| 10279 | { "ldmxcsr", { Md } }, |
| 10280 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
| 10281 | }, |
| 10282 | { |
| 10283 | /* MOD_0FAE_REG_3 */ |
| 10284 | { "stmxcsr", { Md } }, |
| 10285 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
| 10286 | }, |
| 10287 | { |
| 10288 | /* MOD_0FAE_REG_4 */ |
| 10289 | { "xsave", { FXSAVE } }, |
| 10290 | }, |
| 10291 | { |
| 10292 | /* MOD_0FAE_REG_5 */ |
| 10293 | { "xrstor", { FXSAVE } }, |
| 10294 | { RM_TABLE (RM_0FAE_REG_5) }, |
| 10295 | }, |
| 10296 | { |
| 10297 | /* MOD_0FAE_REG_6 */ |
| 10298 | { "xsaveopt", { FXSAVE } }, |
| 10299 | { RM_TABLE (RM_0FAE_REG_6) }, |
| 10300 | }, |
| 10301 | { |
| 10302 | /* MOD_0FAE_REG_7 */ |
| 10303 | { "clflush", { Mb } }, |
| 10304 | { RM_TABLE (RM_0FAE_REG_7) }, |
| 10305 | }, |
| 10306 | { |
| 10307 | /* MOD_0FB2 */ |
| 10308 | { "lssS", { Gv, Mp } }, |
| 10309 | }, |
| 10310 | { |
| 10311 | /* MOD_0FB4 */ |
| 10312 | { "lfsS", { Gv, Mp } }, |
| 10313 | }, |
| 10314 | { |
| 10315 | /* MOD_0FB5 */ |
| 10316 | { "lgsS", { Gv, Mp } }, |
| 10317 | }, |
| 10318 | { |
| 10319 | /* MOD_0FC7_REG_6 */ |
| 10320 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, |
| 10321 | { "rdrand", { Ev } }, |
| 10322 | }, |
| 10323 | { |
| 10324 | /* MOD_0FC7_REG_7 */ |
| 10325 | { "vmptrst", { Mq } }, |
| 10326 | }, |
| 10327 | { |
| 10328 | /* MOD_0FD7 */ |
| 10329 | { Bad_Opcode }, |
| 10330 | { "pmovmskb", { Gdq, MS } }, |
| 10331 | }, |
| 10332 | { |
| 10333 | /* MOD_0FE7_PREFIX_2 */ |
| 10334 | { "movntdq", { Mx, XM } }, |
| 10335 | }, |
| 10336 | { |
| 10337 | /* MOD_0FF0_PREFIX_3 */ |
| 10338 | { "lddqu", { XM, M } }, |
| 10339 | }, |
| 10340 | { |
| 10341 | /* MOD_0F382A_PREFIX_2 */ |
| 10342 | { "movntdqa", { XM, Mx } }, |
| 10343 | }, |
| 10344 | { |
| 10345 | /* MOD_62_32BIT */ |
| 10346 | { "bound{S|}", { Gv, Ma } }, |
| 10347 | }, |
| 10348 | { |
| 10349 | /* MOD_C4_32BIT */ |
| 10350 | { "lesS", { Gv, Mp } }, |
| 10351 | { VEX_C4_TABLE (VEX_0F) }, |
| 10352 | }, |
| 10353 | { |
| 10354 | /* MOD_C5_32BIT */ |
| 10355 | { "ldsS", { Gv, Mp } }, |
| 10356 | { VEX_C5_TABLE (VEX_0F) }, |
| 10357 | }, |
| 10358 | { |
| 10359 | /* MOD_VEX_0F12_PREFIX_0 */ |
| 10360 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, |
| 10361 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, |
| 10362 | }, |
| 10363 | { |
| 10364 | /* MOD_VEX_0F13 */ |
| 10365 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, |
| 10366 | }, |
| 10367 | { |
| 10368 | /* MOD_VEX_0F16_PREFIX_0 */ |
| 10369 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, |
| 10370 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, |
| 10371 | }, |
| 10372 | { |
| 10373 | /* MOD_VEX_0F17 */ |
| 10374 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, |
| 10375 | }, |
| 10376 | { |
| 10377 | /* MOD_VEX_0F2B */ |
| 10378 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, |
| 10379 | }, |
| 10380 | { |
| 10381 | /* MOD_VEX_0F50 */ |
| 10382 | { Bad_Opcode }, |
| 10383 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
| 10384 | }, |
| 10385 | { |
| 10386 | /* MOD_VEX_0F71_REG_2 */ |
| 10387 | { Bad_Opcode }, |
| 10388 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
| 10389 | }, |
| 10390 | { |
| 10391 | /* MOD_VEX_0F71_REG_4 */ |
| 10392 | { Bad_Opcode }, |
| 10393 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
| 10394 | }, |
| 10395 | { |
| 10396 | /* MOD_VEX_0F71_REG_6 */ |
| 10397 | { Bad_Opcode }, |
| 10398 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
| 10399 | }, |
| 10400 | { |
| 10401 | /* MOD_VEX_0F72_REG_2 */ |
| 10402 | { Bad_Opcode }, |
| 10403 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
| 10404 | }, |
| 10405 | { |
| 10406 | /* MOD_VEX_0F72_REG_4 */ |
| 10407 | { Bad_Opcode }, |
| 10408 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
| 10409 | }, |
| 10410 | { |
| 10411 | /* MOD_VEX_0F72_REG_6 */ |
| 10412 | { Bad_Opcode }, |
| 10413 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
| 10414 | }, |
| 10415 | { |
| 10416 | /* MOD_VEX_0F73_REG_2 */ |
| 10417 | { Bad_Opcode }, |
| 10418 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
| 10419 | }, |
| 10420 | { |
| 10421 | /* MOD_VEX_0F73_REG_3 */ |
| 10422 | { Bad_Opcode }, |
| 10423 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
| 10424 | }, |
| 10425 | { |
| 10426 | /* MOD_VEX_0F73_REG_6 */ |
| 10427 | { Bad_Opcode }, |
| 10428 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
| 10429 | }, |
| 10430 | { |
| 10431 | /* MOD_VEX_0F73_REG_7 */ |
| 10432 | { Bad_Opcode }, |
| 10433 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
| 10434 | }, |
| 10435 | { |
| 10436 | /* MOD_VEX_0FAE_REG_2 */ |
| 10437 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, |
| 10438 | }, |
| 10439 | { |
| 10440 | /* MOD_VEX_0FAE_REG_3 */ |
| 10441 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, |
| 10442 | }, |
| 10443 | { |
| 10444 | /* MOD_VEX_0FD7_PREFIX_2 */ |
| 10445 | { Bad_Opcode }, |
| 10446 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
| 10447 | }, |
| 10448 | { |
| 10449 | /* MOD_VEX_0FE7_PREFIX_2 */ |
| 10450 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, |
| 10451 | }, |
| 10452 | { |
| 10453 | /* MOD_VEX_0FF0_PREFIX_3 */ |
| 10454 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, |
| 10455 | }, |
| 10456 | { |
| 10457 | /* MOD_VEX_0F381A_PREFIX_2 */ |
| 10458 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, |
| 10459 | }, |
| 10460 | { |
| 10461 | /* MOD_VEX_0F382A_PREFIX_2 */ |
| 10462 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
| 10463 | }, |
| 10464 | { |
| 10465 | /* MOD_VEX_0F382C_PREFIX_2 */ |
| 10466 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, |
| 10467 | }, |
| 10468 | { |
| 10469 | /* MOD_VEX_0F382D_PREFIX_2 */ |
| 10470 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, |
| 10471 | }, |
| 10472 | { |
| 10473 | /* MOD_VEX_0F382E_PREFIX_2 */ |
| 10474 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, |
| 10475 | }, |
| 10476 | { |
| 10477 | /* MOD_VEX_0F382F_PREFIX_2 */ |
| 10478 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, |
| 10479 | }, |
| 10480 | { |
| 10481 | /* MOD_VEX_0F385A_PREFIX_2 */ |
| 10482 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, |
| 10483 | }, |
| 10484 | { |
| 10485 | /* MOD_VEX_0F388C_PREFIX_2 */ |
| 10486 | { "vpmaskmov%LW", { XM, Vex, Mx } }, |
| 10487 | }, |
| 10488 | { |
| 10489 | /* MOD_VEX_0F388E_PREFIX_2 */ |
| 10490 | { "vpmaskmov%LW", { Mx, Vex, XM } }, |
| 10491 | }, |
| 10492 | }; |
| 10493 | |
| 10494 | static const struct dis386 rm_table[][8] = { |
| 10495 | { |
| 10496 | /* RM_C6_REG_7 */ |
| 10497 | { "xabort", { Skip_MODRM, Ib } }, |
| 10498 | }, |
| 10499 | { |
| 10500 | /* RM_C7_REG_7 */ |
| 10501 | { "xbeginT", { Skip_MODRM, Jv } }, |
| 10502 | }, |
| 10503 | { |
| 10504 | /* RM_0F01_REG_0 */ |
| 10505 | { Bad_Opcode }, |
| 10506 | { "vmcall", { Skip_MODRM } }, |
| 10507 | { "vmlaunch", { Skip_MODRM } }, |
| 10508 | { "vmresume", { Skip_MODRM } }, |
| 10509 | { "vmxoff", { Skip_MODRM } }, |
| 10510 | }, |
| 10511 | { |
| 10512 | /* RM_0F01_REG_1 */ |
| 10513 | { "monitor", { { OP_Monitor, 0 } } }, |
| 10514 | { "mwait", { { OP_Mwait, 0 } } }, |
| 10515 | }, |
| 10516 | { |
| 10517 | /* RM_0F01_REG_2 */ |
| 10518 | { "xgetbv", { Skip_MODRM } }, |
| 10519 | { "xsetbv", { Skip_MODRM } }, |
| 10520 | { Bad_Opcode }, |
| 10521 | { Bad_Opcode }, |
| 10522 | { "vmfunc", { Skip_MODRM } }, |
| 10523 | { "xend", { Skip_MODRM } }, |
| 10524 | { "xtest", { Skip_MODRM } }, |
| 10525 | { Bad_Opcode }, |
| 10526 | }, |
| 10527 | { |
| 10528 | /* RM_0F01_REG_3 */ |
| 10529 | { "vmrun", { Skip_MODRM } }, |
| 10530 | { "vmmcall", { Skip_MODRM } }, |
| 10531 | { "vmload", { Skip_MODRM } }, |
| 10532 | { "vmsave", { Skip_MODRM } }, |
| 10533 | { "stgi", { Skip_MODRM } }, |
| 10534 | { "clgi", { Skip_MODRM } }, |
| 10535 | { "skinit", { Skip_MODRM } }, |
| 10536 | { "invlpga", { Skip_MODRM } }, |
| 10537 | }, |
| 10538 | { |
| 10539 | /* RM_0F01_REG_7 */ |
| 10540 | { "swapgs", { Skip_MODRM } }, |
| 10541 | { "rdtscp", { Skip_MODRM } }, |
| 10542 | }, |
| 10543 | { |
| 10544 | /* RM_0FAE_REG_5 */ |
| 10545 | { "lfence", { Skip_MODRM } }, |
| 10546 | }, |
| 10547 | { |
| 10548 | /* RM_0FAE_REG_6 */ |
| 10549 | { "mfence", { Skip_MODRM } }, |
| 10550 | }, |
| 10551 | { |
| 10552 | /* RM_0FAE_REG_7 */ |
| 10553 | { "sfence", { Skip_MODRM } }, |
| 10554 | }, |
| 10555 | }; |
| 10556 | |
| 10557 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
| 10558 | |
| 10559 | /* We use the high bit to indicate different name for the same |
| 10560 | prefix. */ |
| 10561 | #define ADDR16_PREFIX (0x67 | 0x100) |
| 10562 | #define ADDR32_PREFIX (0x67 | 0x200) |
| 10563 | #define DATA16_PREFIX (0x66 | 0x100) |
| 10564 | #define DATA32_PREFIX (0x66 | 0x200) |
| 10565 | #define REP_PREFIX (0xf3 | 0x100) |
| 10566 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
| 10567 | #define XRELEASE_PREFIX (0xf3 | 0x400) |
| 10568 | |
| 10569 | static int |
| 10570 | ckprefix (void) |
| 10571 | { |
| 10572 | int newrex, i, length; |
| 10573 | rex = 0; |
| 10574 | rex_ignored = 0; |
| 10575 | prefixes = 0; |
| 10576 | used_prefixes = 0; |
| 10577 | rex_used = 0; |
| 10578 | last_lock_prefix = -1; |
| 10579 | last_repz_prefix = -1; |
| 10580 | last_repnz_prefix = -1; |
| 10581 | last_data_prefix = -1; |
| 10582 | last_addr_prefix = -1; |
| 10583 | last_rex_prefix = -1; |
| 10584 | last_seg_prefix = -1; |
| 10585 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
| 10586 | all_prefixes[i] = 0; |
| 10587 | i = 0; |
| 10588 | length = 0; |
| 10589 | /* The maximum instruction length is 15bytes. */ |
| 10590 | while (length < MAX_CODE_LENGTH - 1) |
| 10591 | { |
| 10592 | FETCH_DATA (the_info, codep + 1); |
| 10593 | newrex = 0; |
| 10594 | switch (*codep) |
| 10595 | { |
| 10596 | /* REX prefixes family. */ |
| 10597 | case 0x40: |
| 10598 | case 0x41: |
| 10599 | case 0x42: |
| 10600 | case 0x43: |
| 10601 | case 0x44: |
| 10602 | case 0x45: |
| 10603 | case 0x46: |
| 10604 | case 0x47: |
| 10605 | case 0x48: |
| 10606 | case 0x49: |
| 10607 | case 0x4a: |
| 10608 | case 0x4b: |
| 10609 | case 0x4c: |
| 10610 | case 0x4d: |
| 10611 | case 0x4e: |
| 10612 | case 0x4f: |
| 10613 | if (address_mode == mode_64bit) |
| 10614 | newrex = *codep; |
| 10615 | else |
| 10616 | return 1; |
| 10617 | last_rex_prefix = i; |
| 10618 | break; |
| 10619 | case 0xf3: |
| 10620 | prefixes |= PREFIX_REPZ; |
| 10621 | last_repz_prefix = i; |
| 10622 | break; |
| 10623 | case 0xf2: |
| 10624 | prefixes |= PREFIX_REPNZ; |
| 10625 | last_repnz_prefix = i; |
| 10626 | break; |
| 10627 | case 0xf0: |
| 10628 | prefixes |= PREFIX_LOCK; |
| 10629 | last_lock_prefix = i; |
| 10630 | break; |
| 10631 | case 0x2e: |
| 10632 | prefixes |= PREFIX_CS; |
| 10633 | last_seg_prefix = i; |
| 10634 | break; |
| 10635 | case 0x36: |
| 10636 | prefixes |= PREFIX_SS; |
| 10637 | last_seg_prefix = i; |
| 10638 | break; |
| 10639 | case 0x3e: |
| 10640 | prefixes |= PREFIX_DS; |
| 10641 | last_seg_prefix = i; |
| 10642 | break; |
| 10643 | case 0x26: |
| 10644 | prefixes |= PREFIX_ES; |
| 10645 | last_seg_prefix = i; |
| 10646 | break; |
| 10647 | case 0x64: |
| 10648 | prefixes |= PREFIX_FS; |
| 10649 | last_seg_prefix = i; |
| 10650 | break; |
| 10651 | case 0x65: |
| 10652 | prefixes |= PREFIX_GS; |
| 10653 | last_seg_prefix = i; |
| 10654 | break; |
| 10655 | case 0x66: |
| 10656 | prefixes |= PREFIX_DATA; |
| 10657 | last_data_prefix = i; |
| 10658 | break; |
| 10659 | case 0x67: |
| 10660 | prefixes |= PREFIX_ADDR; |
| 10661 | last_addr_prefix = i; |
| 10662 | break; |
| 10663 | case FWAIT_OPCODE: |
| 10664 | /* fwait is really an instruction. If there are prefixes |
| 10665 | before the fwait, they belong to the fwait, *not* to the |
| 10666 | following instruction. */ |
| 10667 | if (prefixes || rex) |
| 10668 | { |
| 10669 | prefixes |= PREFIX_FWAIT; |
| 10670 | codep++; |
| 10671 | return 1; |
| 10672 | } |
| 10673 | prefixes = PREFIX_FWAIT; |
| 10674 | break; |
| 10675 | default: |
| 10676 | return 1; |
| 10677 | } |
| 10678 | /* Rex is ignored when followed by another prefix. */ |
| 10679 | if (rex) |
| 10680 | { |
| 10681 | rex_used = rex; |
| 10682 | return 1; |
| 10683 | } |
| 10684 | if (*codep != FWAIT_OPCODE) |
| 10685 | all_prefixes[i++] = *codep; |
| 10686 | rex = newrex; |
| 10687 | codep++; |
| 10688 | length++; |
| 10689 | } |
| 10690 | return 0; |
| 10691 | } |
| 10692 | |
| 10693 | static int |
| 10694 | seg_prefix (int pref) |
| 10695 | { |
| 10696 | switch (pref) |
| 10697 | { |
| 10698 | case 0x2e: |
| 10699 | return PREFIX_CS; |
| 10700 | case 0x36: |
| 10701 | return PREFIX_SS; |
| 10702 | case 0x3e: |
| 10703 | return PREFIX_DS; |
| 10704 | case 0x26: |
| 10705 | return PREFIX_ES; |
| 10706 | case 0x64: |
| 10707 | return PREFIX_FS; |
| 10708 | case 0x65: |
| 10709 | return PREFIX_GS; |
| 10710 | default: |
| 10711 | return 0; |
| 10712 | } |
| 10713 | } |
| 10714 | |
| 10715 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
| 10716 | prefix byte. */ |
| 10717 | |
| 10718 | static const char * |
| 10719 | prefix_name (int pref, int sizeflag) |
| 10720 | { |
| 10721 | static const char *rexes [16] = |
| 10722 | { |
| 10723 | "rex", /* 0x40 */ |
| 10724 | "rex.B", /* 0x41 */ |
| 10725 | "rex.X", /* 0x42 */ |
| 10726 | "rex.XB", /* 0x43 */ |
| 10727 | "rex.R", /* 0x44 */ |
| 10728 | "rex.RB", /* 0x45 */ |
| 10729 | "rex.RX", /* 0x46 */ |
| 10730 | "rex.RXB", /* 0x47 */ |
| 10731 | "rex.W", /* 0x48 */ |
| 10732 | "rex.WB", /* 0x49 */ |
| 10733 | "rex.WX", /* 0x4a */ |
| 10734 | "rex.WXB", /* 0x4b */ |
| 10735 | "rex.WR", /* 0x4c */ |
| 10736 | "rex.WRB", /* 0x4d */ |
| 10737 | "rex.WRX", /* 0x4e */ |
| 10738 | "rex.WRXB", /* 0x4f */ |
| 10739 | }; |
| 10740 | |
| 10741 | switch (pref) |
| 10742 | { |
| 10743 | /* REX prefixes family. */ |
| 10744 | case 0x40: |
| 10745 | case 0x41: |
| 10746 | case 0x42: |
| 10747 | case 0x43: |
| 10748 | case 0x44: |
| 10749 | case 0x45: |
| 10750 | case 0x46: |
| 10751 | case 0x47: |
| 10752 | case 0x48: |
| 10753 | case 0x49: |
| 10754 | case 0x4a: |
| 10755 | case 0x4b: |
| 10756 | case 0x4c: |
| 10757 | case 0x4d: |
| 10758 | case 0x4e: |
| 10759 | case 0x4f: |
| 10760 | return rexes [pref - 0x40]; |
| 10761 | case 0xf3: |
| 10762 | return "repz"; |
| 10763 | case 0xf2: |
| 10764 | return "repnz"; |
| 10765 | case 0xf0: |
| 10766 | return "lock"; |
| 10767 | case 0x2e: |
| 10768 | return "cs"; |
| 10769 | case 0x36: |
| 10770 | return "ss"; |
| 10771 | case 0x3e: |
| 10772 | return "ds"; |
| 10773 | case 0x26: |
| 10774 | return "es"; |
| 10775 | case 0x64: |
| 10776 | return "fs"; |
| 10777 | case 0x65: |
| 10778 | return "gs"; |
| 10779 | case 0x66: |
| 10780 | return (sizeflag & DFLAG) ? "data16" : "data32"; |
| 10781 | case 0x67: |
| 10782 | if (address_mode == mode_64bit) |
| 10783 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
| 10784 | else |
| 10785 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
| 10786 | case FWAIT_OPCODE: |
| 10787 | return "fwait"; |
| 10788 | case ADDR16_PREFIX: |
| 10789 | return "addr16"; |
| 10790 | case ADDR32_PREFIX: |
| 10791 | return "addr32"; |
| 10792 | case DATA16_PREFIX: |
| 10793 | return "data16"; |
| 10794 | case DATA32_PREFIX: |
| 10795 | return "data32"; |
| 10796 | case REP_PREFIX: |
| 10797 | return "rep"; |
| 10798 | case XACQUIRE_PREFIX: |
| 10799 | return "xacquire"; |
| 10800 | case XRELEASE_PREFIX: |
| 10801 | return "xrelease"; |
| 10802 | default: |
| 10803 | return NULL; |
| 10804 | } |
| 10805 | } |
| 10806 | |
| 10807 | static char op_out[MAX_OPERANDS][100]; |
| 10808 | static int op_ad, op_index[MAX_OPERANDS]; |
| 10809 | static int two_source_ops; |
| 10810 | static bfd_vma op_address[MAX_OPERANDS]; |
| 10811 | static bfd_vma op_riprel[MAX_OPERANDS]; |
| 10812 | static bfd_vma start_pc; |
| 10813 | |
| 10814 | /* |
| 10815 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. |
| 10816 | * (see topic "Redundant prefixes" in the "Differences from 8086" |
| 10817 | * section of the "Virtual 8086 Mode" chapter.) |
| 10818 | * 'pc' should be the address of this instruction, it will |
| 10819 | * be used to print the target address if this is a relative jump or call |
| 10820 | * The function returns the length of this instruction in bytes. |
| 10821 | */ |
| 10822 | |
| 10823 | static char intel_syntax; |
| 10824 | static char intel_mnemonic = !SYSV386_COMPAT; |
| 10825 | static char open_char; |
| 10826 | static char close_char; |
| 10827 | static char separator_char; |
| 10828 | static char scale_char; |
| 10829 | |
| 10830 | /* Here for backwards compatibility. When gdb stops using |
| 10831 | print_insn_i386_att and print_insn_i386_intel these functions can |
| 10832 | disappear, and print_insn_i386 be merged into print_insn. */ |
| 10833 | int |
| 10834 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
| 10835 | { |
| 10836 | intel_syntax = 0; |
| 10837 | |
| 10838 | return print_insn (pc, info); |
| 10839 | } |
| 10840 | |
| 10841 | int |
| 10842 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
| 10843 | { |
| 10844 | intel_syntax = 1; |
| 10845 | |
| 10846 | return print_insn (pc, info); |
| 10847 | } |
| 10848 | |
| 10849 | int |
| 10850 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
| 10851 | { |
| 10852 | intel_syntax = -1; |
| 10853 | |
| 10854 | return print_insn (pc, info); |
| 10855 | } |
| 10856 | |
| 10857 | void |
| 10858 | print_i386_disassembler_options (FILE *stream) |
| 10859 | { |
| 10860 | fprintf (stream, _("\n\ |
| 10861 | The following i386/x86-64 specific disassembler options are supported for use\n\ |
| 10862 | with the -M switch (multiple options should be separated by commas):\n")); |
| 10863 | |
| 10864 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); |
| 10865 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); |
| 10866 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); |
| 10867 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); |
| 10868 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); |
| 10869 | fprintf (stream, _(" att-mnemonic\n" |
| 10870 | " Display instruction in AT&T mnemonic\n")); |
| 10871 | fprintf (stream, _(" intel-mnemonic\n" |
| 10872 | " Display instruction in Intel mnemonic\n")); |
| 10873 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
| 10874 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); |
| 10875 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); |
| 10876 | fprintf (stream, _(" data32 Assume 32bit data size\n")); |
| 10877 | fprintf (stream, _(" data16 Assume 16bit data size\n")); |
| 10878 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); |
| 10879 | } |
| 10880 | |
| 10881 | /* Bad opcode. */ |
| 10882 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; |
| 10883 | |
| 10884 | /* Get a pointer to struct dis386 with a valid name. */ |
| 10885 | |
| 10886 | static const struct dis386 * |
| 10887 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
| 10888 | { |
| 10889 | int vindex, vex_table_index; |
| 10890 | |
| 10891 | if (dp->name != NULL) |
| 10892 | return dp; |
| 10893 | |
| 10894 | switch (dp->op[0].bytemode) |
| 10895 | { |
| 10896 | case USE_REG_TABLE: |
| 10897 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; |
| 10898 | break; |
| 10899 | |
| 10900 | case USE_MOD_TABLE: |
| 10901 | vindex = modrm.mod == 0x3 ? 1 : 0; |
| 10902 | dp = &mod_table[dp->op[1].bytemode][vindex]; |
| 10903 | break; |
| 10904 | |
| 10905 | case USE_RM_TABLE: |
| 10906 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; |
| 10907 | break; |
| 10908 | |
| 10909 | case USE_PREFIX_TABLE: |
| 10910 | if (need_vex) |
| 10911 | { |
| 10912 | /* The prefix in VEX is implicit. */ |
| 10913 | switch (vex.prefix) |
| 10914 | { |
| 10915 | case 0: |
| 10916 | vindex = 0; |
| 10917 | break; |
| 10918 | case REPE_PREFIX_OPCODE: |
| 10919 | vindex = 1; |
| 10920 | break; |
| 10921 | case DATA_PREFIX_OPCODE: |
| 10922 | vindex = 2; |
| 10923 | break; |
| 10924 | case REPNE_PREFIX_OPCODE: |
| 10925 | vindex = 3; |
| 10926 | break; |
| 10927 | default: |
| 10928 | abort (); |
| 10929 | break; |
| 10930 | } |
| 10931 | } |
| 10932 | else |
| 10933 | { |
| 10934 | vindex = 0; |
| 10935 | used_prefixes |= (prefixes & PREFIX_REPZ); |
| 10936 | if (prefixes & PREFIX_REPZ) |
| 10937 | { |
| 10938 | vindex = 1; |
| 10939 | all_prefixes[last_repz_prefix] = 0; |
| 10940 | } |
| 10941 | else |
| 10942 | { |
| 10943 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
| 10944 | PREFIX_DATA. */ |
| 10945 | used_prefixes |= (prefixes & PREFIX_REPNZ); |
| 10946 | if (prefixes & PREFIX_REPNZ) |
| 10947 | { |
| 10948 | vindex = 3; |
| 10949 | all_prefixes[last_repnz_prefix] = 0; |
| 10950 | } |
| 10951 | else |
| 10952 | { |
| 10953 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 10954 | if (prefixes & PREFIX_DATA) |
| 10955 | { |
| 10956 | vindex = 2; |
| 10957 | all_prefixes[last_data_prefix] = 0; |
| 10958 | } |
| 10959 | } |
| 10960 | } |
| 10961 | } |
| 10962 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
| 10963 | break; |
| 10964 | |
| 10965 | case USE_X86_64_TABLE: |
| 10966 | vindex = address_mode == mode_64bit ? 1 : 0; |
| 10967 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; |
| 10968 | break; |
| 10969 | |
| 10970 | case USE_3BYTE_TABLE: |
| 10971 | FETCH_DATA (info, codep + 2); |
| 10972 | vindex = *codep++; |
| 10973 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
| 10974 | modrm.mod = (*codep >> 6) & 3; |
| 10975 | modrm.reg = (*codep >> 3) & 7; |
| 10976 | modrm.rm = *codep & 7; |
| 10977 | break; |
| 10978 | |
| 10979 | case USE_VEX_LEN_TABLE: |
| 10980 | if (!need_vex) |
| 10981 | abort (); |
| 10982 | |
| 10983 | switch (vex.length) |
| 10984 | { |
| 10985 | case 128: |
| 10986 | vindex = 0; |
| 10987 | break; |
| 10988 | case 256: |
| 10989 | vindex = 1; |
| 10990 | break; |
| 10991 | default: |
| 10992 | abort (); |
| 10993 | break; |
| 10994 | } |
| 10995 | |
| 10996 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
| 10997 | break; |
| 10998 | |
| 10999 | case USE_XOP_8F_TABLE: |
| 11000 | FETCH_DATA (info, codep + 3); |
| 11001 | /* All bits in the REX prefix are ignored. */ |
| 11002 | rex_ignored = rex; |
| 11003 | rex = ~(*codep >> 5) & 0x7; |
| 11004 | |
| 11005 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ |
| 11006 | switch ((*codep & 0x1f)) |
| 11007 | { |
| 11008 | default: |
| 11009 | dp = &bad_opcode; |
| 11010 | return dp; |
| 11011 | case 0x8: |
| 11012 | vex_table_index = XOP_08; |
| 11013 | break; |
| 11014 | case 0x9: |
| 11015 | vex_table_index = XOP_09; |
| 11016 | break; |
| 11017 | case 0xa: |
| 11018 | vex_table_index = XOP_0A; |
| 11019 | break; |
| 11020 | } |
| 11021 | codep++; |
| 11022 | vex.w = *codep & 0x80; |
| 11023 | if (vex.w && address_mode == mode_64bit) |
| 11024 | rex |= REX_W; |
| 11025 | |
| 11026 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
| 11027 | if (address_mode != mode_64bit |
| 11028 | && vex.register_specifier > 0x7) |
| 11029 | { |
| 11030 | dp = &bad_opcode; |
| 11031 | return dp; |
| 11032 | } |
| 11033 | |
| 11034 | vex.length = (*codep & 0x4) ? 256 : 128; |
| 11035 | switch ((*codep & 0x3)) |
| 11036 | { |
| 11037 | case 0: |
| 11038 | vex.prefix = 0; |
| 11039 | break; |
| 11040 | case 1: |
| 11041 | vex.prefix = DATA_PREFIX_OPCODE; |
| 11042 | break; |
| 11043 | case 2: |
| 11044 | vex.prefix = REPE_PREFIX_OPCODE; |
| 11045 | break; |
| 11046 | case 3: |
| 11047 | vex.prefix = REPNE_PREFIX_OPCODE; |
| 11048 | break; |
| 11049 | } |
| 11050 | need_vex = 1; |
| 11051 | need_vex_reg = 1; |
| 11052 | codep++; |
| 11053 | vindex = *codep++; |
| 11054 | dp = &xop_table[vex_table_index][vindex]; |
| 11055 | |
| 11056 | FETCH_DATA (info, codep + 1); |
| 11057 | modrm.mod = (*codep >> 6) & 3; |
| 11058 | modrm.reg = (*codep >> 3) & 7; |
| 11059 | modrm.rm = *codep & 7; |
| 11060 | break; |
| 11061 | |
| 11062 | case USE_VEX_C4_TABLE: |
| 11063 | FETCH_DATA (info, codep + 3); |
| 11064 | /* All bits in the REX prefix are ignored. */ |
| 11065 | rex_ignored = rex; |
| 11066 | rex = ~(*codep >> 5) & 0x7; |
| 11067 | switch ((*codep & 0x1f)) |
| 11068 | { |
| 11069 | default: |
| 11070 | dp = &bad_opcode; |
| 11071 | return dp; |
| 11072 | case 0x1: |
| 11073 | vex_table_index = VEX_0F; |
| 11074 | break; |
| 11075 | case 0x2: |
| 11076 | vex_table_index = VEX_0F38; |
| 11077 | break; |
| 11078 | case 0x3: |
| 11079 | vex_table_index = VEX_0F3A; |
| 11080 | break; |
| 11081 | } |
| 11082 | codep++; |
| 11083 | vex.w = *codep & 0x80; |
| 11084 | if (vex.w && address_mode == mode_64bit) |
| 11085 | rex |= REX_W; |
| 11086 | |
| 11087 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
| 11088 | if (address_mode != mode_64bit |
| 11089 | && vex.register_specifier > 0x7) |
| 11090 | { |
| 11091 | dp = &bad_opcode; |
| 11092 | return dp; |
| 11093 | } |
| 11094 | |
| 11095 | vex.length = (*codep & 0x4) ? 256 : 128; |
| 11096 | switch ((*codep & 0x3)) |
| 11097 | { |
| 11098 | case 0: |
| 11099 | vex.prefix = 0; |
| 11100 | break; |
| 11101 | case 1: |
| 11102 | vex.prefix = DATA_PREFIX_OPCODE; |
| 11103 | break; |
| 11104 | case 2: |
| 11105 | vex.prefix = REPE_PREFIX_OPCODE; |
| 11106 | break; |
| 11107 | case 3: |
| 11108 | vex.prefix = REPNE_PREFIX_OPCODE; |
| 11109 | break; |
| 11110 | } |
| 11111 | need_vex = 1; |
| 11112 | need_vex_reg = 1; |
| 11113 | codep++; |
| 11114 | vindex = *codep++; |
| 11115 | dp = &vex_table[vex_table_index][vindex]; |
| 11116 | /* There is no MODRM byte for VEX [82|77]. */ |
| 11117 | if (vindex != 0x77 && vindex != 0x82) |
| 11118 | { |
| 11119 | FETCH_DATA (info, codep + 1); |
| 11120 | modrm.mod = (*codep >> 6) & 3; |
| 11121 | modrm.reg = (*codep >> 3) & 7; |
| 11122 | modrm.rm = *codep & 7; |
| 11123 | } |
| 11124 | break; |
| 11125 | |
| 11126 | case USE_VEX_C5_TABLE: |
| 11127 | FETCH_DATA (info, codep + 2); |
| 11128 | /* All bits in the REX prefix are ignored. */ |
| 11129 | rex_ignored = rex; |
| 11130 | rex = (*codep & 0x80) ? 0 : REX_R; |
| 11131 | |
| 11132 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
| 11133 | if (address_mode != mode_64bit |
| 11134 | && vex.register_specifier > 0x7) |
| 11135 | { |
| 11136 | dp = &bad_opcode; |
| 11137 | return dp; |
| 11138 | } |
| 11139 | |
| 11140 | vex.w = 0; |
| 11141 | |
| 11142 | vex.length = (*codep & 0x4) ? 256 : 128; |
| 11143 | switch ((*codep & 0x3)) |
| 11144 | { |
| 11145 | case 0: |
| 11146 | vex.prefix = 0; |
| 11147 | break; |
| 11148 | case 1: |
| 11149 | vex.prefix = DATA_PREFIX_OPCODE; |
| 11150 | break; |
| 11151 | case 2: |
| 11152 | vex.prefix = REPE_PREFIX_OPCODE; |
| 11153 | break; |
| 11154 | case 3: |
| 11155 | vex.prefix = REPNE_PREFIX_OPCODE; |
| 11156 | break; |
| 11157 | } |
| 11158 | need_vex = 1; |
| 11159 | need_vex_reg = 1; |
| 11160 | codep++; |
| 11161 | vindex = *codep++; |
| 11162 | dp = &vex_table[dp->op[1].bytemode][vindex]; |
| 11163 | /* There is no MODRM byte for VEX [82|77]. */ |
| 11164 | if (vindex != 0x77 && vindex != 0x82) |
| 11165 | { |
| 11166 | FETCH_DATA (info, codep + 1); |
| 11167 | modrm.mod = (*codep >> 6) & 3; |
| 11168 | modrm.reg = (*codep >> 3) & 7; |
| 11169 | modrm.rm = *codep & 7; |
| 11170 | } |
| 11171 | break; |
| 11172 | |
| 11173 | case USE_VEX_W_TABLE: |
| 11174 | if (!need_vex) |
| 11175 | abort (); |
| 11176 | |
| 11177 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; |
| 11178 | break; |
| 11179 | |
| 11180 | case 0: |
| 11181 | dp = &bad_opcode; |
| 11182 | break; |
| 11183 | |
| 11184 | default: |
| 11185 | abort (); |
| 11186 | } |
| 11187 | |
| 11188 | if (dp->name != NULL) |
| 11189 | return dp; |
| 11190 | else |
| 11191 | return get_valid_dis386 (dp, info); |
| 11192 | } |
| 11193 | |
| 11194 | static void |
| 11195 | get_sib (disassemble_info *info) |
| 11196 | { |
| 11197 | /* If modrm.mod == 3, operand must be register. */ |
| 11198 | if (need_modrm |
| 11199 | && address_mode != mode_16bit |
| 11200 | && modrm.mod != 3 |
| 11201 | && modrm.rm == 4) |
| 11202 | { |
| 11203 | FETCH_DATA (info, codep + 2); |
| 11204 | sib.index = (codep [1] >> 3) & 7; |
| 11205 | sib.scale = (codep [1] >> 6) & 3; |
| 11206 | sib.base = codep [1] & 7; |
| 11207 | } |
| 11208 | } |
| 11209 | |
| 11210 | static int |
| 11211 | print_insn (bfd_vma pc, disassemble_info *info) |
| 11212 | { |
| 11213 | const struct dis386 *dp; |
| 11214 | int i; |
| 11215 | char *op_txt[MAX_OPERANDS]; |
| 11216 | int needcomma; |
| 11217 | int sizeflag; |
| 11218 | const char *p; |
| 11219 | struct dis_private priv; |
| 11220 | int prefix_length; |
| 11221 | int default_prefixes; |
| 11222 | |
| 11223 | priv.orig_sizeflag = AFLAG | DFLAG; |
| 11224 | if ((info->mach & bfd_mach_i386_i386) != 0) |
| 11225 | address_mode = mode_32bit; |
| 11226 | else if (info->mach == bfd_mach_i386_i8086) |
| 11227 | { |
| 11228 | address_mode = mode_16bit; |
| 11229 | priv.orig_sizeflag = 0; |
| 11230 | } |
| 11231 | else |
| 11232 | address_mode = mode_64bit; |
| 11233 | |
| 11234 | if (intel_syntax == (char) -1) |
| 11235 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; |
| 11236 | |
| 11237 | for (p = info->disassembler_options; p != NULL; ) |
| 11238 | { |
| 11239 | if (CONST_STRNEQ (p, "x86-64")) |
| 11240 | { |
| 11241 | address_mode = mode_64bit; |
| 11242 | priv.orig_sizeflag = AFLAG | DFLAG; |
| 11243 | } |
| 11244 | else if (CONST_STRNEQ (p, "i386")) |
| 11245 | { |
| 11246 | address_mode = mode_32bit; |
| 11247 | priv.orig_sizeflag = AFLAG | DFLAG; |
| 11248 | } |
| 11249 | else if (CONST_STRNEQ (p, "i8086")) |
| 11250 | { |
| 11251 | address_mode = mode_16bit; |
| 11252 | priv.orig_sizeflag = 0; |
| 11253 | } |
| 11254 | else if (CONST_STRNEQ (p, "intel")) |
| 11255 | { |
| 11256 | intel_syntax = 1; |
| 11257 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
| 11258 | intel_mnemonic = 1; |
| 11259 | } |
| 11260 | else if (CONST_STRNEQ (p, "att")) |
| 11261 | { |
| 11262 | intel_syntax = 0; |
| 11263 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
| 11264 | intel_mnemonic = 0; |
| 11265 | } |
| 11266 | else if (CONST_STRNEQ (p, "addr")) |
| 11267 | { |
| 11268 | if (address_mode == mode_64bit) |
| 11269 | { |
| 11270 | if (p[4] == '3' && p[5] == '2') |
| 11271 | priv.orig_sizeflag &= ~AFLAG; |
| 11272 | else if (p[4] == '6' && p[5] == '4') |
| 11273 | priv.orig_sizeflag |= AFLAG; |
| 11274 | } |
| 11275 | else |
| 11276 | { |
| 11277 | if (p[4] == '1' && p[5] == '6') |
| 11278 | priv.orig_sizeflag &= ~AFLAG; |
| 11279 | else if (p[4] == '3' && p[5] == '2') |
| 11280 | priv.orig_sizeflag |= AFLAG; |
| 11281 | } |
| 11282 | } |
| 11283 | else if (CONST_STRNEQ (p, "data")) |
| 11284 | { |
| 11285 | if (p[4] == '1' && p[5] == '6') |
| 11286 | priv.orig_sizeflag &= ~DFLAG; |
| 11287 | else if (p[4] == '3' && p[5] == '2') |
| 11288 | priv.orig_sizeflag |= DFLAG; |
| 11289 | } |
| 11290 | else if (CONST_STRNEQ (p, "suffix")) |
| 11291 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
| 11292 | |
| 11293 | p = strchr (p, ','); |
| 11294 | if (p != NULL) |
| 11295 | p++; |
| 11296 | } |
| 11297 | |
| 11298 | if (intel_syntax) |
| 11299 | { |
| 11300 | names64 = intel_names64; |
| 11301 | names32 = intel_names32; |
| 11302 | names16 = intel_names16; |
| 11303 | names8 = intel_names8; |
| 11304 | names8rex = intel_names8rex; |
| 11305 | names_seg = intel_names_seg; |
| 11306 | names_mm = intel_names_mm; |
| 11307 | names_xmm = intel_names_xmm; |
| 11308 | names_ymm = intel_names_ymm; |
| 11309 | index64 = intel_index64; |
| 11310 | index32 = intel_index32; |
| 11311 | index16 = intel_index16; |
| 11312 | open_char = '['; |
| 11313 | close_char = ']'; |
| 11314 | separator_char = '+'; |
| 11315 | scale_char = '*'; |
| 11316 | } |
| 11317 | else |
| 11318 | { |
| 11319 | names64 = att_names64; |
| 11320 | names32 = att_names32; |
| 11321 | names16 = att_names16; |
| 11322 | names8 = att_names8; |
| 11323 | names8rex = att_names8rex; |
| 11324 | names_seg = att_names_seg; |
| 11325 | names_mm = att_names_mm; |
| 11326 | names_xmm = att_names_xmm; |
| 11327 | names_ymm = att_names_ymm; |
| 11328 | index64 = att_index64; |
| 11329 | index32 = att_index32; |
| 11330 | index16 = att_index16; |
| 11331 | open_char = '('; |
| 11332 | close_char = ')'; |
| 11333 | separator_char = ','; |
| 11334 | scale_char = ','; |
| 11335 | } |
| 11336 | |
| 11337 | /* The output looks better if we put 7 bytes on a line, since that |
| 11338 | puts most long word instructions on a single line. Use 8 bytes |
| 11339 | for Intel L1OM. */ |
| 11340 | if ((info->mach & bfd_mach_l1om) != 0) |
| 11341 | info->bytes_per_line = 8; |
| 11342 | else |
| 11343 | info->bytes_per_line = 7; |
| 11344 | |
| 11345 | info->private_data = &priv; |
| 11346 | priv.max_fetched = priv.the_buffer; |
| 11347 | priv.insn_start = pc; |
| 11348 | |
| 11349 | obuf[0] = 0; |
| 11350 | for (i = 0; i < MAX_OPERANDS; ++i) |
| 11351 | { |
| 11352 | op_out[i][0] = 0; |
| 11353 | op_index[i] = -1; |
| 11354 | } |
| 11355 | |
| 11356 | the_info = info; |
| 11357 | start_pc = pc; |
| 11358 | start_codep = priv.the_buffer; |
| 11359 | codep = priv.the_buffer; |
| 11360 | |
| 11361 | if (setjmp (priv.bailout) != 0) |
| 11362 | { |
| 11363 | const char *name; |
| 11364 | |
| 11365 | /* Getting here means we tried for data but didn't get it. That |
| 11366 | means we have an incomplete instruction of some sort. Just |
| 11367 | print the first byte as a prefix or a .byte pseudo-op. */ |
| 11368 | if (codep > priv.the_buffer) |
| 11369 | { |
| 11370 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
| 11371 | if (name != NULL) |
| 11372 | (*info->fprintf_func) (info->stream, "%s", name); |
| 11373 | else |
| 11374 | { |
| 11375 | /* Just print the first byte as a .byte instruction. */ |
| 11376 | (*info->fprintf_func) (info->stream, ".byte 0x%x", |
| 11377 | (unsigned int) priv.the_buffer[0]); |
| 11378 | } |
| 11379 | |
| 11380 | return 1; |
| 11381 | } |
| 11382 | |
| 11383 | return -1; |
| 11384 | } |
| 11385 | |
| 11386 | obufp = obuf; |
| 11387 | sizeflag = priv.orig_sizeflag; |
| 11388 | |
| 11389 | if (!ckprefix () || rex_used) |
| 11390 | { |
| 11391 | /* Too many prefixes or unused REX prefixes. */ |
| 11392 | for (i = 0; |
| 11393 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
| 11394 | i++) |
| 11395 | (*info->fprintf_func) (info->stream, "%s", |
| 11396 | prefix_name (all_prefixes[i], sizeflag)); |
| 11397 | return 1; |
| 11398 | } |
| 11399 | |
| 11400 | insn_codep = codep; |
| 11401 | |
| 11402 | FETCH_DATA (info, codep + 1); |
| 11403 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); |
| 11404 | |
| 11405 | if (((prefixes & PREFIX_FWAIT) |
| 11406 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
| 11407 | { |
| 11408 | (*info->fprintf_func) (info->stream, "fwait"); |
| 11409 | return 1; |
| 11410 | } |
| 11411 | |
| 11412 | if (*codep == 0x0f) |
| 11413 | { |
| 11414 | unsigned char threebyte; |
| 11415 | FETCH_DATA (info, codep + 2); |
| 11416 | threebyte = *++codep; |
| 11417 | dp = &dis386_twobyte[threebyte]; |
| 11418 | need_modrm = twobyte_has_modrm[*codep]; |
| 11419 | codep++; |
| 11420 | } |
| 11421 | else |
| 11422 | { |
| 11423 | dp = &dis386[*codep]; |
| 11424 | need_modrm = onebyte_has_modrm[*codep]; |
| 11425 | codep++; |
| 11426 | } |
| 11427 | |
| 11428 | if ((prefixes & PREFIX_REPZ)) |
| 11429 | used_prefixes |= PREFIX_REPZ; |
| 11430 | if ((prefixes & PREFIX_REPNZ)) |
| 11431 | used_prefixes |= PREFIX_REPNZ; |
| 11432 | if ((prefixes & PREFIX_LOCK)) |
| 11433 | used_prefixes |= PREFIX_LOCK; |
| 11434 | |
| 11435 | default_prefixes = 0; |
| 11436 | if (prefixes & PREFIX_ADDR) |
| 11437 | { |
| 11438 | sizeflag ^= AFLAG; |
| 11439 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
| 11440 | { |
| 11441 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
| 11442 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
| 11443 | else |
| 11444 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
| 11445 | default_prefixes |= PREFIX_ADDR; |
| 11446 | } |
| 11447 | } |
| 11448 | |
| 11449 | if ((prefixes & PREFIX_DATA)) |
| 11450 | { |
| 11451 | sizeflag ^= DFLAG; |
| 11452 | if (dp->op[2].bytemode == cond_jump_mode |
| 11453 | && dp->op[0].bytemode == v_mode |
| 11454 | && !intel_syntax) |
| 11455 | { |
| 11456 | if (sizeflag & DFLAG) |
| 11457 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
| 11458 | else |
| 11459 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
| 11460 | default_prefixes |= PREFIX_DATA; |
| 11461 | } |
| 11462 | else if (rex & REX_W) |
| 11463 | { |
| 11464 | /* REX_W will override PREFIX_DATA. */ |
| 11465 | default_prefixes |= PREFIX_DATA; |
| 11466 | } |
| 11467 | } |
| 11468 | |
| 11469 | if (need_modrm) |
| 11470 | { |
| 11471 | FETCH_DATA (info, codep + 1); |
| 11472 | modrm.mod = (*codep >> 6) & 3; |
| 11473 | modrm.reg = (*codep >> 3) & 7; |
| 11474 | modrm.rm = *codep & 7; |
| 11475 | } |
| 11476 | |
| 11477 | need_vex = 0; |
| 11478 | need_vex_reg = 0; |
| 11479 | vex_w_done = 0; |
| 11480 | |
| 11481 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
| 11482 | { |
| 11483 | get_sib (info); |
| 11484 | dofloat (sizeflag); |
| 11485 | } |
| 11486 | else |
| 11487 | { |
| 11488 | dp = get_valid_dis386 (dp, info); |
| 11489 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
| 11490 | { |
| 11491 | get_sib (info); |
| 11492 | for (i = 0; i < MAX_OPERANDS; ++i) |
| 11493 | { |
| 11494 | obufp = op_out[i]; |
| 11495 | op_ad = MAX_OPERANDS - 1 - i; |
| 11496 | if (dp->op[i].rtn) |
| 11497 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); |
| 11498 | } |
| 11499 | } |
| 11500 | } |
| 11501 | |
| 11502 | /* See if any prefixes were not used. If so, print the first one |
| 11503 | separately. If we don't do this, we'll wind up printing an |
| 11504 | instruction stream which does not precisely correspond to the |
| 11505 | bytes we are disassembling. */ |
| 11506 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
| 11507 | { |
| 11508 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
| 11509 | if (all_prefixes[i]) |
| 11510 | { |
| 11511 | const char *name; |
| 11512 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); |
| 11513 | if (name == NULL) |
| 11514 | name = INTERNAL_DISASSEMBLER_ERROR; |
| 11515 | (*info->fprintf_func) (info->stream, "%s", name); |
| 11516 | return 1; |
| 11517 | } |
| 11518 | } |
| 11519 | |
| 11520 | /* Check if the REX prefix is used. */ |
| 11521 | if (rex_ignored == 0 && (rex ^ rex_used) == 0) |
| 11522 | all_prefixes[last_rex_prefix] = 0; |
| 11523 | |
| 11524 | /* Check if the SEG prefix is used. */ |
| 11525 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
| 11526 | | PREFIX_FS | PREFIX_GS)) != 0 |
| 11527 | && (used_prefixes |
| 11528 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) |
| 11529 | all_prefixes[last_seg_prefix] = 0; |
| 11530 | |
| 11531 | /* Check if the ADDR prefix is used. */ |
| 11532 | if ((prefixes & PREFIX_ADDR) != 0 |
| 11533 | && (used_prefixes & PREFIX_ADDR) != 0) |
| 11534 | all_prefixes[last_addr_prefix] = 0; |
| 11535 | |
| 11536 | /* Check if the DATA prefix is used. */ |
| 11537 | if ((prefixes & PREFIX_DATA) != 0 |
| 11538 | && (used_prefixes & PREFIX_DATA) != 0) |
| 11539 | all_prefixes[last_data_prefix] = 0; |
| 11540 | |
| 11541 | prefix_length = 0; |
| 11542 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
| 11543 | if (all_prefixes[i]) |
| 11544 | { |
| 11545 | const char *name; |
| 11546 | name = prefix_name (all_prefixes[i], sizeflag); |
| 11547 | if (name == NULL) |
| 11548 | abort (); |
| 11549 | prefix_length += strlen (name) + 1; |
| 11550 | (*info->fprintf_func) (info->stream, "%s ", name); |
| 11551 | } |
| 11552 | |
| 11553 | /* Check maximum code length. */ |
| 11554 | if ((codep - start_codep) > MAX_CODE_LENGTH) |
| 11555 | { |
| 11556 | (*info->fprintf_func) (info->stream, "(bad)"); |
| 11557 | return MAX_CODE_LENGTH; |
| 11558 | } |
| 11559 | |
| 11560 | obufp = mnemonicendp; |
| 11561 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
| 11562 | oappend (" "); |
| 11563 | oappend (" "); |
| 11564 | (*info->fprintf_func) (info->stream, "%s", obuf); |
| 11565 | |
| 11566 | /* The enter and bound instructions are printed with operands in the same |
| 11567 | order as the intel book; everything else is printed in reverse order. */ |
| 11568 | if (intel_syntax || two_source_ops) |
| 11569 | { |
| 11570 | bfd_vma riprel; |
| 11571 | |
| 11572 | for (i = 0; i < MAX_OPERANDS; ++i) |
| 11573 | op_txt[i] = op_out[i]; |
| 11574 | |
| 11575 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
| 11576 | { |
| 11577 | op_ad = op_index[i]; |
| 11578 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; |
| 11579 | op_index[MAX_OPERANDS - 1 - i] = op_ad; |
| 11580 | riprel = op_riprel[i]; |
| 11581 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; |
| 11582 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; |
| 11583 | } |
| 11584 | } |
| 11585 | else |
| 11586 | { |
| 11587 | for (i = 0; i < MAX_OPERANDS; ++i) |
| 11588 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
| 11589 | } |
| 11590 | |
| 11591 | needcomma = 0; |
| 11592 | for (i = 0; i < MAX_OPERANDS; ++i) |
| 11593 | if (*op_txt[i]) |
| 11594 | { |
| 11595 | if (needcomma) |
| 11596 | (*info->fprintf_func) (info->stream, ","); |
| 11597 | if (op_index[i] != -1 && !op_riprel[i]) |
| 11598 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); |
| 11599 | else |
| 11600 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); |
| 11601 | needcomma = 1; |
| 11602 | } |
| 11603 | |
| 11604 | for (i = 0; i < MAX_OPERANDS; i++) |
| 11605 | if (op_index[i] != -1 && op_riprel[i]) |
| 11606 | { |
| 11607 | (*info->fprintf_func) (info->stream, " # "); |
| 11608 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep |
| 11609 | + op_address[op_index[i]]), info); |
| 11610 | break; |
| 11611 | } |
| 11612 | return codep - priv.the_buffer; |
| 11613 | } |
| 11614 | |
| 11615 | static const char *float_mem[] = { |
| 11616 | /* d8 */ |
| 11617 | "fadd{s|}", |
| 11618 | "fmul{s|}", |
| 11619 | "fcom{s|}", |
| 11620 | "fcomp{s|}", |
| 11621 | "fsub{s|}", |
| 11622 | "fsubr{s|}", |
| 11623 | "fdiv{s|}", |
| 11624 | "fdivr{s|}", |
| 11625 | /* d9 */ |
| 11626 | "fld{s|}", |
| 11627 | "(bad)", |
| 11628 | "fst{s|}", |
| 11629 | "fstp{s|}", |
| 11630 | "fldenvIC", |
| 11631 | "fldcw", |
| 11632 | "fNstenvIC", |
| 11633 | "fNstcw", |
| 11634 | /* da */ |
| 11635 | "fiadd{l|}", |
| 11636 | "fimul{l|}", |
| 11637 | "ficom{l|}", |
| 11638 | "ficomp{l|}", |
| 11639 | "fisub{l|}", |
| 11640 | "fisubr{l|}", |
| 11641 | "fidiv{l|}", |
| 11642 | "fidivr{l|}", |
| 11643 | /* db */ |
| 11644 | "fild{l|}", |
| 11645 | "fisttp{l|}", |
| 11646 | "fist{l|}", |
| 11647 | "fistp{l|}", |
| 11648 | "(bad)", |
| 11649 | "fld{t||t|}", |
| 11650 | "(bad)", |
| 11651 | "fstp{t||t|}", |
| 11652 | /* dc */ |
| 11653 | "fadd{l|}", |
| 11654 | "fmul{l|}", |
| 11655 | "fcom{l|}", |
| 11656 | "fcomp{l|}", |
| 11657 | "fsub{l|}", |
| 11658 | "fsubr{l|}", |
| 11659 | "fdiv{l|}", |
| 11660 | "fdivr{l|}", |
| 11661 | /* dd */ |
| 11662 | "fld{l|}", |
| 11663 | "fisttp{ll|}", |
| 11664 | "fst{l||}", |
| 11665 | "fstp{l|}", |
| 11666 | "frstorIC", |
| 11667 | "(bad)", |
| 11668 | "fNsaveIC", |
| 11669 | "fNstsw", |
| 11670 | /* de */ |
| 11671 | "fiadd", |
| 11672 | "fimul", |
| 11673 | "ficom", |
| 11674 | "ficomp", |
| 11675 | "fisub", |
| 11676 | "fisubr", |
| 11677 | "fidiv", |
| 11678 | "fidivr", |
| 11679 | /* df */ |
| 11680 | "fild", |
| 11681 | "fisttp", |
| 11682 | "fist", |
| 11683 | "fistp", |
| 11684 | "fbld", |
| 11685 | "fild{ll|}", |
| 11686 | "fbstp", |
| 11687 | "fistp{ll|}", |
| 11688 | }; |
| 11689 | |
| 11690 | static const unsigned char float_mem_mode[] = { |
| 11691 | /* d8 */ |
| 11692 | d_mode, |
| 11693 | d_mode, |
| 11694 | d_mode, |
| 11695 | d_mode, |
| 11696 | d_mode, |
| 11697 | d_mode, |
| 11698 | d_mode, |
| 11699 | d_mode, |
| 11700 | /* d9 */ |
| 11701 | d_mode, |
| 11702 | 0, |
| 11703 | d_mode, |
| 11704 | d_mode, |
| 11705 | 0, |
| 11706 | w_mode, |
| 11707 | 0, |
| 11708 | w_mode, |
| 11709 | /* da */ |
| 11710 | d_mode, |
| 11711 | d_mode, |
| 11712 | d_mode, |
| 11713 | d_mode, |
| 11714 | d_mode, |
| 11715 | d_mode, |
| 11716 | d_mode, |
| 11717 | d_mode, |
| 11718 | /* db */ |
| 11719 | d_mode, |
| 11720 | d_mode, |
| 11721 | d_mode, |
| 11722 | d_mode, |
| 11723 | 0, |
| 11724 | t_mode, |
| 11725 | 0, |
| 11726 | t_mode, |
| 11727 | /* dc */ |
| 11728 | q_mode, |
| 11729 | q_mode, |
| 11730 | q_mode, |
| 11731 | q_mode, |
| 11732 | q_mode, |
| 11733 | q_mode, |
| 11734 | q_mode, |
| 11735 | q_mode, |
| 11736 | /* dd */ |
| 11737 | q_mode, |
| 11738 | q_mode, |
| 11739 | q_mode, |
| 11740 | q_mode, |
| 11741 | 0, |
| 11742 | 0, |
| 11743 | 0, |
| 11744 | w_mode, |
| 11745 | /* de */ |
| 11746 | w_mode, |
| 11747 | w_mode, |
| 11748 | w_mode, |
| 11749 | w_mode, |
| 11750 | w_mode, |
| 11751 | w_mode, |
| 11752 | w_mode, |
| 11753 | w_mode, |
| 11754 | /* df */ |
| 11755 | w_mode, |
| 11756 | w_mode, |
| 11757 | w_mode, |
| 11758 | w_mode, |
| 11759 | t_mode, |
| 11760 | q_mode, |
| 11761 | t_mode, |
| 11762 | q_mode |
| 11763 | }; |
| 11764 | |
| 11765 | #define ST { OP_ST, 0 } |
| 11766 | #define STi { OP_STi, 0 } |
| 11767 | |
| 11768 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
| 11769 | #define FGRPd9_4 NULL, { { NULL, 1 } } |
| 11770 | #define FGRPd9_5 NULL, { { NULL, 2 } } |
| 11771 | #define FGRPd9_6 NULL, { { NULL, 3 } } |
| 11772 | #define FGRPd9_7 NULL, { { NULL, 4 } } |
| 11773 | #define FGRPda_5 NULL, { { NULL, 5 } } |
| 11774 | #define FGRPdb_4 NULL, { { NULL, 6 } } |
| 11775 | #define FGRPde_3 NULL, { { NULL, 7 } } |
| 11776 | #define FGRPdf_4 NULL, { { NULL, 8 } } |
| 11777 | |
| 11778 | static const struct dis386 float_reg[][8] = { |
| 11779 | /* d8 */ |
| 11780 | { |
| 11781 | { "fadd", { ST, STi } }, |
| 11782 | { "fmul", { ST, STi } }, |
| 11783 | { "fcom", { STi } }, |
| 11784 | { "fcomp", { STi } }, |
| 11785 | { "fsub", { ST, STi } }, |
| 11786 | { "fsubr", { ST, STi } }, |
| 11787 | { "fdiv", { ST, STi } }, |
| 11788 | { "fdivr", { ST, STi } }, |
| 11789 | }, |
| 11790 | /* d9 */ |
| 11791 | { |
| 11792 | { "fld", { STi } }, |
| 11793 | { "fxch", { STi } }, |
| 11794 | { FGRPd9_2 }, |
| 11795 | { Bad_Opcode }, |
| 11796 | { FGRPd9_4 }, |
| 11797 | { FGRPd9_5 }, |
| 11798 | { FGRPd9_6 }, |
| 11799 | { FGRPd9_7 }, |
| 11800 | }, |
| 11801 | /* da */ |
| 11802 | { |
| 11803 | { "fcmovb", { ST, STi } }, |
| 11804 | { "fcmove", { ST, STi } }, |
| 11805 | { "fcmovbe",{ ST, STi } }, |
| 11806 | { "fcmovu", { ST, STi } }, |
| 11807 | { Bad_Opcode }, |
| 11808 | { FGRPda_5 }, |
| 11809 | { Bad_Opcode }, |
| 11810 | { Bad_Opcode }, |
| 11811 | }, |
| 11812 | /* db */ |
| 11813 | { |
| 11814 | { "fcmovnb",{ ST, STi } }, |
| 11815 | { "fcmovne",{ ST, STi } }, |
| 11816 | { "fcmovnbe",{ ST, STi } }, |
| 11817 | { "fcmovnu",{ ST, STi } }, |
| 11818 | { FGRPdb_4 }, |
| 11819 | { "fucomi", { ST, STi } }, |
| 11820 | { "fcomi", { ST, STi } }, |
| 11821 | { Bad_Opcode }, |
| 11822 | }, |
| 11823 | /* dc */ |
| 11824 | { |
| 11825 | { "fadd", { STi, ST } }, |
| 11826 | { "fmul", { STi, ST } }, |
| 11827 | { Bad_Opcode }, |
| 11828 | { Bad_Opcode }, |
| 11829 | { "fsub!M", { STi, ST } }, |
| 11830 | { "fsubM", { STi, ST } }, |
| 11831 | { "fdiv!M", { STi, ST } }, |
| 11832 | { "fdivM", { STi, ST } }, |
| 11833 | }, |
| 11834 | /* dd */ |
| 11835 | { |
| 11836 | { "ffree", { STi } }, |
| 11837 | { Bad_Opcode }, |
| 11838 | { "fst", { STi } }, |
| 11839 | { "fstp", { STi } }, |
| 11840 | { "fucom", { STi } }, |
| 11841 | { "fucomp", { STi } }, |
| 11842 | { Bad_Opcode }, |
| 11843 | { Bad_Opcode }, |
| 11844 | }, |
| 11845 | /* de */ |
| 11846 | { |
| 11847 | { "faddp", { STi, ST } }, |
| 11848 | { "fmulp", { STi, ST } }, |
| 11849 | { Bad_Opcode }, |
| 11850 | { FGRPde_3 }, |
| 11851 | { "fsub!Mp", { STi, ST } }, |
| 11852 | { "fsubMp", { STi, ST } }, |
| 11853 | { "fdiv!Mp", { STi, ST } }, |
| 11854 | { "fdivMp", { STi, ST } }, |
| 11855 | }, |
| 11856 | /* df */ |
| 11857 | { |
| 11858 | { "ffreep", { STi } }, |
| 11859 | { Bad_Opcode }, |
| 11860 | { Bad_Opcode }, |
| 11861 | { Bad_Opcode }, |
| 11862 | { FGRPdf_4 }, |
| 11863 | { "fucomip", { ST, STi } }, |
| 11864 | { "fcomip", { ST, STi } }, |
| 11865 | { Bad_Opcode }, |
| 11866 | }, |
| 11867 | }; |
| 11868 | |
| 11869 | static char *fgrps[][8] = { |
| 11870 | /* d9_2 0 */ |
| 11871 | { |
| 11872 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
| 11873 | }, |
| 11874 | |
| 11875 | /* d9_4 1 */ |
| 11876 | { |
| 11877 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", |
| 11878 | }, |
| 11879 | |
| 11880 | /* d9_5 2 */ |
| 11881 | { |
| 11882 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", |
| 11883 | }, |
| 11884 | |
| 11885 | /* d9_6 3 */ |
| 11886 | { |
| 11887 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", |
| 11888 | }, |
| 11889 | |
| 11890 | /* d9_7 4 */ |
| 11891 | { |
| 11892 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", |
| 11893 | }, |
| 11894 | |
| 11895 | /* da_5 5 */ |
| 11896 | { |
| 11897 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
| 11898 | }, |
| 11899 | |
| 11900 | /* db_4 6 */ |
| 11901 | { |
| 11902 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
| 11903 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", |
| 11904 | }, |
| 11905 | |
| 11906 | /* de_3 7 */ |
| 11907 | { |
| 11908 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
| 11909 | }, |
| 11910 | |
| 11911 | /* df_4 8 */ |
| 11912 | { |
| 11913 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", |
| 11914 | }, |
| 11915 | }; |
| 11916 | |
| 11917 | static void |
| 11918 | swap_operand (void) |
| 11919 | { |
| 11920 | mnemonicendp[0] = '.'; |
| 11921 | mnemonicendp[1] = 's'; |
| 11922 | mnemonicendp += 2; |
| 11923 | } |
| 11924 | |
| 11925 | static void |
| 11926 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, |
| 11927 | int sizeflag ATTRIBUTE_UNUSED) |
| 11928 | { |
| 11929 | /* Skip mod/rm byte. */ |
| 11930 | MODRM_CHECK; |
| 11931 | codep++; |
| 11932 | } |
| 11933 | |
| 11934 | static void |
| 11935 | dofloat (int sizeflag) |
| 11936 | { |
| 11937 | const struct dis386 *dp; |
| 11938 | unsigned char floatop; |
| 11939 | |
| 11940 | floatop = codep[-1]; |
| 11941 | |
| 11942 | if (modrm.mod != 3) |
| 11943 | { |
| 11944 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
| 11945 | |
| 11946 | putop (float_mem[fp_indx], sizeflag); |
| 11947 | obufp = op_out[0]; |
| 11948 | op_ad = 2; |
| 11949 | OP_E (float_mem_mode[fp_indx], sizeflag); |
| 11950 | return; |
| 11951 | } |
| 11952 | /* Skip mod/rm byte. */ |
| 11953 | MODRM_CHECK; |
| 11954 | codep++; |
| 11955 | |
| 11956 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
| 11957 | if (dp->name == NULL) |
| 11958 | { |
| 11959 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
| 11960 | |
| 11961 | /* Instruction fnstsw is only one with strange arg. */ |
| 11962 | if (floatop == 0xdf && codep[-1] == 0xe0) |
| 11963 | strcpy (op_out[0], names16[0]); |
| 11964 | } |
| 11965 | else |
| 11966 | { |
| 11967 | putop (dp->name, sizeflag); |
| 11968 | |
| 11969 | obufp = op_out[0]; |
| 11970 | op_ad = 2; |
| 11971 | if (dp->op[0].rtn) |
| 11972 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); |
| 11973 | |
| 11974 | obufp = op_out[1]; |
| 11975 | op_ad = 1; |
| 11976 | if (dp->op[1].rtn) |
| 11977 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); |
| 11978 | } |
| 11979 | } |
| 11980 | |
| 11981 | static void |
| 11982 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 11983 | { |
| 11984 | oappend ("%st" + intel_syntax); |
| 11985 | } |
| 11986 | |
| 11987 | static void |
| 11988 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 11989 | { |
| 11990 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
| 11991 | oappend (scratchbuf + intel_syntax); |
| 11992 | } |
| 11993 | |
| 11994 | /* Capital letters in template are macros. */ |
| 11995 | static int |
| 11996 | putop (const char *in_template, int sizeflag) |
| 11997 | { |
| 11998 | const char *p; |
| 11999 | int alt = 0; |
| 12000 | int cond = 1; |
| 12001 | unsigned int l = 0, len = 1; |
| 12002 | char last[4]; |
| 12003 | |
| 12004 | #define SAVE_LAST(c) \ |
| 12005 | if (l < len && l < sizeof (last)) \ |
| 12006 | last[l++] = c; \ |
| 12007 | else \ |
| 12008 | abort (); |
| 12009 | |
| 12010 | for (p = in_template; *p; p++) |
| 12011 | { |
| 12012 | switch (*p) |
| 12013 | { |
| 12014 | default: |
| 12015 | *obufp++ = *p; |
| 12016 | break; |
| 12017 | case '%': |
| 12018 | len++; |
| 12019 | break; |
| 12020 | case '!': |
| 12021 | cond = 0; |
| 12022 | break; |
| 12023 | case '{': |
| 12024 | alt = 0; |
| 12025 | if (intel_syntax) |
| 12026 | { |
| 12027 | while (*++p != '|') |
| 12028 | if (*p == '}' || *p == '\0') |
| 12029 | abort (); |
| 12030 | } |
| 12031 | /* Fall through. */ |
| 12032 | case 'I': |
| 12033 | alt = 1; |
| 12034 | continue; |
| 12035 | case '|': |
| 12036 | while (*++p != '}') |
| 12037 | { |
| 12038 | if (*p == '\0') |
| 12039 | abort (); |
| 12040 | } |
| 12041 | break; |
| 12042 | case '}': |
| 12043 | break; |
| 12044 | case 'A': |
| 12045 | if (intel_syntax) |
| 12046 | break; |
| 12047 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
| 12048 | *obufp++ = 'b'; |
| 12049 | break; |
| 12050 | case 'B': |
| 12051 | if (l == 0 && len == 1) |
| 12052 | { |
| 12053 | case_B: |
| 12054 | if (intel_syntax) |
| 12055 | break; |
| 12056 | if (sizeflag & SUFFIX_ALWAYS) |
| 12057 | *obufp++ = 'b'; |
| 12058 | } |
| 12059 | else |
| 12060 | { |
| 12061 | if (l != 1 |
| 12062 | || len != 2 |
| 12063 | || last[0] != 'L') |
| 12064 | { |
| 12065 | SAVE_LAST (*p); |
| 12066 | break; |
| 12067 | } |
| 12068 | |
| 12069 | if (address_mode == mode_64bit |
| 12070 | && !(prefixes & PREFIX_ADDR)) |
| 12071 | { |
| 12072 | *obufp++ = 'a'; |
| 12073 | *obufp++ = 'b'; |
| 12074 | *obufp++ = 's'; |
| 12075 | } |
| 12076 | |
| 12077 | goto case_B; |
| 12078 | } |
| 12079 | break; |
| 12080 | case 'C': |
| 12081 | if (intel_syntax && !alt) |
| 12082 | break; |
| 12083 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
| 12084 | { |
| 12085 | if (sizeflag & DFLAG) |
| 12086 | *obufp++ = intel_syntax ? 'd' : 'l'; |
| 12087 | else |
| 12088 | *obufp++ = intel_syntax ? 'w' : 's'; |
| 12089 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12090 | } |
| 12091 | break; |
| 12092 | case 'D': |
| 12093 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
| 12094 | break; |
| 12095 | USED_REX (REX_W); |
| 12096 | if (modrm.mod == 3) |
| 12097 | { |
| 12098 | if (rex & REX_W) |
| 12099 | *obufp++ = 'q'; |
| 12100 | else |
| 12101 | { |
| 12102 | if (sizeflag & DFLAG) |
| 12103 | *obufp++ = intel_syntax ? 'd' : 'l'; |
| 12104 | else |
| 12105 | *obufp++ = 'w'; |
| 12106 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12107 | } |
| 12108 | } |
| 12109 | else |
| 12110 | *obufp++ = 'w'; |
| 12111 | break; |
| 12112 | case 'E': /* For jcxz/jecxz */ |
| 12113 | if (address_mode == mode_64bit) |
| 12114 | { |
| 12115 | if (sizeflag & AFLAG) |
| 12116 | *obufp++ = 'r'; |
| 12117 | else |
| 12118 | *obufp++ = 'e'; |
| 12119 | } |
| 12120 | else |
| 12121 | if (sizeflag & AFLAG) |
| 12122 | *obufp++ = 'e'; |
| 12123 | used_prefixes |= (prefixes & PREFIX_ADDR); |
| 12124 | break; |
| 12125 | case 'F': |
| 12126 | if (intel_syntax) |
| 12127 | break; |
| 12128 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
| 12129 | { |
| 12130 | if (sizeflag & AFLAG) |
| 12131 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
| 12132 | else |
| 12133 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
| 12134 | used_prefixes |= (prefixes & PREFIX_ADDR); |
| 12135 | } |
| 12136 | break; |
| 12137 | case 'G': |
| 12138 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) |
| 12139 | break; |
| 12140 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
| 12141 | *obufp++ = 'l'; |
| 12142 | else |
| 12143 | *obufp++ = 'w'; |
| 12144 | if (!(rex & REX_W)) |
| 12145 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12146 | break; |
| 12147 | case 'H': |
| 12148 | if (intel_syntax) |
| 12149 | break; |
| 12150 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
| 12151 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) |
| 12152 | { |
| 12153 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); |
| 12154 | *obufp++ = ','; |
| 12155 | *obufp++ = 'p'; |
| 12156 | if (prefixes & PREFIX_DS) |
| 12157 | *obufp++ = 't'; |
| 12158 | else |
| 12159 | *obufp++ = 'n'; |
| 12160 | } |
| 12161 | break; |
| 12162 | case 'J': |
| 12163 | if (intel_syntax) |
| 12164 | break; |
| 12165 | *obufp++ = 'l'; |
| 12166 | break; |
| 12167 | case 'K': |
| 12168 | USED_REX (REX_W); |
| 12169 | if (rex & REX_W) |
| 12170 | *obufp++ = 'q'; |
| 12171 | else |
| 12172 | *obufp++ = 'd'; |
| 12173 | break; |
| 12174 | case 'Z': |
| 12175 | if (intel_syntax) |
| 12176 | break; |
| 12177 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) |
| 12178 | { |
| 12179 | *obufp++ = 'q'; |
| 12180 | break; |
| 12181 | } |
| 12182 | /* Fall through. */ |
| 12183 | goto case_L; |
| 12184 | case 'L': |
| 12185 | if (l != 0 || len != 1) |
| 12186 | { |
| 12187 | SAVE_LAST (*p); |
| 12188 | break; |
| 12189 | } |
| 12190 | case_L: |
| 12191 | if (intel_syntax) |
| 12192 | break; |
| 12193 | if (sizeflag & SUFFIX_ALWAYS) |
| 12194 | *obufp++ = 'l'; |
| 12195 | break; |
| 12196 | case 'M': |
| 12197 | if (intel_mnemonic != cond) |
| 12198 | *obufp++ = 'r'; |
| 12199 | break; |
| 12200 | case 'N': |
| 12201 | if ((prefixes & PREFIX_FWAIT) == 0) |
| 12202 | *obufp++ = 'n'; |
| 12203 | else |
| 12204 | used_prefixes |= PREFIX_FWAIT; |
| 12205 | break; |
| 12206 | case 'O': |
| 12207 | USED_REX (REX_W); |
| 12208 | if (rex & REX_W) |
| 12209 | *obufp++ = 'o'; |
| 12210 | else if (intel_syntax && (sizeflag & DFLAG)) |
| 12211 | *obufp++ = 'q'; |
| 12212 | else |
| 12213 | *obufp++ = 'd'; |
| 12214 | if (!(rex & REX_W)) |
| 12215 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12216 | break; |
| 12217 | case 'T': |
| 12218 | if (!intel_syntax |
| 12219 | && address_mode == mode_64bit |
| 12220 | && (sizeflag & DFLAG)) |
| 12221 | { |
| 12222 | *obufp++ = 'q'; |
| 12223 | break; |
| 12224 | } |
| 12225 | /* Fall through. */ |
| 12226 | case 'P': |
| 12227 | if (intel_syntax) |
| 12228 | { |
| 12229 | if ((rex & REX_W) == 0 |
| 12230 | && (prefixes & PREFIX_DATA)) |
| 12231 | { |
| 12232 | if ((sizeflag & DFLAG) == 0) |
| 12233 | *obufp++ = 'w'; |
| 12234 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12235 | } |
| 12236 | break; |
| 12237 | } |
| 12238 | if ((prefixes & PREFIX_DATA) |
| 12239 | || (rex & REX_W) |
| 12240 | || (sizeflag & SUFFIX_ALWAYS)) |
| 12241 | { |
| 12242 | USED_REX (REX_W); |
| 12243 | if (rex & REX_W) |
| 12244 | *obufp++ = 'q'; |
| 12245 | else |
| 12246 | { |
| 12247 | if (sizeflag & DFLAG) |
| 12248 | *obufp++ = 'l'; |
| 12249 | else |
| 12250 | *obufp++ = 'w'; |
| 12251 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12252 | } |
| 12253 | } |
| 12254 | break; |
| 12255 | case 'U': |
| 12256 | if (intel_syntax) |
| 12257 | break; |
| 12258 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
| 12259 | { |
| 12260 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
| 12261 | *obufp++ = 'q'; |
| 12262 | break; |
| 12263 | } |
| 12264 | /* Fall through. */ |
| 12265 | goto case_Q; |
| 12266 | case 'Q': |
| 12267 | if (l == 0 && len == 1) |
| 12268 | { |
| 12269 | case_Q: |
| 12270 | if (intel_syntax && !alt) |
| 12271 | break; |
| 12272 | USED_REX (REX_W); |
| 12273 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
| 12274 | { |
| 12275 | if (rex & REX_W) |
| 12276 | *obufp++ = 'q'; |
| 12277 | else |
| 12278 | { |
| 12279 | if (sizeflag & DFLAG) |
| 12280 | *obufp++ = intel_syntax ? 'd' : 'l'; |
| 12281 | else |
| 12282 | *obufp++ = 'w'; |
| 12283 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12284 | } |
| 12285 | } |
| 12286 | } |
| 12287 | else |
| 12288 | { |
| 12289 | if (l != 1 || len != 2 || last[0] != 'L') |
| 12290 | { |
| 12291 | SAVE_LAST (*p); |
| 12292 | break; |
| 12293 | } |
| 12294 | if (intel_syntax |
| 12295 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
| 12296 | break; |
| 12297 | if ((rex & REX_W)) |
| 12298 | { |
| 12299 | USED_REX (REX_W); |
| 12300 | *obufp++ = 'q'; |
| 12301 | } |
| 12302 | else |
| 12303 | *obufp++ = 'l'; |
| 12304 | } |
| 12305 | break; |
| 12306 | case 'R': |
| 12307 | USED_REX (REX_W); |
| 12308 | if (rex & REX_W) |
| 12309 | *obufp++ = 'q'; |
| 12310 | else if (sizeflag & DFLAG) |
| 12311 | { |
| 12312 | if (intel_syntax) |
| 12313 | *obufp++ = 'd'; |
| 12314 | else |
| 12315 | *obufp++ = 'l'; |
| 12316 | } |
| 12317 | else |
| 12318 | *obufp++ = 'w'; |
| 12319 | if (intel_syntax && !p[1] |
| 12320 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
| 12321 | *obufp++ = 'e'; |
| 12322 | if (!(rex & REX_W)) |
| 12323 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12324 | break; |
| 12325 | case 'V': |
| 12326 | if (l == 0 && len == 1) |
| 12327 | { |
| 12328 | if (intel_syntax) |
| 12329 | break; |
| 12330 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
| 12331 | { |
| 12332 | if (sizeflag & SUFFIX_ALWAYS) |
| 12333 | *obufp++ = 'q'; |
| 12334 | break; |
| 12335 | } |
| 12336 | } |
| 12337 | else |
| 12338 | { |
| 12339 | if (l != 1 |
| 12340 | || len != 2 |
| 12341 | || last[0] != 'L') |
| 12342 | { |
| 12343 | SAVE_LAST (*p); |
| 12344 | break; |
| 12345 | } |
| 12346 | |
| 12347 | if (rex & REX_W) |
| 12348 | { |
| 12349 | *obufp++ = 'a'; |
| 12350 | *obufp++ = 'b'; |
| 12351 | *obufp++ = 's'; |
| 12352 | } |
| 12353 | } |
| 12354 | /* Fall through. */ |
| 12355 | goto case_S; |
| 12356 | case 'S': |
| 12357 | if (l == 0 && len == 1) |
| 12358 | { |
| 12359 | case_S: |
| 12360 | if (intel_syntax) |
| 12361 | break; |
| 12362 | if (sizeflag & SUFFIX_ALWAYS) |
| 12363 | { |
| 12364 | if (rex & REX_W) |
| 12365 | *obufp++ = 'q'; |
| 12366 | else |
| 12367 | { |
| 12368 | if (sizeflag & DFLAG) |
| 12369 | *obufp++ = 'l'; |
| 12370 | else |
| 12371 | *obufp++ = 'w'; |
| 12372 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12373 | } |
| 12374 | } |
| 12375 | } |
| 12376 | else |
| 12377 | { |
| 12378 | if (l != 1 |
| 12379 | || len != 2 |
| 12380 | || last[0] != 'L') |
| 12381 | { |
| 12382 | SAVE_LAST (*p); |
| 12383 | break; |
| 12384 | } |
| 12385 | |
| 12386 | if (address_mode == mode_64bit |
| 12387 | && !(prefixes & PREFIX_ADDR)) |
| 12388 | { |
| 12389 | *obufp++ = 'a'; |
| 12390 | *obufp++ = 'b'; |
| 12391 | *obufp++ = 's'; |
| 12392 | } |
| 12393 | |
| 12394 | goto case_S; |
| 12395 | } |
| 12396 | break; |
| 12397 | case 'X': |
| 12398 | if (l != 0 || len != 1) |
| 12399 | { |
| 12400 | SAVE_LAST (*p); |
| 12401 | break; |
| 12402 | } |
| 12403 | if (need_vex && vex.prefix) |
| 12404 | { |
| 12405 | if (vex.prefix == DATA_PREFIX_OPCODE) |
| 12406 | *obufp++ = 'd'; |
| 12407 | else |
| 12408 | *obufp++ = 's'; |
| 12409 | } |
| 12410 | else |
| 12411 | { |
| 12412 | if (prefixes & PREFIX_DATA) |
| 12413 | *obufp++ = 'd'; |
| 12414 | else |
| 12415 | *obufp++ = 's'; |
| 12416 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12417 | } |
| 12418 | break; |
| 12419 | case 'Y': |
| 12420 | if (l == 0 && len == 1) |
| 12421 | { |
| 12422 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
| 12423 | break; |
| 12424 | if (rex & REX_W) |
| 12425 | { |
| 12426 | USED_REX (REX_W); |
| 12427 | *obufp++ = 'q'; |
| 12428 | } |
| 12429 | break; |
| 12430 | } |
| 12431 | else |
| 12432 | { |
| 12433 | if (l != 1 || len != 2 || last[0] != 'X') |
| 12434 | { |
| 12435 | SAVE_LAST (*p); |
| 12436 | break; |
| 12437 | } |
| 12438 | if (!need_vex) |
| 12439 | abort (); |
| 12440 | if (intel_syntax |
| 12441 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
| 12442 | break; |
| 12443 | switch (vex.length) |
| 12444 | { |
| 12445 | case 128: |
| 12446 | *obufp++ = 'x'; |
| 12447 | break; |
| 12448 | case 256: |
| 12449 | *obufp++ = 'y'; |
| 12450 | break; |
| 12451 | default: |
| 12452 | abort (); |
| 12453 | } |
| 12454 | } |
| 12455 | break; |
| 12456 | case 'W': |
| 12457 | if (l == 0 && len == 1) |
| 12458 | { |
| 12459 | /* operand size flag for cwtl, cbtw */ |
| 12460 | USED_REX (REX_W); |
| 12461 | if (rex & REX_W) |
| 12462 | { |
| 12463 | if (intel_syntax) |
| 12464 | *obufp++ = 'd'; |
| 12465 | else |
| 12466 | *obufp++ = 'l'; |
| 12467 | } |
| 12468 | else if (sizeflag & DFLAG) |
| 12469 | *obufp++ = 'w'; |
| 12470 | else |
| 12471 | *obufp++ = 'b'; |
| 12472 | if (!(rex & REX_W)) |
| 12473 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12474 | } |
| 12475 | else |
| 12476 | { |
| 12477 | if (l != 1 |
| 12478 | || len != 2 |
| 12479 | || (last[0] != 'X' |
| 12480 | && last[0] != 'L')) |
| 12481 | { |
| 12482 | SAVE_LAST (*p); |
| 12483 | break; |
| 12484 | } |
| 12485 | if (!need_vex) |
| 12486 | abort (); |
| 12487 | if (last[0] == 'X') |
| 12488 | *obufp++ = vex.w ? 'd': 's'; |
| 12489 | else |
| 12490 | *obufp++ = vex.w ? 'q': 'd'; |
| 12491 | } |
| 12492 | break; |
| 12493 | } |
| 12494 | alt = 0; |
| 12495 | } |
| 12496 | *obufp = 0; |
| 12497 | mnemonicendp = obufp; |
| 12498 | return 0; |
| 12499 | } |
| 12500 | |
| 12501 | static void |
| 12502 | oappend (const char *s) |
| 12503 | { |
| 12504 | obufp = stpcpy (obufp, s); |
| 12505 | } |
| 12506 | |
| 12507 | static void |
| 12508 | append_seg (void) |
| 12509 | { |
| 12510 | if (prefixes & PREFIX_CS) |
| 12511 | { |
| 12512 | used_prefixes |= PREFIX_CS; |
| 12513 | oappend ("%cs:" + intel_syntax); |
| 12514 | } |
| 12515 | if (prefixes & PREFIX_DS) |
| 12516 | { |
| 12517 | used_prefixes |= PREFIX_DS; |
| 12518 | oappend ("%ds:" + intel_syntax); |
| 12519 | } |
| 12520 | if (prefixes & PREFIX_SS) |
| 12521 | { |
| 12522 | used_prefixes |= PREFIX_SS; |
| 12523 | oappend ("%ss:" + intel_syntax); |
| 12524 | } |
| 12525 | if (prefixes & PREFIX_ES) |
| 12526 | { |
| 12527 | used_prefixes |= PREFIX_ES; |
| 12528 | oappend ("%es:" + intel_syntax); |
| 12529 | } |
| 12530 | if (prefixes & PREFIX_FS) |
| 12531 | { |
| 12532 | used_prefixes |= PREFIX_FS; |
| 12533 | oappend ("%fs:" + intel_syntax); |
| 12534 | } |
| 12535 | if (prefixes & PREFIX_GS) |
| 12536 | { |
| 12537 | used_prefixes |= PREFIX_GS; |
| 12538 | oappend ("%gs:" + intel_syntax); |
| 12539 | } |
| 12540 | } |
| 12541 | |
| 12542 | static void |
| 12543 | OP_indirE (int bytemode, int sizeflag) |
| 12544 | { |
| 12545 | if (!intel_syntax) |
| 12546 | oappend ("*"); |
| 12547 | OP_E (bytemode, sizeflag); |
| 12548 | } |
| 12549 | |
| 12550 | static void |
| 12551 | print_operand_value (char *buf, int hex, bfd_vma disp) |
| 12552 | { |
| 12553 | if (address_mode == mode_64bit) |
| 12554 | { |
| 12555 | if (hex) |
| 12556 | { |
| 12557 | char tmp[30]; |
| 12558 | int i; |
| 12559 | buf[0] = '0'; |
| 12560 | buf[1] = 'x'; |
| 12561 | sprintf_vma (tmp, disp); |
| 12562 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
| 12563 | strcpy (buf + 2, tmp + i); |
| 12564 | } |
| 12565 | else |
| 12566 | { |
| 12567 | bfd_signed_vma v = disp; |
| 12568 | char tmp[30]; |
| 12569 | int i; |
| 12570 | if (v < 0) |
| 12571 | { |
| 12572 | *(buf++) = '-'; |
| 12573 | v = -disp; |
| 12574 | /* Check for possible overflow on 0x8000000000000000. */ |
| 12575 | if (v < 0) |
| 12576 | { |
| 12577 | strcpy (buf, "9223372036854775808"); |
| 12578 | return; |
| 12579 | } |
| 12580 | } |
| 12581 | if (!v) |
| 12582 | { |
| 12583 | strcpy (buf, "0"); |
| 12584 | return; |
| 12585 | } |
| 12586 | |
| 12587 | i = 0; |
| 12588 | tmp[29] = 0; |
| 12589 | while (v) |
| 12590 | { |
| 12591 | tmp[28 - i] = (v % 10) + '0'; |
| 12592 | v /= 10; |
| 12593 | i++; |
| 12594 | } |
| 12595 | strcpy (buf, tmp + 29 - i); |
| 12596 | } |
| 12597 | } |
| 12598 | else |
| 12599 | { |
| 12600 | if (hex) |
| 12601 | sprintf (buf, "0x%x", (unsigned int) disp); |
| 12602 | else |
| 12603 | sprintf (buf, "%d", (int) disp); |
| 12604 | } |
| 12605 | } |
| 12606 | |
| 12607 | /* Put DISP in BUF as signed hex number. */ |
| 12608 | |
| 12609 | static void |
| 12610 | print_displacement (char *buf, bfd_vma disp) |
| 12611 | { |
| 12612 | bfd_signed_vma val = disp; |
| 12613 | char tmp[30]; |
| 12614 | int i, j = 0; |
| 12615 | |
| 12616 | if (val < 0) |
| 12617 | { |
| 12618 | buf[j++] = '-'; |
| 12619 | val = -disp; |
| 12620 | |
| 12621 | /* Check for possible overflow. */ |
| 12622 | if (val < 0) |
| 12623 | { |
| 12624 | switch (address_mode) |
| 12625 | { |
| 12626 | case mode_64bit: |
| 12627 | strcpy (buf + j, "0x8000000000000000"); |
| 12628 | break; |
| 12629 | case mode_32bit: |
| 12630 | strcpy (buf + j, "0x80000000"); |
| 12631 | break; |
| 12632 | case mode_16bit: |
| 12633 | strcpy (buf + j, "0x8000"); |
| 12634 | break; |
| 12635 | } |
| 12636 | return; |
| 12637 | } |
| 12638 | } |
| 12639 | |
| 12640 | buf[j++] = '0'; |
| 12641 | buf[j++] = 'x'; |
| 12642 | |
| 12643 | sprintf_vma (tmp, (bfd_vma) val); |
| 12644 | for (i = 0; tmp[i] == '0'; i++) |
| 12645 | continue; |
| 12646 | if (tmp[i] == '\0') |
| 12647 | i--; |
| 12648 | strcpy (buf + j, tmp + i); |
| 12649 | } |
| 12650 | |
| 12651 | static void |
| 12652 | intel_operand_size (int bytemode, int sizeflag) |
| 12653 | { |
| 12654 | switch (bytemode) |
| 12655 | { |
| 12656 | case b_mode: |
| 12657 | case b_swap_mode: |
| 12658 | case dqb_mode: |
| 12659 | oappend ("BYTE PTR "); |
| 12660 | break; |
| 12661 | case w_mode: |
| 12662 | case dqw_mode: |
| 12663 | oappend ("WORD PTR "); |
| 12664 | break; |
| 12665 | case stack_v_mode: |
| 12666 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
| 12667 | { |
| 12668 | oappend ("QWORD PTR "); |
| 12669 | break; |
| 12670 | } |
| 12671 | /* FALLTHRU */ |
| 12672 | case v_mode: |
| 12673 | case v_swap_mode: |
| 12674 | case dq_mode: |
| 12675 | USED_REX (REX_W); |
| 12676 | if (rex & REX_W) |
| 12677 | oappend ("QWORD PTR "); |
| 12678 | else |
| 12679 | { |
| 12680 | if ((sizeflag & DFLAG) || bytemode == dq_mode) |
| 12681 | oappend ("DWORD PTR "); |
| 12682 | else |
| 12683 | oappend ("WORD PTR "); |
| 12684 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12685 | } |
| 12686 | break; |
| 12687 | case z_mode: |
| 12688 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
| 12689 | *obufp++ = 'D'; |
| 12690 | oappend ("WORD PTR "); |
| 12691 | if (!(rex & REX_W)) |
| 12692 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12693 | break; |
| 12694 | case a_mode: |
| 12695 | if (sizeflag & DFLAG) |
| 12696 | oappend ("QWORD PTR "); |
| 12697 | else |
| 12698 | oappend ("DWORD PTR "); |
| 12699 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12700 | break; |
| 12701 | case d_mode: |
| 12702 | case d_scalar_mode: |
| 12703 | case d_scalar_swap_mode: |
| 12704 | case d_swap_mode: |
| 12705 | case dqd_mode: |
| 12706 | oappend ("DWORD PTR "); |
| 12707 | break; |
| 12708 | case q_mode: |
| 12709 | case q_scalar_mode: |
| 12710 | case q_scalar_swap_mode: |
| 12711 | case q_swap_mode: |
| 12712 | oappend ("QWORD PTR "); |
| 12713 | break; |
| 12714 | case m_mode: |
| 12715 | if (address_mode == mode_64bit) |
| 12716 | oappend ("QWORD PTR "); |
| 12717 | else |
| 12718 | oappend ("DWORD PTR "); |
| 12719 | break; |
| 12720 | case f_mode: |
| 12721 | if (sizeflag & DFLAG) |
| 12722 | oappend ("FWORD PTR "); |
| 12723 | else |
| 12724 | oappend ("DWORD PTR "); |
| 12725 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12726 | break; |
| 12727 | case t_mode: |
| 12728 | oappend ("TBYTE PTR "); |
| 12729 | break; |
| 12730 | case x_mode: |
| 12731 | case x_swap_mode: |
| 12732 | if (need_vex) |
| 12733 | { |
| 12734 | switch (vex.length) |
| 12735 | { |
| 12736 | case 128: |
| 12737 | oappend ("XMMWORD PTR "); |
| 12738 | break; |
| 12739 | case 256: |
| 12740 | oappend ("YMMWORD PTR "); |
| 12741 | break; |
| 12742 | default: |
| 12743 | abort (); |
| 12744 | } |
| 12745 | } |
| 12746 | else |
| 12747 | oappend ("XMMWORD PTR "); |
| 12748 | break; |
| 12749 | case xmm_mode: |
| 12750 | oappend ("XMMWORD PTR "); |
| 12751 | break; |
| 12752 | case xmmq_mode: |
| 12753 | if (!need_vex) |
| 12754 | abort (); |
| 12755 | |
| 12756 | switch (vex.length) |
| 12757 | { |
| 12758 | case 128: |
| 12759 | oappend ("QWORD PTR "); |
| 12760 | break; |
| 12761 | case 256: |
| 12762 | oappend ("XMMWORD PTR "); |
| 12763 | break; |
| 12764 | default: |
| 12765 | abort (); |
| 12766 | } |
| 12767 | break; |
| 12768 | case xmm_mb_mode: |
| 12769 | if (!need_vex) |
| 12770 | abort (); |
| 12771 | |
| 12772 | switch (vex.length) |
| 12773 | { |
| 12774 | case 128: |
| 12775 | case 256: |
| 12776 | oappend ("BYTE PTR "); |
| 12777 | break; |
| 12778 | default: |
| 12779 | abort (); |
| 12780 | } |
| 12781 | break; |
| 12782 | case xmm_mw_mode: |
| 12783 | if (!need_vex) |
| 12784 | abort (); |
| 12785 | |
| 12786 | switch (vex.length) |
| 12787 | { |
| 12788 | case 128: |
| 12789 | case 256: |
| 12790 | oappend ("WORD PTR "); |
| 12791 | break; |
| 12792 | default: |
| 12793 | abort (); |
| 12794 | } |
| 12795 | break; |
| 12796 | case xmm_md_mode: |
| 12797 | if (!need_vex) |
| 12798 | abort (); |
| 12799 | |
| 12800 | switch (vex.length) |
| 12801 | { |
| 12802 | case 128: |
| 12803 | case 256: |
| 12804 | oappend ("DWORD PTR "); |
| 12805 | break; |
| 12806 | default: |
| 12807 | abort (); |
| 12808 | } |
| 12809 | break; |
| 12810 | case xmm_mq_mode: |
| 12811 | if (!need_vex) |
| 12812 | abort (); |
| 12813 | |
| 12814 | switch (vex.length) |
| 12815 | { |
| 12816 | case 128: |
| 12817 | case 256: |
| 12818 | oappend ("QWORD PTR "); |
| 12819 | break; |
| 12820 | default: |
| 12821 | abort (); |
| 12822 | } |
| 12823 | break; |
| 12824 | case xmmdw_mode: |
| 12825 | if (!need_vex) |
| 12826 | abort (); |
| 12827 | |
| 12828 | switch (vex.length) |
| 12829 | { |
| 12830 | case 128: |
| 12831 | oappend ("WORD PTR "); |
| 12832 | break; |
| 12833 | case 256: |
| 12834 | oappend ("DWORD PTR "); |
| 12835 | break; |
| 12836 | default: |
| 12837 | abort (); |
| 12838 | } |
| 12839 | break; |
| 12840 | case xmmqd_mode: |
| 12841 | if (!need_vex) |
| 12842 | abort (); |
| 12843 | |
| 12844 | switch (vex.length) |
| 12845 | { |
| 12846 | case 128: |
| 12847 | oappend ("DWORD PTR "); |
| 12848 | break; |
| 12849 | case 256: |
| 12850 | oappend ("QWORD PTR "); |
| 12851 | break; |
| 12852 | default: |
| 12853 | abort (); |
| 12854 | } |
| 12855 | break; |
| 12856 | case ymmq_mode: |
| 12857 | if (!need_vex) |
| 12858 | abort (); |
| 12859 | |
| 12860 | switch (vex.length) |
| 12861 | { |
| 12862 | case 128: |
| 12863 | oappend ("QWORD PTR "); |
| 12864 | break; |
| 12865 | case 256: |
| 12866 | oappend ("YMMWORD PTR "); |
| 12867 | break; |
| 12868 | default: |
| 12869 | abort (); |
| 12870 | } |
| 12871 | break; |
| 12872 | case ymmxmm_mode: |
| 12873 | if (!need_vex) |
| 12874 | abort (); |
| 12875 | |
| 12876 | switch (vex.length) |
| 12877 | { |
| 12878 | case 128: |
| 12879 | case 256: |
| 12880 | oappend ("XMMWORD PTR "); |
| 12881 | break; |
| 12882 | default: |
| 12883 | abort (); |
| 12884 | } |
| 12885 | break; |
| 12886 | case o_mode: |
| 12887 | oappend ("OWORD PTR "); |
| 12888 | break; |
| 12889 | case vex_w_dq_mode: |
| 12890 | case vex_scalar_w_dq_mode: |
| 12891 | case vex_vsib_d_w_dq_mode: |
| 12892 | case vex_vsib_q_w_dq_mode: |
| 12893 | if (!need_vex) |
| 12894 | abort (); |
| 12895 | |
| 12896 | if (vex.w) |
| 12897 | oappend ("QWORD PTR "); |
| 12898 | else |
| 12899 | oappend ("DWORD PTR "); |
| 12900 | break; |
| 12901 | default: |
| 12902 | break; |
| 12903 | } |
| 12904 | } |
| 12905 | |
| 12906 | static void |
| 12907 | OP_E_register (int bytemode, int sizeflag) |
| 12908 | { |
| 12909 | int reg = modrm.rm; |
| 12910 | const char **names; |
| 12911 | |
| 12912 | USED_REX (REX_B); |
| 12913 | if ((rex & REX_B)) |
| 12914 | reg += 8; |
| 12915 | |
| 12916 | if ((sizeflag & SUFFIX_ALWAYS) |
| 12917 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) |
| 12918 | swap_operand (); |
| 12919 | |
| 12920 | switch (bytemode) |
| 12921 | { |
| 12922 | case b_mode: |
| 12923 | case b_swap_mode: |
| 12924 | USED_REX (0); |
| 12925 | if (rex) |
| 12926 | names = names8rex; |
| 12927 | else |
| 12928 | names = names8; |
| 12929 | break; |
| 12930 | case w_mode: |
| 12931 | names = names16; |
| 12932 | break; |
| 12933 | case d_mode: |
| 12934 | names = names32; |
| 12935 | break; |
| 12936 | case q_mode: |
| 12937 | names = names64; |
| 12938 | break; |
| 12939 | case m_mode: |
| 12940 | names = address_mode == mode_64bit ? names64 : names32; |
| 12941 | break; |
| 12942 | case stack_v_mode: |
| 12943 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
| 12944 | { |
| 12945 | names = names64; |
| 12946 | break; |
| 12947 | } |
| 12948 | bytemode = v_mode; |
| 12949 | /* FALLTHRU */ |
| 12950 | case v_mode: |
| 12951 | case v_swap_mode: |
| 12952 | case dq_mode: |
| 12953 | case dqb_mode: |
| 12954 | case dqd_mode: |
| 12955 | case dqw_mode: |
| 12956 | USED_REX (REX_W); |
| 12957 | if (rex & REX_W) |
| 12958 | names = names64; |
| 12959 | else |
| 12960 | { |
| 12961 | if ((sizeflag & DFLAG) |
| 12962 | || (bytemode != v_mode |
| 12963 | && bytemode != v_swap_mode)) |
| 12964 | names = names32; |
| 12965 | else |
| 12966 | names = names16; |
| 12967 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 12968 | } |
| 12969 | break; |
| 12970 | case 0: |
| 12971 | return; |
| 12972 | default: |
| 12973 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 12974 | return; |
| 12975 | } |
| 12976 | oappend (names[reg]); |
| 12977 | } |
| 12978 | |
| 12979 | static void |
| 12980 | OP_E_memory (int bytemode, int sizeflag) |
| 12981 | { |
| 12982 | bfd_vma disp = 0; |
| 12983 | int add = (rex & REX_B) ? 8 : 0; |
| 12984 | int riprel = 0; |
| 12985 | |
| 12986 | USED_REX (REX_B); |
| 12987 | if (intel_syntax) |
| 12988 | intel_operand_size (bytemode, sizeflag); |
| 12989 | append_seg (); |
| 12990 | |
| 12991 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
| 12992 | { |
| 12993 | /* 32/64 bit address mode */ |
| 12994 | int havedisp; |
| 12995 | int havesib; |
| 12996 | int havebase; |
| 12997 | int haveindex; |
| 12998 | int needindex; |
| 12999 | int base, rbase; |
| 13000 | int vindex = 0; |
| 13001 | int scale = 0; |
| 13002 | const char **indexes64 = names64; |
| 13003 | const char **indexes32 = names32; |
| 13004 | |
| 13005 | havesib = 0; |
| 13006 | havebase = 1; |
| 13007 | haveindex = 0; |
| 13008 | base = modrm.rm; |
| 13009 | |
| 13010 | if (base == 4) |
| 13011 | { |
| 13012 | havesib = 1; |
| 13013 | vindex = sib.index; |
| 13014 | USED_REX (REX_X); |
| 13015 | if (rex & REX_X) |
| 13016 | vindex += 8; |
| 13017 | switch (bytemode) |
| 13018 | { |
| 13019 | case vex_vsib_d_w_dq_mode: |
| 13020 | case vex_vsib_q_w_dq_mode: |
| 13021 | if (!need_vex) |
| 13022 | abort (); |
| 13023 | |
| 13024 | haveindex = 1; |
| 13025 | switch (vex.length) |
| 13026 | { |
| 13027 | case 128: |
| 13028 | indexes64 = indexes32 = names_xmm; |
| 13029 | break; |
| 13030 | case 256: |
| 13031 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) |
| 13032 | indexes64 = indexes32 = names_ymm; |
| 13033 | else |
| 13034 | indexes64 = indexes32 = names_xmm; |
| 13035 | break; |
| 13036 | default: |
| 13037 | abort (); |
| 13038 | } |
| 13039 | break; |
| 13040 | default: |
| 13041 | haveindex = vindex != 4; |
| 13042 | break; |
| 13043 | } |
| 13044 | scale = sib.scale; |
| 13045 | base = sib.base; |
| 13046 | codep++; |
| 13047 | } |
| 13048 | rbase = base + add; |
| 13049 | |
| 13050 | switch (modrm.mod) |
| 13051 | { |
| 13052 | case 0: |
| 13053 | if (base == 5) |
| 13054 | { |
| 13055 | havebase = 0; |
| 13056 | if (address_mode == mode_64bit && !havesib) |
| 13057 | riprel = 1; |
| 13058 | disp = get32s (); |
| 13059 | } |
| 13060 | break; |
| 13061 | case 1: |
| 13062 | FETCH_DATA (the_info, codep + 1); |
| 13063 | disp = *codep++; |
| 13064 | if ((disp & 0x80) != 0) |
| 13065 | disp -= 0x100; |
| 13066 | break; |
| 13067 | case 2: |
| 13068 | disp = get32s (); |
| 13069 | break; |
| 13070 | } |
| 13071 | |
| 13072 | /* In 32bit mode, we need index register to tell [offset] from |
| 13073 | [eiz*1 + offset]. */ |
| 13074 | needindex = (havesib |
| 13075 | && !havebase |
| 13076 | && !haveindex |
| 13077 | && address_mode == mode_32bit); |
| 13078 | havedisp = (havebase |
| 13079 | || needindex |
| 13080 | || (havesib && (haveindex || scale != 0))); |
| 13081 | |
| 13082 | if (!intel_syntax) |
| 13083 | if (modrm.mod != 0 || base == 5) |
| 13084 | { |
| 13085 | if (havedisp || riprel) |
| 13086 | print_displacement (scratchbuf, disp); |
| 13087 | else |
| 13088 | print_operand_value (scratchbuf, 1, disp); |
| 13089 | oappend (scratchbuf); |
| 13090 | if (riprel) |
| 13091 | { |
| 13092 | set_op (disp, 1); |
| 13093 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
| 13094 | } |
| 13095 | } |
| 13096 | |
| 13097 | if (havebase || haveindex || riprel) |
| 13098 | used_prefixes |= PREFIX_ADDR; |
| 13099 | |
| 13100 | if (havedisp || (intel_syntax && riprel)) |
| 13101 | { |
| 13102 | *obufp++ = open_char; |
| 13103 | if (intel_syntax && riprel) |
| 13104 | { |
| 13105 | set_op (disp, 1); |
| 13106 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
| 13107 | } |
| 13108 | *obufp = '\0'; |
| 13109 | if (havebase) |
| 13110 | oappend (address_mode == mode_64bit && (sizeflag & AFLAG) |
| 13111 | ? names64[rbase] : names32[rbase]); |
| 13112 | if (havesib) |
| 13113 | { |
| 13114 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
| 13115 | print index to tell base + index from base. */ |
| 13116 | if (scale != 0 |
| 13117 | || needindex |
| 13118 | || haveindex |
| 13119 | || (havebase && base != ESP_REG_NUM)) |
| 13120 | { |
| 13121 | if (!intel_syntax || havebase) |
| 13122 | { |
| 13123 | *obufp++ = separator_char; |
| 13124 | *obufp = '\0'; |
| 13125 | } |
| 13126 | if (haveindex) |
| 13127 | oappend (address_mode == mode_64bit |
| 13128 | && (sizeflag & AFLAG) |
| 13129 | ? indexes64[vindex] : indexes32[vindex]); |
| 13130 | else |
| 13131 | oappend (address_mode == mode_64bit |
| 13132 | && (sizeflag & AFLAG) |
| 13133 | ? index64 : index32); |
| 13134 | |
| 13135 | *obufp++ = scale_char; |
| 13136 | *obufp = '\0'; |
| 13137 | sprintf (scratchbuf, "%d", 1 << scale); |
| 13138 | oappend (scratchbuf); |
| 13139 | } |
| 13140 | } |
| 13141 | if (intel_syntax |
| 13142 | && (disp || modrm.mod != 0 || base == 5)) |
| 13143 | { |
| 13144 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
| 13145 | { |
| 13146 | *obufp++ = '+'; |
| 13147 | *obufp = '\0'; |
| 13148 | } |
| 13149 | else if (modrm.mod != 1 && disp != -disp) |
| 13150 | { |
| 13151 | *obufp++ = '-'; |
| 13152 | *obufp = '\0'; |
| 13153 | disp = - (bfd_signed_vma) disp; |
| 13154 | } |
| 13155 | |
| 13156 | if (havedisp) |
| 13157 | print_displacement (scratchbuf, disp); |
| 13158 | else |
| 13159 | print_operand_value (scratchbuf, 1, disp); |
| 13160 | oappend (scratchbuf); |
| 13161 | } |
| 13162 | |
| 13163 | *obufp++ = close_char; |
| 13164 | *obufp = '\0'; |
| 13165 | } |
| 13166 | else if (intel_syntax) |
| 13167 | { |
| 13168 | if (modrm.mod != 0 || base == 5) |
| 13169 | { |
| 13170 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
| 13171 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) |
| 13172 | ; |
| 13173 | else |
| 13174 | { |
| 13175 | oappend (names_seg[ds_reg - es_reg]); |
| 13176 | oappend (":"); |
| 13177 | } |
| 13178 | print_operand_value (scratchbuf, 1, disp); |
| 13179 | oappend (scratchbuf); |
| 13180 | } |
| 13181 | } |
| 13182 | } |
| 13183 | else |
| 13184 | { |
| 13185 | /* 16 bit address mode */ |
| 13186 | used_prefixes |= prefixes & PREFIX_ADDR; |
| 13187 | switch (modrm.mod) |
| 13188 | { |
| 13189 | case 0: |
| 13190 | if (modrm.rm == 6) |
| 13191 | { |
| 13192 | disp = get16 (); |
| 13193 | if ((disp & 0x8000) != 0) |
| 13194 | disp -= 0x10000; |
| 13195 | } |
| 13196 | break; |
| 13197 | case 1: |
| 13198 | FETCH_DATA (the_info, codep + 1); |
| 13199 | disp = *codep++; |
| 13200 | if ((disp & 0x80) != 0) |
| 13201 | disp -= 0x100; |
| 13202 | break; |
| 13203 | case 2: |
| 13204 | disp = get16 (); |
| 13205 | if ((disp & 0x8000) != 0) |
| 13206 | disp -= 0x10000; |
| 13207 | break; |
| 13208 | } |
| 13209 | |
| 13210 | if (!intel_syntax) |
| 13211 | if (modrm.mod != 0 || modrm.rm == 6) |
| 13212 | { |
| 13213 | print_displacement (scratchbuf, disp); |
| 13214 | oappend (scratchbuf); |
| 13215 | } |
| 13216 | |
| 13217 | if (modrm.mod != 0 || modrm.rm != 6) |
| 13218 | { |
| 13219 | *obufp++ = open_char; |
| 13220 | *obufp = '\0'; |
| 13221 | oappend (index16[modrm.rm]); |
| 13222 | if (intel_syntax |
| 13223 | && (disp || modrm.mod != 0 || modrm.rm == 6)) |
| 13224 | { |
| 13225 | if ((bfd_signed_vma) disp >= 0) |
| 13226 | { |
| 13227 | *obufp++ = '+'; |
| 13228 | *obufp = '\0'; |
| 13229 | } |
| 13230 | else if (modrm.mod != 1) |
| 13231 | { |
| 13232 | *obufp++ = '-'; |
| 13233 | *obufp = '\0'; |
| 13234 | disp = - (bfd_signed_vma) disp; |
| 13235 | } |
| 13236 | |
| 13237 | print_displacement (scratchbuf, disp); |
| 13238 | oappend (scratchbuf); |
| 13239 | } |
| 13240 | |
| 13241 | *obufp++ = close_char; |
| 13242 | *obufp = '\0'; |
| 13243 | } |
| 13244 | else if (intel_syntax) |
| 13245 | { |
| 13246 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
| 13247 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) |
| 13248 | ; |
| 13249 | else |
| 13250 | { |
| 13251 | oappend (names_seg[ds_reg - es_reg]); |
| 13252 | oappend (":"); |
| 13253 | } |
| 13254 | print_operand_value (scratchbuf, 1, disp & 0xffff); |
| 13255 | oappend (scratchbuf); |
| 13256 | } |
| 13257 | } |
| 13258 | } |
| 13259 | |
| 13260 | static void |
| 13261 | OP_E (int bytemode, int sizeflag) |
| 13262 | { |
| 13263 | /* Skip mod/rm byte. */ |
| 13264 | MODRM_CHECK; |
| 13265 | codep++; |
| 13266 | |
| 13267 | if (modrm.mod == 3) |
| 13268 | OP_E_register (bytemode, sizeflag); |
| 13269 | else |
| 13270 | OP_E_memory (bytemode, sizeflag); |
| 13271 | } |
| 13272 | |
| 13273 | static void |
| 13274 | OP_G (int bytemode, int sizeflag) |
| 13275 | { |
| 13276 | int add = 0; |
| 13277 | USED_REX (REX_R); |
| 13278 | if (rex & REX_R) |
| 13279 | add += 8; |
| 13280 | switch (bytemode) |
| 13281 | { |
| 13282 | case b_mode: |
| 13283 | USED_REX (0); |
| 13284 | if (rex) |
| 13285 | oappend (names8rex[modrm.reg + add]); |
| 13286 | else |
| 13287 | oappend (names8[modrm.reg + add]); |
| 13288 | break; |
| 13289 | case w_mode: |
| 13290 | oappend (names16[modrm.reg + add]); |
| 13291 | break; |
| 13292 | case d_mode: |
| 13293 | oappend (names32[modrm.reg + add]); |
| 13294 | break; |
| 13295 | case q_mode: |
| 13296 | oappend (names64[modrm.reg + add]); |
| 13297 | break; |
| 13298 | case v_mode: |
| 13299 | case dq_mode: |
| 13300 | case dqb_mode: |
| 13301 | case dqd_mode: |
| 13302 | case dqw_mode: |
| 13303 | USED_REX (REX_W); |
| 13304 | if (rex & REX_W) |
| 13305 | oappend (names64[modrm.reg + add]); |
| 13306 | else |
| 13307 | { |
| 13308 | if ((sizeflag & DFLAG) || bytemode != v_mode) |
| 13309 | oappend (names32[modrm.reg + add]); |
| 13310 | else |
| 13311 | oappend (names16[modrm.reg + add]); |
| 13312 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13313 | } |
| 13314 | break; |
| 13315 | case m_mode: |
| 13316 | if (address_mode == mode_64bit) |
| 13317 | oappend (names64[modrm.reg + add]); |
| 13318 | else |
| 13319 | oappend (names32[modrm.reg + add]); |
| 13320 | break; |
| 13321 | default: |
| 13322 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 13323 | break; |
| 13324 | } |
| 13325 | } |
| 13326 | |
| 13327 | static bfd_vma |
| 13328 | get64 (void) |
| 13329 | { |
| 13330 | bfd_vma x; |
| 13331 | #ifdef BFD64 |
| 13332 | unsigned int a; |
| 13333 | unsigned int b; |
| 13334 | |
| 13335 | FETCH_DATA (the_info, codep + 8); |
| 13336 | a = *codep++ & 0xff; |
| 13337 | a |= (*codep++ & 0xff) << 8; |
| 13338 | a |= (*codep++ & 0xff) << 16; |
| 13339 | a |= (*codep++ & 0xff) << 24; |
| 13340 | b = *codep++ & 0xff; |
| 13341 | b |= (*codep++ & 0xff) << 8; |
| 13342 | b |= (*codep++ & 0xff) << 16; |
| 13343 | b |= (*codep++ & 0xff) << 24; |
| 13344 | x = a + ((bfd_vma) b << 32); |
| 13345 | #else |
| 13346 | abort (); |
| 13347 | x = 0; |
| 13348 | #endif |
| 13349 | return x; |
| 13350 | } |
| 13351 | |
| 13352 | static bfd_signed_vma |
| 13353 | get32 (void) |
| 13354 | { |
| 13355 | bfd_signed_vma x = 0; |
| 13356 | |
| 13357 | FETCH_DATA (the_info, codep + 4); |
| 13358 | x = *codep++ & (bfd_signed_vma) 0xff; |
| 13359 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
| 13360 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
| 13361 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
| 13362 | return x; |
| 13363 | } |
| 13364 | |
| 13365 | static bfd_signed_vma |
| 13366 | get32s (void) |
| 13367 | { |
| 13368 | bfd_signed_vma x = 0; |
| 13369 | |
| 13370 | FETCH_DATA (the_info, codep + 4); |
| 13371 | x = *codep++ & (bfd_signed_vma) 0xff; |
| 13372 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; |
| 13373 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; |
| 13374 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; |
| 13375 | |
| 13376 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); |
| 13377 | |
| 13378 | return x; |
| 13379 | } |
| 13380 | |
| 13381 | static int |
| 13382 | get16 (void) |
| 13383 | { |
| 13384 | int x = 0; |
| 13385 | |
| 13386 | FETCH_DATA (the_info, codep + 2); |
| 13387 | x = *codep++ & 0xff; |
| 13388 | x |= (*codep++ & 0xff) << 8; |
| 13389 | return x; |
| 13390 | } |
| 13391 | |
| 13392 | static void |
| 13393 | set_op (bfd_vma op, int riprel) |
| 13394 | { |
| 13395 | op_index[op_ad] = op_ad; |
| 13396 | if (address_mode == mode_64bit) |
| 13397 | { |
| 13398 | op_address[op_ad] = op; |
| 13399 | op_riprel[op_ad] = riprel; |
| 13400 | } |
| 13401 | else |
| 13402 | { |
| 13403 | /* Mask to get a 32-bit address. */ |
| 13404 | op_address[op_ad] = op & 0xffffffff; |
| 13405 | op_riprel[op_ad] = riprel & 0xffffffff; |
| 13406 | } |
| 13407 | } |
| 13408 | |
| 13409 | static void |
| 13410 | OP_REG (int code, int sizeflag) |
| 13411 | { |
| 13412 | const char *s; |
| 13413 | int add; |
| 13414 | USED_REX (REX_B); |
| 13415 | if (rex & REX_B) |
| 13416 | add = 8; |
| 13417 | else |
| 13418 | add = 0; |
| 13419 | |
| 13420 | switch (code) |
| 13421 | { |
| 13422 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
| 13423 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
| 13424 | s = names16[code - ax_reg + add]; |
| 13425 | break; |
| 13426 | case es_reg: case ss_reg: case cs_reg: |
| 13427 | case ds_reg: case fs_reg: case gs_reg: |
| 13428 | s = names_seg[code - es_reg + add]; |
| 13429 | break; |
| 13430 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
| 13431 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
| 13432 | USED_REX (0); |
| 13433 | if (rex) |
| 13434 | s = names8rex[code - al_reg + add]; |
| 13435 | else |
| 13436 | s = names8[code - al_reg]; |
| 13437 | break; |
| 13438 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
| 13439 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: |
| 13440 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
| 13441 | { |
| 13442 | s = names64[code - rAX_reg + add]; |
| 13443 | break; |
| 13444 | } |
| 13445 | code += eAX_reg - rAX_reg; |
| 13446 | /* Fall through. */ |
| 13447 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
| 13448 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
| 13449 | USED_REX (REX_W); |
| 13450 | if (rex & REX_W) |
| 13451 | s = names64[code - eAX_reg + add]; |
| 13452 | else |
| 13453 | { |
| 13454 | if (sizeflag & DFLAG) |
| 13455 | s = names32[code - eAX_reg + add]; |
| 13456 | else |
| 13457 | s = names16[code - eAX_reg + add]; |
| 13458 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13459 | } |
| 13460 | break; |
| 13461 | default: |
| 13462 | s = INTERNAL_DISASSEMBLER_ERROR; |
| 13463 | break; |
| 13464 | } |
| 13465 | oappend (s); |
| 13466 | } |
| 13467 | |
| 13468 | static void |
| 13469 | OP_IMREG (int code, int sizeflag) |
| 13470 | { |
| 13471 | const char *s; |
| 13472 | |
| 13473 | switch (code) |
| 13474 | { |
| 13475 | case indir_dx_reg: |
| 13476 | if (intel_syntax) |
| 13477 | s = "dx"; |
| 13478 | else |
| 13479 | s = "(%dx)"; |
| 13480 | break; |
| 13481 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
| 13482 | case sp_reg: case bp_reg: case si_reg: case di_reg: |
| 13483 | s = names16[code - ax_reg]; |
| 13484 | break; |
| 13485 | case es_reg: case ss_reg: case cs_reg: |
| 13486 | case ds_reg: case fs_reg: case gs_reg: |
| 13487 | s = names_seg[code - es_reg]; |
| 13488 | break; |
| 13489 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
| 13490 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: |
| 13491 | USED_REX (0); |
| 13492 | if (rex) |
| 13493 | s = names8rex[code - al_reg]; |
| 13494 | else |
| 13495 | s = names8[code - al_reg]; |
| 13496 | break; |
| 13497 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
| 13498 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: |
| 13499 | USED_REX (REX_W); |
| 13500 | if (rex & REX_W) |
| 13501 | s = names64[code - eAX_reg]; |
| 13502 | else |
| 13503 | { |
| 13504 | if (sizeflag & DFLAG) |
| 13505 | s = names32[code - eAX_reg]; |
| 13506 | else |
| 13507 | s = names16[code - eAX_reg]; |
| 13508 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13509 | } |
| 13510 | break; |
| 13511 | case z_mode_ax_reg: |
| 13512 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
| 13513 | s = *names32; |
| 13514 | else |
| 13515 | s = *names16; |
| 13516 | if (!(rex & REX_W)) |
| 13517 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13518 | break; |
| 13519 | default: |
| 13520 | s = INTERNAL_DISASSEMBLER_ERROR; |
| 13521 | break; |
| 13522 | } |
| 13523 | oappend (s); |
| 13524 | } |
| 13525 | |
| 13526 | static void |
| 13527 | OP_I (int bytemode, int sizeflag) |
| 13528 | { |
| 13529 | bfd_signed_vma op; |
| 13530 | bfd_signed_vma mask = -1; |
| 13531 | |
| 13532 | switch (bytemode) |
| 13533 | { |
| 13534 | case b_mode: |
| 13535 | FETCH_DATA (the_info, codep + 1); |
| 13536 | op = *codep++; |
| 13537 | mask = 0xff; |
| 13538 | break; |
| 13539 | case q_mode: |
| 13540 | if (address_mode == mode_64bit) |
| 13541 | { |
| 13542 | op = get32s (); |
| 13543 | break; |
| 13544 | } |
| 13545 | /* Fall through. */ |
| 13546 | case v_mode: |
| 13547 | USED_REX (REX_W); |
| 13548 | if (rex & REX_W) |
| 13549 | op = get32s (); |
| 13550 | else |
| 13551 | { |
| 13552 | if (sizeflag & DFLAG) |
| 13553 | { |
| 13554 | op = get32 (); |
| 13555 | mask = 0xffffffff; |
| 13556 | } |
| 13557 | else |
| 13558 | { |
| 13559 | op = get16 (); |
| 13560 | mask = 0xfffff; |
| 13561 | } |
| 13562 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13563 | } |
| 13564 | break; |
| 13565 | case w_mode: |
| 13566 | mask = 0xfffff; |
| 13567 | op = get16 (); |
| 13568 | break; |
| 13569 | case const_1_mode: |
| 13570 | if (intel_syntax) |
| 13571 | oappend ("1"); |
| 13572 | return; |
| 13573 | default: |
| 13574 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 13575 | return; |
| 13576 | } |
| 13577 | |
| 13578 | op &= mask; |
| 13579 | scratchbuf[0] = '$'; |
| 13580 | print_operand_value (scratchbuf + 1, 1, op); |
| 13581 | oappend (scratchbuf + intel_syntax); |
| 13582 | scratchbuf[0] = '\0'; |
| 13583 | } |
| 13584 | |
| 13585 | static void |
| 13586 | OP_I64 (int bytemode, int sizeflag) |
| 13587 | { |
| 13588 | bfd_signed_vma op; |
| 13589 | bfd_signed_vma mask = -1; |
| 13590 | |
| 13591 | if (address_mode != mode_64bit) |
| 13592 | { |
| 13593 | OP_I (bytemode, sizeflag); |
| 13594 | return; |
| 13595 | } |
| 13596 | |
| 13597 | switch (bytemode) |
| 13598 | { |
| 13599 | case b_mode: |
| 13600 | FETCH_DATA (the_info, codep + 1); |
| 13601 | op = *codep++; |
| 13602 | mask = 0xff; |
| 13603 | break; |
| 13604 | case v_mode: |
| 13605 | USED_REX (REX_W); |
| 13606 | if (rex & REX_W) |
| 13607 | op = get64 (); |
| 13608 | else |
| 13609 | { |
| 13610 | if (sizeflag & DFLAG) |
| 13611 | { |
| 13612 | op = get32 (); |
| 13613 | mask = 0xffffffff; |
| 13614 | } |
| 13615 | else |
| 13616 | { |
| 13617 | op = get16 (); |
| 13618 | mask = 0xfffff; |
| 13619 | } |
| 13620 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13621 | } |
| 13622 | break; |
| 13623 | case w_mode: |
| 13624 | mask = 0xfffff; |
| 13625 | op = get16 (); |
| 13626 | break; |
| 13627 | default: |
| 13628 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 13629 | return; |
| 13630 | } |
| 13631 | |
| 13632 | op &= mask; |
| 13633 | scratchbuf[0] = '$'; |
| 13634 | print_operand_value (scratchbuf + 1, 1, op); |
| 13635 | oappend (scratchbuf + intel_syntax); |
| 13636 | scratchbuf[0] = '\0'; |
| 13637 | } |
| 13638 | |
| 13639 | static void |
| 13640 | OP_sI (int bytemode, int sizeflag) |
| 13641 | { |
| 13642 | bfd_signed_vma op; |
| 13643 | |
| 13644 | switch (bytemode) |
| 13645 | { |
| 13646 | case b_mode: |
| 13647 | case b_T_mode: |
| 13648 | FETCH_DATA (the_info, codep + 1); |
| 13649 | op = *codep++; |
| 13650 | if ((op & 0x80) != 0) |
| 13651 | op -= 0x100; |
| 13652 | if (bytemode == b_T_mode) |
| 13653 | { |
| 13654 | if (address_mode != mode_64bit |
| 13655 | || !(sizeflag & DFLAG)) |
| 13656 | { |
| 13657 | if (sizeflag & DFLAG) |
| 13658 | op &= 0xffffffff; |
| 13659 | else |
| 13660 | op &= 0xffff; |
| 13661 | } |
| 13662 | } |
| 13663 | else |
| 13664 | { |
| 13665 | if (!(rex & REX_W)) |
| 13666 | { |
| 13667 | if (sizeflag & DFLAG) |
| 13668 | op &= 0xffffffff; |
| 13669 | else |
| 13670 | op &= 0xffff; |
| 13671 | } |
| 13672 | } |
| 13673 | break; |
| 13674 | case v_mode: |
| 13675 | if (sizeflag & DFLAG) |
| 13676 | op = get32s (); |
| 13677 | else |
| 13678 | op = get16 (); |
| 13679 | break; |
| 13680 | default: |
| 13681 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 13682 | return; |
| 13683 | } |
| 13684 | |
| 13685 | scratchbuf[0] = '$'; |
| 13686 | print_operand_value (scratchbuf + 1, 1, op); |
| 13687 | oappend (scratchbuf + intel_syntax); |
| 13688 | } |
| 13689 | |
| 13690 | static void |
| 13691 | OP_J (int bytemode, int sizeflag) |
| 13692 | { |
| 13693 | bfd_vma disp; |
| 13694 | bfd_vma mask = -1; |
| 13695 | bfd_vma segment = 0; |
| 13696 | |
| 13697 | switch (bytemode) |
| 13698 | { |
| 13699 | case b_mode: |
| 13700 | FETCH_DATA (the_info, codep + 1); |
| 13701 | disp = *codep++; |
| 13702 | if ((disp & 0x80) != 0) |
| 13703 | disp -= 0x100; |
| 13704 | break; |
| 13705 | case v_mode: |
| 13706 | USED_REX (REX_W); |
| 13707 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
| 13708 | disp = get32s (); |
| 13709 | else |
| 13710 | { |
| 13711 | disp = get16 (); |
| 13712 | if ((disp & 0x8000) != 0) |
| 13713 | disp -= 0x10000; |
| 13714 | /* In 16bit mode, address is wrapped around at 64k within |
| 13715 | the same segment. Otherwise, a data16 prefix on a jump |
| 13716 | instruction means that the pc is masked to 16 bits after |
| 13717 | the displacement is added! */ |
| 13718 | mask = 0xffff; |
| 13719 | if ((prefixes & PREFIX_DATA) == 0) |
| 13720 | segment = ((start_pc + codep - start_codep) |
| 13721 | & ~((bfd_vma) 0xffff)); |
| 13722 | } |
| 13723 | if (!(rex & REX_W)) |
| 13724 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13725 | break; |
| 13726 | default: |
| 13727 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 13728 | return; |
| 13729 | } |
| 13730 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
| 13731 | set_op (disp, 0); |
| 13732 | print_operand_value (scratchbuf, 1, disp); |
| 13733 | oappend (scratchbuf); |
| 13734 | } |
| 13735 | |
| 13736 | static void |
| 13737 | OP_SEG (int bytemode, int sizeflag) |
| 13738 | { |
| 13739 | if (bytemode == w_mode) |
| 13740 | oappend (names_seg[modrm.reg]); |
| 13741 | else |
| 13742 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
| 13743 | } |
| 13744 | |
| 13745 | static void |
| 13746 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
| 13747 | { |
| 13748 | int seg, offset; |
| 13749 | |
| 13750 | if (sizeflag & DFLAG) |
| 13751 | { |
| 13752 | offset = get32 (); |
| 13753 | seg = get16 (); |
| 13754 | } |
| 13755 | else |
| 13756 | { |
| 13757 | offset = get16 (); |
| 13758 | seg = get16 (); |
| 13759 | } |
| 13760 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13761 | if (intel_syntax) |
| 13762 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
| 13763 | else |
| 13764 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); |
| 13765 | oappend (scratchbuf); |
| 13766 | } |
| 13767 | |
| 13768 | static void |
| 13769 | OP_OFF (int bytemode, int sizeflag) |
| 13770 | { |
| 13771 | bfd_vma off; |
| 13772 | |
| 13773 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
| 13774 | intel_operand_size (bytemode, sizeflag); |
| 13775 | append_seg (); |
| 13776 | |
| 13777 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
| 13778 | off = get32 (); |
| 13779 | else |
| 13780 | off = get16 (); |
| 13781 | |
| 13782 | if (intel_syntax) |
| 13783 | { |
| 13784 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
| 13785 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
| 13786 | { |
| 13787 | oappend (names_seg[ds_reg - es_reg]); |
| 13788 | oappend (":"); |
| 13789 | } |
| 13790 | } |
| 13791 | print_operand_value (scratchbuf, 1, off); |
| 13792 | oappend (scratchbuf); |
| 13793 | } |
| 13794 | |
| 13795 | static void |
| 13796 | OP_OFF64 (int bytemode, int sizeflag) |
| 13797 | { |
| 13798 | bfd_vma off; |
| 13799 | |
| 13800 | if (address_mode != mode_64bit |
| 13801 | || (prefixes & PREFIX_ADDR)) |
| 13802 | { |
| 13803 | OP_OFF (bytemode, sizeflag); |
| 13804 | return; |
| 13805 | } |
| 13806 | |
| 13807 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
| 13808 | intel_operand_size (bytemode, sizeflag); |
| 13809 | append_seg (); |
| 13810 | |
| 13811 | off = get64 (); |
| 13812 | |
| 13813 | if (intel_syntax) |
| 13814 | { |
| 13815 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
| 13816 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
| 13817 | { |
| 13818 | oappend (names_seg[ds_reg - es_reg]); |
| 13819 | oappend (":"); |
| 13820 | } |
| 13821 | } |
| 13822 | print_operand_value (scratchbuf, 1, off); |
| 13823 | oappend (scratchbuf); |
| 13824 | } |
| 13825 | |
| 13826 | static void |
| 13827 | ptr_reg (int code, int sizeflag) |
| 13828 | { |
| 13829 | const char *s; |
| 13830 | |
| 13831 | *obufp++ = open_char; |
| 13832 | used_prefixes |= (prefixes & PREFIX_ADDR); |
| 13833 | if (address_mode == mode_64bit) |
| 13834 | { |
| 13835 | if (!(sizeflag & AFLAG)) |
| 13836 | s = names32[code - eAX_reg]; |
| 13837 | else |
| 13838 | s = names64[code - eAX_reg]; |
| 13839 | } |
| 13840 | else if (sizeflag & AFLAG) |
| 13841 | s = names32[code - eAX_reg]; |
| 13842 | else |
| 13843 | s = names16[code - eAX_reg]; |
| 13844 | oappend (s); |
| 13845 | *obufp++ = close_char; |
| 13846 | *obufp = 0; |
| 13847 | } |
| 13848 | |
| 13849 | static void |
| 13850 | OP_ESreg (int code, int sizeflag) |
| 13851 | { |
| 13852 | if (intel_syntax) |
| 13853 | { |
| 13854 | switch (codep[-1]) |
| 13855 | { |
| 13856 | case 0x6d: /* insw/insl */ |
| 13857 | intel_operand_size (z_mode, sizeflag); |
| 13858 | break; |
| 13859 | case 0xa5: /* movsw/movsl/movsq */ |
| 13860 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
| 13861 | case 0xab: /* stosw/stosl */ |
| 13862 | case 0xaf: /* scasw/scasl */ |
| 13863 | intel_operand_size (v_mode, sizeflag); |
| 13864 | break; |
| 13865 | default: |
| 13866 | intel_operand_size (b_mode, sizeflag); |
| 13867 | } |
| 13868 | } |
| 13869 | oappend ("%es:" + intel_syntax); |
| 13870 | ptr_reg (code, sizeflag); |
| 13871 | } |
| 13872 | |
| 13873 | static void |
| 13874 | OP_DSreg (int code, int sizeflag) |
| 13875 | { |
| 13876 | if (intel_syntax) |
| 13877 | { |
| 13878 | switch (codep[-1]) |
| 13879 | { |
| 13880 | case 0x6f: /* outsw/outsl */ |
| 13881 | intel_operand_size (z_mode, sizeflag); |
| 13882 | break; |
| 13883 | case 0xa5: /* movsw/movsl/movsq */ |
| 13884 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ |
| 13885 | case 0xad: /* lodsw/lodsl/lodsq */ |
| 13886 | intel_operand_size (v_mode, sizeflag); |
| 13887 | break; |
| 13888 | default: |
| 13889 | intel_operand_size (b_mode, sizeflag); |
| 13890 | } |
| 13891 | } |
| 13892 | if ((prefixes |
| 13893 | & (PREFIX_CS |
| 13894 | | PREFIX_DS |
| 13895 | | PREFIX_SS |
| 13896 | | PREFIX_ES |
| 13897 | | PREFIX_FS |
| 13898 | | PREFIX_GS)) == 0) |
| 13899 | prefixes |= PREFIX_DS; |
| 13900 | append_seg (); |
| 13901 | ptr_reg (code, sizeflag); |
| 13902 | } |
| 13903 | |
| 13904 | static void |
| 13905 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 13906 | { |
| 13907 | int add; |
| 13908 | if (rex & REX_R) |
| 13909 | { |
| 13910 | USED_REX (REX_R); |
| 13911 | add = 8; |
| 13912 | } |
| 13913 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
| 13914 | { |
| 13915 | all_prefixes[last_lock_prefix] = 0; |
| 13916 | used_prefixes |= PREFIX_LOCK; |
| 13917 | add = 8; |
| 13918 | } |
| 13919 | else |
| 13920 | add = 0; |
| 13921 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
| 13922 | oappend (scratchbuf + intel_syntax); |
| 13923 | } |
| 13924 | |
| 13925 | static void |
| 13926 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 13927 | { |
| 13928 | int add; |
| 13929 | USED_REX (REX_R); |
| 13930 | if (rex & REX_R) |
| 13931 | add = 8; |
| 13932 | else |
| 13933 | add = 0; |
| 13934 | if (intel_syntax) |
| 13935 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
| 13936 | else |
| 13937 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
| 13938 | oappend (scratchbuf); |
| 13939 | } |
| 13940 | |
| 13941 | static void |
| 13942 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 13943 | { |
| 13944 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
| 13945 | oappend (scratchbuf + intel_syntax); |
| 13946 | } |
| 13947 | |
| 13948 | static void |
| 13949 | OP_R (int bytemode, int sizeflag) |
| 13950 | { |
| 13951 | if (modrm.mod == 3) |
| 13952 | OP_E (bytemode, sizeflag); |
| 13953 | else |
| 13954 | BadOp (); |
| 13955 | } |
| 13956 | |
| 13957 | static void |
| 13958 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 13959 | { |
| 13960 | int reg = modrm.reg; |
| 13961 | const char **names; |
| 13962 | |
| 13963 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 13964 | if (prefixes & PREFIX_DATA) |
| 13965 | { |
| 13966 | names = names_xmm; |
| 13967 | USED_REX (REX_R); |
| 13968 | if (rex & REX_R) |
| 13969 | reg += 8; |
| 13970 | } |
| 13971 | else |
| 13972 | names = names_mm; |
| 13973 | oappend (names[reg]); |
| 13974 | } |
| 13975 | |
| 13976 | static void |
| 13977 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
| 13978 | { |
| 13979 | int reg = modrm.reg; |
| 13980 | const char **names; |
| 13981 | |
| 13982 | USED_REX (REX_R); |
| 13983 | if (rex & REX_R) |
| 13984 | reg += 8; |
| 13985 | if (need_vex |
| 13986 | && bytemode != xmm_mode |
| 13987 | && bytemode != scalar_mode) |
| 13988 | { |
| 13989 | switch (vex.length) |
| 13990 | { |
| 13991 | case 128: |
| 13992 | names = names_xmm; |
| 13993 | break; |
| 13994 | case 256: |
| 13995 | if (vex.w || bytemode != vex_vsib_q_w_dq_mode) |
| 13996 | names = names_ymm; |
| 13997 | else |
| 13998 | names = names_xmm; |
| 13999 | break; |
| 14000 | default: |
| 14001 | abort (); |
| 14002 | } |
| 14003 | } |
| 14004 | else |
| 14005 | names = names_xmm; |
| 14006 | oappend (names[reg]); |
| 14007 | } |
| 14008 | |
| 14009 | static void |
| 14010 | OP_EM (int bytemode, int sizeflag) |
| 14011 | { |
| 14012 | int reg; |
| 14013 | const char **names; |
| 14014 | |
| 14015 | if (modrm.mod != 3) |
| 14016 | { |
| 14017 | if (intel_syntax |
| 14018 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
| 14019 | { |
| 14020 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
| 14021 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14022 | } |
| 14023 | OP_E (bytemode, sizeflag); |
| 14024 | return; |
| 14025 | } |
| 14026 | |
| 14027 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
| 14028 | swap_operand (); |
| 14029 | |
| 14030 | /* Skip mod/rm byte. */ |
| 14031 | MODRM_CHECK; |
| 14032 | codep++; |
| 14033 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14034 | reg = modrm.rm; |
| 14035 | if (prefixes & PREFIX_DATA) |
| 14036 | { |
| 14037 | names = names_xmm; |
| 14038 | USED_REX (REX_B); |
| 14039 | if (rex & REX_B) |
| 14040 | reg += 8; |
| 14041 | } |
| 14042 | else |
| 14043 | names = names_mm; |
| 14044 | oappend (names[reg]); |
| 14045 | } |
| 14046 | |
| 14047 | /* cvt* are the only instructions in sse2 which have |
| 14048 | both SSE and MMX operands and also have 0x66 prefix |
| 14049 | in their opcode. 0x66 was originally used to differentiate |
| 14050 | between SSE and MMX instruction(operands). So we have to handle the |
| 14051 | cvt* separately using OP_EMC and OP_MXC */ |
| 14052 | static void |
| 14053 | OP_EMC (int bytemode, int sizeflag) |
| 14054 | { |
| 14055 | if (modrm.mod != 3) |
| 14056 | { |
| 14057 | if (intel_syntax && bytemode == v_mode) |
| 14058 | { |
| 14059 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
| 14060 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14061 | } |
| 14062 | OP_E (bytemode, sizeflag); |
| 14063 | return; |
| 14064 | } |
| 14065 | |
| 14066 | /* Skip mod/rm byte. */ |
| 14067 | MODRM_CHECK; |
| 14068 | codep++; |
| 14069 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14070 | oappend (names_mm[modrm.rm]); |
| 14071 | } |
| 14072 | |
| 14073 | static void |
| 14074 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 14075 | { |
| 14076 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14077 | oappend (names_mm[modrm.reg]); |
| 14078 | } |
| 14079 | |
| 14080 | static void |
| 14081 | OP_EX (int bytemode, int sizeflag) |
| 14082 | { |
| 14083 | int reg; |
| 14084 | const char **names; |
| 14085 | |
| 14086 | /* Skip mod/rm byte. */ |
| 14087 | MODRM_CHECK; |
| 14088 | codep++; |
| 14089 | |
| 14090 | if (modrm.mod != 3) |
| 14091 | { |
| 14092 | OP_E_memory (bytemode, sizeflag); |
| 14093 | return; |
| 14094 | } |
| 14095 | |
| 14096 | reg = modrm.rm; |
| 14097 | USED_REX (REX_B); |
| 14098 | if (rex & REX_B) |
| 14099 | reg += 8; |
| 14100 | |
| 14101 | if ((sizeflag & SUFFIX_ALWAYS) |
| 14102 | && (bytemode == x_swap_mode |
| 14103 | || bytemode == d_swap_mode |
| 14104 | || bytemode == d_scalar_swap_mode |
| 14105 | || bytemode == q_swap_mode |
| 14106 | || bytemode == q_scalar_swap_mode)) |
| 14107 | swap_operand (); |
| 14108 | |
| 14109 | if (need_vex |
| 14110 | && bytemode != xmm_mode |
| 14111 | && bytemode != xmmdw_mode |
| 14112 | && bytemode != xmmqd_mode |
| 14113 | && bytemode != xmm_mb_mode |
| 14114 | && bytemode != xmm_mw_mode |
| 14115 | && bytemode != xmm_md_mode |
| 14116 | && bytemode != xmm_mq_mode |
| 14117 | && bytemode != xmmq_mode |
| 14118 | && bytemode != d_scalar_mode |
| 14119 | && bytemode != d_scalar_swap_mode |
| 14120 | && bytemode != q_scalar_mode |
| 14121 | && bytemode != q_scalar_swap_mode |
| 14122 | && bytemode != vex_scalar_w_dq_mode) |
| 14123 | { |
| 14124 | switch (vex.length) |
| 14125 | { |
| 14126 | case 128: |
| 14127 | names = names_xmm; |
| 14128 | break; |
| 14129 | case 256: |
| 14130 | names = names_ymm; |
| 14131 | break; |
| 14132 | default: |
| 14133 | abort (); |
| 14134 | } |
| 14135 | } |
| 14136 | else |
| 14137 | names = names_xmm; |
| 14138 | oappend (names[reg]); |
| 14139 | } |
| 14140 | |
| 14141 | static void |
| 14142 | OP_MS (int bytemode, int sizeflag) |
| 14143 | { |
| 14144 | if (modrm.mod == 3) |
| 14145 | OP_EM (bytemode, sizeflag); |
| 14146 | else |
| 14147 | BadOp (); |
| 14148 | } |
| 14149 | |
| 14150 | static void |
| 14151 | OP_XS (int bytemode, int sizeflag) |
| 14152 | { |
| 14153 | if (modrm.mod == 3) |
| 14154 | OP_EX (bytemode, sizeflag); |
| 14155 | else |
| 14156 | BadOp (); |
| 14157 | } |
| 14158 | |
| 14159 | static void |
| 14160 | OP_M (int bytemode, int sizeflag) |
| 14161 | { |
| 14162 | if (modrm.mod == 3) |
| 14163 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
| 14164 | BadOp (); |
| 14165 | else |
| 14166 | OP_E (bytemode, sizeflag); |
| 14167 | } |
| 14168 | |
| 14169 | static void |
| 14170 | OP_0f07 (int bytemode, int sizeflag) |
| 14171 | { |
| 14172 | if (modrm.mod != 3 || modrm.rm != 0) |
| 14173 | BadOp (); |
| 14174 | else |
| 14175 | OP_E (bytemode, sizeflag); |
| 14176 | } |
| 14177 | |
| 14178 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
| 14179 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
| 14180 | |
| 14181 | static void |
| 14182 | NOP_Fixup1 (int bytemode, int sizeflag) |
| 14183 | { |
| 14184 | if ((prefixes & PREFIX_DATA) != 0 |
| 14185 | || (rex != 0 |
| 14186 | && rex != 0x48 |
| 14187 | && address_mode == mode_64bit)) |
| 14188 | OP_REG (bytemode, sizeflag); |
| 14189 | else |
| 14190 | strcpy (obuf, "nop"); |
| 14191 | } |
| 14192 | |
| 14193 | static void |
| 14194 | NOP_Fixup2 (int bytemode, int sizeflag) |
| 14195 | { |
| 14196 | if ((prefixes & PREFIX_DATA) != 0 |
| 14197 | || (rex != 0 |
| 14198 | && rex != 0x48 |
| 14199 | && address_mode == mode_64bit)) |
| 14200 | OP_IMREG (bytemode, sizeflag); |
| 14201 | } |
| 14202 | |
| 14203 | static const char *const Suffix3DNow[] = { |
| 14204 | /* 00 */ NULL, NULL, NULL, NULL, |
| 14205 | /* 04 */ NULL, NULL, NULL, NULL, |
| 14206 | /* 08 */ NULL, NULL, NULL, NULL, |
| 14207 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
| 14208 | /* 10 */ NULL, NULL, NULL, NULL, |
| 14209 | /* 14 */ NULL, NULL, NULL, NULL, |
| 14210 | /* 18 */ NULL, NULL, NULL, NULL, |
| 14211 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
| 14212 | /* 20 */ NULL, NULL, NULL, NULL, |
| 14213 | /* 24 */ NULL, NULL, NULL, NULL, |
| 14214 | /* 28 */ NULL, NULL, NULL, NULL, |
| 14215 | /* 2C */ NULL, NULL, NULL, NULL, |
| 14216 | /* 30 */ NULL, NULL, NULL, NULL, |
| 14217 | /* 34 */ NULL, NULL, NULL, NULL, |
| 14218 | /* 38 */ NULL, NULL, NULL, NULL, |
| 14219 | /* 3C */ NULL, NULL, NULL, NULL, |
| 14220 | /* 40 */ NULL, NULL, NULL, NULL, |
| 14221 | /* 44 */ NULL, NULL, NULL, NULL, |
| 14222 | /* 48 */ NULL, NULL, NULL, NULL, |
| 14223 | /* 4C */ NULL, NULL, NULL, NULL, |
| 14224 | /* 50 */ NULL, NULL, NULL, NULL, |
| 14225 | /* 54 */ NULL, NULL, NULL, NULL, |
| 14226 | /* 58 */ NULL, NULL, NULL, NULL, |
| 14227 | /* 5C */ NULL, NULL, NULL, NULL, |
| 14228 | /* 60 */ NULL, NULL, NULL, NULL, |
| 14229 | /* 64 */ NULL, NULL, NULL, NULL, |
| 14230 | /* 68 */ NULL, NULL, NULL, NULL, |
| 14231 | /* 6C */ NULL, NULL, NULL, NULL, |
| 14232 | /* 70 */ NULL, NULL, NULL, NULL, |
| 14233 | /* 74 */ NULL, NULL, NULL, NULL, |
| 14234 | /* 78 */ NULL, NULL, NULL, NULL, |
| 14235 | /* 7C */ NULL, NULL, NULL, NULL, |
| 14236 | /* 80 */ NULL, NULL, NULL, NULL, |
| 14237 | /* 84 */ NULL, NULL, NULL, NULL, |
| 14238 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
| 14239 | /* 8C */ NULL, NULL, "pfpnacc", NULL, |
| 14240 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
| 14241 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", |
| 14242 | /* 98 */ NULL, NULL, "pfsub", NULL, |
| 14243 | /* 9C */ NULL, NULL, "pfadd", NULL, |
| 14244 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, |
| 14245 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", |
| 14246 | /* A8 */ NULL, NULL, "pfsubr", NULL, |
| 14247 | /* AC */ NULL, NULL, "pfacc", NULL, |
| 14248 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, |
| 14249 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
| 14250 | /* B8 */ NULL, NULL, NULL, "pswapd", |
| 14251 | /* BC */ NULL, NULL, NULL, "pavgusb", |
| 14252 | /* C0 */ NULL, NULL, NULL, NULL, |
| 14253 | /* C4 */ NULL, NULL, NULL, NULL, |
| 14254 | /* C8 */ NULL, NULL, NULL, NULL, |
| 14255 | /* CC */ NULL, NULL, NULL, NULL, |
| 14256 | /* D0 */ NULL, NULL, NULL, NULL, |
| 14257 | /* D4 */ NULL, NULL, NULL, NULL, |
| 14258 | /* D8 */ NULL, NULL, NULL, NULL, |
| 14259 | /* DC */ NULL, NULL, NULL, NULL, |
| 14260 | /* E0 */ NULL, NULL, NULL, NULL, |
| 14261 | /* E4 */ NULL, NULL, NULL, NULL, |
| 14262 | /* E8 */ NULL, NULL, NULL, NULL, |
| 14263 | /* EC */ NULL, NULL, NULL, NULL, |
| 14264 | /* F0 */ NULL, NULL, NULL, NULL, |
| 14265 | /* F4 */ NULL, NULL, NULL, NULL, |
| 14266 | /* F8 */ NULL, NULL, NULL, NULL, |
| 14267 | /* FC */ NULL, NULL, NULL, NULL, |
| 14268 | }; |
| 14269 | |
| 14270 | static void |
| 14271 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 14272 | { |
| 14273 | const char *mnemonic; |
| 14274 | |
| 14275 | FETCH_DATA (the_info, codep + 1); |
| 14276 | /* AMD 3DNow! instructions are specified by an opcode suffix in the |
| 14277 | place where an 8-bit immediate would normally go. ie. the last |
| 14278 | byte of the instruction. */ |
| 14279 | obufp = mnemonicendp; |
| 14280 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
| 14281 | if (mnemonic) |
| 14282 | oappend (mnemonic); |
| 14283 | else |
| 14284 | { |
| 14285 | /* Since a variable sized modrm/sib chunk is between the start |
| 14286 | of the opcode (0x0f0f) and the opcode suffix, we need to do |
| 14287 | all the modrm processing first, and don't know until now that |
| 14288 | we have a bad opcode. This necessitates some cleaning up. */ |
| 14289 | op_out[0][0] = '\0'; |
| 14290 | op_out[1][0] = '\0'; |
| 14291 | BadOp (); |
| 14292 | } |
| 14293 | mnemonicendp = obufp; |
| 14294 | } |
| 14295 | |
| 14296 | static struct op simd_cmp_op[] = |
| 14297 | { |
| 14298 | { STRING_COMMA_LEN ("eq") }, |
| 14299 | { STRING_COMMA_LEN ("lt") }, |
| 14300 | { STRING_COMMA_LEN ("le") }, |
| 14301 | { STRING_COMMA_LEN ("unord") }, |
| 14302 | { STRING_COMMA_LEN ("neq") }, |
| 14303 | { STRING_COMMA_LEN ("nlt") }, |
| 14304 | { STRING_COMMA_LEN ("nle") }, |
| 14305 | { STRING_COMMA_LEN ("ord") } |
| 14306 | }; |
| 14307 | |
| 14308 | static void |
| 14309 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 14310 | { |
| 14311 | unsigned int cmp_type; |
| 14312 | |
| 14313 | FETCH_DATA (the_info, codep + 1); |
| 14314 | cmp_type = *codep++ & 0xff; |
| 14315 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
| 14316 | { |
| 14317 | char suffix [3]; |
| 14318 | char *p = mnemonicendp - 2; |
| 14319 | suffix[0] = p[0]; |
| 14320 | suffix[1] = p[1]; |
| 14321 | suffix[2] = '\0'; |
| 14322 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
| 14323 | mnemonicendp += simd_cmp_op[cmp_type].len; |
| 14324 | } |
| 14325 | else |
| 14326 | { |
| 14327 | /* We have a reserved extension byte. Output it directly. */ |
| 14328 | scratchbuf[0] = '$'; |
| 14329 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
| 14330 | oappend (scratchbuf + intel_syntax); |
| 14331 | scratchbuf[0] = '\0'; |
| 14332 | } |
| 14333 | } |
| 14334 | |
| 14335 | static void |
| 14336 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
| 14337 | int sizeflag ATTRIBUTE_UNUSED) |
| 14338 | { |
| 14339 | /* mwait %eax,%ecx */ |
| 14340 | if (!intel_syntax) |
| 14341 | { |
| 14342 | const char **names = (address_mode == mode_64bit |
| 14343 | ? names64 : names32); |
| 14344 | strcpy (op_out[0], names[0]); |
| 14345 | strcpy (op_out[1], names[1]); |
| 14346 | two_source_ops = 1; |
| 14347 | } |
| 14348 | /* Skip mod/rm byte. */ |
| 14349 | MODRM_CHECK; |
| 14350 | codep++; |
| 14351 | } |
| 14352 | |
| 14353 | static void |
| 14354 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, |
| 14355 | int sizeflag ATTRIBUTE_UNUSED) |
| 14356 | { |
| 14357 | /* monitor %eax,%ecx,%edx" */ |
| 14358 | if (!intel_syntax) |
| 14359 | { |
| 14360 | const char **op1_names; |
| 14361 | const char **names = (address_mode == mode_64bit |
| 14362 | ? names64 : names32); |
| 14363 | |
| 14364 | if (!(prefixes & PREFIX_ADDR)) |
| 14365 | op1_names = (address_mode == mode_16bit |
| 14366 | ? names16 : names); |
| 14367 | else |
| 14368 | { |
| 14369 | /* Remove "addr16/addr32". */ |
| 14370 | all_prefixes[last_addr_prefix] = 0; |
| 14371 | op1_names = (address_mode != mode_32bit |
| 14372 | ? names32 : names16); |
| 14373 | used_prefixes |= PREFIX_ADDR; |
| 14374 | } |
| 14375 | strcpy (op_out[0], op1_names[0]); |
| 14376 | strcpy (op_out[1], names[1]); |
| 14377 | strcpy (op_out[2], names[2]); |
| 14378 | two_source_ops = 1; |
| 14379 | } |
| 14380 | /* Skip mod/rm byte. */ |
| 14381 | MODRM_CHECK; |
| 14382 | codep++; |
| 14383 | } |
| 14384 | |
| 14385 | static void |
| 14386 | BadOp (void) |
| 14387 | { |
| 14388 | /* Throw away prefixes and 1st. opcode byte. */ |
| 14389 | codep = insn_codep + 1; |
| 14390 | oappend ("(bad)"); |
| 14391 | } |
| 14392 | |
| 14393 | static void |
| 14394 | REP_Fixup (int bytemode, int sizeflag) |
| 14395 | { |
| 14396 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, |
| 14397 | lods and stos. */ |
| 14398 | if (prefixes & PREFIX_REPZ) |
| 14399 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
| 14400 | |
| 14401 | switch (bytemode) |
| 14402 | { |
| 14403 | case al_reg: |
| 14404 | case eAX_reg: |
| 14405 | case indir_dx_reg: |
| 14406 | OP_IMREG (bytemode, sizeflag); |
| 14407 | break; |
| 14408 | case eDI_reg: |
| 14409 | OP_ESreg (bytemode, sizeflag); |
| 14410 | break; |
| 14411 | case eSI_reg: |
| 14412 | OP_DSreg (bytemode, sizeflag); |
| 14413 | break; |
| 14414 | default: |
| 14415 | abort (); |
| 14416 | break; |
| 14417 | } |
| 14418 | } |
| 14419 | |
| 14420 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
| 14421 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. |
| 14422 | */ |
| 14423 | |
| 14424 | static void |
| 14425 | HLE_Fixup1 (int bytemode, int sizeflag) |
| 14426 | { |
| 14427 | if (modrm.mod != 3 |
| 14428 | && (prefixes & PREFIX_LOCK) != 0) |
| 14429 | { |
| 14430 | if (prefixes & PREFIX_REPZ) |
| 14431 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
| 14432 | if (prefixes & PREFIX_REPNZ) |
| 14433 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
| 14434 | } |
| 14435 | |
| 14436 | OP_E (bytemode, sizeflag); |
| 14437 | } |
| 14438 | |
| 14439 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
| 14440 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. |
| 14441 | */ |
| 14442 | |
| 14443 | static void |
| 14444 | HLE_Fixup2 (int bytemode, int sizeflag) |
| 14445 | { |
| 14446 | if (modrm.mod != 3) |
| 14447 | { |
| 14448 | if (prefixes & PREFIX_REPZ) |
| 14449 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
| 14450 | if (prefixes & PREFIX_REPNZ) |
| 14451 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
| 14452 | } |
| 14453 | |
| 14454 | OP_E (bytemode, sizeflag); |
| 14455 | } |
| 14456 | |
| 14457 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as |
| 14458 | "xrelease" for memory operand. No check for LOCK prefix. */ |
| 14459 | |
| 14460 | static void |
| 14461 | HLE_Fixup3 (int bytemode, int sizeflag) |
| 14462 | { |
| 14463 | if (modrm.mod != 3 |
| 14464 | && last_repz_prefix > last_repnz_prefix |
| 14465 | && (prefixes & PREFIX_REPZ) != 0) |
| 14466 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
| 14467 | |
| 14468 | OP_E (bytemode, sizeflag); |
| 14469 | } |
| 14470 | |
| 14471 | static void |
| 14472 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) |
| 14473 | { |
| 14474 | USED_REX (REX_W); |
| 14475 | if (rex & REX_W) |
| 14476 | { |
| 14477 | /* Change cmpxchg8b to cmpxchg16b. */ |
| 14478 | char *p = mnemonicendp - 2; |
| 14479 | mnemonicendp = stpcpy (p, "16b"); |
| 14480 | bytemode = o_mode; |
| 14481 | } |
| 14482 | else if ((prefixes & PREFIX_LOCK) != 0) |
| 14483 | { |
| 14484 | if (prefixes & PREFIX_REPZ) |
| 14485 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; |
| 14486 | if (prefixes & PREFIX_REPNZ) |
| 14487 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; |
| 14488 | } |
| 14489 | |
| 14490 | OP_M (bytemode, sizeflag); |
| 14491 | } |
| 14492 | |
| 14493 | static void |
| 14494 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) |
| 14495 | { |
| 14496 | const char **names; |
| 14497 | |
| 14498 | if (need_vex) |
| 14499 | { |
| 14500 | switch (vex.length) |
| 14501 | { |
| 14502 | case 128: |
| 14503 | names = names_xmm; |
| 14504 | break; |
| 14505 | case 256: |
| 14506 | names = names_ymm; |
| 14507 | break; |
| 14508 | default: |
| 14509 | abort (); |
| 14510 | } |
| 14511 | } |
| 14512 | else |
| 14513 | names = names_xmm; |
| 14514 | oappend (names[reg]); |
| 14515 | } |
| 14516 | |
| 14517 | static void |
| 14518 | CRC32_Fixup (int bytemode, int sizeflag) |
| 14519 | { |
| 14520 | /* Add proper suffix to "crc32". */ |
| 14521 | char *p = mnemonicendp; |
| 14522 | |
| 14523 | switch (bytemode) |
| 14524 | { |
| 14525 | case b_mode: |
| 14526 | if (intel_syntax) |
| 14527 | goto skip; |
| 14528 | |
| 14529 | *p++ = 'b'; |
| 14530 | break; |
| 14531 | case v_mode: |
| 14532 | if (intel_syntax) |
| 14533 | goto skip; |
| 14534 | |
| 14535 | USED_REX (REX_W); |
| 14536 | if (rex & REX_W) |
| 14537 | *p++ = 'q'; |
| 14538 | else |
| 14539 | { |
| 14540 | if (sizeflag & DFLAG) |
| 14541 | *p++ = 'l'; |
| 14542 | else |
| 14543 | *p++ = 'w'; |
| 14544 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14545 | } |
| 14546 | break; |
| 14547 | default: |
| 14548 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 14549 | break; |
| 14550 | } |
| 14551 | mnemonicendp = p; |
| 14552 | *p = '\0'; |
| 14553 | |
| 14554 | skip: |
| 14555 | if (modrm.mod == 3) |
| 14556 | { |
| 14557 | int add; |
| 14558 | |
| 14559 | /* Skip mod/rm byte. */ |
| 14560 | MODRM_CHECK; |
| 14561 | codep++; |
| 14562 | |
| 14563 | USED_REX (REX_B); |
| 14564 | add = (rex & REX_B) ? 8 : 0; |
| 14565 | if (bytemode == b_mode) |
| 14566 | { |
| 14567 | USED_REX (0); |
| 14568 | if (rex) |
| 14569 | oappend (names8rex[modrm.rm + add]); |
| 14570 | else |
| 14571 | oappend (names8[modrm.rm + add]); |
| 14572 | } |
| 14573 | else |
| 14574 | { |
| 14575 | USED_REX (REX_W); |
| 14576 | if (rex & REX_W) |
| 14577 | oappend (names64[modrm.rm + add]); |
| 14578 | else if ((prefixes & PREFIX_DATA)) |
| 14579 | oappend (names16[modrm.rm + add]); |
| 14580 | else |
| 14581 | oappend (names32[modrm.rm + add]); |
| 14582 | } |
| 14583 | } |
| 14584 | else |
| 14585 | OP_E (bytemode, sizeflag); |
| 14586 | } |
| 14587 | |
| 14588 | static void |
| 14589 | FXSAVE_Fixup (int bytemode, int sizeflag) |
| 14590 | { |
| 14591 | /* Add proper suffix to "fxsave" and "fxrstor". */ |
| 14592 | USED_REX (REX_W); |
| 14593 | if (rex & REX_W) |
| 14594 | { |
| 14595 | char *p = mnemonicendp; |
| 14596 | *p++ = '6'; |
| 14597 | *p++ = '4'; |
| 14598 | *p = '\0'; |
| 14599 | mnemonicendp = p; |
| 14600 | } |
| 14601 | OP_M (bytemode, sizeflag); |
| 14602 | } |
| 14603 | |
| 14604 | /* Display the destination register operand for instructions with |
| 14605 | VEX. */ |
| 14606 | |
| 14607 | static void |
| 14608 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
| 14609 | { |
| 14610 | int reg; |
| 14611 | const char **names; |
| 14612 | |
| 14613 | if (!need_vex) |
| 14614 | abort (); |
| 14615 | |
| 14616 | if (!need_vex_reg) |
| 14617 | return; |
| 14618 | |
| 14619 | reg = vex.register_specifier; |
| 14620 | if (bytemode == vex_scalar_mode) |
| 14621 | { |
| 14622 | oappend (names_xmm[reg]); |
| 14623 | return; |
| 14624 | } |
| 14625 | |
| 14626 | switch (vex.length) |
| 14627 | { |
| 14628 | case 128: |
| 14629 | switch (bytemode) |
| 14630 | { |
| 14631 | case vex_mode: |
| 14632 | case vex128_mode: |
| 14633 | case vex_vsib_q_w_dq_mode: |
| 14634 | names = names_xmm; |
| 14635 | break; |
| 14636 | case dq_mode: |
| 14637 | if (vex.w) |
| 14638 | names = names64; |
| 14639 | else |
| 14640 | names = names32; |
| 14641 | break; |
| 14642 | default: |
| 14643 | abort (); |
| 14644 | return; |
| 14645 | } |
| 14646 | break; |
| 14647 | case 256: |
| 14648 | switch (bytemode) |
| 14649 | { |
| 14650 | case vex_mode: |
| 14651 | case vex256_mode: |
| 14652 | names = names_ymm; |
| 14653 | break; |
| 14654 | case vex_vsib_q_w_dq_mode: |
| 14655 | names = vex.w ? names_ymm : names_xmm; |
| 14656 | break; |
| 14657 | default: |
| 14658 | abort (); |
| 14659 | return; |
| 14660 | } |
| 14661 | break; |
| 14662 | default: |
| 14663 | abort (); |
| 14664 | break; |
| 14665 | } |
| 14666 | oappend (names[reg]); |
| 14667 | } |
| 14668 | |
| 14669 | /* Get the VEX immediate byte without moving codep. */ |
| 14670 | |
| 14671 | static unsigned char |
| 14672 | get_vex_imm8 (int sizeflag, int opnum) |
| 14673 | { |
| 14674 | int bytes_before_imm = 0; |
| 14675 | |
| 14676 | if (modrm.mod != 3) |
| 14677 | { |
| 14678 | /* There are SIB/displacement bytes. */ |
| 14679 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
| 14680 | { |
| 14681 | /* 32/64 bit address mode */ |
| 14682 | int base = modrm.rm; |
| 14683 | |
| 14684 | /* Check SIB byte. */ |
| 14685 | if (base == 4) |
| 14686 | { |
| 14687 | FETCH_DATA (the_info, codep + 1); |
| 14688 | base = *codep & 7; |
| 14689 | /* When decoding the third source, don't increase |
| 14690 | bytes_before_imm as this has already been incremented |
| 14691 | by one in OP_E_memory while decoding the second |
| 14692 | source operand. */ |
| 14693 | if (opnum == 0) |
| 14694 | bytes_before_imm++; |
| 14695 | } |
| 14696 | |
| 14697 | /* Don't increase bytes_before_imm when decoding the third source, |
| 14698 | it has already been incremented by OP_E_memory while decoding |
| 14699 | the second source operand. */ |
| 14700 | if (opnum == 0) |
| 14701 | { |
| 14702 | switch (modrm.mod) |
| 14703 | { |
| 14704 | case 0: |
| 14705 | /* When modrm.rm == 5 or modrm.rm == 4 and base in |
| 14706 | SIB == 5, there is a 4 byte displacement. */ |
| 14707 | if (base != 5) |
| 14708 | /* No displacement. */ |
| 14709 | break; |
| 14710 | case 2: |
| 14711 | /* 4 byte displacement. */ |
| 14712 | bytes_before_imm += 4; |
| 14713 | break; |
| 14714 | case 1: |
| 14715 | /* 1 byte displacement. */ |
| 14716 | bytes_before_imm++; |
| 14717 | break; |
| 14718 | } |
| 14719 | } |
| 14720 | } |
| 14721 | else |
| 14722 | { |
| 14723 | /* 16 bit address mode */ |
| 14724 | /* Don't increase bytes_before_imm when decoding the third source, |
| 14725 | it has already been incremented by OP_E_memory while decoding |
| 14726 | the second source operand. */ |
| 14727 | if (opnum == 0) |
| 14728 | { |
| 14729 | switch (modrm.mod) |
| 14730 | { |
| 14731 | case 0: |
| 14732 | /* When modrm.rm == 6, there is a 2 byte displacement. */ |
| 14733 | if (modrm.rm != 6) |
| 14734 | /* No displacement. */ |
| 14735 | break; |
| 14736 | case 2: |
| 14737 | /* 2 byte displacement. */ |
| 14738 | bytes_before_imm += 2; |
| 14739 | break; |
| 14740 | case 1: |
| 14741 | /* 1 byte displacement: when decoding the third source, |
| 14742 | don't increase bytes_before_imm as this has already |
| 14743 | been incremented by one in OP_E_memory while decoding |
| 14744 | the second source operand. */ |
| 14745 | if (opnum == 0) |
| 14746 | bytes_before_imm++; |
| 14747 | |
| 14748 | break; |
| 14749 | } |
| 14750 | } |
| 14751 | } |
| 14752 | } |
| 14753 | |
| 14754 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); |
| 14755 | return codep [bytes_before_imm]; |
| 14756 | } |
| 14757 | |
| 14758 | static void |
| 14759 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) |
| 14760 | { |
| 14761 | const char **names; |
| 14762 | |
| 14763 | if (reg == -1 && modrm.mod != 3) |
| 14764 | { |
| 14765 | OP_E_memory (bytemode, sizeflag); |
| 14766 | return; |
| 14767 | } |
| 14768 | else |
| 14769 | { |
| 14770 | if (reg == -1) |
| 14771 | { |
| 14772 | reg = modrm.rm; |
| 14773 | USED_REX (REX_B); |
| 14774 | if (rex & REX_B) |
| 14775 | reg += 8; |
| 14776 | } |
| 14777 | else if (reg > 7 && address_mode != mode_64bit) |
| 14778 | BadOp (); |
| 14779 | } |
| 14780 | |
| 14781 | switch (vex.length) |
| 14782 | { |
| 14783 | case 128: |
| 14784 | names = names_xmm; |
| 14785 | break; |
| 14786 | case 256: |
| 14787 | names = names_ymm; |
| 14788 | break; |
| 14789 | default: |
| 14790 | abort (); |
| 14791 | } |
| 14792 | oappend (names[reg]); |
| 14793 | } |
| 14794 | |
| 14795 | static void |
| 14796 | OP_EX_VexImmW (int bytemode, int sizeflag) |
| 14797 | { |
| 14798 | int reg = -1; |
| 14799 | static unsigned char vex_imm8; |
| 14800 | |
| 14801 | if (vex_w_done == 0) |
| 14802 | { |
| 14803 | vex_w_done = 1; |
| 14804 | |
| 14805 | /* Skip mod/rm byte. */ |
| 14806 | MODRM_CHECK; |
| 14807 | codep++; |
| 14808 | |
| 14809 | vex_imm8 = get_vex_imm8 (sizeflag, 0); |
| 14810 | |
| 14811 | if (vex.w) |
| 14812 | reg = vex_imm8 >> 4; |
| 14813 | |
| 14814 | OP_EX_VexReg (bytemode, sizeflag, reg); |
| 14815 | } |
| 14816 | else if (vex_w_done == 1) |
| 14817 | { |
| 14818 | vex_w_done = 2; |
| 14819 | |
| 14820 | if (!vex.w) |
| 14821 | reg = vex_imm8 >> 4; |
| 14822 | |
| 14823 | OP_EX_VexReg (bytemode, sizeflag, reg); |
| 14824 | } |
| 14825 | else |
| 14826 | { |
| 14827 | /* Output the imm8 directly. */ |
| 14828 | scratchbuf[0] = '$'; |
| 14829 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); |
| 14830 | oappend (scratchbuf + intel_syntax); |
| 14831 | scratchbuf[0] = '\0'; |
| 14832 | codep++; |
| 14833 | } |
| 14834 | } |
| 14835 | |
| 14836 | static void |
| 14837 | OP_Vex_2src (int bytemode, int sizeflag) |
| 14838 | { |
| 14839 | if (modrm.mod == 3) |
| 14840 | { |
| 14841 | int reg = modrm.rm; |
| 14842 | USED_REX (REX_B); |
| 14843 | if (rex & REX_B) |
| 14844 | reg += 8; |
| 14845 | oappend (names_xmm[reg]); |
| 14846 | } |
| 14847 | else |
| 14848 | { |
| 14849 | if (intel_syntax |
| 14850 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
| 14851 | { |
| 14852 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; |
| 14853 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 14854 | } |
| 14855 | OP_E (bytemode, sizeflag); |
| 14856 | } |
| 14857 | } |
| 14858 | |
| 14859 | static void |
| 14860 | OP_Vex_2src_1 (int bytemode, int sizeflag) |
| 14861 | { |
| 14862 | if (modrm.mod == 3) |
| 14863 | { |
| 14864 | /* Skip mod/rm byte. */ |
| 14865 | MODRM_CHECK; |
| 14866 | codep++; |
| 14867 | } |
| 14868 | |
| 14869 | if (vex.w) |
| 14870 | oappend (names_xmm[vex.register_specifier]); |
| 14871 | else |
| 14872 | OP_Vex_2src (bytemode, sizeflag); |
| 14873 | } |
| 14874 | |
| 14875 | static void |
| 14876 | OP_Vex_2src_2 (int bytemode, int sizeflag) |
| 14877 | { |
| 14878 | if (vex.w) |
| 14879 | OP_Vex_2src (bytemode, sizeflag); |
| 14880 | else |
| 14881 | oappend (names_xmm[vex.register_specifier]); |
| 14882 | } |
| 14883 | |
| 14884 | static void |
| 14885 | OP_EX_VexW (int bytemode, int sizeflag) |
| 14886 | { |
| 14887 | int reg = -1; |
| 14888 | |
| 14889 | if (!vex_w_done) |
| 14890 | { |
| 14891 | vex_w_done = 1; |
| 14892 | |
| 14893 | /* Skip mod/rm byte. */ |
| 14894 | MODRM_CHECK; |
| 14895 | codep++; |
| 14896 | |
| 14897 | if (vex.w) |
| 14898 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
| 14899 | } |
| 14900 | else |
| 14901 | { |
| 14902 | if (!vex.w) |
| 14903 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
| 14904 | } |
| 14905 | |
| 14906 | OP_EX_VexReg (bytemode, sizeflag, reg); |
| 14907 | } |
| 14908 | |
| 14909 | static void |
| 14910 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, |
| 14911 | int sizeflag ATTRIBUTE_UNUSED) |
| 14912 | { |
| 14913 | /* Skip the immediate byte and check for invalid bits. */ |
| 14914 | FETCH_DATA (the_info, codep + 1); |
| 14915 | if (*codep++ & 0xf) |
| 14916 | BadOp (); |
| 14917 | } |
| 14918 | |
| 14919 | static void |
| 14920 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
| 14921 | { |
| 14922 | int reg; |
| 14923 | const char **names; |
| 14924 | |
| 14925 | FETCH_DATA (the_info, codep + 1); |
| 14926 | reg = *codep++; |
| 14927 | |
| 14928 | if (bytemode != x_mode) |
| 14929 | abort (); |
| 14930 | |
| 14931 | if (reg & 0xf) |
| 14932 | BadOp (); |
| 14933 | |
| 14934 | reg >>= 4; |
| 14935 | if (reg > 7 && address_mode != mode_64bit) |
| 14936 | BadOp (); |
| 14937 | |
| 14938 | switch (vex.length) |
| 14939 | { |
| 14940 | case 128: |
| 14941 | names = names_xmm; |
| 14942 | break; |
| 14943 | case 256: |
| 14944 | names = names_ymm; |
| 14945 | break; |
| 14946 | default: |
| 14947 | abort (); |
| 14948 | } |
| 14949 | oappend (names[reg]); |
| 14950 | } |
| 14951 | |
| 14952 | static void |
| 14953 | OP_XMM_VexW (int bytemode, int sizeflag) |
| 14954 | { |
| 14955 | /* Turn off the REX.W bit since it is used for swapping operands |
| 14956 | now. */ |
| 14957 | rex &= ~REX_W; |
| 14958 | OP_XMM (bytemode, sizeflag); |
| 14959 | } |
| 14960 | |
| 14961 | static void |
| 14962 | OP_EX_Vex (int bytemode, int sizeflag) |
| 14963 | { |
| 14964 | if (modrm.mod != 3) |
| 14965 | { |
| 14966 | if (vex.register_specifier != 0) |
| 14967 | BadOp (); |
| 14968 | need_vex_reg = 0; |
| 14969 | } |
| 14970 | OP_EX (bytemode, sizeflag); |
| 14971 | } |
| 14972 | |
| 14973 | static void |
| 14974 | OP_XMM_Vex (int bytemode, int sizeflag) |
| 14975 | { |
| 14976 | if (modrm.mod != 3) |
| 14977 | { |
| 14978 | if (vex.register_specifier != 0) |
| 14979 | BadOp (); |
| 14980 | need_vex_reg = 0; |
| 14981 | } |
| 14982 | OP_XMM (bytemode, sizeflag); |
| 14983 | } |
| 14984 | |
| 14985 | static void |
| 14986 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 14987 | { |
| 14988 | switch (vex.length) |
| 14989 | { |
| 14990 | case 128: |
| 14991 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
| 14992 | break; |
| 14993 | case 256: |
| 14994 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
| 14995 | break; |
| 14996 | default: |
| 14997 | abort (); |
| 14998 | } |
| 14999 | } |
| 15000 | |
| 15001 | static struct op vex_cmp_op[] = |
| 15002 | { |
| 15003 | { STRING_COMMA_LEN ("eq") }, |
| 15004 | { STRING_COMMA_LEN ("lt") }, |
| 15005 | { STRING_COMMA_LEN ("le") }, |
| 15006 | { STRING_COMMA_LEN ("unord") }, |
| 15007 | { STRING_COMMA_LEN ("neq") }, |
| 15008 | { STRING_COMMA_LEN ("nlt") }, |
| 15009 | { STRING_COMMA_LEN ("nle") }, |
| 15010 | { STRING_COMMA_LEN ("ord") }, |
| 15011 | { STRING_COMMA_LEN ("eq_uq") }, |
| 15012 | { STRING_COMMA_LEN ("nge") }, |
| 15013 | { STRING_COMMA_LEN ("ngt") }, |
| 15014 | { STRING_COMMA_LEN ("false") }, |
| 15015 | { STRING_COMMA_LEN ("neq_oq") }, |
| 15016 | { STRING_COMMA_LEN ("ge") }, |
| 15017 | { STRING_COMMA_LEN ("gt") }, |
| 15018 | { STRING_COMMA_LEN ("true") }, |
| 15019 | { STRING_COMMA_LEN ("eq_os") }, |
| 15020 | { STRING_COMMA_LEN ("lt_oq") }, |
| 15021 | { STRING_COMMA_LEN ("le_oq") }, |
| 15022 | { STRING_COMMA_LEN ("unord_s") }, |
| 15023 | { STRING_COMMA_LEN ("neq_us") }, |
| 15024 | { STRING_COMMA_LEN ("nlt_uq") }, |
| 15025 | { STRING_COMMA_LEN ("nle_uq") }, |
| 15026 | { STRING_COMMA_LEN ("ord_s") }, |
| 15027 | { STRING_COMMA_LEN ("eq_us") }, |
| 15028 | { STRING_COMMA_LEN ("nge_uq") }, |
| 15029 | { STRING_COMMA_LEN ("ngt_uq") }, |
| 15030 | { STRING_COMMA_LEN ("false_os") }, |
| 15031 | { STRING_COMMA_LEN ("neq_os") }, |
| 15032 | { STRING_COMMA_LEN ("ge_oq") }, |
| 15033 | { STRING_COMMA_LEN ("gt_oq") }, |
| 15034 | { STRING_COMMA_LEN ("true_us") }, |
| 15035 | }; |
| 15036 | |
| 15037 | static void |
| 15038 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 15039 | { |
| 15040 | unsigned int cmp_type; |
| 15041 | |
| 15042 | FETCH_DATA (the_info, codep + 1); |
| 15043 | cmp_type = *codep++ & 0xff; |
| 15044 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) |
| 15045 | { |
| 15046 | char suffix [3]; |
| 15047 | char *p = mnemonicendp - 2; |
| 15048 | suffix[0] = p[0]; |
| 15049 | suffix[1] = p[1]; |
| 15050 | suffix[2] = '\0'; |
| 15051 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
| 15052 | mnemonicendp += vex_cmp_op[cmp_type].len; |
| 15053 | } |
| 15054 | else |
| 15055 | { |
| 15056 | /* We have a reserved extension byte. Output it directly. */ |
| 15057 | scratchbuf[0] = '$'; |
| 15058 | print_operand_value (scratchbuf + 1, 1, cmp_type); |
| 15059 | oappend (scratchbuf + intel_syntax); |
| 15060 | scratchbuf[0] = '\0'; |
| 15061 | } |
| 15062 | } |
| 15063 | |
| 15064 | static const struct op pclmul_op[] = |
| 15065 | { |
| 15066 | { STRING_COMMA_LEN ("lql") }, |
| 15067 | { STRING_COMMA_LEN ("hql") }, |
| 15068 | { STRING_COMMA_LEN ("lqh") }, |
| 15069 | { STRING_COMMA_LEN ("hqh") } |
| 15070 | }; |
| 15071 | |
| 15072 | static void |
| 15073 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, |
| 15074 | int sizeflag ATTRIBUTE_UNUSED) |
| 15075 | { |
| 15076 | unsigned int pclmul_type; |
| 15077 | |
| 15078 | FETCH_DATA (the_info, codep + 1); |
| 15079 | pclmul_type = *codep++ & 0xff; |
| 15080 | switch (pclmul_type) |
| 15081 | { |
| 15082 | case 0x10: |
| 15083 | pclmul_type = 2; |
| 15084 | break; |
| 15085 | case 0x11: |
| 15086 | pclmul_type = 3; |
| 15087 | break; |
| 15088 | default: |
| 15089 | break; |
| 15090 | } |
| 15091 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
| 15092 | { |
| 15093 | char suffix [4]; |
| 15094 | char *p = mnemonicendp - 3; |
| 15095 | suffix[0] = p[0]; |
| 15096 | suffix[1] = p[1]; |
| 15097 | suffix[2] = p[2]; |
| 15098 | suffix[3] = '\0'; |
| 15099 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
| 15100 | mnemonicendp += pclmul_op[pclmul_type].len; |
| 15101 | } |
| 15102 | else |
| 15103 | { |
| 15104 | /* We have a reserved extension byte. Output it directly. */ |
| 15105 | scratchbuf[0] = '$'; |
| 15106 | print_operand_value (scratchbuf + 1, 1, pclmul_type); |
| 15107 | oappend (scratchbuf + intel_syntax); |
| 15108 | scratchbuf[0] = '\0'; |
| 15109 | } |
| 15110 | } |
| 15111 | |
| 15112 | static void |
| 15113 | MOVBE_Fixup (int bytemode, int sizeflag) |
| 15114 | { |
| 15115 | /* Add proper suffix to "movbe". */ |
| 15116 | char *p = mnemonicendp; |
| 15117 | |
| 15118 | switch (bytemode) |
| 15119 | { |
| 15120 | case v_mode: |
| 15121 | if (intel_syntax) |
| 15122 | goto skip; |
| 15123 | |
| 15124 | USED_REX (REX_W); |
| 15125 | if (sizeflag & SUFFIX_ALWAYS) |
| 15126 | { |
| 15127 | if (rex & REX_W) |
| 15128 | *p++ = 'q'; |
| 15129 | else |
| 15130 | { |
| 15131 | if (sizeflag & DFLAG) |
| 15132 | *p++ = 'l'; |
| 15133 | else |
| 15134 | *p++ = 'w'; |
| 15135 | used_prefixes |= (prefixes & PREFIX_DATA); |
| 15136 | } |
| 15137 | } |
| 15138 | break; |
| 15139 | default: |
| 15140 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
| 15141 | break; |
| 15142 | } |
| 15143 | mnemonicendp = p; |
| 15144 | *p = '\0'; |
| 15145 | |
| 15146 | skip: |
| 15147 | OP_M (bytemode, sizeflag); |
| 15148 | } |
| 15149 | |
| 15150 | static void |
| 15151 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 15152 | { |
| 15153 | int reg; |
| 15154 | const char **names; |
| 15155 | |
| 15156 | /* Skip mod/rm byte. */ |
| 15157 | MODRM_CHECK; |
| 15158 | codep++; |
| 15159 | |
| 15160 | if (vex.w) |
| 15161 | names = names64; |
| 15162 | else |
| 15163 | names = names32; |
| 15164 | |
| 15165 | reg = modrm.rm; |
| 15166 | USED_REX (REX_B); |
| 15167 | if (rex & REX_B) |
| 15168 | reg += 8; |
| 15169 | |
| 15170 | oappend (names[reg]); |
| 15171 | } |
| 15172 | |
| 15173 | static void |
| 15174 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
| 15175 | { |
| 15176 | const char **names; |
| 15177 | |
| 15178 | if (vex.w) |
| 15179 | names = names64; |
| 15180 | else |
| 15181 | names = names32; |
| 15182 | |
| 15183 | oappend (names[vex.register_specifier]); |
| 15184 | } |
| 15185 | |