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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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1/* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28/* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35#include "sysdep.h"
36#include "disassemble.h"
37#include "opintl.h"
38#include "opcode/i386.h"
39#include "libiberty.h"
40
41#include <setjmp.h>
42
43static int print_insn (bfd_vma, disassemble_info *);
44static void dofloat (int);
45static void OP_ST (int, int);
46static void OP_STi (int, int);
47static int putop (const char *, int);
48static void oappend (const char *);
49static void append_seg (void);
50static void OP_indirE (int, int);
51static void print_operand_value (char *, int, bfd_vma);
52static void OP_E_register (int, int);
53static void OP_E_memory (int, int);
54static void print_displacement (char *, bfd_vma);
55static void OP_E (int, int);
56static void OP_G (int, int);
57static bfd_vma get64 (void);
58static bfd_signed_vma get32 (void);
59static bfd_signed_vma get32s (void);
60static int get16 (void);
61static void set_op (bfd_vma, int);
62static void OP_Skip_MODRM (int, int);
63static void OP_REG (int, int);
64static void OP_IMREG (int, int);
65static void OP_I (int, int);
66static void OP_I64 (int, int);
67static void OP_sI (int, int);
68static void OP_J (int, int);
69static void OP_SEG (int, int);
70static void OP_DIR (int, int);
71static void OP_OFF (int, int);
72static void OP_OFF64 (int, int);
73static void ptr_reg (int, int);
74static void OP_ESreg (int, int);
75static void OP_DSreg (int, int);
76static void OP_C (int, int);
77static void OP_D (int, int);
78static void OP_T (int, int);
79static void OP_R (int, int);
80static void OP_MMX (int, int);
81static void OP_XMM (int, int);
82static void OP_EM (int, int);
83static void OP_EX (int, int);
84static void OP_EMC (int,int);
85static void OP_MXC (int,int);
86static void OP_MS (int, int);
87static void OP_XS (int, int);
88static void OP_M (int, int);
89static void OP_VEX (int, int);
90static void OP_EX_Vex (int, int);
91static void OP_EX_VexW (int, int);
92static void OP_EX_VexImmW (int, int);
93static void OP_XMM_Vex (int, int);
94static void OP_XMM_VexW (int, int);
95static void OP_Rounding (int, int);
96static void OP_REG_VexI4 (int, int);
97static void PCLMUL_Fixup (int, int);
98static void VEXI4_Fixup (int, int);
99static void VZERO_Fixup (int, int);
100static void VCMP_Fixup (int, int);
101static void VPCMP_Fixup (int, int);
102static void OP_0f07 (int, int);
103static void OP_Monitor (int, int);
104static void OP_Mwait (int, int);
105static void OP_Mwaitx (int, int);
106static void NOP_Fixup1 (int, int);
107static void NOP_Fixup2 (int, int);
108static void OP_3DNowSuffix (int, int);
109static void CMP_Fixup (int, int);
110static void BadOp (void);
111static void REP_Fixup (int, int);
112static void BND_Fixup (int, int);
113static void NOTRACK_Fixup (int, int);
114static void HLE_Fixup1 (int, int);
115static void HLE_Fixup2 (int, int);
116static void HLE_Fixup3 (int, int);
117static void CMPXCHG8B_Fixup (int, int);
118static void XMM_Fixup (int, int);
119static void CRC32_Fixup (int, int);
120static void FXSAVE_Fixup (int, int);
121static void PCMPESTR_Fixup (int, int);
122static void OP_LWPCB_E (int, int);
123static void OP_LWP_E (int, int);
124static void OP_Vex_2src_1 (int, int);
125static void OP_Vex_2src_2 (int, int);
126
127static void MOVBE_Fixup (int, int);
128
129static void OP_Mask (int, int);
130
131struct dis_private {
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
135 bfd_vma insn_start;
136 int orig_sizeflag;
137 OPCODES_SIGJMP_BUF bailout;
138};
139
140enum address_mode
141{
142 mode_16bit,
143 mode_32bit,
144 mode_64bit
145};
146
147enum address_mode address_mode;
148
149/* Flags for the prefixes for the current instruction. See below. */
150static int prefixes;
151
152/* REX prefix the current instruction. See below. */
153static int rex;
154/* Bits of REX we've already used. */
155static int rex_used;
156/* REX bits in original REX prefix ignored. */
157static int rex_ignored;
158/* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162#define USED_REX(value) \
163 { \
164 if (value) \
165 { \
166 if ((rex & value)) \
167 rex_used |= (value) | REX_OPCODE; \
168 } \
169 else \
170 rex_used |= REX_OPCODE; \
171 }
172
173/* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175static int used_prefixes;
176
177/* Flags stored in PREFIXES. */
178#define PREFIX_REPZ 1
179#define PREFIX_REPNZ 2
180#define PREFIX_LOCK 4
181#define PREFIX_CS 8
182#define PREFIX_SS 0x10
183#define PREFIX_DS 0x20
184#define PREFIX_ES 0x40
185#define PREFIX_FS 0x80
186#define PREFIX_GS 0x100
187#define PREFIX_DATA 0x200
188#define PREFIX_ADDR 0x400
189#define PREFIX_FWAIT 0x800
190
191/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 on error. */
194#define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
197
198static int
199fetch_data (struct disassemble_info *info, bfd_byte *addr)
200{
201 int status;
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
207 priv->max_fetched,
208 addr - priv->max_fetched,
209 info);
210 else
211 status = -1;
212 if (status != 0)
213 {
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
217 STATUS. */
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
221 }
222 else
223 priv->max_fetched = addr;
224 return 1;
225}
226
227/* Possible values for prefix requirement. */
228#define PREFIX_IGNORED_SHIFT 16
229#define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230#define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231#define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232#define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233#define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234
235/* Opcode prefixes. */
236#define PREFIX_OPCODE (PREFIX_REPZ \
237 | PREFIX_REPNZ \
238 | PREFIX_DATA)
239
240/* Prefixes ignored. */
241#define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
244
245#define XX { NULL, 0 }
246#define Bad_Opcode NULL, { { NULL, 0 } }, 0
247
248#define Eb { OP_E, b_mode }
249#define Ebnd { OP_E, bnd_mode }
250#define EbS { OP_E, b_swap_mode }
251#define Ev { OP_E, v_mode }
252#define Ev_bnd { OP_E, v_bnd_mode }
253#define EvS { OP_E, v_swap_mode }
254#define Ed { OP_E, d_mode }
255#define Edq { OP_E, dq_mode }
256#define Edqw { OP_E, dqw_mode }
257#define Edqb { OP_E, dqb_mode }
258#define Edb { OP_E, db_mode }
259#define Edw { OP_E, dw_mode }
260#define Edqd { OP_E, dqd_mode }
261#define Eq { OP_E, q_mode }
262#define indirEv { OP_indirE, indir_v_mode }
263#define indirEp { OP_indirE, f_mode }
264#define stackEv { OP_E, stack_v_mode }
265#define Em { OP_E, m_mode }
266#define Ew { OP_E, w_mode }
267#define M { OP_M, 0 } /* lea, lgdt, etc. */
268#define Ma { OP_M, a_mode }
269#define Mb { OP_M, b_mode }
270#define Md { OP_M, d_mode }
271#define Mo { OP_M, o_mode }
272#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273#define Mq { OP_M, q_mode }
274#define Mx { OP_M, x_mode }
275#define Mxmm { OP_M, xmm_mode }
276#define Gb { OP_G, b_mode }
277#define Gbnd { OP_G, bnd_mode }
278#define Gv { OP_G, v_mode }
279#define Gd { OP_G, d_mode }
280#define Gdq { OP_G, dq_mode }
281#define Gm { OP_G, m_mode }
282#define Gw { OP_G, w_mode }
283#define Rd { OP_R, d_mode }
284#define Rdq { OP_R, dq_mode }
285#define Rm { OP_R, m_mode }
286#define Ib { OP_I, b_mode }
287#define sIb { OP_sI, b_mode } /* sign extened byte */
288#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289#define Iv { OP_I, v_mode }
290#define sIv { OP_sI, v_mode }
291#define Iq { OP_I, q_mode }
292#define Iv64 { OP_I64, v_mode }
293#define Iw { OP_I, w_mode }
294#define I1 { OP_I, const_1_mode }
295#define Jb { OP_J, b_mode }
296#define Jv { OP_J, v_mode }
297#define Cm { OP_C, m_mode }
298#define Dm { OP_D, m_mode }
299#define Td { OP_T, d_mode }
300#define Skip_MODRM { OP_Skip_MODRM, 0 }
301
302#define RMeAX { OP_REG, eAX_reg }
303#define RMeBX { OP_REG, eBX_reg }
304#define RMeCX { OP_REG, eCX_reg }
305#define RMeDX { OP_REG, eDX_reg }
306#define RMeSP { OP_REG, eSP_reg }
307#define RMeBP { OP_REG, eBP_reg }
308#define RMeSI { OP_REG, eSI_reg }
309#define RMeDI { OP_REG, eDI_reg }
310#define RMrAX { OP_REG, rAX_reg }
311#define RMrBX { OP_REG, rBX_reg }
312#define RMrCX { OP_REG, rCX_reg }
313#define RMrDX { OP_REG, rDX_reg }
314#define RMrSP { OP_REG, rSP_reg }
315#define RMrBP { OP_REG, rBP_reg }
316#define RMrSI { OP_REG, rSI_reg }
317#define RMrDI { OP_REG, rDI_reg }
318#define RMAL { OP_REG, al_reg }
319#define RMCL { OP_REG, cl_reg }
320#define RMDL { OP_REG, dl_reg }
321#define RMBL { OP_REG, bl_reg }
322#define RMAH { OP_REG, ah_reg }
323#define RMCH { OP_REG, ch_reg }
324#define RMDH { OP_REG, dh_reg }
325#define RMBH { OP_REG, bh_reg }
326#define RMAX { OP_REG, ax_reg }
327#define RMDX { OP_REG, dx_reg }
328
329#define eAX { OP_IMREG, eAX_reg }
330#define eBX { OP_IMREG, eBX_reg }
331#define eCX { OP_IMREG, eCX_reg }
332#define eDX { OP_IMREG, eDX_reg }
333#define eSP { OP_IMREG, eSP_reg }
334#define eBP { OP_IMREG, eBP_reg }
335#define eSI { OP_IMREG, eSI_reg }
336#define eDI { OP_IMREG, eDI_reg }
337#define AL { OP_IMREG, al_reg }
338#define CL { OP_IMREG, cl_reg }
339#define DL { OP_IMREG, dl_reg }
340#define BL { OP_IMREG, bl_reg }
341#define AH { OP_IMREG, ah_reg }
342#define CH { OP_IMREG, ch_reg }
343#define DH { OP_IMREG, dh_reg }
344#define BH { OP_IMREG, bh_reg }
345#define AX { OP_IMREG, ax_reg }
346#define DX { OP_IMREG, dx_reg }
347#define zAX { OP_IMREG, z_mode_ax_reg }
348#define indirDX { OP_IMREG, indir_dx_reg }
349
350#define Sw { OP_SEG, w_mode }
351#define Sv { OP_SEG, v_mode }
352#define Ap { OP_DIR, 0 }
353#define Ob { OP_OFF64, b_mode }
354#define Ov { OP_OFF64, v_mode }
355#define Xb { OP_DSreg, eSI_reg }
356#define Xv { OP_DSreg, eSI_reg }
357#define Xz { OP_DSreg, eSI_reg }
358#define Yb { OP_ESreg, eDI_reg }
359#define Yv { OP_ESreg, eDI_reg }
360#define DSBX { OP_DSreg, eBX_reg }
361
362#define es { OP_REG, es_reg }
363#define ss { OP_REG, ss_reg }
364#define cs { OP_REG, cs_reg }
365#define ds { OP_REG, ds_reg }
366#define fs { OP_REG, fs_reg }
367#define gs { OP_REG, gs_reg }
368
369#define MX { OP_MMX, 0 }
370#define XM { OP_XMM, 0 }
371#define XMScalar { OP_XMM, scalar_mode }
372#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373#define XMM { OP_XMM, xmm_mode }
374#define XMxmmq { OP_XMM, xmmq_mode }
375#define EM { OP_EM, v_mode }
376#define EMS { OP_EM, v_swap_mode }
377#define EMd { OP_EM, d_mode }
378#define EMx { OP_EM, x_mode }
379#define EXbScalar { OP_EX, b_scalar_mode }
380#define EXw { OP_EX, w_mode }
381#define EXwScalar { OP_EX, w_scalar_mode }
382#define EXd { OP_EX, d_mode }
383#define EXdScalar { OP_EX, d_scalar_mode }
384#define EXdS { OP_EX, d_swap_mode }
385#define EXdScalarS { OP_EX, d_scalar_swap_mode }
386#define EXq { OP_EX, q_mode }
387#define EXqScalar { OP_EX, q_scalar_mode }
388#define EXqScalarS { OP_EX, q_scalar_swap_mode }
389#define EXqS { OP_EX, q_swap_mode }
390#define EXx { OP_EX, x_mode }
391#define EXxS { OP_EX, x_swap_mode }
392#define EXxmm { OP_EX, xmm_mode }
393#define EXymm { OP_EX, ymm_mode }
394#define EXxmmq { OP_EX, xmmq_mode }
395#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396#define EXxmm_mb { OP_EX, xmm_mb_mode }
397#define EXxmm_mw { OP_EX, xmm_mw_mode }
398#define EXxmm_md { OP_EX, xmm_md_mode }
399#define EXxmm_mq { OP_EX, xmm_mq_mode }
400#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
401#define EXxmmdw { OP_EX, xmmdw_mode }
402#define EXxmmqd { OP_EX, xmmqd_mode }
403#define EXymmq { OP_EX, ymmq_mode }
404#define EXVexWdq { OP_EX, vex_w_dq_mode }
405#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
406#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
407#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
408#define MS { OP_MS, v_mode }
409#define XS { OP_XS, v_mode }
410#define EMCq { OP_EMC, q_mode }
411#define MXC { OP_MXC, 0 }
412#define OPSUF { OP_3DNowSuffix, 0 }
413#define CMP { CMP_Fixup, 0 }
414#define XMM0 { XMM_Fixup, 0 }
415#define FXSAVE { FXSAVE_Fixup, 0 }
416#define Vex_2src_1 { OP_Vex_2src_1, 0 }
417#define Vex_2src_2 { OP_Vex_2src_2, 0 }
418
419#define Vex { OP_VEX, vex_mode }
420#define VexScalar { OP_VEX, vex_scalar_mode }
421#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
422#define Vex128 { OP_VEX, vex128_mode }
423#define Vex256 { OP_VEX, vex256_mode }
424#define VexGdq { OP_VEX, dq_mode }
425#define VexI4 { VEXI4_Fixup, 0}
426#define EXdVex { OP_EX_Vex, d_mode }
427#define EXdVexS { OP_EX_Vex, d_swap_mode }
428#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429#define EXqVex { OP_EX_Vex, q_mode }
430#define EXqVexS { OP_EX_Vex, q_swap_mode }
431#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432#define EXVexW { OP_EX_VexW, x_mode }
433#define EXdVexW { OP_EX_VexW, d_mode }
434#define EXqVexW { OP_EX_VexW, q_mode }
435#define EXVexImmW { OP_EX_VexImmW, x_mode }
436#define XMVex { OP_XMM_Vex, 0 }
437#define XMVexScalar { OP_XMM_Vex, scalar_mode }
438#define XMVexW { OP_XMM_VexW, 0 }
439#define XMVexI4 { OP_REG_VexI4, x_mode }
440#define PCLMUL { PCLMUL_Fixup, 0 }
441#define VZERO { VZERO_Fixup, 0 }
442#define VCMP { VCMP_Fixup, 0 }
443#define VPCMP { VPCMP_Fixup, 0 }
444
445#define EXxEVexR { OP_Rounding, evex_rounding_mode }
446#define EXxEVexS { OP_Rounding, evex_sae_mode }
447
448#define XMask { OP_Mask, mask_mode }
449#define MaskG { OP_G, mask_mode }
450#define MaskE { OP_E, mask_mode }
451#define MaskBDE { OP_E, mask_bd_mode }
452#define MaskR { OP_R, mask_mode }
453#define MaskVex { OP_VEX, mask_mode }
454
455#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
459
460/* Used handle "rep" prefix for string instructions. */
461#define Xbr { REP_Fixup, eSI_reg }
462#define Xvr { REP_Fixup, eSI_reg }
463#define Ybr { REP_Fixup, eDI_reg }
464#define Yvr { REP_Fixup, eDI_reg }
465#define Yzr { REP_Fixup, eDI_reg }
466#define indirDXr { REP_Fixup, indir_dx_reg }
467#define ALr { REP_Fixup, al_reg }
468#define eAXr { REP_Fixup, eAX_reg }
469
470/* Used handle HLE prefix for lockable instructions. */
471#define Ebh1 { HLE_Fixup1, b_mode }
472#define Evh1 { HLE_Fixup1, v_mode }
473#define Ebh2 { HLE_Fixup2, b_mode }
474#define Evh2 { HLE_Fixup2, v_mode }
475#define Ebh3 { HLE_Fixup3, b_mode }
476#define Evh3 { HLE_Fixup3, v_mode }
477
478#define BND { BND_Fixup, 0 }
479#define NOTRACK { NOTRACK_Fixup, 0 }
480
481#define cond_jump_flag { NULL, cond_jump_mode }
482#define loop_jcxz_flag { NULL, loop_jcxz_mode }
483
484/* bits in sizeflag */
485#define SUFFIX_ALWAYS 4
486#define AFLAG 2
487#define DFLAG 1
488
489enum
490{
491 /* byte operand */
492 b_mode = 1,
493 /* byte operand with operand swapped */
494 b_swap_mode,
495 /* byte operand, sign extend like 'T' suffix */
496 b_T_mode,
497 /* operand size depends on prefixes */
498 v_mode,
499 /* operand size depends on prefixes with operand swapped */
500 v_swap_mode,
501 /* word operand */
502 w_mode,
503 /* double word operand */
504 d_mode,
505 /* double word operand with operand swapped */
506 d_swap_mode,
507 /* quad word operand */
508 q_mode,
509 /* quad word operand with operand swapped */
510 q_swap_mode,
511 /* ten-byte operand */
512 t_mode,
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
515 x_mode,
516 /* Similar to x_mode, but with different EVEX mem shifts. */
517 evex_x_gscat_mode,
518 /* Similar to x_mode, but with disabled broadcast. */
519 evex_x_nobcst_mode,
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
521 in EVEX. */
522 x_swap_mode,
523 /* 16-byte XMM operand */
524 xmm_mode,
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
527 allowed. */
528 xmmq_mode,
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode,
531 /* XMM register or byte memory operand */
532 xmm_mb_mode,
533 /* XMM register or word memory operand */
534 xmm_mw_mode,
535 /* XMM register or double word memory operand */
536 xmm_md_mode,
537 /* XMM register or quad word memory operand */
538 xmm_mq_mode,
539 /* XMM register or double/quad word memory operand, depending on
540 VEX.W. */
541 xmm_mdq_mode,
542 /* 16-byte XMM, word, double word or quad word operand. */
543 xmmdw_mode,
544 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
545 xmmqd_mode,
546 /* 32-byte YMM operand */
547 ymm_mode,
548 /* quad word, ymmword or zmmword memory operand. */
549 ymmq_mode,
550 /* 32-byte YMM or 16-byte word operand */
551 ymmxmm_mode,
552 /* d_mode in 32bit, q_mode in 64bit mode. */
553 m_mode,
554 /* pair of v_mode operands */
555 a_mode,
556 cond_jump_mode,
557 loop_jcxz_mode,
558 v_bnd_mode,
559 /* operand size depends on REX prefixes. */
560 dq_mode,
561 /* registers like dq_mode, memory like w_mode. */
562 dqw_mode,
563 bnd_mode,
564 /* 4- or 6-byte pointer operand */
565 f_mode,
566 const_1_mode,
567 /* v_mode for indirect branch opcodes. */
568 indir_v_mode,
569 /* v_mode for stack-related opcodes. */
570 stack_v_mode,
571 /* non-quad operand size depends on prefixes */
572 z_mode,
573 /* 16-byte operand */
574 o_mode,
575 /* registers like dq_mode, memory like b_mode. */
576 dqb_mode,
577 /* registers like d_mode, memory like b_mode. */
578 db_mode,
579 /* registers like d_mode, memory like w_mode. */
580 dw_mode,
581 /* registers like dq_mode, memory like d_mode. */
582 dqd_mode,
583 /* normal vex mode */
584 vex_mode,
585 /* 128bit vex mode */
586 vex128_mode,
587 /* 256bit vex mode */
588 vex256_mode,
589 /* operand size depends on the VEX.W bit. */
590 vex_w_dq_mode,
591
592 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
595 vex_vsib_d_w_d_mode,
596 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 vex_vsib_q_w_d_mode,
600
601 /* scalar, ignore vector length. */
602 scalar_mode,
603 /* like b_mode, ignore vector length. */
604 b_scalar_mode,
605 /* like w_mode, ignore vector length. */
606 w_scalar_mode,
607 /* like d_mode, ignore vector length. */
608 d_scalar_mode,
609 /* like d_swap_mode, ignore vector length. */
610 d_scalar_swap_mode,
611 /* like q_mode, ignore vector length. */
612 q_scalar_mode,
613 /* like q_swap_mode, ignore vector length. */
614 q_scalar_swap_mode,
615 /* like vex_mode, ignore vector length. */
616 vex_scalar_mode,
617 /* like vex_w_dq_mode, ignore vector length. */
618 vex_scalar_w_dq_mode,
619
620 /* Static rounding. */
621 evex_rounding_mode,
622 /* Supress all exceptions. */
623 evex_sae_mode,
624
625 /* Mask register operand. */
626 mask_mode,
627 /* Mask register operand. */
628 mask_bd_mode,
629
630 es_reg,
631 cs_reg,
632 ss_reg,
633 ds_reg,
634 fs_reg,
635 gs_reg,
636
637 eAX_reg,
638 eCX_reg,
639 eDX_reg,
640 eBX_reg,
641 eSP_reg,
642 eBP_reg,
643 eSI_reg,
644 eDI_reg,
645
646 al_reg,
647 cl_reg,
648 dl_reg,
649 bl_reg,
650 ah_reg,
651 ch_reg,
652 dh_reg,
653 bh_reg,
654
655 ax_reg,
656 cx_reg,
657 dx_reg,
658 bx_reg,
659 sp_reg,
660 bp_reg,
661 si_reg,
662 di_reg,
663
664 rAX_reg,
665 rCX_reg,
666 rDX_reg,
667 rBX_reg,
668 rSP_reg,
669 rBP_reg,
670 rSI_reg,
671 rDI_reg,
672
673 z_mode_ax_reg,
674 indir_dx_reg
675};
676
677enum
678{
679 FLOATCODE = 1,
680 USE_REG_TABLE,
681 USE_MOD_TABLE,
682 USE_RM_TABLE,
683 USE_PREFIX_TABLE,
684 USE_X86_64_TABLE,
685 USE_3BYTE_TABLE,
686 USE_XOP_8F_TABLE,
687 USE_VEX_C4_TABLE,
688 USE_VEX_C5_TABLE,
689 USE_VEX_LEN_TABLE,
690 USE_VEX_W_TABLE,
691 USE_EVEX_TABLE
692};
693
694#define FLOAT NULL, { { NULL, FLOATCODE } }, 0
695
696#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
697#define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
698#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
699#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
700#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
701#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
702#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
703#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
704#define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
705#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
706#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
707#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
708#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
709#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
710#define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
711
712enum
713{
714 REG_80 = 0,
715 REG_81,
716 REG_83,
717 REG_8F,
718 REG_C0,
719 REG_C1,
720 REG_C6,
721 REG_C7,
722 REG_D0,
723 REG_D1,
724 REG_D2,
725 REG_D3,
726 REG_F6,
727 REG_F7,
728 REG_FE,
729 REG_FF,
730 REG_0F00,
731 REG_0F01,
732 REG_0F0D,
733 REG_0F18,
734 REG_0F1E_MOD_3,
735 REG_0F71,
736 REG_0F72,
737 REG_0F73,
738 REG_0FA6,
739 REG_0FA7,
740 REG_0FAE,
741 REG_0FBA,
742 REG_0FC7,
743 REG_VEX_0F71,
744 REG_VEX_0F72,
745 REG_VEX_0F73,
746 REG_VEX_0FAE,
747 REG_VEX_0F38F3,
748 REG_XOP_LWPCB,
749 REG_XOP_LWP,
750 REG_XOP_TBM_01,
751 REG_XOP_TBM_02,
752
753 REG_EVEX_0F71,
754 REG_EVEX_0F72,
755 REG_EVEX_0F73,
756 REG_EVEX_0F38C6,
757 REG_EVEX_0F38C7
758};
759
760enum
761{
762 MOD_8D = 0,
763 MOD_C6_REG_7,
764 MOD_C7_REG_7,
765 MOD_FF_REG_3,
766 MOD_FF_REG_5,
767 MOD_0F01_REG_0,
768 MOD_0F01_REG_1,
769 MOD_0F01_REG_2,
770 MOD_0F01_REG_3,
771 MOD_0F01_REG_5,
772 MOD_0F01_REG_7,
773 MOD_0F12_PREFIX_0,
774 MOD_0F13,
775 MOD_0F16_PREFIX_0,
776 MOD_0F17,
777 MOD_0F18_REG_0,
778 MOD_0F18_REG_1,
779 MOD_0F18_REG_2,
780 MOD_0F18_REG_3,
781 MOD_0F18_REG_4,
782 MOD_0F18_REG_5,
783 MOD_0F18_REG_6,
784 MOD_0F18_REG_7,
785 MOD_0F1A_PREFIX_0,
786 MOD_0F1B_PREFIX_0,
787 MOD_0F1B_PREFIX_1,
788 MOD_0F1E_PREFIX_1,
789 MOD_0F24,
790 MOD_0F26,
791 MOD_0F2B_PREFIX_0,
792 MOD_0F2B_PREFIX_1,
793 MOD_0F2B_PREFIX_2,
794 MOD_0F2B_PREFIX_3,
795 MOD_0F51,
796 MOD_0F71_REG_2,
797 MOD_0F71_REG_4,
798 MOD_0F71_REG_6,
799 MOD_0F72_REG_2,
800 MOD_0F72_REG_4,
801 MOD_0F72_REG_6,
802 MOD_0F73_REG_2,
803 MOD_0F73_REG_3,
804 MOD_0F73_REG_6,
805 MOD_0F73_REG_7,
806 MOD_0FAE_REG_0,
807 MOD_0FAE_REG_1,
808 MOD_0FAE_REG_2,
809 MOD_0FAE_REG_3,
810 MOD_0FAE_REG_4,
811 MOD_0FAE_REG_5,
812 MOD_0FAE_REG_6,
813 MOD_0FAE_REG_7,
814 MOD_0FB2,
815 MOD_0FB4,
816 MOD_0FB5,
817 MOD_0FC3,
818 MOD_0FC7_REG_3,
819 MOD_0FC7_REG_4,
820 MOD_0FC7_REG_5,
821 MOD_0FC7_REG_6,
822 MOD_0FC7_REG_7,
823 MOD_0FD7,
824 MOD_0FE7_PREFIX_2,
825 MOD_0FF0_PREFIX_3,
826 MOD_0F382A_PREFIX_2,
827 MOD_0F38F5_PREFIX_2,
828 MOD_0F38F6_PREFIX_0,
829 MOD_62_32BIT,
830 MOD_C4_32BIT,
831 MOD_C5_32BIT,
832 MOD_VEX_0F12_PREFIX_0,
833 MOD_VEX_0F13,
834 MOD_VEX_0F16_PREFIX_0,
835 MOD_VEX_0F17,
836 MOD_VEX_0F2B,
837 MOD_VEX_W_0_0F41_P_0_LEN_1,
838 MOD_VEX_W_1_0F41_P_0_LEN_1,
839 MOD_VEX_W_0_0F41_P_2_LEN_1,
840 MOD_VEX_W_1_0F41_P_2_LEN_1,
841 MOD_VEX_W_0_0F42_P_0_LEN_1,
842 MOD_VEX_W_1_0F42_P_0_LEN_1,
843 MOD_VEX_W_0_0F42_P_2_LEN_1,
844 MOD_VEX_W_1_0F42_P_2_LEN_1,
845 MOD_VEX_W_0_0F44_P_0_LEN_1,
846 MOD_VEX_W_1_0F44_P_0_LEN_1,
847 MOD_VEX_W_0_0F44_P_2_LEN_1,
848 MOD_VEX_W_1_0F44_P_2_LEN_1,
849 MOD_VEX_W_0_0F45_P_0_LEN_1,
850 MOD_VEX_W_1_0F45_P_0_LEN_1,
851 MOD_VEX_W_0_0F45_P_2_LEN_1,
852 MOD_VEX_W_1_0F45_P_2_LEN_1,
853 MOD_VEX_W_0_0F46_P_0_LEN_1,
854 MOD_VEX_W_1_0F46_P_0_LEN_1,
855 MOD_VEX_W_0_0F46_P_2_LEN_1,
856 MOD_VEX_W_1_0F46_P_2_LEN_1,
857 MOD_VEX_W_0_0F47_P_0_LEN_1,
858 MOD_VEX_W_1_0F47_P_0_LEN_1,
859 MOD_VEX_W_0_0F47_P_2_LEN_1,
860 MOD_VEX_W_1_0F47_P_2_LEN_1,
861 MOD_VEX_W_0_0F4A_P_0_LEN_1,
862 MOD_VEX_W_1_0F4A_P_0_LEN_1,
863 MOD_VEX_W_0_0F4A_P_2_LEN_1,
864 MOD_VEX_W_1_0F4A_P_2_LEN_1,
865 MOD_VEX_W_0_0F4B_P_0_LEN_1,
866 MOD_VEX_W_1_0F4B_P_0_LEN_1,
867 MOD_VEX_W_0_0F4B_P_2_LEN_1,
868 MOD_VEX_0F50,
869 MOD_VEX_0F71_REG_2,
870 MOD_VEX_0F71_REG_4,
871 MOD_VEX_0F71_REG_6,
872 MOD_VEX_0F72_REG_2,
873 MOD_VEX_0F72_REG_4,
874 MOD_VEX_0F72_REG_6,
875 MOD_VEX_0F73_REG_2,
876 MOD_VEX_0F73_REG_3,
877 MOD_VEX_0F73_REG_6,
878 MOD_VEX_0F73_REG_7,
879 MOD_VEX_W_0_0F91_P_0_LEN_0,
880 MOD_VEX_W_1_0F91_P_0_LEN_0,
881 MOD_VEX_W_0_0F91_P_2_LEN_0,
882 MOD_VEX_W_1_0F91_P_2_LEN_0,
883 MOD_VEX_W_0_0F92_P_0_LEN_0,
884 MOD_VEX_W_0_0F92_P_2_LEN_0,
885 MOD_VEX_W_0_0F92_P_3_LEN_0,
886 MOD_VEX_W_1_0F92_P_3_LEN_0,
887 MOD_VEX_W_0_0F93_P_0_LEN_0,
888 MOD_VEX_W_0_0F93_P_2_LEN_0,
889 MOD_VEX_W_0_0F93_P_3_LEN_0,
890 MOD_VEX_W_1_0F93_P_3_LEN_0,
891 MOD_VEX_W_0_0F98_P_0_LEN_0,
892 MOD_VEX_W_1_0F98_P_0_LEN_0,
893 MOD_VEX_W_0_0F98_P_2_LEN_0,
894 MOD_VEX_W_1_0F98_P_2_LEN_0,
895 MOD_VEX_W_0_0F99_P_0_LEN_0,
896 MOD_VEX_W_1_0F99_P_0_LEN_0,
897 MOD_VEX_W_0_0F99_P_2_LEN_0,
898 MOD_VEX_W_1_0F99_P_2_LEN_0,
899 MOD_VEX_0FAE_REG_2,
900 MOD_VEX_0FAE_REG_3,
901 MOD_VEX_0FD7_PREFIX_2,
902 MOD_VEX_0FE7_PREFIX_2,
903 MOD_VEX_0FF0_PREFIX_3,
904 MOD_VEX_0F381A_PREFIX_2,
905 MOD_VEX_0F382A_PREFIX_2,
906 MOD_VEX_0F382C_PREFIX_2,
907 MOD_VEX_0F382D_PREFIX_2,
908 MOD_VEX_0F382E_PREFIX_2,
909 MOD_VEX_0F382F_PREFIX_2,
910 MOD_VEX_0F385A_PREFIX_2,
911 MOD_VEX_0F388C_PREFIX_2,
912 MOD_VEX_0F388E_PREFIX_2,
913 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
914 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
915 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
916 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
917 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
918 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
919 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
920 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
921
922 MOD_EVEX_0F10_PREFIX_1,
923 MOD_EVEX_0F10_PREFIX_3,
924 MOD_EVEX_0F11_PREFIX_1,
925 MOD_EVEX_0F11_PREFIX_3,
926 MOD_EVEX_0F12_PREFIX_0,
927 MOD_EVEX_0F16_PREFIX_0,
928 MOD_EVEX_0F38C6_REG_1,
929 MOD_EVEX_0F38C6_REG_2,
930 MOD_EVEX_0F38C6_REG_5,
931 MOD_EVEX_0F38C6_REG_6,
932 MOD_EVEX_0F38C7_REG_1,
933 MOD_EVEX_0F38C7_REG_2,
934 MOD_EVEX_0F38C7_REG_5,
935 MOD_EVEX_0F38C7_REG_6
936};
937
938enum
939{
940 RM_C6_REG_7 = 0,
941 RM_C7_REG_7,
942 RM_0F01_REG_0,
943 RM_0F01_REG_1,
944 RM_0F01_REG_2,
945 RM_0F01_REG_3,
946 RM_0F01_REG_5,
947 RM_0F01_REG_7,
948 RM_0F1E_MOD_3_REG_7,
949 RM_0FAE_REG_6,
950 RM_0FAE_REG_7
951};
952
953enum
954{
955 PREFIX_90 = 0,
956 PREFIX_MOD_0_0F01_REG_5,
957 PREFIX_MOD_3_0F01_REG_5_RM_0,
958 PREFIX_MOD_3_0F01_REG_5_RM_2,
959 PREFIX_0F10,
960 PREFIX_0F11,
961 PREFIX_0F12,
962 PREFIX_0F16,
963 PREFIX_0F1A,
964 PREFIX_0F1B,
965 PREFIX_0F1E,
966 PREFIX_0F2A,
967 PREFIX_0F2B,
968 PREFIX_0F2C,
969 PREFIX_0F2D,
970 PREFIX_0F2E,
971 PREFIX_0F2F,
972 PREFIX_0F51,
973 PREFIX_0F52,
974 PREFIX_0F53,
975 PREFIX_0F58,
976 PREFIX_0F59,
977 PREFIX_0F5A,
978 PREFIX_0F5B,
979 PREFIX_0F5C,
980 PREFIX_0F5D,
981 PREFIX_0F5E,
982 PREFIX_0F5F,
983 PREFIX_0F60,
984 PREFIX_0F61,
985 PREFIX_0F62,
986 PREFIX_0F6C,
987 PREFIX_0F6D,
988 PREFIX_0F6F,
989 PREFIX_0F70,
990 PREFIX_0F73_REG_3,
991 PREFIX_0F73_REG_7,
992 PREFIX_0F78,
993 PREFIX_0F79,
994 PREFIX_0F7C,
995 PREFIX_0F7D,
996 PREFIX_0F7E,
997 PREFIX_0F7F,
998 PREFIX_0FAE_REG_0,
999 PREFIX_0FAE_REG_1,
1000 PREFIX_0FAE_REG_2,
1001 PREFIX_0FAE_REG_3,
1002 PREFIX_MOD_0_0FAE_REG_4,
1003 PREFIX_MOD_3_0FAE_REG_4,
1004 PREFIX_MOD_0_0FAE_REG_5,
1005 PREFIX_MOD_3_0FAE_REG_5,
1006 PREFIX_0FAE_REG_6,
1007 PREFIX_0FAE_REG_7,
1008 PREFIX_0FB8,
1009 PREFIX_0FBC,
1010 PREFIX_0FBD,
1011 PREFIX_0FC2,
1012 PREFIX_MOD_0_0FC3,
1013 PREFIX_MOD_0_0FC7_REG_6,
1014 PREFIX_MOD_3_0FC7_REG_6,
1015 PREFIX_MOD_3_0FC7_REG_7,
1016 PREFIX_0FD0,
1017 PREFIX_0FD6,
1018 PREFIX_0FE6,
1019 PREFIX_0FE7,
1020 PREFIX_0FF0,
1021 PREFIX_0FF7,
1022 PREFIX_0F3810,
1023 PREFIX_0F3814,
1024 PREFIX_0F3815,
1025 PREFIX_0F3817,
1026 PREFIX_0F3820,
1027 PREFIX_0F3821,
1028 PREFIX_0F3822,
1029 PREFIX_0F3823,
1030 PREFIX_0F3824,
1031 PREFIX_0F3825,
1032 PREFIX_0F3828,
1033 PREFIX_0F3829,
1034 PREFIX_0F382A,
1035 PREFIX_0F382B,
1036 PREFIX_0F3830,
1037 PREFIX_0F3831,
1038 PREFIX_0F3832,
1039 PREFIX_0F3833,
1040 PREFIX_0F3834,
1041 PREFIX_0F3835,
1042 PREFIX_0F3837,
1043 PREFIX_0F3838,
1044 PREFIX_0F3839,
1045 PREFIX_0F383A,
1046 PREFIX_0F383B,
1047 PREFIX_0F383C,
1048 PREFIX_0F383D,
1049 PREFIX_0F383E,
1050 PREFIX_0F383F,
1051 PREFIX_0F3840,
1052 PREFIX_0F3841,
1053 PREFIX_0F3880,
1054 PREFIX_0F3881,
1055 PREFIX_0F3882,
1056 PREFIX_0F38C8,
1057 PREFIX_0F38C9,
1058 PREFIX_0F38CA,
1059 PREFIX_0F38CB,
1060 PREFIX_0F38CC,
1061 PREFIX_0F38CD,
1062 PREFIX_0F38CF,
1063 PREFIX_0F38DB,
1064 PREFIX_0F38DC,
1065 PREFIX_0F38DD,
1066 PREFIX_0F38DE,
1067 PREFIX_0F38DF,
1068 PREFIX_0F38F0,
1069 PREFIX_0F38F1,
1070 PREFIX_0F38F5,
1071 PREFIX_0F38F6,
1072 PREFIX_0F3A08,
1073 PREFIX_0F3A09,
1074 PREFIX_0F3A0A,
1075 PREFIX_0F3A0B,
1076 PREFIX_0F3A0C,
1077 PREFIX_0F3A0D,
1078 PREFIX_0F3A0E,
1079 PREFIX_0F3A14,
1080 PREFIX_0F3A15,
1081 PREFIX_0F3A16,
1082 PREFIX_0F3A17,
1083 PREFIX_0F3A20,
1084 PREFIX_0F3A21,
1085 PREFIX_0F3A22,
1086 PREFIX_0F3A40,
1087 PREFIX_0F3A41,
1088 PREFIX_0F3A42,
1089 PREFIX_0F3A44,
1090 PREFIX_0F3A60,
1091 PREFIX_0F3A61,
1092 PREFIX_0F3A62,
1093 PREFIX_0F3A63,
1094 PREFIX_0F3ACC,
1095 PREFIX_0F3ACE,
1096 PREFIX_0F3ACF,
1097 PREFIX_0F3ADF,
1098 PREFIX_VEX_0F10,
1099 PREFIX_VEX_0F11,
1100 PREFIX_VEX_0F12,
1101 PREFIX_VEX_0F16,
1102 PREFIX_VEX_0F2A,
1103 PREFIX_VEX_0F2C,
1104 PREFIX_VEX_0F2D,
1105 PREFIX_VEX_0F2E,
1106 PREFIX_VEX_0F2F,
1107 PREFIX_VEX_0F41,
1108 PREFIX_VEX_0F42,
1109 PREFIX_VEX_0F44,
1110 PREFIX_VEX_0F45,
1111 PREFIX_VEX_0F46,
1112 PREFIX_VEX_0F47,
1113 PREFIX_VEX_0F4A,
1114 PREFIX_VEX_0F4B,
1115 PREFIX_VEX_0F51,
1116 PREFIX_VEX_0F52,
1117 PREFIX_VEX_0F53,
1118 PREFIX_VEX_0F58,
1119 PREFIX_VEX_0F59,
1120 PREFIX_VEX_0F5A,
1121 PREFIX_VEX_0F5B,
1122 PREFIX_VEX_0F5C,
1123 PREFIX_VEX_0F5D,
1124 PREFIX_VEX_0F5E,
1125 PREFIX_VEX_0F5F,
1126 PREFIX_VEX_0F60,
1127 PREFIX_VEX_0F61,
1128 PREFIX_VEX_0F62,
1129 PREFIX_VEX_0F63,
1130 PREFIX_VEX_0F64,
1131 PREFIX_VEX_0F65,
1132 PREFIX_VEX_0F66,
1133 PREFIX_VEX_0F67,
1134 PREFIX_VEX_0F68,
1135 PREFIX_VEX_0F69,
1136 PREFIX_VEX_0F6A,
1137 PREFIX_VEX_0F6B,
1138 PREFIX_VEX_0F6C,
1139 PREFIX_VEX_0F6D,
1140 PREFIX_VEX_0F6E,
1141 PREFIX_VEX_0F6F,
1142 PREFIX_VEX_0F70,
1143 PREFIX_VEX_0F71_REG_2,
1144 PREFIX_VEX_0F71_REG_4,
1145 PREFIX_VEX_0F71_REG_6,
1146 PREFIX_VEX_0F72_REG_2,
1147 PREFIX_VEX_0F72_REG_4,
1148 PREFIX_VEX_0F72_REG_6,
1149 PREFIX_VEX_0F73_REG_2,
1150 PREFIX_VEX_0F73_REG_3,
1151 PREFIX_VEX_0F73_REG_6,
1152 PREFIX_VEX_0F73_REG_7,
1153 PREFIX_VEX_0F74,
1154 PREFIX_VEX_0F75,
1155 PREFIX_VEX_0F76,
1156 PREFIX_VEX_0F77,
1157 PREFIX_VEX_0F7C,
1158 PREFIX_VEX_0F7D,
1159 PREFIX_VEX_0F7E,
1160 PREFIX_VEX_0F7F,
1161 PREFIX_VEX_0F90,
1162 PREFIX_VEX_0F91,
1163 PREFIX_VEX_0F92,
1164 PREFIX_VEX_0F93,
1165 PREFIX_VEX_0F98,
1166 PREFIX_VEX_0F99,
1167 PREFIX_VEX_0FC2,
1168 PREFIX_VEX_0FC4,
1169 PREFIX_VEX_0FC5,
1170 PREFIX_VEX_0FD0,
1171 PREFIX_VEX_0FD1,
1172 PREFIX_VEX_0FD2,
1173 PREFIX_VEX_0FD3,
1174 PREFIX_VEX_0FD4,
1175 PREFIX_VEX_0FD5,
1176 PREFIX_VEX_0FD6,
1177 PREFIX_VEX_0FD7,
1178 PREFIX_VEX_0FD8,
1179 PREFIX_VEX_0FD9,
1180 PREFIX_VEX_0FDA,
1181 PREFIX_VEX_0FDB,
1182 PREFIX_VEX_0FDC,
1183 PREFIX_VEX_0FDD,
1184 PREFIX_VEX_0FDE,
1185 PREFIX_VEX_0FDF,
1186 PREFIX_VEX_0FE0,
1187 PREFIX_VEX_0FE1,
1188 PREFIX_VEX_0FE2,
1189 PREFIX_VEX_0FE3,
1190 PREFIX_VEX_0FE4,
1191 PREFIX_VEX_0FE5,
1192 PREFIX_VEX_0FE6,
1193 PREFIX_VEX_0FE7,
1194 PREFIX_VEX_0FE8,
1195 PREFIX_VEX_0FE9,
1196 PREFIX_VEX_0FEA,
1197 PREFIX_VEX_0FEB,
1198 PREFIX_VEX_0FEC,
1199 PREFIX_VEX_0FED,
1200 PREFIX_VEX_0FEE,
1201 PREFIX_VEX_0FEF,
1202 PREFIX_VEX_0FF0,
1203 PREFIX_VEX_0FF1,
1204 PREFIX_VEX_0FF2,
1205 PREFIX_VEX_0FF3,
1206 PREFIX_VEX_0FF4,
1207 PREFIX_VEX_0FF5,
1208 PREFIX_VEX_0FF6,
1209 PREFIX_VEX_0FF7,
1210 PREFIX_VEX_0FF8,
1211 PREFIX_VEX_0FF9,
1212 PREFIX_VEX_0FFA,
1213 PREFIX_VEX_0FFB,
1214 PREFIX_VEX_0FFC,
1215 PREFIX_VEX_0FFD,
1216 PREFIX_VEX_0FFE,
1217 PREFIX_VEX_0F3800,
1218 PREFIX_VEX_0F3801,
1219 PREFIX_VEX_0F3802,
1220 PREFIX_VEX_0F3803,
1221 PREFIX_VEX_0F3804,
1222 PREFIX_VEX_0F3805,
1223 PREFIX_VEX_0F3806,
1224 PREFIX_VEX_0F3807,
1225 PREFIX_VEX_0F3808,
1226 PREFIX_VEX_0F3809,
1227 PREFIX_VEX_0F380A,
1228 PREFIX_VEX_0F380B,
1229 PREFIX_VEX_0F380C,
1230 PREFIX_VEX_0F380D,
1231 PREFIX_VEX_0F380E,
1232 PREFIX_VEX_0F380F,
1233 PREFIX_VEX_0F3813,
1234 PREFIX_VEX_0F3816,
1235 PREFIX_VEX_0F3817,
1236 PREFIX_VEX_0F3818,
1237 PREFIX_VEX_0F3819,
1238 PREFIX_VEX_0F381A,
1239 PREFIX_VEX_0F381C,
1240 PREFIX_VEX_0F381D,
1241 PREFIX_VEX_0F381E,
1242 PREFIX_VEX_0F3820,
1243 PREFIX_VEX_0F3821,
1244 PREFIX_VEX_0F3822,
1245 PREFIX_VEX_0F3823,
1246 PREFIX_VEX_0F3824,
1247 PREFIX_VEX_0F3825,
1248 PREFIX_VEX_0F3828,
1249 PREFIX_VEX_0F3829,
1250 PREFIX_VEX_0F382A,
1251 PREFIX_VEX_0F382B,
1252 PREFIX_VEX_0F382C,
1253 PREFIX_VEX_0F382D,
1254 PREFIX_VEX_0F382E,
1255 PREFIX_VEX_0F382F,
1256 PREFIX_VEX_0F3830,
1257 PREFIX_VEX_0F3831,
1258 PREFIX_VEX_0F3832,
1259 PREFIX_VEX_0F3833,
1260 PREFIX_VEX_0F3834,
1261 PREFIX_VEX_0F3835,
1262 PREFIX_VEX_0F3836,
1263 PREFIX_VEX_0F3837,
1264 PREFIX_VEX_0F3838,
1265 PREFIX_VEX_0F3839,
1266 PREFIX_VEX_0F383A,
1267 PREFIX_VEX_0F383B,
1268 PREFIX_VEX_0F383C,
1269 PREFIX_VEX_0F383D,
1270 PREFIX_VEX_0F383E,
1271 PREFIX_VEX_0F383F,
1272 PREFIX_VEX_0F3840,
1273 PREFIX_VEX_0F3841,
1274 PREFIX_VEX_0F3845,
1275 PREFIX_VEX_0F3846,
1276 PREFIX_VEX_0F3847,
1277 PREFIX_VEX_0F3858,
1278 PREFIX_VEX_0F3859,
1279 PREFIX_VEX_0F385A,
1280 PREFIX_VEX_0F3878,
1281 PREFIX_VEX_0F3879,
1282 PREFIX_VEX_0F388C,
1283 PREFIX_VEX_0F388E,
1284 PREFIX_VEX_0F3890,
1285 PREFIX_VEX_0F3891,
1286 PREFIX_VEX_0F3892,
1287 PREFIX_VEX_0F3893,
1288 PREFIX_VEX_0F3896,
1289 PREFIX_VEX_0F3897,
1290 PREFIX_VEX_0F3898,
1291 PREFIX_VEX_0F3899,
1292 PREFIX_VEX_0F389A,
1293 PREFIX_VEX_0F389B,
1294 PREFIX_VEX_0F389C,
1295 PREFIX_VEX_0F389D,
1296 PREFIX_VEX_0F389E,
1297 PREFIX_VEX_0F389F,
1298 PREFIX_VEX_0F38A6,
1299 PREFIX_VEX_0F38A7,
1300 PREFIX_VEX_0F38A8,
1301 PREFIX_VEX_0F38A9,
1302 PREFIX_VEX_0F38AA,
1303 PREFIX_VEX_0F38AB,
1304 PREFIX_VEX_0F38AC,
1305 PREFIX_VEX_0F38AD,
1306 PREFIX_VEX_0F38AE,
1307 PREFIX_VEX_0F38AF,
1308 PREFIX_VEX_0F38B6,
1309 PREFIX_VEX_0F38B7,
1310 PREFIX_VEX_0F38B8,
1311 PREFIX_VEX_0F38B9,
1312 PREFIX_VEX_0F38BA,
1313 PREFIX_VEX_0F38BB,
1314 PREFIX_VEX_0F38BC,
1315 PREFIX_VEX_0F38BD,
1316 PREFIX_VEX_0F38BE,
1317 PREFIX_VEX_0F38BF,
1318 PREFIX_VEX_0F38CF,
1319 PREFIX_VEX_0F38DB,
1320 PREFIX_VEX_0F38DC,
1321 PREFIX_VEX_0F38DD,
1322 PREFIX_VEX_0F38DE,
1323 PREFIX_VEX_0F38DF,
1324 PREFIX_VEX_0F38F2,
1325 PREFIX_VEX_0F38F3_REG_1,
1326 PREFIX_VEX_0F38F3_REG_2,
1327 PREFIX_VEX_0F38F3_REG_3,
1328 PREFIX_VEX_0F38F5,
1329 PREFIX_VEX_0F38F6,
1330 PREFIX_VEX_0F38F7,
1331 PREFIX_VEX_0F3A00,
1332 PREFIX_VEX_0F3A01,
1333 PREFIX_VEX_0F3A02,
1334 PREFIX_VEX_0F3A04,
1335 PREFIX_VEX_0F3A05,
1336 PREFIX_VEX_0F3A06,
1337 PREFIX_VEX_0F3A08,
1338 PREFIX_VEX_0F3A09,
1339 PREFIX_VEX_0F3A0A,
1340 PREFIX_VEX_0F3A0B,
1341 PREFIX_VEX_0F3A0C,
1342 PREFIX_VEX_0F3A0D,
1343 PREFIX_VEX_0F3A0E,
1344 PREFIX_VEX_0F3A0F,
1345 PREFIX_VEX_0F3A14,
1346 PREFIX_VEX_0F3A15,
1347 PREFIX_VEX_0F3A16,
1348 PREFIX_VEX_0F3A17,
1349 PREFIX_VEX_0F3A18,
1350 PREFIX_VEX_0F3A19,
1351 PREFIX_VEX_0F3A1D,
1352 PREFIX_VEX_0F3A20,
1353 PREFIX_VEX_0F3A21,
1354 PREFIX_VEX_0F3A22,
1355 PREFIX_VEX_0F3A30,
1356 PREFIX_VEX_0F3A31,
1357 PREFIX_VEX_0F3A32,
1358 PREFIX_VEX_0F3A33,
1359 PREFIX_VEX_0F3A38,
1360 PREFIX_VEX_0F3A39,
1361 PREFIX_VEX_0F3A40,
1362 PREFIX_VEX_0F3A41,
1363 PREFIX_VEX_0F3A42,
1364 PREFIX_VEX_0F3A44,
1365 PREFIX_VEX_0F3A46,
1366 PREFIX_VEX_0F3A48,
1367 PREFIX_VEX_0F3A49,
1368 PREFIX_VEX_0F3A4A,
1369 PREFIX_VEX_0F3A4B,
1370 PREFIX_VEX_0F3A4C,
1371 PREFIX_VEX_0F3A5C,
1372 PREFIX_VEX_0F3A5D,
1373 PREFIX_VEX_0F3A5E,
1374 PREFIX_VEX_0F3A5F,
1375 PREFIX_VEX_0F3A60,
1376 PREFIX_VEX_0F3A61,
1377 PREFIX_VEX_0F3A62,
1378 PREFIX_VEX_0F3A63,
1379 PREFIX_VEX_0F3A68,
1380 PREFIX_VEX_0F3A69,
1381 PREFIX_VEX_0F3A6A,
1382 PREFIX_VEX_0F3A6B,
1383 PREFIX_VEX_0F3A6C,
1384 PREFIX_VEX_0F3A6D,
1385 PREFIX_VEX_0F3A6E,
1386 PREFIX_VEX_0F3A6F,
1387 PREFIX_VEX_0F3A78,
1388 PREFIX_VEX_0F3A79,
1389 PREFIX_VEX_0F3A7A,
1390 PREFIX_VEX_0F3A7B,
1391 PREFIX_VEX_0F3A7C,
1392 PREFIX_VEX_0F3A7D,
1393 PREFIX_VEX_0F3A7E,
1394 PREFIX_VEX_0F3A7F,
1395 PREFIX_VEX_0F3ACE,
1396 PREFIX_VEX_0F3ACF,
1397 PREFIX_VEX_0F3ADF,
1398 PREFIX_VEX_0F3AF0,
1399
1400 PREFIX_EVEX_0F10,
1401 PREFIX_EVEX_0F11,
1402 PREFIX_EVEX_0F12,
1403 PREFIX_EVEX_0F13,
1404 PREFIX_EVEX_0F14,
1405 PREFIX_EVEX_0F15,
1406 PREFIX_EVEX_0F16,
1407 PREFIX_EVEX_0F17,
1408 PREFIX_EVEX_0F28,
1409 PREFIX_EVEX_0F29,
1410 PREFIX_EVEX_0F2A,
1411 PREFIX_EVEX_0F2B,
1412 PREFIX_EVEX_0F2C,
1413 PREFIX_EVEX_0F2D,
1414 PREFIX_EVEX_0F2E,
1415 PREFIX_EVEX_0F2F,
1416 PREFIX_EVEX_0F51,
1417 PREFIX_EVEX_0F54,
1418 PREFIX_EVEX_0F55,
1419 PREFIX_EVEX_0F56,
1420 PREFIX_EVEX_0F57,
1421 PREFIX_EVEX_0F58,
1422 PREFIX_EVEX_0F59,
1423 PREFIX_EVEX_0F5A,
1424 PREFIX_EVEX_0F5B,
1425 PREFIX_EVEX_0F5C,
1426 PREFIX_EVEX_0F5D,
1427 PREFIX_EVEX_0F5E,
1428 PREFIX_EVEX_0F5F,
1429 PREFIX_EVEX_0F60,
1430 PREFIX_EVEX_0F61,
1431 PREFIX_EVEX_0F62,
1432 PREFIX_EVEX_0F63,
1433 PREFIX_EVEX_0F64,
1434 PREFIX_EVEX_0F65,
1435 PREFIX_EVEX_0F66,
1436 PREFIX_EVEX_0F67,
1437 PREFIX_EVEX_0F68,
1438 PREFIX_EVEX_0F69,
1439 PREFIX_EVEX_0F6A,
1440 PREFIX_EVEX_0F6B,
1441 PREFIX_EVEX_0F6C,
1442 PREFIX_EVEX_0F6D,
1443 PREFIX_EVEX_0F6E,
1444 PREFIX_EVEX_0F6F,
1445 PREFIX_EVEX_0F70,
1446 PREFIX_EVEX_0F71_REG_2,
1447 PREFIX_EVEX_0F71_REG_4,
1448 PREFIX_EVEX_0F71_REG_6,
1449 PREFIX_EVEX_0F72_REG_0,
1450 PREFIX_EVEX_0F72_REG_1,
1451 PREFIX_EVEX_0F72_REG_2,
1452 PREFIX_EVEX_0F72_REG_4,
1453 PREFIX_EVEX_0F72_REG_6,
1454 PREFIX_EVEX_0F73_REG_2,
1455 PREFIX_EVEX_0F73_REG_3,
1456 PREFIX_EVEX_0F73_REG_6,
1457 PREFIX_EVEX_0F73_REG_7,
1458 PREFIX_EVEX_0F74,
1459 PREFIX_EVEX_0F75,
1460 PREFIX_EVEX_0F76,
1461 PREFIX_EVEX_0F78,
1462 PREFIX_EVEX_0F79,
1463 PREFIX_EVEX_0F7A,
1464 PREFIX_EVEX_0F7B,
1465 PREFIX_EVEX_0F7E,
1466 PREFIX_EVEX_0F7F,
1467 PREFIX_EVEX_0FC2,
1468 PREFIX_EVEX_0FC4,
1469 PREFIX_EVEX_0FC5,
1470 PREFIX_EVEX_0FC6,
1471 PREFIX_EVEX_0FD1,
1472 PREFIX_EVEX_0FD2,
1473 PREFIX_EVEX_0FD3,
1474 PREFIX_EVEX_0FD4,
1475 PREFIX_EVEX_0FD5,
1476 PREFIX_EVEX_0FD6,
1477 PREFIX_EVEX_0FD8,
1478 PREFIX_EVEX_0FD9,
1479 PREFIX_EVEX_0FDA,
1480 PREFIX_EVEX_0FDB,
1481 PREFIX_EVEX_0FDC,
1482 PREFIX_EVEX_0FDD,
1483 PREFIX_EVEX_0FDE,
1484 PREFIX_EVEX_0FDF,
1485 PREFIX_EVEX_0FE0,
1486 PREFIX_EVEX_0FE1,
1487 PREFIX_EVEX_0FE2,
1488 PREFIX_EVEX_0FE3,
1489 PREFIX_EVEX_0FE4,
1490 PREFIX_EVEX_0FE5,
1491 PREFIX_EVEX_0FE6,
1492 PREFIX_EVEX_0FE7,
1493 PREFIX_EVEX_0FE8,
1494 PREFIX_EVEX_0FE9,
1495 PREFIX_EVEX_0FEA,
1496 PREFIX_EVEX_0FEB,
1497 PREFIX_EVEX_0FEC,
1498 PREFIX_EVEX_0FED,
1499 PREFIX_EVEX_0FEE,
1500 PREFIX_EVEX_0FEF,
1501 PREFIX_EVEX_0FF1,
1502 PREFIX_EVEX_0FF2,
1503 PREFIX_EVEX_0FF3,
1504 PREFIX_EVEX_0FF4,
1505 PREFIX_EVEX_0FF5,
1506 PREFIX_EVEX_0FF6,
1507 PREFIX_EVEX_0FF8,
1508 PREFIX_EVEX_0FF9,
1509 PREFIX_EVEX_0FFA,
1510 PREFIX_EVEX_0FFB,
1511 PREFIX_EVEX_0FFC,
1512 PREFIX_EVEX_0FFD,
1513 PREFIX_EVEX_0FFE,
1514 PREFIX_EVEX_0F3800,
1515 PREFIX_EVEX_0F3804,
1516 PREFIX_EVEX_0F380B,
1517 PREFIX_EVEX_0F380C,
1518 PREFIX_EVEX_0F380D,
1519 PREFIX_EVEX_0F3810,
1520 PREFIX_EVEX_0F3811,
1521 PREFIX_EVEX_0F3812,
1522 PREFIX_EVEX_0F3813,
1523 PREFIX_EVEX_0F3814,
1524 PREFIX_EVEX_0F3815,
1525 PREFIX_EVEX_0F3816,
1526 PREFIX_EVEX_0F3818,
1527 PREFIX_EVEX_0F3819,
1528 PREFIX_EVEX_0F381A,
1529 PREFIX_EVEX_0F381B,
1530 PREFIX_EVEX_0F381C,
1531 PREFIX_EVEX_0F381D,
1532 PREFIX_EVEX_0F381E,
1533 PREFIX_EVEX_0F381F,
1534 PREFIX_EVEX_0F3820,
1535 PREFIX_EVEX_0F3821,
1536 PREFIX_EVEX_0F3822,
1537 PREFIX_EVEX_0F3823,
1538 PREFIX_EVEX_0F3824,
1539 PREFIX_EVEX_0F3825,
1540 PREFIX_EVEX_0F3826,
1541 PREFIX_EVEX_0F3827,
1542 PREFIX_EVEX_0F3828,
1543 PREFIX_EVEX_0F3829,
1544 PREFIX_EVEX_0F382A,
1545 PREFIX_EVEX_0F382B,
1546 PREFIX_EVEX_0F382C,
1547 PREFIX_EVEX_0F382D,
1548 PREFIX_EVEX_0F3830,
1549 PREFIX_EVEX_0F3831,
1550 PREFIX_EVEX_0F3832,
1551 PREFIX_EVEX_0F3833,
1552 PREFIX_EVEX_0F3834,
1553 PREFIX_EVEX_0F3835,
1554 PREFIX_EVEX_0F3836,
1555 PREFIX_EVEX_0F3837,
1556 PREFIX_EVEX_0F3838,
1557 PREFIX_EVEX_0F3839,
1558 PREFIX_EVEX_0F383A,
1559 PREFIX_EVEX_0F383B,
1560 PREFIX_EVEX_0F383C,
1561 PREFIX_EVEX_0F383D,
1562 PREFIX_EVEX_0F383E,
1563 PREFIX_EVEX_0F383F,
1564 PREFIX_EVEX_0F3840,
1565 PREFIX_EVEX_0F3842,
1566 PREFIX_EVEX_0F3843,
1567 PREFIX_EVEX_0F3844,
1568 PREFIX_EVEX_0F3845,
1569 PREFIX_EVEX_0F3846,
1570 PREFIX_EVEX_0F3847,
1571 PREFIX_EVEX_0F384C,
1572 PREFIX_EVEX_0F384D,
1573 PREFIX_EVEX_0F384E,
1574 PREFIX_EVEX_0F384F,
1575 PREFIX_EVEX_0F3852,
1576 PREFIX_EVEX_0F3853,
1577 PREFIX_EVEX_0F3855,
1578 PREFIX_EVEX_0F3858,
1579 PREFIX_EVEX_0F3859,
1580 PREFIX_EVEX_0F385A,
1581 PREFIX_EVEX_0F385B,
1582 PREFIX_EVEX_0F3862,
1583 PREFIX_EVEX_0F3863,
1584 PREFIX_EVEX_0F3864,
1585 PREFIX_EVEX_0F3865,
1586 PREFIX_EVEX_0F3866,
1587 PREFIX_EVEX_0F3870,
1588 PREFIX_EVEX_0F3871,
1589 PREFIX_EVEX_0F3872,
1590 PREFIX_EVEX_0F3873,
1591 PREFIX_EVEX_0F3875,
1592 PREFIX_EVEX_0F3876,
1593 PREFIX_EVEX_0F3877,
1594 PREFIX_EVEX_0F3878,
1595 PREFIX_EVEX_0F3879,
1596 PREFIX_EVEX_0F387A,
1597 PREFIX_EVEX_0F387B,
1598 PREFIX_EVEX_0F387C,
1599 PREFIX_EVEX_0F387D,
1600 PREFIX_EVEX_0F387E,
1601 PREFIX_EVEX_0F387F,
1602 PREFIX_EVEX_0F3883,
1603 PREFIX_EVEX_0F3888,
1604 PREFIX_EVEX_0F3889,
1605 PREFIX_EVEX_0F388A,
1606 PREFIX_EVEX_0F388B,
1607 PREFIX_EVEX_0F388D,
1608 PREFIX_EVEX_0F3890,
1609 PREFIX_EVEX_0F3891,
1610 PREFIX_EVEX_0F3892,
1611 PREFIX_EVEX_0F3893,
1612 PREFIX_EVEX_0F3896,
1613 PREFIX_EVEX_0F3897,
1614 PREFIX_EVEX_0F3898,
1615 PREFIX_EVEX_0F3899,
1616 PREFIX_EVEX_0F389A,
1617 PREFIX_EVEX_0F389B,
1618 PREFIX_EVEX_0F389C,
1619 PREFIX_EVEX_0F389D,
1620 PREFIX_EVEX_0F389E,
1621 PREFIX_EVEX_0F389F,
1622 PREFIX_EVEX_0F38A0,
1623 PREFIX_EVEX_0F38A1,
1624 PREFIX_EVEX_0F38A2,
1625 PREFIX_EVEX_0F38A3,
1626 PREFIX_EVEX_0F38A6,
1627 PREFIX_EVEX_0F38A7,
1628 PREFIX_EVEX_0F38A8,
1629 PREFIX_EVEX_0F38A9,
1630 PREFIX_EVEX_0F38AA,
1631 PREFIX_EVEX_0F38AB,
1632 PREFIX_EVEX_0F38AC,
1633 PREFIX_EVEX_0F38AD,
1634 PREFIX_EVEX_0F38AE,
1635 PREFIX_EVEX_0F38AF,
1636 PREFIX_EVEX_0F38B4,
1637 PREFIX_EVEX_0F38B5,
1638 PREFIX_EVEX_0F38B6,
1639 PREFIX_EVEX_0F38B7,
1640 PREFIX_EVEX_0F38B8,
1641 PREFIX_EVEX_0F38B9,
1642 PREFIX_EVEX_0F38BA,
1643 PREFIX_EVEX_0F38BB,
1644 PREFIX_EVEX_0F38BC,
1645 PREFIX_EVEX_0F38BD,
1646 PREFIX_EVEX_0F38BE,
1647 PREFIX_EVEX_0F38BF,
1648 PREFIX_EVEX_0F38C4,
1649 PREFIX_EVEX_0F38C6_REG_1,
1650 PREFIX_EVEX_0F38C6_REG_2,
1651 PREFIX_EVEX_0F38C6_REG_5,
1652 PREFIX_EVEX_0F38C6_REG_6,
1653 PREFIX_EVEX_0F38C7_REG_1,
1654 PREFIX_EVEX_0F38C7_REG_2,
1655 PREFIX_EVEX_0F38C7_REG_5,
1656 PREFIX_EVEX_0F38C7_REG_6,
1657 PREFIX_EVEX_0F38C8,
1658 PREFIX_EVEX_0F38CA,
1659 PREFIX_EVEX_0F38CB,
1660 PREFIX_EVEX_0F38CC,
1661 PREFIX_EVEX_0F38CD,
1662 PREFIX_EVEX_0F38CF,
1663
1664 PREFIX_EVEX_0F3A00,
1665 PREFIX_EVEX_0F3A01,
1666 PREFIX_EVEX_0F3A03,
1667 PREFIX_EVEX_0F3A04,
1668 PREFIX_EVEX_0F3A05,
1669 PREFIX_EVEX_0F3A08,
1670 PREFIX_EVEX_0F3A09,
1671 PREFIX_EVEX_0F3A0A,
1672 PREFIX_EVEX_0F3A0B,
1673 PREFIX_EVEX_0F3A0F,
1674 PREFIX_EVEX_0F3A14,
1675 PREFIX_EVEX_0F3A15,
1676 PREFIX_EVEX_0F3A16,
1677 PREFIX_EVEX_0F3A17,
1678 PREFIX_EVEX_0F3A18,
1679 PREFIX_EVEX_0F3A19,
1680 PREFIX_EVEX_0F3A1A,
1681 PREFIX_EVEX_0F3A1B,
1682 PREFIX_EVEX_0F3A1D,
1683 PREFIX_EVEX_0F3A1E,
1684 PREFIX_EVEX_0F3A1F,
1685 PREFIX_EVEX_0F3A20,
1686 PREFIX_EVEX_0F3A21,
1687 PREFIX_EVEX_0F3A22,
1688 PREFIX_EVEX_0F3A23,
1689 PREFIX_EVEX_0F3A25,
1690 PREFIX_EVEX_0F3A26,
1691 PREFIX_EVEX_0F3A27,
1692 PREFIX_EVEX_0F3A38,
1693 PREFIX_EVEX_0F3A39,
1694 PREFIX_EVEX_0F3A3A,
1695 PREFIX_EVEX_0F3A3B,
1696 PREFIX_EVEX_0F3A3E,
1697 PREFIX_EVEX_0F3A3F,
1698 PREFIX_EVEX_0F3A42,
1699 PREFIX_EVEX_0F3A43,
1700 PREFIX_EVEX_0F3A50,
1701 PREFIX_EVEX_0F3A51,
1702 PREFIX_EVEX_0F3A54,
1703 PREFIX_EVEX_0F3A55,
1704 PREFIX_EVEX_0F3A56,
1705 PREFIX_EVEX_0F3A57,
1706 PREFIX_EVEX_0F3A66,
1707 PREFIX_EVEX_0F3A67,
1708 PREFIX_EVEX_0F3A70,
1709 PREFIX_EVEX_0F3A71,
1710 PREFIX_EVEX_0F3A72,
1711 PREFIX_EVEX_0F3A73,
1712 PREFIX_EVEX_0F3ACE,
1713 PREFIX_EVEX_0F3ACF
1714};
1715
1716enum
1717{
1718 X86_64_06 = 0,
1719 X86_64_07,
1720 X86_64_0D,
1721 X86_64_16,
1722 X86_64_17,
1723 X86_64_1E,
1724 X86_64_1F,
1725 X86_64_27,
1726 X86_64_2F,
1727 X86_64_37,
1728 X86_64_3F,
1729 X86_64_60,
1730 X86_64_61,
1731 X86_64_62,
1732 X86_64_63,
1733 X86_64_6D,
1734 X86_64_6F,
1735 X86_64_82,
1736 X86_64_9A,
1737 X86_64_C4,
1738 X86_64_C5,
1739 X86_64_CE,
1740 X86_64_D4,
1741 X86_64_D5,
1742 X86_64_E8,
1743 X86_64_E9,
1744 X86_64_EA,
1745 X86_64_0F01_REG_0,
1746 X86_64_0F01_REG_1,
1747 X86_64_0F01_REG_2,
1748 X86_64_0F01_REG_3
1749};
1750
1751enum
1752{
1753 THREE_BYTE_0F38 = 0,
1754 THREE_BYTE_0F3A
1755};
1756
1757enum
1758{
1759 XOP_08 = 0,
1760 XOP_09,
1761 XOP_0A
1762};
1763
1764enum
1765{
1766 VEX_0F = 0,
1767 VEX_0F38,
1768 VEX_0F3A
1769};
1770
1771enum
1772{
1773 EVEX_0F = 0,
1774 EVEX_0F38,
1775 EVEX_0F3A
1776};
1777
1778enum
1779{
1780 VEX_LEN_0F10_P_1 = 0,
1781 VEX_LEN_0F10_P_3,
1782 VEX_LEN_0F11_P_1,
1783 VEX_LEN_0F11_P_3,
1784 VEX_LEN_0F12_P_0_M_0,
1785 VEX_LEN_0F12_P_0_M_1,
1786 VEX_LEN_0F12_P_2,
1787 VEX_LEN_0F13_M_0,
1788 VEX_LEN_0F16_P_0_M_0,
1789 VEX_LEN_0F16_P_0_M_1,
1790 VEX_LEN_0F16_P_2,
1791 VEX_LEN_0F17_M_0,
1792 VEX_LEN_0F2A_P_1,
1793 VEX_LEN_0F2A_P_3,
1794 VEX_LEN_0F2C_P_1,
1795 VEX_LEN_0F2C_P_3,
1796 VEX_LEN_0F2D_P_1,
1797 VEX_LEN_0F2D_P_3,
1798 VEX_LEN_0F2E_P_0,
1799 VEX_LEN_0F2E_P_2,
1800 VEX_LEN_0F2F_P_0,
1801 VEX_LEN_0F2F_P_2,
1802 VEX_LEN_0F41_P_0,
1803 VEX_LEN_0F41_P_2,
1804 VEX_LEN_0F42_P_0,
1805 VEX_LEN_0F42_P_2,
1806 VEX_LEN_0F44_P_0,
1807 VEX_LEN_0F44_P_2,
1808 VEX_LEN_0F45_P_0,
1809 VEX_LEN_0F45_P_2,
1810 VEX_LEN_0F46_P_0,
1811 VEX_LEN_0F46_P_2,
1812 VEX_LEN_0F47_P_0,
1813 VEX_LEN_0F47_P_2,
1814 VEX_LEN_0F4A_P_0,
1815 VEX_LEN_0F4A_P_2,
1816 VEX_LEN_0F4B_P_0,
1817 VEX_LEN_0F4B_P_2,
1818 VEX_LEN_0F51_P_1,
1819 VEX_LEN_0F51_P_3,
1820 VEX_LEN_0F52_P_1,
1821 VEX_LEN_0F53_P_1,
1822 VEX_LEN_0F58_P_1,
1823 VEX_LEN_0F58_P_3,
1824 VEX_LEN_0F59_P_1,
1825 VEX_LEN_0F59_P_3,
1826 VEX_LEN_0F5A_P_1,
1827 VEX_LEN_0F5A_P_3,
1828 VEX_LEN_0F5C_P_1,
1829 VEX_LEN_0F5C_P_3,
1830 VEX_LEN_0F5D_P_1,
1831 VEX_LEN_0F5D_P_3,
1832 VEX_LEN_0F5E_P_1,
1833 VEX_LEN_0F5E_P_3,
1834 VEX_LEN_0F5F_P_1,
1835 VEX_LEN_0F5F_P_3,
1836 VEX_LEN_0F6E_P_2,
1837 VEX_LEN_0F7E_P_1,
1838 VEX_LEN_0F7E_P_2,
1839 VEX_LEN_0F90_P_0,
1840 VEX_LEN_0F90_P_2,
1841 VEX_LEN_0F91_P_0,
1842 VEX_LEN_0F91_P_2,
1843 VEX_LEN_0F92_P_0,
1844 VEX_LEN_0F92_P_2,
1845 VEX_LEN_0F92_P_3,
1846 VEX_LEN_0F93_P_0,
1847 VEX_LEN_0F93_P_2,
1848 VEX_LEN_0F93_P_3,
1849 VEX_LEN_0F98_P_0,
1850 VEX_LEN_0F98_P_2,
1851 VEX_LEN_0F99_P_0,
1852 VEX_LEN_0F99_P_2,
1853 VEX_LEN_0FAE_R_2_M_0,
1854 VEX_LEN_0FAE_R_3_M_0,
1855 VEX_LEN_0FC2_P_1,
1856 VEX_LEN_0FC2_P_3,
1857 VEX_LEN_0FC4_P_2,
1858 VEX_LEN_0FC5_P_2,
1859 VEX_LEN_0FD6_P_2,
1860 VEX_LEN_0FF7_P_2,
1861 VEX_LEN_0F3816_P_2,
1862 VEX_LEN_0F3819_P_2,
1863 VEX_LEN_0F381A_P_2_M_0,
1864 VEX_LEN_0F3836_P_2,
1865 VEX_LEN_0F3841_P_2,
1866 VEX_LEN_0F385A_P_2_M_0,
1867 VEX_LEN_0F38DB_P_2,
1868 VEX_LEN_0F38DC_P_2,
1869 VEX_LEN_0F38DD_P_2,
1870 VEX_LEN_0F38DE_P_2,
1871 VEX_LEN_0F38DF_P_2,
1872 VEX_LEN_0F38F2_P_0,
1873 VEX_LEN_0F38F3_R_1_P_0,
1874 VEX_LEN_0F38F3_R_2_P_0,
1875 VEX_LEN_0F38F3_R_3_P_0,
1876 VEX_LEN_0F38F5_P_0,
1877 VEX_LEN_0F38F5_P_1,
1878 VEX_LEN_0F38F5_P_3,
1879 VEX_LEN_0F38F6_P_3,
1880 VEX_LEN_0F38F7_P_0,
1881 VEX_LEN_0F38F7_P_1,
1882 VEX_LEN_0F38F7_P_2,
1883 VEX_LEN_0F38F7_P_3,
1884 VEX_LEN_0F3A00_P_2,
1885 VEX_LEN_0F3A01_P_2,
1886 VEX_LEN_0F3A06_P_2,
1887 VEX_LEN_0F3A0A_P_2,
1888 VEX_LEN_0F3A0B_P_2,
1889 VEX_LEN_0F3A14_P_2,
1890 VEX_LEN_0F3A15_P_2,
1891 VEX_LEN_0F3A16_P_2,
1892 VEX_LEN_0F3A17_P_2,
1893 VEX_LEN_0F3A18_P_2,
1894 VEX_LEN_0F3A19_P_2,
1895 VEX_LEN_0F3A20_P_2,
1896 VEX_LEN_0F3A21_P_2,
1897 VEX_LEN_0F3A22_P_2,
1898 VEX_LEN_0F3A30_P_2,
1899 VEX_LEN_0F3A31_P_2,
1900 VEX_LEN_0F3A32_P_2,
1901 VEX_LEN_0F3A33_P_2,
1902 VEX_LEN_0F3A38_P_2,
1903 VEX_LEN_0F3A39_P_2,
1904 VEX_LEN_0F3A41_P_2,
1905 VEX_LEN_0F3A44_P_2,
1906 VEX_LEN_0F3A46_P_2,
1907 VEX_LEN_0F3A60_P_2,
1908 VEX_LEN_0F3A61_P_2,
1909 VEX_LEN_0F3A62_P_2,
1910 VEX_LEN_0F3A63_P_2,
1911 VEX_LEN_0F3A6A_P_2,
1912 VEX_LEN_0F3A6B_P_2,
1913 VEX_LEN_0F3A6E_P_2,
1914 VEX_LEN_0F3A6F_P_2,
1915 VEX_LEN_0F3A7A_P_2,
1916 VEX_LEN_0F3A7B_P_2,
1917 VEX_LEN_0F3A7E_P_2,
1918 VEX_LEN_0F3A7F_P_2,
1919 VEX_LEN_0F3ADF_P_2,
1920 VEX_LEN_0F3AF0_P_3,
1921 VEX_LEN_0FXOP_08_CC,
1922 VEX_LEN_0FXOP_08_CD,
1923 VEX_LEN_0FXOP_08_CE,
1924 VEX_LEN_0FXOP_08_CF,
1925 VEX_LEN_0FXOP_08_EC,
1926 VEX_LEN_0FXOP_08_ED,
1927 VEX_LEN_0FXOP_08_EE,
1928 VEX_LEN_0FXOP_08_EF,
1929 VEX_LEN_0FXOP_09_80,
1930 VEX_LEN_0FXOP_09_81
1931};
1932
1933enum
1934{
1935 VEX_W_0F10_P_0 = 0,
1936 VEX_W_0F10_P_1,
1937 VEX_W_0F10_P_2,
1938 VEX_W_0F10_P_3,
1939 VEX_W_0F11_P_0,
1940 VEX_W_0F11_P_1,
1941 VEX_W_0F11_P_2,
1942 VEX_W_0F11_P_3,
1943 VEX_W_0F12_P_0_M_0,
1944 VEX_W_0F12_P_0_M_1,
1945 VEX_W_0F12_P_1,
1946 VEX_W_0F12_P_2,
1947 VEX_W_0F12_P_3,
1948 VEX_W_0F13_M_0,
1949 VEX_W_0F14,
1950 VEX_W_0F15,
1951 VEX_W_0F16_P_0_M_0,
1952 VEX_W_0F16_P_0_M_1,
1953 VEX_W_0F16_P_1,
1954 VEX_W_0F16_P_2,
1955 VEX_W_0F17_M_0,
1956 VEX_W_0F28,
1957 VEX_W_0F29,
1958 VEX_W_0F2B_M_0,
1959 VEX_W_0F2E_P_0,
1960 VEX_W_0F2E_P_2,
1961 VEX_W_0F2F_P_0,
1962 VEX_W_0F2F_P_2,
1963 VEX_W_0F41_P_0_LEN_1,
1964 VEX_W_0F41_P_2_LEN_1,
1965 VEX_W_0F42_P_0_LEN_1,
1966 VEX_W_0F42_P_2_LEN_1,
1967 VEX_W_0F44_P_0_LEN_0,
1968 VEX_W_0F44_P_2_LEN_0,
1969 VEX_W_0F45_P_0_LEN_1,
1970 VEX_W_0F45_P_2_LEN_1,
1971 VEX_W_0F46_P_0_LEN_1,
1972 VEX_W_0F46_P_2_LEN_1,
1973 VEX_W_0F47_P_0_LEN_1,
1974 VEX_W_0F47_P_2_LEN_1,
1975 VEX_W_0F4A_P_0_LEN_1,
1976 VEX_W_0F4A_P_2_LEN_1,
1977 VEX_W_0F4B_P_0_LEN_1,
1978 VEX_W_0F4B_P_2_LEN_1,
1979 VEX_W_0F50_M_0,
1980 VEX_W_0F51_P_0,
1981 VEX_W_0F51_P_1,
1982 VEX_W_0F51_P_2,
1983 VEX_W_0F51_P_3,
1984 VEX_W_0F52_P_0,
1985 VEX_W_0F52_P_1,
1986 VEX_W_0F53_P_0,
1987 VEX_W_0F53_P_1,
1988 VEX_W_0F58_P_0,
1989 VEX_W_0F58_P_1,
1990 VEX_W_0F58_P_2,
1991 VEX_W_0F58_P_3,
1992 VEX_W_0F59_P_0,
1993 VEX_W_0F59_P_1,
1994 VEX_W_0F59_P_2,
1995 VEX_W_0F59_P_3,
1996 VEX_W_0F5A_P_0,
1997 VEX_W_0F5A_P_1,
1998 VEX_W_0F5A_P_3,
1999 VEX_W_0F5B_P_0,
2000 VEX_W_0F5B_P_1,
2001 VEX_W_0F5B_P_2,
2002 VEX_W_0F5C_P_0,
2003 VEX_W_0F5C_P_1,
2004 VEX_W_0F5C_P_2,
2005 VEX_W_0F5C_P_3,
2006 VEX_W_0F5D_P_0,
2007 VEX_W_0F5D_P_1,
2008 VEX_W_0F5D_P_2,
2009 VEX_W_0F5D_P_3,
2010 VEX_W_0F5E_P_0,
2011 VEX_W_0F5E_P_1,
2012 VEX_W_0F5E_P_2,
2013 VEX_W_0F5E_P_3,
2014 VEX_W_0F5F_P_0,
2015 VEX_W_0F5F_P_1,
2016 VEX_W_0F5F_P_2,
2017 VEX_W_0F5F_P_3,
2018 VEX_W_0F60_P_2,
2019 VEX_W_0F61_P_2,
2020 VEX_W_0F62_P_2,
2021 VEX_W_0F63_P_2,
2022 VEX_W_0F64_P_2,
2023 VEX_W_0F65_P_2,
2024 VEX_W_0F66_P_2,
2025 VEX_W_0F67_P_2,
2026 VEX_W_0F68_P_2,
2027 VEX_W_0F69_P_2,
2028 VEX_W_0F6A_P_2,
2029 VEX_W_0F6B_P_2,
2030 VEX_W_0F6C_P_2,
2031 VEX_W_0F6D_P_2,
2032 VEX_W_0F6F_P_1,
2033 VEX_W_0F6F_P_2,
2034 VEX_W_0F70_P_1,
2035 VEX_W_0F70_P_2,
2036 VEX_W_0F70_P_3,
2037 VEX_W_0F71_R_2_P_2,
2038 VEX_W_0F71_R_4_P_2,
2039 VEX_W_0F71_R_6_P_2,
2040 VEX_W_0F72_R_2_P_2,
2041 VEX_W_0F72_R_4_P_2,
2042 VEX_W_0F72_R_6_P_2,
2043 VEX_W_0F73_R_2_P_2,
2044 VEX_W_0F73_R_3_P_2,
2045 VEX_W_0F73_R_6_P_2,
2046 VEX_W_0F73_R_7_P_2,
2047 VEX_W_0F74_P_2,
2048 VEX_W_0F75_P_2,
2049 VEX_W_0F76_P_2,
2050 VEX_W_0F77_P_0,
2051 VEX_W_0F7C_P_2,
2052 VEX_W_0F7C_P_3,
2053 VEX_W_0F7D_P_2,
2054 VEX_W_0F7D_P_3,
2055 VEX_W_0F7E_P_1,
2056 VEX_W_0F7F_P_1,
2057 VEX_W_0F7F_P_2,
2058 VEX_W_0F90_P_0_LEN_0,
2059 VEX_W_0F90_P_2_LEN_0,
2060 VEX_W_0F91_P_0_LEN_0,
2061 VEX_W_0F91_P_2_LEN_0,
2062 VEX_W_0F92_P_0_LEN_0,
2063 VEX_W_0F92_P_2_LEN_0,
2064 VEX_W_0F92_P_3_LEN_0,
2065 VEX_W_0F93_P_0_LEN_0,
2066 VEX_W_0F93_P_2_LEN_0,
2067 VEX_W_0F93_P_3_LEN_0,
2068 VEX_W_0F98_P_0_LEN_0,
2069 VEX_W_0F98_P_2_LEN_0,
2070 VEX_W_0F99_P_0_LEN_0,
2071 VEX_W_0F99_P_2_LEN_0,
2072 VEX_W_0FAE_R_2_M_0,
2073 VEX_W_0FAE_R_3_M_0,
2074 VEX_W_0FC2_P_0,
2075 VEX_W_0FC2_P_1,
2076 VEX_W_0FC2_P_2,
2077 VEX_W_0FC2_P_3,
2078 VEX_W_0FC4_P_2,
2079 VEX_W_0FC5_P_2,
2080 VEX_W_0FD0_P_2,
2081 VEX_W_0FD0_P_3,
2082 VEX_W_0FD1_P_2,
2083 VEX_W_0FD2_P_2,
2084 VEX_W_0FD3_P_2,
2085 VEX_W_0FD4_P_2,
2086 VEX_W_0FD5_P_2,
2087 VEX_W_0FD6_P_2,
2088 VEX_W_0FD7_P_2_M_1,
2089 VEX_W_0FD8_P_2,
2090 VEX_W_0FD9_P_2,
2091 VEX_W_0FDA_P_2,
2092 VEX_W_0FDB_P_2,
2093 VEX_W_0FDC_P_2,
2094 VEX_W_0FDD_P_2,
2095 VEX_W_0FDE_P_2,
2096 VEX_W_0FDF_P_2,
2097 VEX_W_0FE0_P_2,
2098 VEX_W_0FE1_P_2,
2099 VEX_W_0FE2_P_2,
2100 VEX_W_0FE3_P_2,
2101 VEX_W_0FE4_P_2,
2102 VEX_W_0FE5_P_2,
2103 VEX_W_0FE6_P_1,
2104 VEX_W_0FE6_P_2,
2105 VEX_W_0FE6_P_3,
2106 VEX_W_0FE7_P_2_M_0,
2107 VEX_W_0FE8_P_2,
2108 VEX_W_0FE9_P_2,
2109 VEX_W_0FEA_P_2,
2110 VEX_W_0FEB_P_2,
2111 VEX_W_0FEC_P_2,
2112 VEX_W_0FED_P_2,
2113 VEX_W_0FEE_P_2,
2114 VEX_W_0FEF_P_2,
2115 VEX_W_0FF0_P_3_M_0,
2116 VEX_W_0FF1_P_2,
2117 VEX_W_0FF2_P_2,
2118 VEX_W_0FF3_P_2,
2119 VEX_W_0FF4_P_2,
2120 VEX_W_0FF5_P_2,
2121 VEX_W_0FF6_P_2,
2122 VEX_W_0FF7_P_2,
2123 VEX_W_0FF8_P_2,
2124 VEX_W_0FF9_P_2,
2125 VEX_W_0FFA_P_2,
2126 VEX_W_0FFB_P_2,
2127 VEX_W_0FFC_P_2,
2128 VEX_W_0FFD_P_2,
2129 VEX_W_0FFE_P_2,
2130 VEX_W_0F3800_P_2,
2131 VEX_W_0F3801_P_2,
2132 VEX_W_0F3802_P_2,
2133 VEX_W_0F3803_P_2,
2134 VEX_W_0F3804_P_2,
2135 VEX_W_0F3805_P_2,
2136 VEX_W_0F3806_P_2,
2137 VEX_W_0F3807_P_2,
2138 VEX_W_0F3808_P_2,
2139 VEX_W_0F3809_P_2,
2140 VEX_W_0F380A_P_2,
2141 VEX_W_0F380B_P_2,
2142 VEX_W_0F380C_P_2,
2143 VEX_W_0F380D_P_2,
2144 VEX_W_0F380E_P_2,
2145 VEX_W_0F380F_P_2,
2146 VEX_W_0F3816_P_2,
2147 VEX_W_0F3817_P_2,
2148 VEX_W_0F3818_P_2,
2149 VEX_W_0F3819_P_2,
2150 VEX_W_0F381A_P_2_M_0,
2151 VEX_W_0F381C_P_2,
2152 VEX_W_0F381D_P_2,
2153 VEX_W_0F381E_P_2,
2154 VEX_W_0F3820_P_2,
2155 VEX_W_0F3821_P_2,
2156 VEX_W_0F3822_P_2,
2157 VEX_W_0F3823_P_2,
2158 VEX_W_0F3824_P_2,
2159 VEX_W_0F3825_P_2,
2160 VEX_W_0F3828_P_2,
2161 VEX_W_0F3829_P_2,
2162 VEX_W_0F382A_P_2_M_0,
2163 VEX_W_0F382B_P_2,
2164 VEX_W_0F382C_P_2_M_0,
2165 VEX_W_0F382D_P_2_M_0,
2166 VEX_W_0F382E_P_2_M_0,
2167 VEX_W_0F382F_P_2_M_0,
2168 VEX_W_0F3830_P_2,
2169 VEX_W_0F3831_P_2,
2170 VEX_W_0F3832_P_2,
2171 VEX_W_0F3833_P_2,
2172 VEX_W_0F3834_P_2,
2173 VEX_W_0F3835_P_2,
2174 VEX_W_0F3836_P_2,
2175 VEX_W_0F3837_P_2,
2176 VEX_W_0F3838_P_2,
2177 VEX_W_0F3839_P_2,
2178 VEX_W_0F383A_P_2,
2179 VEX_W_0F383B_P_2,
2180 VEX_W_0F383C_P_2,
2181 VEX_W_0F383D_P_2,
2182 VEX_W_0F383E_P_2,
2183 VEX_W_0F383F_P_2,
2184 VEX_W_0F3840_P_2,
2185 VEX_W_0F3841_P_2,
2186 VEX_W_0F3846_P_2,
2187 VEX_W_0F3858_P_2,
2188 VEX_W_0F3859_P_2,
2189 VEX_W_0F385A_P_2_M_0,
2190 VEX_W_0F3878_P_2,
2191 VEX_W_0F3879_P_2,
2192 VEX_W_0F38CF_P_2,
2193 VEX_W_0F38DB_P_2,
2194 VEX_W_0F38DC_P_2,
2195 VEX_W_0F38DD_P_2,
2196 VEX_W_0F38DE_P_2,
2197 VEX_W_0F38DF_P_2,
2198 VEX_W_0F3A00_P_2,
2199 VEX_W_0F3A01_P_2,
2200 VEX_W_0F3A02_P_2,
2201 VEX_W_0F3A04_P_2,
2202 VEX_W_0F3A05_P_2,
2203 VEX_W_0F3A06_P_2,
2204 VEX_W_0F3A08_P_2,
2205 VEX_W_0F3A09_P_2,
2206 VEX_W_0F3A0A_P_2,
2207 VEX_W_0F3A0B_P_2,
2208 VEX_W_0F3A0C_P_2,
2209 VEX_W_0F3A0D_P_2,
2210 VEX_W_0F3A0E_P_2,
2211 VEX_W_0F3A0F_P_2,
2212 VEX_W_0F3A14_P_2,
2213 VEX_W_0F3A15_P_2,
2214 VEX_W_0F3A18_P_2,
2215 VEX_W_0F3A19_P_2,
2216 VEX_W_0F3A20_P_2,
2217 VEX_W_0F3A21_P_2,
2218 VEX_W_0F3A30_P_2_LEN_0,
2219 VEX_W_0F3A31_P_2_LEN_0,
2220 VEX_W_0F3A32_P_2_LEN_0,
2221 VEX_W_0F3A33_P_2_LEN_0,
2222 VEX_W_0F3A38_P_2,
2223 VEX_W_0F3A39_P_2,
2224 VEX_W_0F3A40_P_2,
2225 VEX_W_0F3A41_P_2,
2226 VEX_W_0F3A42_P_2,
2227 VEX_W_0F3A44_P_2,
2228 VEX_W_0F3A46_P_2,
2229 VEX_W_0F3A48_P_2,
2230 VEX_W_0F3A49_P_2,
2231 VEX_W_0F3A4A_P_2,
2232 VEX_W_0F3A4B_P_2,
2233 VEX_W_0F3A4C_P_2,
2234 VEX_W_0F3A62_P_2,
2235 VEX_W_0F3A63_P_2,
2236 VEX_W_0F3ACE_P_2,
2237 VEX_W_0F3ACF_P_2,
2238 VEX_W_0F3ADF_P_2,
2239
2240 EVEX_W_0F10_P_0,
2241 EVEX_W_0F10_P_1_M_0,
2242 EVEX_W_0F10_P_1_M_1,
2243 EVEX_W_0F10_P_2,
2244 EVEX_W_0F10_P_3_M_0,
2245 EVEX_W_0F10_P_3_M_1,
2246 EVEX_W_0F11_P_0,
2247 EVEX_W_0F11_P_1_M_0,
2248 EVEX_W_0F11_P_1_M_1,
2249 EVEX_W_0F11_P_2,
2250 EVEX_W_0F11_P_3_M_0,
2251 EVEX_W_0F11_P_3_M_1,
2252 EVEX_W_0F12_P_0_M_0,
2253 EVEX_W_0F12_P_0_M_1,
2254 EVEX_W_0F12_P_1,
2255 EVEX_W_0F12_P_2,
2256 EVEX_W_0F12_P_3,
2257 EVEX_W_0F13_P_0,
2258 EVEX_W_0F13_P_2,
2259 EVEX_W_0F14_P_0,
2260 EVEX_W_0F14_P_2,
2261 EVEX_W_0F15_P_0,
2262 EVEX_W_0F15_P_2,
2263 EVEX_W_0F16_P_0_M_0,
2264 EVEX_W_0F16_P_0_M_1,
2265 EVEX_W_0F16_P_1,
2266 EVEX_W_0F16_P_2,
2267 EVEX_W_0F17_P_0,
2268 EVEX_W_0F17_P_2,
2269 EVEX_W_0F28_P_0,
2270 EVEX_W_0F28_P_2,
2271 EVEX_W_0F29_P_0,
2272 EVEX_W_0F29_P_2,
2273 EVEX_W_0F2A_P_1,
2274 EVEX_W_0F2A_P_3,
2275 EVEX_W_0F2B_P_0,
2276 EVEX_W_0F2B_P_2,
2277 EVEX_W_0F2E_P_0,
2278 EVEX_W_0F2E_P_2,
2279 EVEX_W_0F2F_P_0,
2280 EVEX_W_0F2F_P_2,
2281 EVEX_W_0F51_P_0,
2282 EVEX_W_0F51_P_1,
2283 EVEX_W_0F51_P_2,
2284 EVEX_W_0F51_P_3,
2285 EVEX_W_0F54_P_0,
2286 EVEX_W_0F54_P_2,
2287 EVEX_W_0F55_P_0,
2288 EVEX_W_0F55_P_2,
2289 EVEX_W_0F56_P_0,
2290 EVEX_W_0F56_P_2,
2291 EVEX_W_0F57_P_0,
2292 EVEX_W_0F57_P_2,
2293 EVEX_W_0F58_P_0,
2294 EVEX_W_0F58_P_1,
2295 EVEX_W_0F58_P_2,
2296 EVEX_W_0F58_P_3,
2297 EVEX_W_0F59_P_0,
2298 EVEX_W_0F59_P_1,
2299 EVEX_W_0F59_P_2,
2300 EVEX_W_0F59_P_3,
2301 EVEX_W_0F5A_P_0,
2302 EVEX_W_0F5A_P_1,
2303 EVEX_W_0F5A_P_2,
2304 EVEX_W_0F5A_P_3,
2305 EVEX_W_0F5B_P_0,
2306 EVEX_W_0F5B_P_1,
2307 EVEX_W_0F5B_P_2,
2308 EVEX_W_0F5C_P_0,
2309 EVEX_W_0F5C_P_1,
2310 EVEX_W_0F5C_P_2,
2311 EVEX_W_0F5C_P_3,
2312 EVEX_W_0F5D_P_0,
2313 EVEX_W_0F5D_P_1,
2314 EVEX_W_0F5D_P_2,
2315 EVEX_W_0F5D_P_3,
2316 EVEX_W_0F5E_P_0,
2317 EVEX_W_0F5E_P_1,
2318 EVEX_W_0F5E_P_2,
2319 EVEX_W_0F5E_P_3,
2320 EVEX_W_0F5F_P_0,
2321 EVEX_W_0F5F_P_1,
2322 EVEX_W_0F5F_P_2,
2323 EVEX_W_0F5F_P_3,
2324 EVEX_W_0F62_P_2,
2325 EVEX_W_0F66_P_2,
2326 EVEX_W_0F6A_P_2,
2327 EVEX_W_0F6B_P_2,
2328 EVEX_W_0F6C_P_2,
2329 EVEX_W_0F6D_P_2,
2330 EVEX_W_0F6E_P_2,
2331 EVEX_W_0F6F_P_1,
2332 EVEX_W_0F6F_P_2,
2333 EVEX_W_0F6F_P_3,
2334 EVEX_W_0F70_P_2,
2335 EVEX_W_0F72_R_2_P_2,
2336 EVEX_W_0F72_R_6_P_2,
2337 EVEX_W_0F73_R_2_P_2,
2338 EVEX_W_0F73_R_6_P_2,
2339 EVEX_W_0F76_P_2,
2340 EVEX_W_0F78_P_0,
2341 EVEX_W_0F78_P_2,
2342 EVEX_W_0F79_P_0,
2343 EVEX_W_0F79_P_2,
2344 EVEX_W_0F7A_P_1,
2345 EVEX_W_0F7A_P_2,
2346 EVEX_W_0F7A_P_3,
2347 EVEX_W_0F7B_P_1,
2348 EVEX_W_0F7B_P_2,
2349 EVEX_W_0F7B_P_3,
2350 EVEX_W_0F7E_P_1,
2351 EVEX_W_0F7E_P_2,
2352 EVEX_W_0F7F_P_1,
2353 EVEX_W_0F7F_P_2,
2354 EVEX_W_0F7F_P_3,
2355 EVEX_W_0FC2_P_0,
2356 EVEX_W_0FC2_P_1,
2357 EVEX_W_0FC2_P_2,
2358 EVEX_W_0FC2_P_3,
2359 EVEX_W_0FC6_P_0,
2360 EVEX_W_0FC6_P_2,
2361 EVEX_W_0FD2_P_2,
2362 EVEX_W_0FD3_P_2,
2363 EVEX_W_0FD4_P_2,
2364 EVEX_W_0FD6_P_2,
2365 EVEX_W_0FE6_P_1,
2366 EVEX_W_0FE6_P_2,
2367 EVEX_W_0FE6_P_3,
2368 EVEX_W_0FE7_P_2,
2369 EVEX_W_0FF2_P_2,
2370 EVEX_W_0FF3_P_2,
2371 EVEX_W_0FF4_P_2,
2372 EVEX_W_0FFA_P_2,
2373 EVEX_W_0FFB_P_2,
2374 EVEX_W_0FFE_P_2,
2375 EVEX_W_0F380C_P_2,
2376 EVEX_W_0F380D_P_2,
2377 EVEX_W_0F3810_P_1,
2378 EVEX_W_0F3810_P_2,
2379 EVEX_W_0F3811_P_1,
2380 EVEX_W_0F3811_P_2,
2381 EVEX_W_0F3812_P_1,
2382 EVEX_W_0F3812_P_2,
2383 EVEX_W_0F3813_P_1,
2384 EVEX_W_0F3813_P_2,
2385 EVEX_W_0F3814_P_1,
2386 EVEX_W_0F3815_P_1,
2387 EVEX_W_0F3818_P_2,
2388 EVEX_W_0F3819_P_2,
2389 EVEX_W_0F381A_P_2,
2390 EVEX_W_0F381B_P_2,
2391 EVEX_W_0F381E_P_2,
2392 EVEX_W_0F381F_P_2,
2393 EVEX_W_0F3820_P_1,
2394 EVEX_W_0F3821_P_1,
2395 EVEX_W_0F3822_P_1,
2396 EVEX_W_0F3823_P_1,
2397 EVEX_W_0F3824_P_1,
2398 EVEX_W_0F3825_P_1,
2399 EVEX_W_0F3825_P_2,
2400 EVEX_W_0F3826_P_1,
2401 EVEX_W_0F3826_P_2,
2402 EVEX_W_0F3828_P_1,
2403 EVEX_W_0F3828_P_2,
2404 EVEX_W_0F3829_P_1,
2405 EVEX_W_0F3829_P_2,
2406 EVEX_W_0F382A_P_1,
2407 EVEX_W_0F382A_P_2,
2408 EVEX_W_0F382B_P_2,
2409 EVEX_W_0F3830_P_1,
2410 EVEX_W_0F3831_P_1,
2411 EVEX_W_0F3832_P_1,
2412 EVEX_W_0F3833_P_1,
2413 EVEX_W_0F3834_P_1,
2414 EVEX_W_0F3835_P_1,
2415 EVEX_W_0F3835_P_2,
2416 EVEX_W_0F3837_P_2,
2417 EVEX_W_0F3838_P_1,
2418 EVEX_W_0F3839_P_1,
2419 EVEX_W_0F383A_P_1,
2420 EVEX_W_0F3840_P_2,
2421 EVEX_W_0F3855_P_2,
2422 EVEX_W_0F3858_P_2,
2423 EVEX_W_0F3859_P_2,
2424 EVEX_W_0F385A_P_2,
2425 EVEX_W_0F385B_P_2,
2426 EVEX_W_0F3862_P_2,
2427 EVEX_W_0F3863_P_2,
2428 EVEX_W_0F3866_P_2,
2429 EVEX_W_0F3870_P_2,
2430 EVEX_W_0F3871_P_2,
2431 EVEX_W_0F3872_P_2,
2432 EVEX_W_0F3873_P_2,
2433 EVEX_W_0F3875_P_2,
2434 EVEX_W_0F3878_P_2,
2435 EVEX_W_0F3879_P_2,
2436 EVEX_W_0F387A_P_2,
2437 EVEX_W_0F387B_P_2,
2438 EVEX_W_0F387D_P_2,
2439 EVEX_W_0F3883_P_2,
2440 EVEX_W_0F388D_P_2,
2441 EVEX_W_0F3891_P_2,
2442 EVEX_W_0F3893_P_2,
2443 EVEX_W_0F38A1_P_2,
2444 EVEX_W_0F38A3_P_2,
2445 EVEX_W_0F38C7_R_1_P_2,
2446 EVEX_W_0F38C7_R_2_P_2,
2447 EVEX_W_0F38C7_R_5_P_2,
2448 EVEX_W_0F38C7_R_6_P_2,
2449
2450 EVEX_W_0F3A00_P_2,
2451 EVEX_W_0F3A01_P_2,
2452 EVEX_W_0F3A04_P_2,
2453 EVEX_W_0F3A05_P_2,
2454 EVEX_W_0F3A08_P_2,
2455 EVEX_W_0F3A09_P_2,
2456 EVEX_W_0F3A0A_P_2,
2457 EVEX_W_0F3A0B_P_2,
2458 EVEX_W_0F3A16_P_2,
2459 EVEX_W_0F3A18_P_2,
2460 EVEX_W_0F3A19_P_2,
2461 EVEX_W_0F3A1A_P_2,
2462 EVEX_W_0F3A1B_P_2,
2463 EVEX_W_0F3A1D_P_2,
2464 EVEX_W_0F3A21_P_2,
2465 EVEX_W_0F3A22_P_2,
2466 EVEX_W_0F3A23_P_2,
2467 EVEX_W_0F3A38_P_2,
2468 EVEX_W_0F3A39_P_2,
2469 EVEX_W_0F3A3A_P_2,
2470 EVEX_W_0F3A3B_P_2,
2471 EVEX_W_0F3A3E_P_2,
2472 EVEX_W_0F3A3F_P_2,
2473 EVEX_W_0F3A42_P_2,
2474 EVEX_W_0F3A43_P_2,
2475 EVEX_W_0F3A50_P_2,
2476 EVEX_W_0F3A51_P_2,
2477 EVEX_W_0F3A56_P_2,
2478 EVEX_W_0F3A57_P_2,
2479 EVEX_W_0F3A66_P_2,
2480 EVEX_W_0F3A67_P_2,
2481 EVEX_W_0F3A70_P_2,
2482 EVEX_W_0F3A71_P_2,
2483 EVEX_W_0F3A72_P_2,
2484 EVEX_W_0F3A73_P_2,
2485 EVEX_W_0F3ACE_P_2,
2486 EVEX_W_0F3ACF_P_2
2487};
2488
2489typedef void (*op_rtn) (int bytemode, int sizeflag);
2490
2491struct dis386 {
2492 const char *name;
2493 struct
2494 {
2495 op_rtn rtn;
2496 int bytemode;
2497 } op[MAX_OPERANDS];
2498 unsigned int prefix_requirement;
2499};
2500
2501/* Upper case letters in the instruction names here are macros.
2502 'A' => print 'b' if no register operands or suffix_always is true
2503 'B' => print 'b' if suffix_always is true
2504 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2505 size prefix
2506 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2507 suffix_always is true
2508 'E' => print 'e' if 32-bit form of jcxz
2509 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2510 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2511 'H' => print ",pt" or ",pn" branch hint
2512 'I' => honor following macro letter even in Intel mode (implemented only
2513 for some of the macro letters)
2514 'J' => print 'l'
2515 'K' => print 'd' or 'q' if rex prefix is present.
2516 'L' => print 'l' if suffix_always is true
2517 'M' => print 'r' if intel_mnemonic is false.
2518 'N' => print 'n' if instruction has no wait "prefix"
2519 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2520 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2521 or suffix_always is true. print 'q' if rex prefix is present.
2522 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2523 is true
2524 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2525 'S' => print 'w', 'l' or 'q' if suffix_always is true
2526 'T' => print 'q' in 64bit mode if instruction has no operand size
2527 prefix and behave as 'P' otherwise
2528 'U' => print 'q' in 64bit mode if instruction has no operand size
2529 prefix and behave as 'Q' otherwise
2530 'V' => print 'q' in 64bit mode if instruction has no operand size
2531 prefix and behave as 'S' otherwise
2532 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2533 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2534 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2535 suffix_always is true.
2536 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2537 '!' => change condition from true to false or from false to true.
2538 '%' => add 1 upper case letter to the macro.
2539 '^' => print 'w' or 'l' depending on operand size prefix or
2540 suffix_always is true (lcall/ljmp).
2541 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2542 on operand size prefix.
2543 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2544 has no operand size prefix for AMD64 ISA, behave as 'P'
2545 otherwise
2546
2547 2 upper case letter macros:
2548 "XY" => print 'x' or 'y' if suffix_always is true or no register
2549 operands and no broadcast.
2550 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2551 register operands and no broadcast.
2552 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2553 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2554 or suffix_always is true
2555 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2556 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2557 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2558 "LW" => print 'd', 'q' depending on the VEX.W bit
2559 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2560 an operand size prefix, or suffix_always is true. print
2561 'q' if rex prefix is present.
2562
2563 Many of the above letters print nothing in Intel mode. See "putop"
2564 for the details.
2565
2566 Braces '{' and '}', and vertical bars '|', indicate alternative
2567 mnemonic strings for AT&T and Intel. */
2568
2569static const struct dis386 dis386[] = {
2570 /* 00 */
2571 { "addB", { Ebh1, Gb }, 0 },
2572 { "addS", { Evh1, Gv }, 0 },
2573 { "addB", { Gb, EbS }, 0 },
2574 { "addS", { Gv, EvS }, 0 },
2575 { "addB", { AL, Ib }, 0 },
2576 { "addS", { eAX, Iv }, 0 },
2577 { X86_64_TABLE (X86_64_06) },
2578 { X86_64_TABLE (X86_64_07) },
2579 /* 08 */
2580 { "orB", { Ebh1, Gb }, 0 },
2581 { "orS", { Evh1, Gv }, 0 },
2582 { "orB", { Gb, EbS }, 0 },
2583 { "orS", { Gv, EvS }, 0 },
2584 { "orB", { AL, Ib }, 0 },
2585 { "orS", { eAX, Iv }, 0 },
2586 { X86_64_TABLE (X86_64_0D) },
2587 { Bad_Opcode }, /* 0x0f extended opcode escape */
2588 /* 10 */
2589 { "adcB", { Ebh1, Gb }, 0 },
2590 { "adcS", { Evh1, Gv }, 0 },
2591 { "adcB", { Gb, EbS }, 0 },
2592 { "adcS", { Gv, EvS }, 0 },
2593 { "adcB", { AL, Ib }, 0 },
2594 { "adcS", { eAX, Iv }, 0 },
2595 { X86_64_TABLE (X86_64_16) },
2596 { X86_64_TABLE (X86_64_17) },
2597 /* 18 */
2598 { "sbbB", { Ebh1, Gb }, 0 },
2599 { "sbbS", { Evh1, Gv }, 0 },
2600 { "sbbB", { Gb, EbS }, 0 },
2601 { "sbbS", { Gv, EvS }, 0 },
2602 { "sbbB", { AL, Ib }, 0 },
2603 { "sbbS", { eAX, Iv }, 0 },
2604 { X86_64_TABLE (X86_64_1E) },
2605 { X86_64_TABLE (X86_64_1F) },
2606 /* 20 */
2607 { "andB", { Ebh1, Gb }, 0 },
2608 { "andS", { Evh1, Gv }, 0 },
2609 { "andB", { Gb, EbS }, 0 },
2610 { "andS", { Gv, EvS }, 0 },
2611 { "andB", { AL, Ib }, 0 },
2612 { "andS", { eAX, Iv }, 0 },
2613 { Bad_Opcode }, /* SEG ES prefix */
2614 { X86_64_TABLE (X86_64_27) },
2615 /* 28 */
2616 { "subB", { Ebh1, Gb }, 0 },
2617 { "subS", { Evh1, Gv }, 0 },
2618 { "subB", { Gb, EbS }, 0 },
2619 { "subS", { Gv, EvS }, 0 },
2620 { "subB", { AL, Ib }, 0 },
2621 { "subS", { eAX, Iv }, 0 },
2622 { Bad_Opcode }, /* SEG CS prefix */
2623 { X86_64_TABLE (X86_64_2F) },
2624 /* 30 */
2625 { "xorB", { Ebh1, Gb }, 0 },
2626 { "xorS", { Evh1, Gv }, 0 },
2627 { "xorB", { Gb, EbS }, 0 },
2628 { "xorS", { Gv, EvS }, 0 },
2629 { "xorB", { AL, Ib }, 0 },
2630 { "xorS", { eAX, Iv }, 0 },
2631 { Bad_Opcode }, /* SEG SS prefix */
2632 { X86_64_TABLE (X86_64_37) },
2633 /* 38 */
2634 { "cmpB", { Eb, Gb }, 0 },
2635 { "cmpS", { Ev, Gv }, 0 },
2636 { "cmpB", { Gb, EbS }, 0 },
2637 { "cmpS", { Gv, EvS }, 0 },
2638 { "cmpB", { AL, Ib }, 0 },
2639 { "cmpS", { eAX, Iv }, 0 },
2640 { Bad_Opcode }, /* SEG DS prefix */
2641 { X86_64_TABLE (X86_64_3F) },
2642 /* 40 */
2643 { "inc{S|}", { RMeAX }, 0 },
2644 { "inc{S|}", { RMeCX }, 0 },
2645 { "inc{S|}", { RMeDX }, 0 },
2646 { "inc{S|}", { RMeBX }, 0 },
2647 { "inc{S|}", { RMeSP }, 0 },
2648 { "inc{S|}", { RMeBP }, 0 },
2649 { "inc{S|}", { RMeSI }, 0 },
2650 { "inc{S|}", { RMeDI }, 0 },
2651 /* 48 */
2652 { "dec{S|}", { RMeAX }, 0 },
2653 { "dec{S|}", { RMeCX }, 0 },
2654 { "dec{S|}", { RMeDX }, 0 },
2655 { "dec{S|}", { RMeBX }, 0 },
2656 { "dec{S|}", { RMeSP }, 0 },
2657 { "dec{S|}", { RMeBP }, 0 },
2658 { "dec{S|}", { RMeSI }, 0 },
2659 { "dec{S|}", { RMeDI }, 0 },
2660 /* 50 */
2661 { "pushV", { RMrAX }, 0 },
2662 { "pushV", { RMrCX }, 0 },
2663 { "pushV", { RMrDX }, 0 },
2664 { "pushV", { RMrBX }, 0 },
2665 { "pushV", { RMrSP }, 0 },
2666 { "pushV", { RMrBP }, 0 },
2667 { "pushV", { RMrSI }, 0 },
2668 { "pushV", { RMrDI }, 0 },
2669 /* 58 */
2670 { "popV", { RMrAX }, 0 },
2671 { "popV", { RMrCX }, 0 },
2672 { "popV", { RMrDX }, 0 },
2673 { "popV", { RMrBX }, 0 },
2674 { "popV", { RMrSP }, 0 },
2675 { "popV", { RMrBP }, 0 },
2676 { "popV", { RMrSI }, 0 },
2677 { "popV", { RMrDI }, 0 },
2678 /* 60 */
2679 { X86_64_TABLE (X86_64_60) },
2680 { X86_64_TABLE (X86_64_61) },
2681 { X86_64_TABLE (X86_64_62) },
2682 { X86_64_TABLE (X86_64_63) },
2683 { Bad_Opcode }, /* seg fs */
2684 { Bad_Opcode }, /* seg gs */
2685 { Bad_Opcode }, /* op size prefix */
2686 { Bad_Opcode }, /* adr size prefix */
2687 /* 68 */
2688 { "pushT", { sIv }, 0 },
2689 { "imulS", { Gv, Ev, Iv }, 0 },
2690 { "pushT", { sIbT }, 0 },
2691 { "imulS", { Gv, Ev, sIb }, 0 },
2692 { "ins{b|}", { Ybr, indirDX }, 0 },
2693 { X86_64_TABLE (X86_64_6D) },
2694 { "outs{b|}", { indirDXr, Xb }, 0 },
2695 { X86_64_TABLE (X86_64_6F) },
2696 /* 70 */
2697 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2698 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2699 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2700 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2701 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2702 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2703 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2704 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2705 /* 78 */
2706 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2707 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2708 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2709 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2710 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2711 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2712 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2713 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2714 /* 80 */
2715 { REG_TABLE (REG_80) },
2716 { REG_TABLE (REG_81) },
2717 { X86_64_TABLE (X86_64_82) },
2718 { REG_TABLE (REG_83) },
2719 { "testB", { Eb, Gb }, 0 },
2720 { "testS", { Ev, Gv }, 0 },
2721 { "xchgB", { Ebh2, Gb }, 0 },
2722 { "xchgS", { Evh2, Gv }, 0 },
2723 /* 88 */
2724 { "movB", { Ebh3, Gb }, 0 },
2725 { "movS", { Evh3, Gv }, 0 },
2726 { "movB", { Gb, EbS }, 0 },
2727 { "movS", { Gv, EvS }, 0 },
2728 { "movD", { Sv, Sw }, 0 },
2729 { MOD_TABLE (MOD_8D) },
2730 { "movD", { Sw, Sv }, 0 },
2731 { REG_TABLE (REG_8F) },
2732 /* 90 */
2733 { PREFIX_TABLE (PREFIX_90) },
2734 { "xchgS", { RMeCX, eAX }, 0 },
2735 { "xchgS", { RMeDX, eAX }, 0 },
2736 { "xchgS", { RMeBX, eAX }, 0 },
2737 { "xchgS", { RMeSP, eAX }, 0 },
2738 { "xchgS", { RMeBP, eAX }, 0 },
2739 { "xchgS", { RMeSI, eAX }, 0 },
2740 { "xchgS", { RMeDI, eAX }, 0 },
2741 /* 98 */
2742 { "cW{t|}R", { XX }, 0 },
2743 { "cR{t|}O", { XX }, 0 },
2744 { X86_64_TABLE (X86_64_9A) },
2745 { Bad_Opcode }, /* fwait */
2746 { "pushfT", { XX }, 0 },
2747 { "popfT", { XX }, 0 },
2748 { "sahf", { XX }, 0 },
2749 { "lahf", { XX }, 0 },
2750 /* a0 */
2751 { "mov%LB", { AL, Ob }, 0 },
2752 { "mov%LS", { eAX, Ov }, 0 },
2753 { "mov%LB", { Ob, AL }, 0 },
2754 { "mov%LS", { Ov, eAX }, 0 },
2755 { "movs{b|}", { Ybr, Xb }, 0 },
2756 { "movs{R|}", { Yvr, Xv }, 0 },
2757 { "cmps{b|}", { Xb, Yb }, 0 },
2758 { "cmps{R|}", { Xv, Yv }, 0 },
2759 /* a8 */
2760 { "testB", { AL, Ib }, 0 },
2761 { "testS", { eAX, Iv }, 0 },
2762 { "stosB", { Ybr, AL }, 0 },
2763 { "stosS", { Yvr, eAX }, 0 },
2764 { "lodsB", { ALr, Xb }, 0 },
2765 { "lodsS", { eAXr, Xv }, 0 },
2766 { "scasB", { AL, Yb }, 0 },
2767 { "scasS", { eAX, Yv }, 0 },
2768 /* b0 */
2769 { "movB", { RMAL, Ib }, 0 },
2770 { "movB", { RMCL, Ib }, 0 },
2771 { "movB", { RMDL, Ib }, 0 },
2772 { "movB", { RMBL, Ib }, 0 },
2773 { "movB", { RMAH, Ib }, 0 },
2774 { "movB", { RMCH, Ib }, 0 },
2775 { "movB", { RMDH, Ib }, 0 },
2776 { "movB", { RMBH, Ib }, 0 },
2777 /* b8 */
2778 { "mov%LV", { RMeAX, Iv64 }, 0 },
2779 { "mov%LV", { RMeCX, Iv64 }, 0 },
2780 { "mov%LV", { RMeDX, Iv64 }, 0 },
2781 { "mov%LV", { RMeBX, Iv64 }, 0 },
2782 { "mov%LV", { RMeSP, Iv64 }, 0 },
2783 { "mov%LV", { RMeBP, Iv64 }, 0 },
2784 { "mov%LV", { RMeSI, Iv64 }, 0 },
2785 { "mov%LV", { RMeDI, Iv64 }, 0 },
2786 /* c0 */
2787 { REG_TABLE (REG_C0) },
2788 { REG_TABLE (REG_C1) },
2789 { "retT", { Iw, BND }, 0 },
2790 { "retT", { BND }, 0 },
2791 { X86_64_TABLE (X86_64_C4) },
2792 { X86_64_TABLE (X86_64_C5) },
2793 { REG_TABLE (REG_C6) },
2794 { REG_TABLE (REG_C7) },
2795 /* c8 */
2796 { "enterT", { Iw, Ib }, 0 },
2797 { "leaveT", { XX }, 0 },
2798 { "Jret{|f}P", { Iw }, 0 },
2799 { "Jret{|f}P", { XX }, 0 },
2800 { "int3", { XX }, 0 },
2801 { "int", { Ib }, 0 },
2802 { X86_64_TABLE (X86_64_CE) },
2803 { "iret%LP", { XX }, 0 },
2804 /* d0 */
2805 { REG_TABLE (REG_D0) },
2806 { REG_TABLE (REG_D1) },
2807 { REG_TABLE (REG_D2) },
2808 { REG_TABLE (REG_D3) },
2809 { X86_64_TABLE (X86_64_D4) },
2810 { X86_64_TABLE (X86_64_D5) },
2811 { Bad_Opcode },
2812 { "xlat", { DSBX }, 0 },
2813 /* d8 */
2814 { FLOAT },
2815 { FLOAT },
2816 { FLOAT },
2817 { FLOAT },
2818 { FLOAT },
2819 { FLOAT },
2820 { FLOAT },
2821 { FLOAT },
2822 /* e0 */
2823 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2824 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2825 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2826 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2827 { "inB", { AL, Ib }, 0 },
2828 { "inG", { zAX, Ib }, 0 },
2829 { "outB", { Ib, AL }, 0 },
2830 { "outG", { Ib, zAX }, 0 },
2831 /* e8 */
2832 { X86_64_TABLE (X86_64_E8) },
2833 { X86_64_TABLE (X86_64_E9) },
2834 { X86_64_TABLE (X86_64_EA) },
2835 { "jmp", { Jb, BND }, 0 },
2836 { "inB", { AL, indirDX }, 0 },
2837 { "inG", { zAX, indirDX }, 0 },
2838 { "outB", { indirDX, AL }, 0 },
2839 { "outG", { indirDX, zAX }, 0 },
2840 /* f0 */
2841 { Bad_Opcode }, /* lock prefix */
2842 { "icebp", { XX }, 0 },
2843 { Bad_Opcode }, /* repne */
2844 { Bad_Opcode }, /* repz */
2845 { "hlt", { XX }, 0 },
2846 { "cmc", { XX }, 0 },
2847 { REG_TABLE (REG_F6) },
2848 { REG_TABLE (REG_F7) },
2849 /* f8 */
2850 { "clc", { XX }, 0 },
2851 { "stc", { XX }, 0 },
2852 { "cli", { XX }, 0 },
2853 { "sti", { XX }, 0 },
2854 { "cld", { XX }, 0 },
2855 { "std", { XX }, 0 },
2856 { REG_TABLE (REG_FE) },
2857 { REG_TABLE (REG_FF) },
2858};
2859
2860static const struct dis386 dis386_twobyte[] = {
2861 /* 00 */
2862 { REG_TABLE (REG_0F00 ) },
2863 { REG_TABLE (REG_0F01 ) },
2864 { "larS", { Gv, Ew }, 0 },
2865 { "lslS", { Gv, Ew }, 0 },
2866 { Bad_Opcode },
2867 { "syscall", { XX }, 0 },
2868 { "clts", { XX }, 0 },
2869 { "sysret%LP", { XX }, 0 },
2870 /* 08 */
2871 { "invd", { XX }, 0 },
2872 { "wbinvd", { XX }, 0 },
2873 { Bad_Opcode },
2874 { "ud2", { XX }, 0 },
2875 { Bad_Opcode },
2876 { REG_TABLE (REG_0F0D) },
2877 { "femms", { XX }, 0 },
2878 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2879 /* 10 */
2880 { PREFIX_TABLE (PREFIX_0F10) },
2881 { PREFIX_TABLE (PREFIX_0F11) },
2882 { PREFIX_TABLE (PREFIX_0F12) },
2883 { MOD_TABLE (MOD_0F13) },
2884 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2885 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2886 { PREFIX_TABLE (PREFIX_0F16) },
2887 { MOD_TABLE (MOD_0F17) },
2888 /* 18 */
2889 { REG_TABLE (REG_0F18) },
2890 { "nopQ", { Ev }, 0 },
2891 { PREFIX_TABLE (PREFIX_0F1A) },
2892 { PREFIX_TABLE (PREFIX_0F1B) },
2893 { "nopQ", { Ev }, 0 },
2894 { "nopQ", { Ev }, 0 },
2895 { PREFIX_TABLE (PREFIX_0F1E) },
2896 { "nopQ", { Ev }, 0 },
2897 /* 20 */
2898 { "movZ", { Rm, Cm }, 0 },
2899 { "movZ", { Rm, Dm }, 0 },
2900 { "movZ", { Cm, Rm }, 0 },
2901 { "movZ", { Dm, Rm }, 0 },
2902 { MOD_TABLE (MOD_0F24) },
2903 { Bad_Opcode },
2904 { MOD_TABLE (MOD_0F26) },
2905 { Bad_Opcode },
2906 /* 28 */
2907 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2908 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2909 { PREFIX_TABLE (PREFIX_0F2A) },
2910 { PREFIX_TABLE (PREFIX_0F2B) },
2911 { PREFIX_TABLE (PREFIX_0F2C) },
2912 { PREFIX_TABLE (PREFIX_0F2D) },
2913 { PREFIX_TABLE (PREFIX_0F2E) },
2914 { PREFIX_TABLE (PREFIX_0F2F) },
2915 /* 30 */
2916 { "wrmsr", { XX }, 0 },
2917 { "rdtsc", { XX }, 0 },
2918 { "rdmsr", { XX }, 0 },
2919 { "rdpmc", { XX }, 0 },
2920 { "sysenter", { XX }, 0 },
2921 { "sysexit", { XX }, 0 },
2922 { Bad_Opcode },
2923 { "getsec", { XX }, 0 },
2924 /* 38 */
2925 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2926 { Bad_Opcode },
2927 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2928 { Bad_Opcode },
2929 { Bad_Opcode },
2930 { Bad_Opcode },
2931 { Bad_Opcode },
2932 { Bad_Opcode },
2933 /* 40 */
2934 { "cmovoS", { Gv, Ev }, 0 },
2935 { "cmovnoS", { Gv, Ev }, 0 },
2936 { "cmovbS", { Gv, Ev }, 0 },
2937 { "cmovaeS", { Gv, Ev }, 0 },
2938 { "cmoveS", { Gv, Ev }, 0 },
2939 { "cmovneS", { Gv, Ev }, 0 },
2940 { "cmovbeS", { Gv, Ev }, 0 },
2941 { "cmovaS", { Gv, Ev }, 0 },
2942 /* 48 */
2943 { "cmovsS", { Gv, Ev }, 0 },
2944 { "cmovnsS", { Gv, Ev }, 0 },
2945 { "cmovpS", { Gv, Ev }, 0 },
2946 { "cmovnpS", { Gv, Ev }, 0 },
2947 { "cmovlS", { Gv, Ev }, 0 },
2948 { "cmovgeS", { Gv, Ev }, 0 },
2949 { "cmovleS", { Gv, Ev }, 0 },
2950 { "cmovgS", { Gv, Ev }, 0 },
2951 /* 50 */
2952 { MOD_TABLE (MOD_0F51) },
2953 { PREFIX_TABLE (PREFIX_0F51) },
2954 { PREFIX_TABLE (PREFIX_0F52) },
2955 { PREFIX_TABLE (PREFIX_0F53) },
2956 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2957 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2958 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2959 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2960 /* 58 */
2961 { PREFIX_TABLE (PREFIX_0F58) },
2962 { PREFIX_TABLE (PREFIX_0F59) },
2963 { PREFIX_TABLE (PREFIX_0F5A) },
2964 { PREFIX_TABLE (PREFIX_0F5B) },
2965 { PREFIX_TABLE (PREFIX_0F5C) },
2966 { PREFIX_TABLE (PREFIX_0F5D) },
2967 { PREFIX_TABLE (PREFIX_0F5E) },
2968 { PREFIX_TABLE (PREFIX_0F5F) },
2969 /* 60 */
2970 { PREFIX_TABLE (PREFIX_0F60) },
2971 { PREFIX_TABLE (PREFIX_0F61) },
2972 { PREFIX_TABLE (PREFIX_0F62) },
2973 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2974 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2975 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2976 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2977 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2978 /* 68 */
2979 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2980 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2981 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2982 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2983 { PREFIX_TABLE (PREFIX_0F6C) },
2984 { PREFIX_TABLE (PREFIX_0F6D) },
2985 { "movK", { MX, Edq }, PREFIX_OPCODE },
2986 { PREFIX_TABLE (PREFIX_0F6F) },
2987 /* 70 */
2988 { PREFIX_TABLE (PREFIX_0F70) },
2989 { REG_TABLE (REG_0F71) },
2990 { REG_TABLE (REG_0F72) },
2991 { REG_TABLE (REG_0F73) },
2992 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2993 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2994 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2995 { "emms", { XX }, PREFIX_OPCODE },
2996 /* 78 */
2997 { PREFIX_TABLE (PREFIX_0F78) },
2998 { PREFIX_TABLE (PREFIX_0F79) },
2999 { Bad_Opcode },
3000 { Bad_Opcode },
3001 { PREFIX_TABLE (PREFIX_0F7C) },
3002 { PREFIX_TABLE (PREFIX_0F7D) },
3003 { PREFIX_TABLE (PREFIX_0F7E) },
3004 { PREFIX_TABLE (PREFIX_0F7F) },
3005 /* 80 */
3006 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3007 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3008 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3009 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3010 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3011 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3012 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3013 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3014 /* 88 */
3015 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3016 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3017 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3018 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3019 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3020 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3021 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3022 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3023 /* 90 */
3024 { "seto", { Eb }, 0 },
3025 { "setno", { Eb }, 0 },
3026 { "setb", { Eb }, 0 },
3027 { "setae", { Eb }, 0 },
3028 { "sete", { Eb }, 0 },
3029 { "setne", { Eb }, 0 },
3030 { "setbe", { Eb }, 0 },
3031 { "seta", { Eb }, 0 },
3032 /* 98 */
3033 { "sets", { Eb }, 0 },
3034 { "setns", { Eb }, 0 },
3035 { "setp", { Eb }, 0 },
3036 { "setnp", { Eb }, 0 },
3037 { "setl", { Eb }, 0 },
3038 { "setge", { Eb }, 0 },
3039 { "setle", { Eb }, 0 },
3040 { "setg", { Eb }, 0 },
3041 /* a0 */
3042 { "pushT", { fs }, 0 },
3043 { "popT", { fs }, 0 },
3044 { "cpuid", { XX }, 0 },
3045 { "btS", { Ev, Gv }, 0 },
3046 { "shldS", { Ev, Gv, Ib }, 0 },
3047 { "shldS", { Ev, Gv, CL }, 0 },
3048 { REG_TABLE (REG_0FA6) },
3049 { REG_TABLE (REG_0FA7) },
3050 /* a8 */
3051 { "pushT", { gs }, 0 },
3052 { "popT", { gs }, 0 },
3053 { "rsm", { XX }, 0 },
3054 { "btsS", { Evh1, Gv }, 0 },
3055 { "shrdS", { Ev, Gv, Ib }, 0 },
3056 { "shrdS", { Ev, Gv, CL }, 0 },
3057 { REG_TABLE (REG_0FAE) },
3058 { "imulS", { Gv, Ev }, 0 },
3059 /* b0 */
3060 { "cmpxchgB", { Ebh1, Gb }, 0 },
3061 { "cmpxchgS", { Evh1, Gv }, 0 },
3062 { MOD_TABLE (MOD_0FB2) },
3063 { "btrS", { Evh1, Gv }, 0 },
3064 { MOD_TABLE (MOD_0FB4) },
3065 { MOD_TABLE (MOD_0FB5) },
3066 { "movz{bR|x}", { Gv, Eb }, 0 },
3067 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3068 /* b8 */
3069 { PREFIX_TABLE (PREFIX_0FB8) },
3070 { "ud1", { XX }, 0 },
3071 { REG_TABLE (REG_0FBA) },
3072 { "btcS", { Evh1, Gv }, 0 },
3073 { PREFIX_TABLE (PREFIX_0FBC) },
3074 { PREFIX_TABLE (PREFIX_0FBD) },
3075 { "movs{bR|x}", { Gv, Eb }, 0 },
3076 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3077 /* c0 */
3078 { "xaddB", { Ebh1, Gb }, 0 },
3079 { "xaddS", { Evh1, Gv }, 0 },
3080 { PREFIX_TABLE (PREFIX_0FC2) },
3081 { MOD_TABLE (MOD_0FC3) },
3082 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3083 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3084 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3085 { REG_TABLE (REG_0FC7) },
3086 /* c8 */
3087 { "bswap", { RMeAX }, 0 },
3088 { "bswap", { RMeCX }, 0 },
3089 { "bswap", { RMeDX }, 0 },
3090 { "bswap", { RMeBX }, 0 },
3091 { "bswap", { RMeSP }, 0 },
3092 { "bswap", { RMeBP }, 0 },
3093 { "bswap", { RMeSI }, 0 },
3094 { "bswap", { RMeDI }, 0 },
3095 /* d0 */
3096 { PREFIX_TABLE (PREFIX_0FD0) },
3097 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3098 { "psrld", { MX, EM }, PREFIX_OPCODE },
3099 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3100 { "paddq", { MX, EM }, PREFIX_OPCODE },
3101 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3102 { PREFIX_TABLE (PREFIX_0FD6) },
3103 { MOD_TABLE (MOD_0FD7) },
3104 /* d8 */
3105 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3106 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3107 { "pminub", { MX, EM }, PREFIX_OPCODE },
3108 { "pand", { MX, EM }, PREFIX_OPCODE },
3109 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3110 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3111 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3112 { "pandn", { MX, EM }, PREFIX_OPCODE },
3113 /* e0 */
3114 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3115 { "psraw", { MX, EM }, PREFIX_OPCODE },
3116 { "psrad", { MX, EM }, PREFIX_OPCODE },
3117 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3118 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3119 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3120 { PREFIX_TABLE (PREFIX_0FE6) },
3121 { PREFIX_TABLE (PREFIX_0FE7) },
3122 /* e8 */
3123 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3124 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3125 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3126 { "por", { MX, EM }, PREFIX_OPCODE },
3127 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3128 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3129 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3130 { "pxor", { MX, EM }, PREFIX_OPCODE },
3131 /* f0 */
3132 { PREFIX_TABLE (PREFIX_0FF0) },
3133 { "psllw", { MX, EM }, PREFIX_OPCODE },
3134 { "pslld", { MX, EM }, PREFIX_OPCODE },
3135 { "psllq", { MX, EM }, PREFIX_OPCODE },
3136 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3137 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3138 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3139 { PREFIX_TABLE (PREFIX_0FF7) },
3140 /* f8 */
3141 { "psubb", { MX, EM }, PREFIX_OPCODE },
3142 { "psubw", { MX, EM }, PREFIX_OPCODE },
3143 { "psubd", { MX, EM }, PREFIX_OPCODE },
3144 { "psubq", { MX, EM }, PREFIX_OPCODE },
3145 { "paddb", { MX, EM }, PREFIX_OPCODE },
3146 { "paddw", { MX, EM }, PREFIX_OPCODE },
3147 { "paddd", { MX, EM }, PREFIX_OPCODE },
3148 { Bad_Opcode },
3149};
3150
3151static const unsigned char onebyte_has_modrm[256] = {
3152 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3153 /* ------------------------------- */
3154 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3155 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3156 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3157 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3158 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3159 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3160 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3161 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3162 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3163 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3164 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3165 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3166 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3167 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3168 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3169 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3170 /* ------------------------------- */
3171 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3172};
3173
3174static const unsigned char twobyte_has_modrm[256] = {
3175 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3176 /* ------------------------------- */
3177 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3178 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3179 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3180 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3181 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3182 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3183 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3184 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3185 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3186 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3187 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3188 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3189 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3190 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3191 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3192 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3193 /* ------------------------------- */
3194 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3195};
3196
3197static char obuf[100];
3198static char *obufp;
3199static char *mnemonicendp;
3200static char scratchbuf[100];
3201static unsigned char *start_codep;
3202static unsigned char *insn_codep;
3203static unsigned char *codep;
3204static unsigned char *end_codep;
3205static int last_lock_prefix;
3206static int last_repz_prefix;
3207static int last_repnz_prefix;
3208static int last_data_prefix;
3209static int last_addr_prefix;
3210static int last_rex_prefix;
3211static int last_seg_prefix;
3212static int fwait_prefix;
3213/* The active segment register prefix. */
3214static int active_seg_prefix;
3215#define MAX_CODE_LENGTH 15
3216/* We can up to 14 prefixes since the maximum instruction length is
3217 15bytes. */
3218static int all_prefixes[MAX_CODE_LENGTH - 1];
3219static disassemble_info *the_info;
3220static struct
3221 {
3222 int mod;
3223 int reg;
3224 int rm;
3225 }
3226modrm;
3227static unsigned char need_modrm;
3228static struct
3229 {
3230 int scale;
3231 int index;
3232 int base;
3233 }
3234sib;
3235static struct
3236 {
3237 int register_specifier;
3238 int length;
3239 int prefix;
3240 int w;
3241 int evex;
3242 int r;
3243 int v;
3244 int mask_register_specifier;
3245 int zeroing;
3246 int ll;
3247 int b;
3248 }
3249vex;
3250static unsigned char need_vex;
3251static unsigned char need_vex_reg;
3252static unsigned char vex_w_done;
3253
3254struct op
3255 {
3256 const char *name;
3257 unsigned int len;
3258 };
3259
3260/* If we are accessing mod/rm/reg without need_modrm set, then the
3261 values are stale. Hitting this abort likely indicates that you
3262 need to update onebyte_has_modrm or twobyte_has_modrm. */
3263#define MODRM_CHECK if (!need_modrm) abort ()
3264
3265static const char **names64;
3266static const char **names32;
3267static const char **names16;
3268static const char **names8;
3269static const char **names8rex;
3270static const char **names_seg;
3271static const char *index64;
3272static const char *index32;
3273static const char **index16;
3274static const char **names_bnd;
3275
3276static const char *intel_names64[] = {
3277 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3278 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3279};
3280static const char *intel_names32[] = {
3281 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3282 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3283};
3284static const char *intel_names16[] = {
3285 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3286 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3287};
3288static const char *intel_names8[] = {
3289 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3290};
3291static const char *intel_names8rex[] = {
3292 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3293 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3294};
3295static const char *intel_names_seg[] = {
3296 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3297};
3298static const char *intel_index64 = "riz";
3299static const char *intel_index32 = "eiz";
3300static const char *intel_index16[] = {
3301 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3302};
3303
3304static const char *att_names64[] = {
3305 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3306 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3307};
3308static const char *att_names32[] = {
3309 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3310 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3311};
3312static const char *att_names16[] = {
3313 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3314 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3315};
3316static const char *att_names8[] = {
3317 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3318};
3319static const char *att_names8rex[] = {
3320 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3321 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3322};
3323static const char *att_names_seg[] = {
3324 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3325};
3326static const char *att_index64 = "%riz";
3327static const char *att_index32 = "%eiz";
3328static const char *att_index16[] = {
3329 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3330};
3331
3332static const char **names_mm;
3333static const char *intel_names_mm[] = {
3334 "mm0", "mm1", "mm2", "mm3",
3335 "mm4", "mm5", "mm6", "mm7"
3336};
3337static const char *att_names_mm[] = {
3338 "%mm0", "%mm1", "%mm2", "%mm3",
3339 "%mm4", "%mm5", "%mm6", "%mm7"
3340};
3341
3342static const char *intel_names_bnd[] = {
3343 "bnd0", "bnd1", "bnd2", "bnd3"
3344};
3345
3346static const char *att_names_bnd[] = {
3347 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3348};
3349
3350static const char **names_xmm;
3351static const char *intel_names_xmm[] = {
3352 "xmm0", "xmm1", "xmm2", "xmm3",
3353 "xmm4", "xmm5", "xmm6", "xmm7",
3354 "xmm8", "xmm9", "xmm10", "xmm11",
3355 "xmm12", "xmm13", "xmm14", "xmm15",
3356 "xmm16", "xmm17", "xmm18", "xmm19",
3357 "xmm20", "xmm21", "xmm22", "xmm23",
3358 "xmm24", "xmm25", "xmm26", "xmm27",
3359 "xmm28", "xmm29", "xmm30", "xmm31"
3360};
3361static const char *att_names_xmm[] = {
3362 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3363 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3364 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3365 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3366 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3367 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3368 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3369 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3370};
3371
3372static const char **names_ymm;
3373static const char *intel_names_ymm[] = {
3374 "ymm0", "ymm1", "ymm2", "ymm3",
3375 "ymm4", "ymm5", "ymm6", "ymm7",
3376 "ymm8", "ymm9", "ymm10", "ymm11",
3377 "ymm12", "ymm13", "ymm14", "ymm15",
3378 "ymm16", "ymm17", "ymm18", "ymm19",
3379 "ymm20", "ymm21", "ymm22", "ymm23",
3380 "ymm24", "ymm25", "ymm26", "ymm27",
3381 "ymm28", "ymm29", "ymm30", "ymm31"
3382};
3383static const char *att_names_ymm[] = {
3384 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3385 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3386 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3387 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3388 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3389 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3390 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3391 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3392};
3393
3394static const char **names_zmm;
3395static const char *intel_names_zmm[] = {
3396 "zmm0", "zmm1", "zmm2", "zmm3",
3397 "zmm4", "zmm5", "zmm6", "zmm7",
3398 "zmm8", "zmm9", "zmm10", "zmm11",
3399 "zmm12", "zmm13", "zmm14", "zmm15",
3400 "zmm16", "zmm17", "zmm18", "zmm19",
3401 "zmm20", "zmm21", "zmm22", "zmm23",
3402 "zmm24", "zmm25", "zmm26", "zmm27",
3403 "zmm28", "zmm29", "zmm30", "zmm31"
3404};
3405static const char *att_names_zmm[] = {
3406 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3407 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3408 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3409 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3410 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3411 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3412 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3413 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3414};
3415
3416static const char **names_mask;
3417static const char *intel_names_mask[] = {
3418 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3419};
3420static const char *att_names_mask[] = {
3421 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3422};
3423
3424static const char *names_rounding[] =
3425{
3426 "{rn-sae}",
3427 "{rd-sae}",
3428 "{ru-sae}",
3429 "{rz-sae}"
3430};
3431
3432static const struct dis386 reg_table[][8] = {
3433 /* REG_80 */
3434 {
3435 { "addA", { Ebh1, Ib }, 0 },
3436 { "orA", { Ebh1, Ib }, 0 },
3437 { "adcA", { Ebh1, Ib }, 0 },
3438 { "sbbA", { Ebh1, Ib }, 0 },
3439 { "andA", { Ebh1, Ib }, 0 },
3440 { "subA", { Ebh1, Ib }, 0 },
3441 { "xorA", { Ebh1, Ib }, 0 },
3442 { "cmpA", { Eb, Ib }, 0 },
3443 },
3444 /* REG_81 */
3445 {
3446 { "addQ", { Evh1, Iv }, 0 },
3447 { "orQ", { Evh1, Iv }, 0 },
3448 { "adcQ", { Evh1, Iv }, 0 },
3449 { "sbbQ", { Evh1, Iv }, 0 },
3450 { "andQ", { Evh1, Iv }, 0 },
3451 { "subQ", { Evh1, Iv }, 0 },
3452 { "xorQ", { Evh1, Iv }, 0 },
3453 { "cmpQ", { Ev, Iv }, 0 },
3454 },
3455 /* REG_83 */
3456 {
3457 { "addQ", { Evh1, sIb }, 0 },
3458 { "orQ", { Evh1, sIb }, 0 },
3459 { "adcQ", { Evh1, sIb }, 0 },
3460 { "sbbQ", { Evh1, sIb }, 0 },
3461 { "andQ", { Evh1, sIb }, 0 },
3462 { "subQ", { Evh1, sIb }, 0 },
3463 { "xorQ", { Evh1, sIb }, 0 },
3464 { "cmpQ", { Ev, sIb }, 0 },
3465 },
3466 /* REG_8F */
3467 {
3468 { "popU", { stackEv }, 0 },
3469 { XOP_8F_TABLE (XOP_09) },
3470 { Bad_Opcode },
3471 { Bad_Opcode },
3472 { Bad_Opcode },
3473 { XOP_8F_TABLE (XOP_09) },
3474 },
3475 /* REG_C0 */
3476 {
3477 { "rolA", { Eb, Ib }, 0 },
3478 { "rorA", { Eb, Ib }, 0 },
3479 { "rclA", { Eb, Ib }, 0 },
3480 { "rcrA", { Eb, Ib }, 0 },
3481 { "shlA", { Eb, Ib }, 0 },
3482 { "shrA", { Eb, Ib }, 0 },
3483 { "shlA", { Eb, Ib }, 0 },
3484 { "sarA", { Eb, Ib }, 0 },
3485 },
3486 /* REG_C1 */
3487 {
3488 { "rolQ", { Ev, Ib }, 0 },
3489 { "rorQ", { Ev, Ib }, 0 },
3490 { "rclQ", { Ev, Ib }, 0 },
3491 { "rcrQ", { Ev, Ib }, 0 },
3492 { "shlQ", { Ev, Ib }, 0 },
3493 { "shrQ", { Ev, Ib }, 0 },
3494 { "shlQ", { Ev, Ib }, 0 },
3495 { "sarQ", { Ev, Ib }, 0 },
3496 },
3497 /* REG_C6 */
3498 {
3499 { "movA", { Ebh3, Ib }, 0 },
3500 { Bad_Opcode },
3501 { Bad_Opcode },
3502 { Bad_Opcode },
3503 { Bad_Opcode },
3504 { Bad_Opcode },
3505 { Bad_Opcode },
3506 { MOD_TABLE (MOD_C6_REG_7) },
3507 },
3508 /* REG_C7 */
3509 {
3510 { "movQ", { Evh3, Iv }, 0 },
3511 { Bad_Opcode },
3512 { Bad_Opcode },
3513 { Bad_Opcode },
3514 { Bad_Opcode },
3515 { Bad_Opcode },
3516 { Bad_Opcode },
3517 { MOD_TABLE (MOD_C7_REG_7) },
3518 },
3519 /* REG_D0 */
3520 {
3521 { "rolA", { Eb, I1 }, 0 },
3522 { "rorA", { Eb, I1 }, 0 },
3523 { "rclA", { Eb, I1 }, 0 },
3524 { "rcrA", { Eb, I1 }, 0 },
3525 { "shlA", { Eb, I1 }, 0 },
3526 { "shrA", { Eb, I1 }, 0 },
3527 { "shlA", { Eb, I1 }, 0 },
3528 { "sarA", { Eb, I1 }, 0 },
3529 },
3530 /* REG_D1 */
3531 {
3532 { "rolQ", { Ev, I1 }, 0 },
3533 { "rorQ", { Ev, I1 }, 0 },
3534 { "rclQ", { Ev, I1 }, 0 },
3535 { "rcrQ", { Ev, I1 }, 0 },
3536 { "shlQ", { Ev, I1 }, 0 },
3537 { "shrQ", { Ev, I1 }, 0 },
3538 { "shlQ", { Ev, I1 }, 0 },
3539 { "sarQ", { Ev, I1 }, 0 },
3540 },
3541 /* REG_D2 */
3542 {
3543 { "rolA", { Eb, CL }, 0 },
3544 { "rorA", { Eb, CL }, 0 },
3545 { "rclA", { Eb, CL }, 0 },
3546 { "rcrA", { Eb, CL }, 0 },
3547 { "shlA", { Eb, CL }, 0 },
3548 { "shrA", { Eb, CL }, 0 },
3549 { "shlA", { Eb, CL }, 0 },
3550 { "sarA", { Eb, CL }, 0 },
3551 },
3552 /* REG_D3 */
3553 {
3554 { "rolQ", { Ev, CL }, 0 },
3555 { "rorQ", { Ev, CL }, 0 },
3556 { "rclQ", { Ev, CL }, 0 },
3557 { "rcrQ", { Ev, CL }, 0 },
3558 { "shlQ", { Ev, CL }, 0 },
3559 { "shrQ", { Ev, CL }, 0 },
3560 { "shlQ", { Ev, CL }, 0 },
3561 { "sarQ", { Ev, CL }, 0 },
3562 },
3563 /* REG_F6 */
3564 {
3565 { "testA", { Eb, Ib }, 0 },
3566 { "testA", { Eb, Ib }, 0 },
3567 { "notA", { Ebh1 }, 0 },
3568 { "negA", { Ebh1 }, 0 },
3569 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3570 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3571 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3572 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3573 },
3574 /* REG_F7 */
3575 {
3576 { "testQ", { Ev, Iv }, 0 },
3577 { "testQ", { Ev, Iv }, 0 },
3578 { "notQ", { Evh1 }, 0 },
3579 { "negQ", { Evh1 }, 0 },
3580 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3581 { "imulQ", { Ev }, 0 },
3582 { "divQ", { Ev }, 0 },
3583 { "idivQ", { Ev }, 0 },
3584 },
3585 /* REG_FE */
3586 {
3587 { "incA", { Ebh1 }, 0 },
3588 { "decA", { Ebh1 }, 0 },
3589 },
3590 /* REG_FF */
3591 {
3592 { "incQ", { Evh1 }, 0 },
3593 { "decQ", { Evh1 }, 0 },
3594 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3595 { MOD_TABLE (MOD_FF_REG_3) },
3596 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3597 { MOD_TABLE (MOD_FF_REG_5) },
3598 { "pushU", { stackEv }, 0 },
3599 { Bad_Opcode },
3600 },
3601 /* REG_0F00 */
3602 {
3603 { "sldtD", { Sv }, 0 },
3604 { "strD", { Sv }, 0 },
3605 { "lldt", { Ew }, 0 },
3606 { "ltr", { Ew }, 0 },
3607 { "verr", { Ew }, 0 },
3608 { "verw", { Ew }, 0 },
3609 { Bad_Opcode },
3610 { Bad_Opcode },
3611 },
3612 /* REG_0F01 */
3613 {
3614 { MOD_TABLE (MOD_0F01_REG_0) },
3615 { MOD_TABLE (MOD_0F01_REG_1) },
3616 { MOD_TABLE (MOD_0F01_REG_2) },
3617 { MOD_TABLE (MOD_0F01_REG_3) },
3618 { "smswD", { Sv }, 0 },
3619 { MOD_TABLE (MOD_0F01_REG_5) },
3620 { "lmsw", { Ew }, 0 },
3621 { MOD_TABLE (MOD_0F01_REG_7) },
3622 },
3623 /* REG_0F0D */
3624 {
3625 { "prefetch", { Mb }, 0 },
3626 { "prefetchw", { Mb }, 0 },
3627 { "prefetchwt1", { Mb }, 0 },
3628 { "prefetch", { Mb }, 0 },
3629 { "prefetch", { Mb }, 0 },
3630 { "prefetch", { Mb }, 0 },
3631 { "prefetch", { Mb }, 0 },
3632 { "prefetch", { Mb }, 0 },
3633 },
3634 /* REG_0F18 */
3635 {
3636 { MOD_TABLE (MOD_0F18_REG_0) },
3637 { MOD_TABLE (MOD_0F18_REG_1) },
3638 { MOD_TABLE (MOD_0F18_REG_2) },
3639 { MOD_TABLE (MOD_0F18_REG_3) },
3640 { MOD_TABLE (MOD_0F18_REG_4) },
3641 { MOD_TABLE (MOD_0F18_REG_5) },
3642 { MOD_TABLE (MOD_0F18_REG_6) },
3643 { MOD_TABLE (MOD_0F18_REG_7) },
3644 },
3645 /* REG_0F1E_MOD_3 */
3646 {
3647 { "nopQ", { Ev }, 0 },
3648 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3649 { "nopQ", { Ev }, 0 },
3650 { "nopQ", { Ev }, 0 },
3651 { "nopQ", { Ev }, 0 },
3652 { "nopQ", { Ev }, 0 },
3653 { "nopQ", { Ev }, 0 },
3654 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3655 },
3656 /* REG_0F71 */
3657 {
3658 { Bad_Opcode },
3659 { Bad_Opcode },
3660 { MOD_TABLE (MOD_0F71_REG_2) },
3661 { Bad_Opcode },
3662 { MOD_TABLE (MOD_0F71_REG_4) },
3663 { Bad_Opcode },
3664 { MOD_TABLE (MOD_0F71_REG_6) },
3665 },
3666 /* REG_0F72 */
3667 {
3668 { Bad_Opcode },
3669 { Bad_Opcode },
3670 { MOD_TABLE (MOD_0F72_REG_2) },
3671 { Bad_Opcode },
3672 { MOD_TABLE (MOD_0F72_REG_4) },
3673 { Bad_Opcode },
3674 { MOD_TABLE (MOD_0F72_REG_6) },
3675 },
3676 /* REG_0F73 */
3677 {
3678 { Bad_Opcode },
3679 { Bad_Opcode },
3680 { MOD_TABLE (MOD_0F73_REG_2) },
3681 { MOD_TABLE (MOD_0F73_REG_3) },
3682 { Bad_Opcode },
3683 { Bad_Opcode },
3684 { MOD_TABLE (MOD_0F73_REG_6) },
3685 { MOD_TABLE (MOD_0F73_REG_7) },
3686 },
3687 /* REG_0FA6 */
3688 {
3689 { "montmul", { { OP_0f07, 0 } }, 0 },
3690 { "xsha1", { { OP_0f07, 0 } }, 0 },
3691 { "xsha256", { { OP_0f07, 0 } }, 0 },
3692 },
3693 /* REG_0FA7 */
3694 {
3695 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3696 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3697 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3698 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3699 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3700 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3701 },
3702 /* REG_0FAE */
3703 {
3704 { MOD_TABLE (MOD_0FAE_REG_0) },
3705 { MOD_TABLE (MOD_0FAE_REG_1) },
3706 { MOD_TABLE (MOD_0FAE_REG_2) },
3707 { MOD_TABLE (MOD_0FAE_REG_3) },
3708 { MOD_TABLE (MOD_0FAE_REG_4) },
3709 { MOD_TABLE (MOD_0FAE_REG_5) },
3710 { MOD_TABLE (MOD_0FAE_REG_6) },
3711 { MOD_TABLE (MOD_0FAE_REG_7) },
3712 },
3713 /* REG_0FBA */
3714 {
3715 { Bad_Opcode },
3716 { Bad_Opcode },
3717 { Bad_Opcode },
3718 { Bad_Opcode },
3719 { "btQ", { Ev, Ib }, 0 },
3720 { "btsQ", { Evh1, Ib }, 0 },
3721 { "btrQ", { Evh1, Ib }, 0 },
3722 { "btcQ", { Evh1, Ib }, 0 },
3723 },
3724 /* REG_0FC7 */
3725 {
3726 { Bad_Opcode },
3727 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3728 { Bad_Opcode },
3729 { MOD_TABLE (MOD_0FC7_REG_3) },
3730 { MOD_TABLE (MOD_0FC7_REG_4) },
3731 { MOD_TABLE (MOD_0FC7_REG_5) },
3732 { MOD_TABLE (MOD_0FC7_REG_6) },
3733 { MOD_TABLE (MOD_0FC7_REG_7) },
3734 },
3735 /* REG_VEX_0F71 */
3736 {
3737 { Bad_Opcode },
3738 { Bad_Opcode },
3739 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3740 { Bad_Opcode },
3741 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3742 { Bad_Opcode },
3743 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3744 },
3745 /* REG_VEX_0F72 */
3746 {
3747 { Bad_Opcode },
3748 { Bad_Opcode },
3749 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3750 { Bad_Opcode },
3751 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3752 { Bad_Opcode },
3753 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3754 },
3755 /* REG_VEX_0F73 */
3756 {
3757 { Bad_Opcode },
3758 { Bad_Opcode },
3759 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3760 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3761 { Bad_Opcode },
3762 { Bad_Opcode },
3763 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3764 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3765 },
3766 /* REG_VEX_0FAE */
3767 {
3768 { Bad_Opcode },
3769 { Bad_Opcode },
3770 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3771 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3772 },
3773 /* REG_VEX_0F38F3 */
3774 {
3775 { Bad_Opcode },
3776 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3777 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3778 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3779 },
3780 /* REG_XOP_LWPCB */
3781 {
3782 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3783 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3784 },
3785 /* REG_XOP_LWP */
3786 {
3787 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3788 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3789 },
3790 /* REG_XOP_TBM_01 */
3791 {
3792 { Bad_Opcode },
3793 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3794 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3795 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3796 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3797 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3798 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3799 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3800 },
3801 /* REG_XOP_TBM_02 */
3802 {
3803 { Bad_Opcode },
3804 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3805 { Bad_Opcode },
3806 { Bad_Opcode },
3807 { Bad_Opcode },
3808 { Bad_Opcode },
3809 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3810 },
3811#define NEED_REG_TABLE
3812#include "i386-dis-evex.h"
3813#undef NEED_REG_TABLE
3814};
3815
3816static const struct dis386 prefix_table[][4] = {
3817 /* PREFIX_90 */
3818 {
3819 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3820 { "pause", { XX }, 0 },
3821 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3822 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3823 },
3824
3825 /* PREFIX_MOD_0_0F01_REG_5 */
3826 {
3827 { Bad_Opcode },
3828 { "rstorssp", { Mq }, PREFIX_OPCODE },
3829 },
3830
3831 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3832 {
3833 { Bad_Opcode },
3834 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3835 },
3836
3837 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3838 {
3839 { Bad_Opcode },
3840 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3841 },
3842
3843 /* PREFIX_0F10 */
3844 {
3845 { "movups", { XM, EXx }, PREFIX_OPCODE },
3846 { "movss", { XM, EXd }, PREFIX_OPCODE },
3847 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3848 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3849 },
3850
3851 /* PREFIX_0F11 */
3852 {
3853 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3854 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3855 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3856 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3857 },
3858
3859 /* PREFIX_0F12 */
3860 {
3861 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3862 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3863 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3864 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3865 },
3866
3867 /* PREFIX_0F16 */
3868 {
3869 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3870 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3871 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3872 },
3873
3874 /* PREFIX_0F1A */
3875 {
3876 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3877 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3878 { "bndmov", { Gbnd, Ebnd }, 0 },
3879 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3880 },
3881
3882 /* PREFIX_0F1B */
3883 {
3884 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3885 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3886 { "bndmov", { Ebnd, Gbnd }, 0 },
3887 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3888 },
3889
3890 /* PREFIX_0F1E */
3891 {
3892 { "nopQ", { Ev }, PREFIX_OPCODE },
3893 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3894 { "nopQ", { Ev }, PREFIX_OPCODE },
3895 { "nopQ", { Ev }, PREFIX_OPCODE },
3896 },
3897
3898 /* PREFIX_0F2A */
3899 {
3900 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3901 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3902 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3903 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3904 },
3905
3906 /* PREFIX_0F2B */
3907 {
3908 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3909 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3910 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3911 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3912 },
3913
3914 /* PREFIX_0F2C */
3915 {
3916 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3917 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3918 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3919 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3920 },
3921
3922 /* PREFIX_0F2D */
3923 {
3924 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3925 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3926 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3927 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3928 },
3929
3930 /* PREFIX_0F2E */
3931 {
3932 { "ucomiss",{ XM, EXd }, 0 },
3933 { Bad_Opcode },
3934 { "ucomisd",{ XM, EXq }, 0 },
3935 },
3936
3937 /* PREFIX_0F2F */
3938 {
3939 { "comiss", { XM, EXd }, 0 },
3940 { Bad_Opcode },
3941 { "comisd", { XM, EXq }, 0 },
3942 },
3943
3944 /* PREFIX_0F51 */
3945 {
3946 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3947 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3948 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3949 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3950 },
3951
3952 /* PREFIX_0F52 */
3953 {
3954 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3955 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3956 },
3957
3958 /* PREFIX_0F53 */
3959 {
3960 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3961 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3962 },
3963
3964 /* PREFIX_0F58 */
3965 {
3966 { "addps", { XM, EXx }, PREFIX_OPCODE },
3967 { "addss", { XM, EXd }, PREFIX_OPCODE },
3968 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3969 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3970 },
3971
3972 /* PREFIX_0F59 */
3973 {
3974 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3975 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3976 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3977 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3978 },
3979
3980 /* PREFIX_0F5A */
3981 {
3982 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3983 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3984 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3985 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3986 },
3987
3988 /* PREFIX_0F5B */
3989 {
3990 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3991 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3992 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3993 },
3994
3995 /* PREFIX_0F5C */
3996 {
3997 { "subps", { XM, EXx }, PREFIX_OPCODE },
3998 { "subss", { XM, EXd }, PREFIX_OPCODE },
3999 { "subpd", { XM, EXx }, PREFIX_OPCODE },
4000 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4001 },
4002
4003 /* PREFIX_0F5D */
4004 {
4005 { "minps", { XM, EXx }, PREFIX_OPCODE },
4006 { "minss", { XM, EXd }, PREFIX_OPCODE },
4007 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4008 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4009 },
4010
4011 /* PREFIX_0F5E */
4012 {
4013 { "divps", { XM, EXx }, PREFIX_OPCODE },
4014 { "divss", { XM, EXd }, PREFIX_OPCODE },
4015 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4016 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4017 },
4018
4019 /* PREFIX_0F5F */
4020 {
4021 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4022 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4023 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4024 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4025 },
4026
4027 /* PREFIX_0F60 */
4028 {
4029 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4030 { Bad_Opcode },
4031 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4032 },
4033
4034 /* PREFIX_0F61 */
4035 {
4036 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4037 { Bad_Opcode },
4038 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4039 },
4040
4041 /* PREFIX_0F62 */
4042 {
4043 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4044 { Bad_Opcode },
4045 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4046 },
4047
4048 /* PREFIX_0F6C */
4049 {
4050 { Bad_Opcode },
4051 { Bad_Opcode },
4052 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4053 },
4054
4055 /* PREFIX_0F6D */
4056 {
4057 { Bad_Opcode },
4058 { Bad_Opcode },
4059 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4060 },
4061
4062 /* PREFIX_0F6F */
4063 {
4064 { "movq", { MX, EM }, PREFIX_OPCODE },
4065 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4066 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4067 },
4068
4069 /* PREFIX_0F70 */
4070 {
4071 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4072 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4073 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4074 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4075 },
4076
4077 /* PREFIX_0F73_REG_3 */
4078 {
4079 { Bad_Opcode },
4080 { Bad_Opcode },
4081 { "psrldq", { XS, Ib }, 0 },
4082 },
4083
4084 /* PREFIX_0F73_REG_7 */
4085 {
4086 { Bad_Opcode },
4087 { Bad_Opcode },
4088 { "pslldq", { XS, Ib }, 0 },
4089 },
4090
4091 /* PREFIX_0F78 */
4092 {
4093 {"vmread", { Em, Gm }, 0 },
4094 { Bad_Opcode },
4095 {"extrq", { XS, Ib, Ib }, 0 },
4096 {"insertq", { XM, XS, Ib, Ib }, 0 },
4097 },
4098
4099 /* PREFIX_0F79 */
4100 {
4101 {"vmwrite", { Gm, Em }, 0 },
4102 { Bad_Opcode },
4103 {"extrq", { XM, XS }, 0 },
4104 {"insertq", { XM, XS }, 0 },
4105 },
4106
4107 /* PREFIX_0F7C */
4108 {
4109 { Bad_Opcode },
4110 { Bad_Opcode },
4111 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4112 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4113 },
4114
4115 /* PREFIX_0F7D */
4116 {
4117 { Bad_Opcode },
4118 { Bad_Opcode },
4119 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4120 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4121 },
4122
4123 /* PREFIX_0F7E */
4124 {
4125 { "movK", { Edq, MX }, PREFIX_OPCODE },
4126 { "movq", { XM, EXq }, PREFIX_OPCODE },
4127 { "movK", { Edq, XM }, PREFIX_OPCODE },
4128 },
4129
4130 /* PREFIX_0F7F */
4131 {
4132 { "movq", { EMS, MX }, PREFIX_OPCODE },
4133 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4134 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4135 },
4136
4137 /* PREFIX_0FAE_REG_0 */
4138 {
4139 { Bad_Opcode },
4140 { "rdfsbase", { Ev }, 0 },
4141 },
4142
4143 /* PREFIX_0FAE_REG_1 */
4144 {
4145 { Bad_Opcode },
4146 { "rdgsbase", { Ev }, 0 },
4147 },
4148
4149 /* PREFIX_0FAE_REG_2 */
4150 {
4151 { Bad_Opcode },
4152 { "wrfsbase", { Ev }, 0 },
4153 },
4154
4155 /* PREFIX_0FAE_REG_3 */
4156 {
4157 { Bad_Opcode },
4158 { "wrgsbase", { Ev }, 0 },
4159 },
4160
4161 /* PREFIX_MOD_0_0FAE_REG_4 */
4162 {
4163 { "xsave", { FXSAVE }, 0 },
4164 { "ptwrite%LQ", { Edq }, 0 },
4165 },
4166
4167 /* PREFIX_MOD_3_0FAE_REG_4 */
4168 {
4169 { Bad_Opcode },
4170 { "ptwrite%LQ", { Edq }, 0 },
4171 },
4172
4173 /* PREFIX_MOD_0_0FAE_REG_5 */
4174 {
4175 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4176 },
4177
4178 /* PREFIX_MOD_3_0FAE_REG_5 */
4179 {
4180 { "lfence", { Skip_MODRM }, 0 },
4181 { "incsspK", { Rdq }, PREFIX_OPCODE },
4182 },
4183
4184 /* PREFIX_0FAE_REG_6 */
4185 {
4186 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4187 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4188 { "clwb", { Mb }, PREFIX_OPCODE },
4189 },
4190
4191 /* PREFIX_0FAE_REG_7 */
4192 {
4193 { "clflush", { Mb }, 0 },
4194 { Bad_Opcode },
4195 { "clflushopt", { Mb }, 0 },
4196 },
4197
4198 /* PREFIX_0FB8 */
4199 {
4200 { Bad_Opcode },
4201 { "popcntS", { Gv, Ev }, 0 },
4202 },
4203
4204 /* PREFIX_0FBC */
4205 {
4206 { "bsfS", { Gv, Ev }, 0 },
4207 { "tzcntS", { Gv, Ev }, 0 },
4208 { "bsfS", { Gv, Ev }, 0 },
4209 },
4210
4211 /* PREFIX_0FBD */
4212 {
4213 { "bsrS", { Gv, Ev }, 0 },
4214 { "lzcntS", { Gv, Ev }, 0 },
4215 { "bsrS", { Gv, Ev }, 0 },
4216 },
4217
4218 /* PREFIX_0FC2 */
4219 {
4220 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4221 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4222 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4223 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4224 },
4225
4226 /* PREFIX_MOD_0_0FC3 */
4227 {
4228 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4229 },
4230
4231 /* PREFIX_MOD_0_0FC7_REG_6 */
4232 {
4233 { "vmptrld",{ Mq }, 0 },
4234 { "vmxon", { Mq }, 0 },
4235 { "vmclear",{ Mq }, 0 },
4236 },
4237
4238 /* PREFIX_MOD_3_0FC7_REG_6 */
4239 {
4240 { "rdrand", { Ev }, 0 },
4241 { Bad_Opcode },
4242 { "rdrand", { Ev }, 0 }
4243 },
4244
4245 /* PREFIX_MOD_3_0FC7_REG_7 */
4246 {
4247 { "rdseed", { Ev }, 0 },
4248 { "rdpid", { Em }, 0 },
4249 { "rdseed", { Ev }, 0 },
4250 },
4251
4252 /* PREFIX_0FD0 */
4253 {
4254 { Bad_Opcode },
4255 { Bad_Opcode },
4256 { "addsubpd", { XM, EXx }, 0 },
4257 { "addsubps", { XM, EXx }, 0 },
4258 },
4259
4260 /* PREFIX_0FD6 */
4261 {
4262 { Bad_Opcode },
4263 { "movq2dq",{ XM, MS }, 0 },
4264 { "movq", { EXqS, XM }, 0 },
4265 { "movdq2q",{ MX, XS }, 0 },
4266 },
4267
4268 /* PREFIX_0FE6 */
4269 {
4270 { Bad_Opcode },
4271 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4272 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4273 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4274 },
4275
4276 /* PREFIX_0FE7 */
4277 {
4278 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4279 { Bad_Opcode },
4280 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4281 },
4282
4283 /* PREFIX_0FF0 */
4284 {
4285 { Bad_Opcode },
4286 { Bad_Opcode },
4287 { Bad_Opcode },
4288 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4289 },
4290
4291 /* PREFIX_0FF7 */
4292 {
4293 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4294 { Bad_Opcode },
4295 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4296 },
4297
4298 /* PREFIX_0F3810 */
4299 {
4300 { Bad_Opcode },
4301 { Bad_Opcode },
4302 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4303 },
4304
4305 /* PREFIX_0F3814 */
4306 {
4307 { Bad_Opcode },
4308 { Bad_Opcode },
4309 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4310 },
4311
4312 /* PREFIX_0F3815 */
4313 {
4314 { Bad_Opcode },
4315 { Bad_Opcode },
4316 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4317 },
4318
4319 /* PREFIX_0F3817 */
4320 {
4321 { Bad_Opcode },
4322 { Bad_Opcode },
4323 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4324 },
4325
4326 /* PREFIX_0F3820 */
4327 {
4328 { Bad_Opcode },
4329 { Bad_Opcode },
4330 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4331 },
4332
4333 /* PREFIX_0F3821 */
4334 {
4335 { Bad_Opcode },
4336 { Bad_Opcode },
4337 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4338 },
4339
4340 /* PREFIX_0F3822 */
4341 {
4342 { Bad_Opcode },
4343 { Bad_Opcode },
4344 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4345 },
4346
4347 /* PREFIX_0F3823 */
4348 {
4349 { Bad_Opcode },
4350 { Bad_Opcode },
4351 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4352 },
4353
4354 /* PREFIX_0F3824 */
4355 {
4356 { Bad_Opcode },
4357 { Bad_Opcode },
4358 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4359 },
4360
4361 /* PREFIX_0F3825 */
4362 {
4363 { Bad_Opcode },
4364 { Bad_Opcode },
4365 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4366 },
4367
4368 /* PREFIX_0F3828 */
4369 {
4370 { Bad_Opcode },
4371 { Bad_Opcode },
4372 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4373 },
4374
4375 /* PREFIX_0F3829 */
4376 {
4377 { Bad_Opcode },
4378 { Bad_Opcode },
4379 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4380 },
4381
4382 /* PREFIX_0F382A */
4383 {
4384 { Bad_Opcode },
4385 { Bad_Opcode },
4386 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4387 },
4388
4389 /* PREFIX_0F382B */
4390 {
4391 { Bad_Opcode },
4392 { Bad_Opcode },
4393 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4394 },
4395
4396 /* PREFIX_0F3830 */
4397 {
4398 { Bad_Opcode },
4399 { Bad_Opcode },
4400 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4401 },
4402
4403 /* PREFIX_0F3831 */
4404 {
4405 { Bad_Opcode },
4406 { Bad_Opcode },
4407 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4408 },
4409
4410 /* PREFIX_0F3832 */
4411 {
4412 { Bad_Opcode },
4413 { Bad_Opcode },
4414 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4415 },
4416
4417 /* PREFIX_0F3833 */
4418 {
4419 { Bad_Opcode },
4420 { Bad_Opcode },
4421 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4422 },
4423
4424 /* PREFIX_0F3834 */
4425 {
4426 { Bad_Opcode },
4427 { Bad_Opcode },
4428 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4429 },
4430
4431 /* PREFIX_0F3835 */
4432 {
4433 { Bad_Opcode },
4434 { Bad_Opcode },
4435 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4436 },
4437
4438 /* PREFIX_0F3837 */
4439 {
4440 { Bad_Opcode },
4441 { Bad_Opcode },
4442 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4443 },
4444
4445 /* PREFIX_0F3838 */
4446 {
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4450 },
4451
4452 /* PREFIX_0F3839 */
4453 {
4454 { Bad_Opcode },
4455 { Bad_Opcode },
4456 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4457 },
4458
4459 /* PREFIX_0F383A */
4460 {
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4464 },
4465
4466 /* PREFIX_0F383B */
4467 {
4468 { Bad_Opcode },
4469 { Bad_Opcode },
4470 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4471 },
4472
4473 /* PREFIX_0F383C */
4474 {
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4478 },
4479
4480 /* PREFIX_0F383D */
4481 {
4482 { Bad_Opcode },
4483 { Bad_Opcode },
4484 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4485 },
4486
4487 /* PREFIX_0F383E */
4488 {
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4492 },
4493
4494 /* PREFIX_0F383F */
4495 {
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4499 },
4500
4501 /* PREFIX_0F3840 */
4502 {
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4506 },
4507
4508 /* PREFIX_0F3841 */
4509 {
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4513 },
4514
4515 /* PREFIX_0F3880 */
4516 {
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4520 },
4521
4522 /* PREFIX_0F3881 */
4523 {
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4527 },
4528
4529 /* PREFIX_0F3882 */
4530 {
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4534 },
4535
4536 /* PREFIX_0F38C8 */
4537 {
4538 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4539 },
4540
4541 /* PREFIX_0F38C9 */
4542 {
4543 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4544 },
4545
4546 /* PREFIX_0F38CA */
4547 {
4548 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4549 },
4550
4551 /* PREFIX_0F38CB */
4552 {
4553 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4554 },
4555
4556 /* PREFIX_0F38CC */
4557 {
4558 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4559 },
4560
4561 /* PREFIX_0F38CD */
4562 {
4563 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4564 },
4565
4566 /* PREFIX_0F38CF */
4567 {
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4571 },
4572
4573 /* PREFIX_0F38DB */
4574 {
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4578 },
4579
4580 /* PREFIX_0F38DC */
4581 {
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4585 },
4586
4587 /* PREFIX_0F38DD */
4588 {
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4592 },
4593
4594 /* PREFIX_0F38DE */
4595 {
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4599 },
4600
4601 /* PREFIX_0F38DF */
4602 {
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4606 },
4607
4608 /* PREFIX_0F38F0 */
4609 {
4610 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4611 { Bad_Opcode },
4612 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4613 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4614 },
4615
4616 /* PREFIX_0F38F1 */
4617 {
4618 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4619 { Bad_Opcode },
4620 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4621 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4622 },
4623
4624 /* PREFIX_0F38F5 */
4625 {
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4629 },
4630
4631 /* PREFIX_0F38F6 */
4632 {
4633 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4634 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4635 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4636 { Bad_Opcode },
4637 },
4638
4639 /* PREFIX_0F3A08 */
4640 {
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4644 },
4645
4646 /* PREFIX_0F3A09 */
4647 {
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4651 },
4652
4653 /* PREFIX_0F3A0A */
4654 {
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4658 },
4659
4660 /* PREFIX_0F3A0B */
4661 {
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4665 },
4666
4667 /* PREFIX_0F3A0C */
4668 {
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4672 },
4673
4674 /* PREFIX_0F3A0D */
4675 {
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4679 },
4680
4681 /* PREFIX_0F3A0E */
4682 {
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4686 },
4687
4688 /* PREFIX_0F3A14 */
4689 {
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4693 },
4694
4695 /* PREFIX_0F3A15 */
4696 {
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4700 },
4701
4702 /* PREFIX_0F3A16 */
4703 {
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4707 },
4708
4709 /* PREFIX_0F3A17 */
4710 {
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4714 },
4715
4716 /* PREFIX_0F3A20 */
4717 {
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4721 },
4722
4723 /* PREFIX_0F3A21 */
4724 {
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4728 },
4729
4730 /* PREFIX_0F3A22 */
4731 {
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4735 },
4736
4737 /* PREFIX_0F3A40 */
4738 {
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4742 },
4743
4744 /* PREFIX_0F3A41 */
4745 {
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4749 },
4750
4751 /* PREFIX_0F3A42 */
4752 {
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4756 },
4757
4758 /* PREFIX_0F3A44 */
4759 {
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4763 },
4764
4765 /* PREFIX_0F3A60 */
4766 {
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4770 },
4771
4772 /* PREFIX_0F3A61 */
4773 {
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4777 },
4778
4779 /* PREFIX_0F3A62 */
4780 {
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4784 },
4785
4786 /* PREFIX_0F3A63 */
4787 {
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4791 },
4792
4793 /* PREFIX_0F3ACC */
4794 {
4795 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4796 },
4797
4798 /* PREFIX_0F3ACE */
4799 {
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4803 },
4804
4805 /* PREFIX_0F3ACF */
4806 {
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4810 },
4811
4812 /* PREFIX_0F3ADF */
4813 {
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4817 },
4818
4819 /* PREFIX_VEX_0F10 */
4820 {
4821 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4822 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4823 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4824 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4825 },
4826
4827 /* PREFIX_VEX_0F11 */
4828 {
4829 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4830 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4831 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4832 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4833 },
4834
4835 /* PREFIX_VEX_0F12 */
4836 {
4837 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4838 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4840 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4841 },
4842
4843 /* PREFIX_VEX_0F16 */
4844 {
4845 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4846 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4848 },
4849
4850 /* PREFIX_VEX_0F2A */
4851 {
4852 { Bad_Opcode },
4853 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4854 { Bad_Opcode },
4855 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4856 },
4857
4858 /* PREFIX_VEX_0F2C */
4859 {
4860 { Bad_Opcode },
4861 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4862 { Bad_Opcode },
4863 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4864 },
4865
4866 /* PREFIX_VEX_0F2D */
4867 {
4868 { Bad_Opcode },
4869 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4870 { Bad_Opcode },
4871 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4872 },
4873
4874 /* PREFIX_VEX_0F2E */
4875 {
4876 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4877 { Bad_Opcode },
4878 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4879 },
4880
4881 /* PREFIX_VEX_0F2F */
4882 {
4883 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4884 { Bad_Opcode },
4885 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4886 },
4887
4888 /* PREFIX_VEX_0F41 */
4889 {
4890 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4891 { Bad_Opcode },
4892 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4893 },
4894
4895 /* PREFIX_VEX_0F42 */
4896 {
4897 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4898 { Bad_Opcode },
4899 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4900 },
4901
4902 /* PREFIX_VEX_0F44 */
4903 {
4904 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4905 { Bad_Opcode },
4906 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4907 },
4908
4909 /* PREFIX_VEX_0F45 */
4910 {
4911 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4912 { Bad_Opcode },
4913 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4914 },
4915
4916 /* PREFIX_VEX_0F46 */
4917 {
4918 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4919 { Bad_Opcode },
4920 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4921 },
4922
4923 /* PREFIX_VEX_0F47 */
4924 {
4925 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4926 { Bad_Opcode },
4927 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4928 },
4929
4930 /* PREFIX_VEX_0F4A */
4931 {
4932 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4933 { Bad_Opcode },
4934 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4935 },
4936
4937 /* PREFIX_VEX_0F4B */
4938 {
4939 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4940 { Bad_Opcode },
4941 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4942 },
4943
4944 /* PREFIX_VEX_0F51 */
4945 {
4946 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4947 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4948 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4949 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4950 },
4951
4952 /* PREFIX_VEX_0F52 */
4953 {
4954 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4955 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4956 },
4957
4958 /* PREFIX_VEX_0F53 */
4959 {
4960 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4961 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4962 },
4963
4964 /* PREFIX_VEX_0F58 */
4965 {
4966 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4967 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4968 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4969 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4970 },
4971
4972 /* PREFIX_VEX_0F59 */
4973 {
4974 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4975 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4976 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4977 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4978 },
4979
4980 /* PREFIX_VEX_0F5A */
4981 {
4982 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4983 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4984 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4985 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4986 },
4987
4988 /* PREFIX_VEX_0F5B */
4989 {
4990 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4991 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4992 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4993 },
4994
4995 /* PREFIX_VEX_0F5C */
4996 {
4997 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4998 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4999 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5000 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5001 },
5002
5003 /* PREFIX_VEX_0F5D */
5004 {
5005 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5006 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5007 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5008 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5009 },
5010
5011 /* PREFIX_VEX_0F5E */
5012 {
5013 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5014 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5015 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5016 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5017 },
5018
5019 /* PREFIX_VEX_0F5F */
5020 {
5021 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5022 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5023 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5024 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5025 },
5026
5027 /* PREFIX_VEX_0F60 */
5028 {
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5032 },
5033
5034 /* PREFIX_VEX_0F61 */
5035 {
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5039 },
5040
5041 /* PREFIX_VEX_0F62 */
5042 {
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5046 },
5047
5048 /* PREFIX_VEX_0F63 */
5049 {
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5053 },
5054
5055 /* PREFIX_VEX_0F64 */
5056 {
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5060 },
5061
5062 /* PREFIX_VEX_0F65 */
5063 {
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5067 },
5068
5069 /* PREFIX_VEX_0F66 */
5070 {
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5074 },
5075
5076 /* PREFIX_VEX_0F67 */
5077 {
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5081 },
5082
5083 /* PREFIX_VEX_0F68 */
5084 {
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5088 },
5089
5090 /* PREFIX_VEX_0F69 */
5091 {
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5095 },
5096
5097 /* PREFIX_VEX_0F6A */
5098 {
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5102 },
5103
5104 /* PREFIX_VEX_0F6B */
5105 {
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5109 },
5110
5111 /* PREFIX_VEX_0F6C */
5112 {
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5116 },
5117
5118 /* PREFIX_VEX_0F6D */
5119 {
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5123 },
5124
5125 /* PREFIX_VEX_0F6E */
5126 {
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5130 },
5131
5132 /* PREFIX_VEX_0F6F */
5133 {
5134 { Bad_Opcode },
5135 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5136 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5137 },
5138
5139 /* PREFIX_VEX_0F70 */
5140 {
5141 { Bad_Opcode },
5142 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5143 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5144 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5145 },
5146
5147 /* PREFIX_VEX_0F71_REG_2 */
5148 {
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5152 },
5153
5154 /* PREFIX_VEX_0F71_REG_4 */
5155 {
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5159 },
5160
5161 /* PREFIX_VEX_0F71_REG_6 */
5162 {
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5166 },
5167
5168 /* PREFIX_VEX_0F72_REG_2 */
5169 {
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5173 },
5174
5175 /* PREFIX_VEX_0F72_REG_4 */
5176 {
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5180 },
5181
5182 /* PREFIX_VEX_0F72_REG_6 */
5183 {
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5187 },
5188
5189 /* PREFIX_VEX_0F73_REG_2 */
5190 {
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5194 },
5195
5196 /* PREFIX_VEX_0F73_REG_3 */
5197 {
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5201 },
5202
5203 /* PREFIX_VEX_0F73_REG_6 */
5204 {
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5208 },
5209
5210 /* PREFIX_VEX_0F73_REG_7 */
5211 {
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5215 },
5216
5217 /* PREFIX_VEX_0F74 */
5218 {
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5222 },
5223
5224 /* PREFIX_VEX_0F75 */
5225 {
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5229 },
5230
5231 /* PREFIX_VEX_0F76 */
5232 {
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5236 },
5237
5238 /* PREFIX_VEX_0F77 */
5239 {
5240 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5241 },
5242
5243 /* PREFIX_VEX_0F7C */
5244 {
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5248 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5249 },
5250
5251 /* PREFIX_VEX_0F7D */
5252 {
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5256 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5257 },
5258
5259 /* PREFIX_VEX_0F7E */
5260 {
5261 { Bad_Opcode },
5262 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5263 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5264 },
5265
5266 /* PREFIX_VEX_0F7F */
5267 {
5268 { Bad_Opcode },
5269 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5270 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5271 },
5272
5273 /* PREFIX_VEX_0F90 */
5274 {
5275 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5276 { Bad_Opcode },
5277 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5278 },
5279
5280 /* PREFIX_VEX_0F91 */
5281 {
5282 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5283 { Bad_Opcode },
5284 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5285 },
5286
5287 /* PREFIX_VEX_0F92 */
5288 {
5289 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5290 { Bad_Opcode },
5291 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5292 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5293 },
5294
5295 /* PREFIX_VEX_0F93 */
5296 {
5297 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5298 { Bad_Opcode },
5299 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5300 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5301 },
5302
5303 /* PREFIX_VEX_0F98 */
5304 {
5305 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5306 { Bad_Opcode },
5307 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5308 },
5309
5310 /* PREFIX_VEX_0F99 */
5311 {
5312 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5313 { Bad_Opcode },
5314 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5315 },
5316
5317 /* PREFIX_VEX_0FC2 */
5318 {
5319 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5320 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5321 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5322 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5323 },
5324
5325 /* PREFIX_VEX_0FC4 */
5326 {
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5330 },
5331
5332 /* PREFIX_VEX_0FC5 */
5333 {
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5337 },
5338
5339 /* PREFIX_VEX_0FD0 */
5340 {
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5344 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5345 },
5346
5347 /* PREFIX_VEX_0FD1 */
5348 {
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5352 },
5353
5354 /* PREFIX_VEX_0FD2 */
5355 {
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5359 },
5360
5361 /* PREFIX_VEX_0FD3 */
5362 {
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5366 },
5367
5368 /* PREFIX_VEX_0FD4 */
5369 {
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5373 },
5374
5375 /* PREFIX_VEX_0FD5 */
5376 {
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5380 },
5381
5382 /* PREFIX_VEX_0FD6 */
5383 {
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5387 },
5388
5389 /* PREFIX_VEX_0FD7 */
5390 {
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5394 },
5395
5396 /* PREFIX_VEX_0FD8 */
5397 {
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5401 },
5402
5403 /* PREFIX_VEX_0FD9 */
5404 {
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5408 },
5409
5410 /* PREFIX_VEX_0FDA */
5411 {
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5415 },
5416
5417 /* PREFIX_VEX_0FDB */
5418 {
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5422 },
5423
5424 /* PREFIX_VEX_0FDC */
5425 {
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5429 },
5430
5431 /* PREFIX_VEX_0FDD */
5432 {
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5436 },
5437
5438 /* PREFIX_VEX_0FDE */
5439 {
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5443 },
5444
5445 /* PREFIX_VEX_0FDF */
5446 {
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5450 },
5451
5452 /* PREFIX_VEX_0FE0 */
5453 {
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5457 },
5458
5459 /* PREFIX_VEX_0FE1 */
5460 {
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5464 },
5465
5466 /* PREFIX_VEX_0FE2 */
5467 {
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5471 },
5472
5473 /* PREFIX_VEX_0FE3 */
5474 {
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5478 },
5479
5480 /* PREFIX_VEX_0FE4 */
5481 {
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5485 },
5486
5487 /* PREFIX_VEX_0FE5 */
5488 {
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5492 },
5493
5494 /* PREFIX_VEX_0FE6 */
5495 {
5496 { Bad_Opcode },
5497 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5498 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5499 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5500 },
5501
5502 /* PREFIX_VEX_0FE7 */
5503 {
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5507 },
5508
5509 /* PREFIX_VEX_0FE8 */
5510 {
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5514 },
5515
5516 /* PREFIX_VEX_0FE9 */
5517 {
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5521 },
5522
5523 /* PREFIX_VEX_0FEA */
5524 {
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5528 },
5529
5530 /* PREFIX_VEX_0FEB */
5531 {
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5535 },
5536
5537 /* PREFIX_VEX_0FEC */
5538 {
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5542 },
5543
5544 /* PREFIX_VEX_0FED */
5545 {
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5549 },
5550
5551 /* PREFIX_VEX_0FEE */
5552 {
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5556 },
5557
5558 /* PREFIX_VEX_0FEF */
5559 {
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5563 },
5564
5565 /* PREFIX_VEX_0FF0 */
5566 {
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5571 },
5572
5573 /* PREFIX_VEX_0FF1 */
5574 {
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5578 },
5579
5580 /* PREFIX_VEX_0FF2 */
5581 {
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5585 },
5586
5587 /* PREFIX_VEX_0FF3 */
5588 {
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5592 },
5593
5594 /* PREFIX_VEX_0FF4 */
5595 {
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5599 },
5600
5601 /* PREFIX_VEX_0FF5 */
5602 {
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5606 },
5607
5608 /* PREFIX_VEX_0FF6 */
5609 {
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5613 },
5614
5615 /* PREFIX_VEX_0FF7 */
5616 {
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5620 },
5621
5622 /* PREFIX_VEX_0FF8 */
5623 {
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5627 },
5628
5629 /* PREFIX_VEX_0FF9 */
5630 {
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5634 },
5635
5636 /* PREFIX_VEX_0FFA */
5637 {
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5641 },
5642
5643 /* PREFIX_VEX_0FFB */
5644 {
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5648 },
5649
5650 /* PREFIX_VEX_0FFC */
5651 {
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5655 },
5656
5657 /* PREFIX_VEX_0FFD */
5658 {
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5662 },
5663
5664 /* PREFIX_VEX_0FFE */
5665 {
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5669 },
5670
5671 /* PREFIX_VEX_0F3800 */
5672 {
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5676 },
5677
5678 /* PREFIX_VEX_0F3801 */
5679 {
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5683 },
5684
5685 /* PREFIX_VEX_0F3802 */
5686 {
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5690 },
5691
5692 /* PREFIX_VEX_0F3803 */
5693 {
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5697 },
5698
5699 /* PREFIX_VEX_0F3804 */
5700 {
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5704 },
5705
5706 /* PREFIX_VEX_0F3805 */
5707 {
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5711 },
5712
5713 /* PREFIX_VEX_0F3806 */
5714 {
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5718 },
5719
5720 /* PREFIX_VEX_0F3807 */
5721 {
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5725 },
5726
5727 /* PREFIX_VEX_0F3808 */
5728 {
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5732 },
5733
5734 /* PREFIX_VEX_0F3809 */
5735 {
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5739 },
5740
5741 /* PREFIX_VEX_0F380A */
5742 {
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5746 },
5747
5748 /* PREFIX_VEX_0F380B */
5749 {
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5753 },
5754
5755 /* PREFIX_VEX_0F380C */
5756 {
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5760 },
5761
5762 /* PREFIX_VEX_0F380D */
5763 {
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5767 },
5768
5769 /* PREFIX_VEX_0F380E */
5770 {
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5774 },
5775
5776 /* PREFIX_VEX_0F380F */
5777 {
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5781 },
5782
5783 /* PREFIX_VEX_0F3813 */
5784 {
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5788 },
5789
5790 /* PREFIX_VEX_0F3816 */
5791 {
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5795 },
5796
5797 /* PREFIX_VEX_0F3817 */
5798 {
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5802 },
5803
5804 /* PREFIX_VEX_0F3818 */
5805 {
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5809 },
5810
5811 /* PREFIX_VEX_0F3819 */
5812 {
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5816 },
5817
5818 /* PREFIX_VEX_0F381A */
5819 {
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5823 },
5824
5825 /* PREFIX_VEX_0F381C */
5826 {
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5830 },
5831
5832 /* PREFIX_VEX_0F381D */
5833 {
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5837 },
5838
5839 /* PREFIX_VEX_0F381E */
5840 {
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5844 },
5845
5846 /* PREFIX_VEX_0F3820 */
5847 {
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5851 },
5852
5853 /* PREFIX_VEX_0F3821 */
5854 {
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5858 },
5859
5860 /* PREFIX_VEX_0F3822 */
5861 {
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5865 },
5866
5867 /* PREFIX_VEX_0F3823 */
5868 {
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5872 },
5873
5874 /* PREFIX_VEX_0F3824 */
5875 {
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5879 },
5880
5881 /* PREFIX_VEX_0F3825 */
5882 {
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5886 },
5887
5888 /* PREFIX_VEX_0F3828 */
5889 {
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5893 },
5894
5895 /* PREFIX_VEX_0F3829 */
5896 {
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5900 },
5901
5902 /* PREFIX_VEX_0F382A */
5903 {
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5907 },
5908
5909 /* PREFIX_VEX_0F382B */
5910 {
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5914 },
5915
5916 /* PREFIX_VEX_0F382C */
5917 {
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5921 },
5922
5923 /* PREFIX_VEX_0F382D */
5924 {
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5928 },
5929
5930 /* PREFIX_VEX_0F382E */
5931 {
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5935 },
5936
5937 /* PREFIX_VEX_0F382F */
5938 {
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5942 },
5943
5944 /* PREFIX_VEX_0F3830 */
5945 {
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5949 },
5950
5951 /* PREFIX_VEX_0F3831 */
5952 {
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5956 },
5957
5958 /* PREFIX_VEX_0F3832 */
5959 {
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5963 },
5964
5965 /* PREFIX_VEX_0F3833 */
5966 {
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5970 },
5971
5972 /* PREFIX_VEX_0F3834 */
5973 {
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5977 },
5978
5979 /* PREFIX_VEX_0F3835 */
5980 {
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5984 },
5985
5986 /* PREFIX_VEX_0F3836 */
5987 {
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5991 },
5992
5993 /* PREFIX_VEX_0F3837 */
5994 {
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5998 },
5999
6000 /* PREFIX_VEX_0F3838 */
6001 {
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6005 },
6006
6007 /* PREFIX_VEX_0F3839 */
6008 {
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6012 },
6013
6014 /* PREFIX_VEX_0F383A */
6015 {
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6019 },
6020
6021 /* PREFIX_VEX_0F383B */
6022 {
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6026 },
6027
6028 /* PREFIX_VEX_0F383C */
6029 {
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6033 },
6034
6035 /* PREFIX_VEX_0F383D */
6036 {
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6040 },
6041
6042 /* PREFIX_VEX_0F383E */
6043 {
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6047 },
6048
6049 /* PREFIX_VEX_0F383F */
6050 {
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6054 },
6055
6056 /* PREFIX_VEX_0F3840 */
6057 {
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6061 },
6062
6063 /* PREFIX_VEX_0F3841 */
6064 {
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6068 },
6069
6070 /* PREFIX_VEX_0F3845 */
6071 {
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6075 },
6076
6077 /* PREFIX_VEX_0F3846 */
6078 {
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6082 },
6083
6084 /* PREFIX_VEX_0F3847 */
6085 {
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6089 },
6090
6091 /* PREFIX_VEX_0F3858 */
6092 {
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6096 },
6097
6098 /* PREFIX_VEX_0F3859 */
6099 {
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6103 },
6104
6105 /* PREFIX_VEX_0F385A */
6106 {
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6110 },
6111
6112 /* PREFIX_VEX_0F3878 */
6113 {
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6117 },
6118
6119 /* PREFIX_VEX_0F3879 */
6120 {
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6124 },
6125
6126 /* PREFIX_VEX_0F388C */
6127 {
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6131 },
6132
6133 /* PREFIX_VEX_0F388E */
6134 {
6135 { Bad_Opcode },
6136 { Bad_Opcode },
6137 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6138 },
6139
6140 /* PREFIX_VEX_0F3890 */
6141 {
6142 { Bad_Opcode },
6143 { Bad_Opcode },
6144 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6145 },
6146
6147 /* PREFIX_VEX_0F3891 */
6148 {
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6152 },
6153
6154 /* PREFIX_VEX_0F3892 */
6155 {
6156 { Bad_Opcode },
6157 { Bad_Opcode },
6158 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6159 },
6160
6161 /* PREFIX_VEX_0F3893 */
6162 {
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6166 },
6167
6168 /* PREFIX_VEX_0F3896 */
6169 {
6170 { Bad_Opcode },
6171 { Bad_Opcode },
6172 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6173 },
6174
6175 /* PREFIX_VEX_0F3897 */
6176 {
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6180 },
6181
6182 /* PREFIX_VEX_0F3898 */
6183 {
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6187 },
6188
6189 /* PREFIX_VEX_0F3899 */
6190 {
6191 { Bad_Opcode },
6192 { Bad_Opcode },
6193 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6194 },
6195
6196 /* PREFIX_VEX_0F389A */
6197 {
6198 { Bad_Opcode },
6199 { Bad_Opcode },
6200 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6201 },
6202
6203 /* PREFIX_VEX_0F389B */
6204 {
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6208 },
6209
6210 /* PREFIX_VEX_0F389C */
6211 {
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6215 },
6216
6217 /* PREFIX_VEX_0F389D */
6218 {
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6222 },
6223
6224 /* PREFIX_VEX_0F389E */
6225 {
6226 { Bad_Opcode },
6227 { Bad_Opcode },
6228 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6229 },
6230
6231 /* PREFIX_VEX_0F389F */
6232 {
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6236 },
6237
6238 /* PREFIX_VEX_0F38A6 */
6239 {
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6243 { Bad_Opcode },
6244 },
6245
6246 /* PREFIX_VEX_0F38A7 */
6247 {
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6251 },
6252
6253 /* PREFIX_VEX_0F38A8 */
6254 {
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6258 },
6259
6260 /* PREFIX_VEX_0F38A9 */
6261 {
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6265 },
6266
6267 /* PREFIX_VEX_0F38AA */
6268 {
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6272 },
6273
6274 /* PREFIX_VEX_0F38AB */
6275 {
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6279 },
6280
6281 /* PREFIX_VEX_0F38AC */
6282 {
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6286 },
6287
6288 /* PREFIX_VEX_0F38AD */
6289 {
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6293 },
6294
6295 /* PREFIX_VEX_0F38AE */
6296 {
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6300 },
6301
6302 /* PREFIX_VEX_0F38AF */
6303 {
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6307 },
6308
6309 /* PREFIX_VEX_0F38B6 */
6310 {
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6314 },
6315
6316 /* PREFIX_VEX_0F38B7 */
6317 {
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6321 },
6322
6323 /* PREFIX_VEX_0F38B8 */
6324 {
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6328 },
6329
6330 /* PREFIX_VEX_0F38B9 */
6331 {
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6334 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6335 },
6336
6337 /* PREFIX_VEX_0F38BA */
6338 {
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6342 },
6343
6344 /* PREFIX_VEX_0F38BB */
6345 {
6346 { Bad_Opcode },
6347 { Bad_Opcode },
6348 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6349 },
6350
6351 /* PREFIX_VEX_0F38BC */
6352 {
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6356 },
6357
6358 /* PREFIX_VEX_0F38BD */
6359 {
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6363 },
6364
6365 /* PREFIX_VEX_0F38BE */
6366 {
6367 { Bad_Opcode },
6368 { Bad_Opcode },
6369 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6370 },
6371
6372 /* PREFIX_VEX_0F38BF */
6373 {
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6377 },
6378
6379 /* PREFIX_VEX_0F38CF */
6380 {
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6384 },
6385
6386 /* PREFIX_VEX_0F38DB */
6387 {
6388 { Bad_Opcode },
6389 { Bad_Opcode },
6390 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6391 },
6392
6393 /* PREFIX_VEX_0F38DC */
6394 {
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6398 },
6399
6400 /* PREFIX_VEX_0F38DD */
6401 {
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6405 },
6406
6407 /* PREFIX_VEX_0F38DE */
6408 {
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6412 },
6413
6414 /* PREFIX_VEX_0F38DF */
6415 {
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6419 },
6420
6421 /* PREFIX_VEX_0F38F2 */
6422 {
6423 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6424 },
6425
6426 /* PREFIX_VEX_0F38F3_REG_1 */
6427 {
6428 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6429 },
6430
6431 /* PREFIX_VEX_0F38F3_REG_2 */
6432 {
6433 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6434 },
6435
6436 /* PREFIX_VEX_0F38F3_REG_3 */
6437 {
6438 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6439 },
6440
6441 /* PREFIX_VEX_0F38F5 */
6442 {
6443 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6444 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6445 { Bad_Opcode },
6446 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6447 },
6448
6449 /* PREFIX_VEX_0F38F6 */
6450 {
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6455 },
6456
6457 /* PREFIX_VEX_0F38F7 */
6458 {
6459 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6460 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6461 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6462 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6463 },
6464
6465 /* PREFIX_VEX_0F3A00 */
6466 {
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6470 },
6471
6472 /* PREFIX_VEX_0F3A01 */
6473 {
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6477 },
6478
6479 /* PREFIX_VEX_0F3A02 */
6480 {
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6484 },
6485
6486 /* PREFIX_VEX_0F3A04 */
6487 {
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6491 },
6492
6493 /* PREFIX_VEX_0F3A05 */
6494 {
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6498 },
6499
6500 /* PREFIX_VEX_0F3A06 */
6501 {
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6505 },
6506
6507 /* PREFIX_VEX_0F3A08 */
6508 {
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6512 },
6513
6514 /* PREFIX_VEX_0F3A09 */
6515 {
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6519 },
6520
6521 /* PREFIX_VEX_0F3A0A */
6522 {
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6526 },
6527
6528 /* PREFIX_VEX_0F3A0B */
6529 {
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6533 },
6534
6535 /* PREFIX_VEX_0F3A0C */
6536 {
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6540 },
6541
6542 /* PREFIX_VEX_0F3A0D */
6543 {
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6547 },
6548
6549 /* PREFIX_VEX_0F3A0E */
6550 {
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6554 },
6555
6556 /* PREFIX_VEX_0F3A0F */
6557 {
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6561 },
6562
6563 /* PREFIX_VEX_0F3A14 */
6564 {
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6568 },
6569
6570 /* PREFIX_VEX_0F3A15 */
6571 {
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6575 },
6576
6577 /* PREFIX_VEX_0F3A16 */
6578 {
6579 { Bad_Opcode },
6580 { Bad_Opcode },
6581 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6582 },
6583
6584 /* PREFIX_VEX_0F3A17 */
6585 {
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6589 },
6590
6591 /* PREFIX_VEX_0F3A18 */
6592 {
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6596 },
6597
6598 /* PREFIX_VEX_0F3A19 */
6599 {
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6603 },
6604
6605 /* PREFIX_VEX_0F3A1D */
6606 {
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6610 },
6611
6612 /* PREFIX_VEX_0F3A20 */
6613 {
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6617 },
6618
6619 /* PREFIX_VEX_0F3A21 */
6620 {
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6624 },
6625
6626 /* PREFIX_VEX_0F3A22 */
6627 {
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6631 },
6632
6633 /* PREFIX_VEX_0F3A30 */
6634 {
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6638 },
6639
6640 /* PREFIX_VEX_0F3A31 */
6641 {
6642 { Bad_Opcode },
6643 { Bad_Opcode },
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6645 },
6646
6647 /* PREFIX_VEX_0F3A32 */
6648 {
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6652 },
6653
6654 /* PREFIX_VEX_0F3A33 */
6655 {
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6659 },
6660
6661 /* PREFIX_VEX_0F3A38 */
6662 {
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6666 },
6667
6668 /* PREFIX_VEX_0F3A39 */
6669 {
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6673 },
6674
6675 /* PREFIX_VEX_0F3A40 */
6676 {
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6680 },
6681
6682 /* PREFIX_VEX_0F3A41 */
6683 {
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6687 },
6688
6689 /* PREFIX_VEX_0F3A42 */
6690 {
6691 { Bad_Opcode },
6692 { Bad_Opcode },
6693 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6694 },
6695
6696 /* PREFIX_VEX_0F3A44 */
6697 {
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6701 },
6702
6703 /* PREFIX_VEX_0F3A46 */
6704 {
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6708 },
6709
6710 /* PREFIX_VEX_0F3A48 */
6711 {
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6715 },
6716
6717 /* PREFIX_VEX_0F3A49 */
6718 {
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6722 },
6723
6724 /* PREFIX_VEX_0F3A4A */
6725 {
6726 { Bad_Opcode },
6727 { Bad_Opcode },
6728 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6729 },
6730
6731 /* PREFIX_VEX_0F3A4B */
6732 {
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6736 },
6737
6738 /* PREFIX_VEX_0F3A4C */
6739 {
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6743 },
6744
6745 /* PREFIX_VEX_0F3A5C */
6746 {
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6750 },
6751
6752 /* PREFIX_VEX_0F3A5D */
6753 {
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6757 },
6758
6759 /* PREFIX_VEX_0F3A5E */
6760 {
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6764 },
6765
6766 /* PREFIX_VEX_0F3A5F */
6767 {
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6771 },
6772
6773 /* PREFIX_VEX_0F3A60 */
6774 {
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6778 { Bad_Opcode },
6779 },
6780
6781 /* PREFIX_VEX_0F3A61 */
6782 {
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6786 },
6787
6788 /* PREFIX_VEX_0F3A62 */
6789 {
6790 { Bad_Opcode },
6791 { Bad_Opcode },
6792 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6793 },
6794
6795 /* PREFIX_VEX_0F3A63 */
6796 {
6797 { Bad_Opcode },
6798 { Bad_Opcode },
6799 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6800 },
6801
6802 /* PREFIX_VEX_0F3A68 */
6803 {
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6807 },
6808
6809 /* PREFIX_VEX_0F3A69 */
6810 {
6811 { Bad_Opcode },
6812 { Bad_Opcode },
6813 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6814 },
6815
6816 /* PREFIX_VEX_0F3A6A */
6817 {
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6821 },
6822
6823 /* PREFIX_VEX_0F3A6B */
6824 {
6825 { Bad_Opcode },
6826 { Bad_Opcode },
6827 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6828 },
6829
6830 /* PREFIX_VEX_0F3A6C */
6831 {
6832 { Bad_Opcode },
6833 { Bad_Opcode },
6834 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6835 },
6836
6837 /* PREFIX_VEX_0F3A6D */
6838 {
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6842 },
6843
6844 /* PREFIX_VEX_0F3A6E */
6845 {
6846 { Bad_Opcode },
6847 { Bad_Opcode },
6848 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6849 },
6850
6851 /* PREFIX_VEX_0F3A6F */
6852 {
6853 { Bad_Opcode },
6854 { Bad_Opcode },
6855 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6856 },
6857
6858 /* PREFIX_VEX_0F3A78 */
6859 {
6860 { Bad_Opcode },
6861 { Bad_Opcode },
6862 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6863 },
6864
6865 /* PREFIX_VEX_0F3A79 */
6866 {
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6870 },
6871
6872 /* PREFIX_VEX_0F3A7A */
6873 {
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6877 },
6878
6879 /* PREFIX_VEX_0F3A7B */
6880 {
6881 { Bad_Opcode },
6882 { Bad_Opcode },
6883 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6884 },
6885
6886 /* PREFIX_VEX_0F3A7C */
6887 {
6888 { Bad_Opcode },
6889 { Bad_Opcode },
6890 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6891 { Bad_Opcode },
6892 },
6893
6894 /* PREFIX_VEX_0F3A7D */
6895 {
6896 { Bad_Opcode },
6897 { Bad_Opcode },
6898 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6899 },
6900
6901 /* PREFIX_VEX_0F3A7E */
6902 {
6903 { Bad_Opcode },
6904 { Bad_Opcode },
6905 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6906 },
6907
6908 /* PREFIX_VEX_0F3A7F */
6909 {
6910 { Bad_Opcode },
6911 { Bad_Opcode },
6912 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6913 },
6914
6915 /* PREFIX_VEX_0F3ACE */
6916 {
6917 { Bad_Opcode },
6918 { Bad_Opcode },
6919 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6920 },
6921
6922 /* PREFIX_VEX_0F3ACF */
6923 {
6924 { Bad_Opcode },
6925 { Bad_Opcode },
6926 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6927 },
6928
6929 /* PREFIX_VEX_0F3ADF */
6930 {
6931 { Bad_Opcode },
6932 { Bad_Opcode },
6933 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6934 },
6935
6936 /* PREFIX_VEX_0F3AF0 */
6937 {
6938 { Bad_Opcode },
6939 { Bad_Opcode },
6940 { Bad_Opcode },
6941 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6942 },
6943
6944#define NEED_PREFIX_TABLE
6945#include "i386-dis-evex.h"
6946#undef NEED_PREFIX_TABLE
6947};
6948
6949static const struct dis386 x86_64_table[][2] = {
6950 /* X86_64_06 */
6951 {
6952 { "pushP", { es }, 0 },
6953 },
6954
6955 /* X86_64_07 */
6956 {
6957 { "popP", { es }, 0 },
6958 },
6959
6960 /* X86_64_0D */
6961 {
6962 { "pushP", { cs }, 0 },
6963 },
6964
6965 /* X86_64_16 */
6966 {
6967 { "pushP", { ss }, 0 },
6968 },
6969
6970 /* X86_64_17 */
6971 {
6972 { "popP", { ss }, 0 },
6973 },
6974
6975 /* X86_64_1E */
6976 {
6977 { "pushP", { ds }, 0 },
6978 },
6979
6980 /* X86_64_1F */
6981 {
6982 { "popP", { ds }, 0 },
6983 },
6984
6985 /* X86_64_27 */
6986 {
6987 { "daa", { XX }, 0 },
6988 },
6989
6990 /* X86_64_2F */
6991 {
6992 { "das", { XX }, 0 },
6993 },
6994
6995 /* X86_64_37 */
6996 {
6997 { "aaa", { XX }, 0 },
6998 },
6999
7000 /* X86_64_3F */
7001 {
7002 { "aas", { XX }, 0 },
7003 },
7004
7005 /* X86_64_60 */
7006 {
7007 { "pushaP", { XX }, 0 },
7008 },
7009
7010 /* X86_64_61 */
7011 {
7012 { "popaP", { XX }, 0 },
7013 },
7014
7015 /* X86_64_62 */
7016 {
7017 { MOD_TABLE (MOD_62_32BIT) },
7018 { EVEX_TABLE (EVEX_0F) },
7019 },
7020
7021 /* X86_64_63 */
7022 {
7023 { "arpl", { Ew, Gw }, 0 },
7024 { "movs{lq|xd}", { Gv, Ed }, 0 },
7025 },
7026
7027 /* X86_64_6D */
7028 {
7029 { "ins{R|}", { Yzr, indirDX }, 0 },
7030 { "ins{G|}", { Yzr, indirDX }, 0 },
7031 },
7032
7033 /* X86_64_6F */
7034 {
7035 { "outs{R|}", { indirDXr, Xz }, 0 },
7036 { "outs{G|}", { indirDXr, Xz }, 0 },
7037 },
7038
7039 /* X86_64_82 */
7040 {
7041 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7042 { REG_TABLE (REG_80) },
7043 },
7044
7045 /* X86_64_9A */
7046 {
7047 { "Jcall{T|}", { Ap }, 0 },
7048 },
7049
7050 /* X86_64_C4 */
7051 {
7052 { MOD_TABLE (MOD_C4_32BIT) },
7053 { VEX_C4_TABLE (VEX_0F) },
7054 },
7055
7056 /* X86_64_C5 */
7057 {
7058 { MOD_TABLE (MOD_C5_32BIT) },
7059 { VEX_C5_TABLE (VEX_0F) },
7060 },
7061
7062 /* X86_64_CE */
7063 {
7064 { "into", { XX }, 0 },
7065 },
7066
7067 /* X86_64_D4 */
7068 {
7069 { "aam", { Ib }, 0 },
7070 },
7071
7072 /* X86_64_D5 */
7073 {
7074 { "aad", { Ib }, 0 },
7075 },
7076
7077 /* X86_64_E8 */
7078 {
7079 { "callP", { Jv, BND }, 0 },
7080 { "call@", { Jv, BND }, 0 }
7081 },
7082
7083 /* X86_64_E9 */
7084 {
7085 { "jmpP", { Jv, BND }, 0 },
7086 { "jmp@", { Jv, BND }, 0 }
7087 },
7088
7089 /* X86_64_EA */
7090 {
7091 { "Jjmp{T|}", { Ap }, 0 },
7092 },
7093
7094 /* X86_64_0F01_REG_0 */
7095 {
7096 { "sgdt{Q|IQ}", { M }, 0 },
7097 { "sgdt", { M }, 0 },
7098 },
7099
7100 /* X86_64_0F01_REG_1 */
7101 {
7102 { "sidt{Q|IQ}", { M }, 0 },
7103 { "sidt", { M }, 0 },
7104 },
7105
7106 /* X86_64_0F01_REG_2 */
7107 {
7108 { "lgdt{Q|Q}", { M }, 0 },
7109 { "lgdt", { M }, 0 },
7110 },
7111
7112 /* X86_64_0F01_REG_3 */
7113 {
7114 { "lidt{Q|Q}", { M }, 0 },
7115 { "lidt", { M }, 0 },
7116 },
7117};
7118
7119static const struct dis386 three_byte_table[][256] = {
7120
7121 /* THREE_BYTE_0F38 */
7122 {
7123 /* 00 */
7124 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7125 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7126 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7127 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7128 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7129 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7130 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7131 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7132 /* 08 */
7133 { "psignb", { MX, EM }, PREFIX_OPCODE },
7134 { "psignw", { MX, EM }, PREFIX_OPCODE },
7135 { "psignd", { MX, EM }, PREFIX_OPCODE },
7136 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7137 { Bad_Opcode },
7138 { Bad_Opcode },
7139 { Bad_Opcode },
7140 { Bad_Opcode },
7141 /* 10 */
7142 { PREFIX_TABLE (PREFIX_0F3810) },
7143 { Bad_Opcode },
7144 { Bad_Opcode },
7145 { Bad_Opcode },
7146 { PREFIX_TABLE (PREFIX_0F3814) },
7147 { PREFIX_TABLE (PREFIX_0F3815) },
7148 { Bad_Opcode },
7149 { PREFIX_TABLE (PREFIX_0F3817) },
7150 /* 18 */
7151 { Bad_Opcode },
7152 { Bad_Opcode },
7153 { Bad_Opcode },
7154 { Bad_Opcode },
7155 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7156 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7157 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7158 { Bad_Opcode },
7159 /* 20 */
7160 { PREFIX_TABLE (PREFIX_0F3820) },
7161 { PREFIX_TABLE (PREFIX_0F3821) },
7162 { PREFIX_TABLE (PREFIX_0F3822) },
7163 { PREFIX_TABLE (PREFIX_0F3823) },
7164 { PREFIX_TABLE (PREFIX_0F3824) },
7165 { PREFIX_TABLE (PREFIX_0F3825) },
7166 { Bad_Opcode },
7167 { Bad_Opcode },
7168 /* 28 */
7169 { PREFIX_TABLE (PREFIX_0F3828) },
7170 { PREFIX_TABLE (PREFIX_0F3829) },
7171 { PREFIX_TABLE (PREFIX_0F382A) },
7172 { PREFIX_TABLE (PREFIX_0F382B) },
7173 { Bad_Opcode },
7174 { Bad_Opcode },
7175 { Bad_Opcode },
7176 { Bad_Opcode },
7177 /* 30 */
7178 { PREFIX_TABLE (PREFIX_0F3830) },
7179 { PREFIX_TABLE (PREFIX_0F3831) },
7180 { PREFIX_TABLE (PREFIX_0F3832) },
7181 { PREFIX_TABLE (PREFIX_0F3833) },
7182 { PREFIX_TABLE (PREFIX_0F3834) },
7183 { PREFIX_TABLE (PREFIX_0F3835) },
7184 { Bad_Opcode },
7185 { PREFIX_TABLE (PREFIX_0F3837) },
7186 /* 38 */
7187 { PREFIX_TABLE (PREFIX_0F3838) },
7188 { PREFIX_TABLE (PREFIX_0F3839) },
7189 { PREFIX_TABLE (PREFIX_0F383A) },
7190 { PREFIX_TABLE (PREFIX_0F383B) },
7191 { PREFIX_TABLE (PREFIX_0F383C) },
7192 { PREFIX_TABLE (PREFIX_0F383D) },
7193 { PREFIX_TABLE (PREFIX_0F383E) },
7194 { PREFIX_TABLE (PREFIX_0F383F) },
7195 /* 40 */
7196 { PREFIX_TABLE (PREFIX_0F3840) },
7197 { PREFIX_TABLE (PREFIX_0F3841) },
7198 { Bad_Opcode },
7199 { Bad_Opcode },
7200 { Bad_Opcode },
7201 { Bad_Opcode },
7202 { Bad_Opcode },
7203 { Bad_Opcode },
7204 /* 48 */
7205 { Bad_Opcode },
7206 { Bad_Opcode },
7207 { Bad_Opcode },
7208 { Bad_Opcode },
7209 { Bad_Opcode },
7210 { Bad_Opcode },
7211 { Bad_Opcode },
7212 { Bad_Opcode },
7213 /* 50 */
7214 { Bad_Opcode },
7215 { Bad_Opcode },
7216 { Bad_Opcode },
7217 { Bad_Opcode },
7218 { Bad_Opcode },
7219 { Bad_Opcode },
7220 { Bad_Opcode },
7221 { Bad_Opcode },
7222 /* 58 */
7223 { Bad_Opcode },
7224 { Bad_Opcode },
7225 { Bad_Opcode },
7226 { Bad_Opcode },
7227 { Bad_Opcode },
7228 { Bad_Opcode },
7229 { Bad_Opcode },
7230 { Bad_Opcode },
7231 /* 60 */
7232 { Bad_Opcode },
7233 { Bad_Opcode },
7234 { Bad_Opcode },
7235 { Bad_Opcode },
7236 { Bad_Opcode },
7237 { Bad_Opcode },
7238 { Bad_Opcode },
7239 { Bad_Opcode },
7240 /* 68 */
7241 { Bad_Opcode },
7242 { Bad_Opcode },
7243 { Bad_Opcode },
7244 { Bad_Opcode },
7245 { Bad_Opcode },
7246 { Bad_Opcode },
7247 { Bad_Opcode },
7248 { Bad_Opcode },
7249 /* 70 */
7250 { Bad_Opcode },
7251 { Bad_Opcode },
7252 { Bad_Opcode },
7253 { Bad_Opcode },
7254 { Bad_Opcode },
7255 { Bad_Opcode },
7256 { Bad_Opcode },
7257 { Bad_Opcode },
7258 /* 78 */
7259 { Bad_Opcode },
7260 { Bad_Opcode },
7261 { Bad_Opcode },
7262 { Bad_Opcode },
7263 { Bad_Opcode },
7264 { Bad_Opcode },
7265 { Bad_Opcode },
7266 { Bad_Opcode },
7267 /* 80 */
7268 { PREFIX_TABLE (PREFIX_0F3880) },
7269 { PREFIX_TABLE (PREFIX_0F3881) },
7270 { PREFIX_TABLE (PREFIX_0F3882) },
7271 { Bad_Opcode },
7272 { Bad_Opcode },
7273 { Bad_Opcode },
7274 { Bad_Opcode },
7275 { Bad_Opcode },
7276 /* 88 */
7277 { Bad_Opcode },
7278 { Bad_Opcode },
7279 { Bad_Opcode },
7280 { Bad_Opcode },
7281 { Bad_Opcode },
7282 { Bad_Opcode },
7283 { Bad_Opcode },
7284 { Bad_Opcode },
7285 /* 90 */
7286 { Bad_Opcode },
7287 { Bad_Opcode },
7288 { Bad_Opcode },
7289 { Bad_Opcode },
7290 { Bad_Opcode },
7291 { Bad_Opcode },
7292 { Bad_Opcode },
7293 { Bad_Opcode },
7294 /* 98 */
7295 { Bad_Opcode },
7296 { Bad_Opcode },
7297 { Bad_Opcode },
7298 { Bad_Opcode },
7299 { Bad_Opcode },
7300 { Bad_Opcode },
7301 { Bad_Opcode },
7302 { Bad_Opcode },
7303 /* a0 */
7304 { Bad_Opcode },
7305 { Bad_Opcode },
7306 { Bad_Opcode },
7307 { Bad_Opcode },
7308 { Bad_Opcode },
7309 { Bad_Opcode },
7310 { Bad_Opcode },
7311 { Bad_Opcode },
7312 /* a8 */
7313 { Bad_Opcode },
7314 { Bad_Opcode },
7315 { Bad_Opcode },
7316 { Bad_Opcode },
7317 { Bad_Opcode },
7318 { Bad_Opcode },
7319 { Bad_Opcode },
7320 { Bad_Opcode },
7321 /* b0 */
7322 { Bad_Opcode },
7323 { Bad_Opcode },
7324 { Bad_Opcode },
7325 { Bad_Opcode },
7326 { Bad_Opcode },
7327 { Bad_Opcode },
7328 { Bad_Opcode },
7329 { Bad_Opcode },
7330 /* b8 */
7331 { Bad_Opcode },
7332 { Bad_Opcode },
7333 { Bad_Opcode },
7334 { Bad_Opcode },
7335 { Bad_Opcode },
7336 { Bad_Opcode },
7337 { Bad_Opcode },
7338 { Bad_Opcode },
7339 /* c0 */
7340 { Bad_Opcode },
7341 { Bad_Opcode },
7342 { Bad_Opcode },
7343 { Bad_Opcode },
7344 { Bad_Opcode },
7345 { Bad_Opcode },
7346 { Bad_Opcode },
7347 { Bad_Opcode },
7348 /* c8 */
7349 { PREFIX_TABLE (PREFIX_0F38C8) },
7350 { PREFIX_TABLE (PREFIX_0F38C9) },
7351 { PREFIX_TABLE (PREFIX_0F38CA) },
7352 { PREFIX_TABLE (PREFIX_0F38CB) },
7353 { PREFIX_TABLE (PREFIX_0F38CC) },
7354 { PREFIX_TABLE (PREFIX_0F38CD) },
7355 { Bad_Opcode },
7356 { PREFIX_TABLE (PREFIX_0F38CF) },
7357 /* d0 */
7358 { Bad_Opcode },
7359 { Bad_Opcode },
7360 { Bad_Opcode },
7361 { Bad_Opcode },
7362 { Bad_Opcode },
7363 { Bad_Opcode },
7364 { Bad_Opcode },
7365 { Bad_Opcode },
7366 /* d8 */
7367 { Bad_Opcode },
7368 { Bad_Opcode },
7369 { Bad_Opcode },
7370 { PREFIX_TABLE (PREFIX_0F38DB) },
7371 { PREFIX_TABLE (PREFIX_0F38DC) },
7372 { PREFIX_TABLE (PREFIX_0F38DD) },
7373 { PREFIX_TABLE (PREFIX_0F38DE) },
7374 { PREFIX_TABLE (PREFIX_0F38DF) },
7375 /* e0 */
7376 { Bad_Opcode },
7377 { Bad_Opcode },
7378 { Bad_Opcode },
7379 { Bad_Opcode },
7380 { Bad_Opcode },
7381 { Bad_Opcode },
7382 { Bad_Opcode },
7383 { Bad_Opcode },
7384 /* e8 */
7385 { Bad_Opcode },
7386 { Bad_Opcode },
7387 { Bad_Opcode },
7388 { Bad_Opcode },
7389 { Bad_Opcode },
7390 { Bad_Opcode },
7391 { Bad_Opcode },
7392 { Bad_Opcode },
7393 /* f0 */
7394 { PREFIX_TABLE (PREFIX_0F38F0) },
7395 { PREFIX_TABLE (PREFIX_0F38F1) },
7396 { Bad_Opcode },
7397 { Bad_Opcode },
7398 { Bad_Opcode },
7399 { PREFIX_TABLE (PREFIX_0F38F5) },
7400 { PREFIX_TABLE (PREFIX_0F38F6) },
7401 { Bad_Opcode },
7402 /* f8 */
7403 { Bad_Opcode },
7404 { Bad_Opcode },
7405 { Bad_Opcode },
7406 { Bad_Opcode },
7407 { Bad_Opcode },
7408 { Bad_Opcode },
7409 { Bad_Opcode },
7410 { Bad_Opcode },
7411 },
7412 /* THREE_BYTE_0F3A */
7413 {
7414 /* 00 */
7415 { Bad_Opcode },
7416 { Bad_Opcode },
7417 { Bad_Opcode },
7418 { Bad_Opcode },
7419 { Bad_Opcode },
7420 { Bad_Opcode },
7421 { Bad_Opcode },
7422 { Bad_Opcode },
7423 /* 08 */
7424 { PREFIX_TABLE (PREFIX_0F3A08) },
7425 { PREFIX_TABLE (PREFIX_0F3A09) },
7426 { PREFIX_TABLE (PREFIX_0F3A0A) },
7427 { PREFIX_TABLE (PREFIX_0F3A0B) },
7428 { PREFIX_TABLE (PREFIX_0F3A0C) },
7429 { PREFIX_TABLE (PREFIX_0F3A0D) },
7430 { PREFIX_TABLE (PREFIX_0F3A0E) },
7431 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7432 /* 10 */
7433 { Bad_Opcode },
7434 { Bad_Opcode },
7435 { Bad_Opcode },
7436 { Bad_Opcode },
7437 { PREFIX_TABLE (PREFIX_0F3A14) },
7438 { PREFIX_TABLE (PREFIX_0F3A15) },
7439 { PREFIX_TABLE (PREFIX_0F3A16) },
7440 { PREFIX_TABLE (PREFIX_0F3A17) },
7441 /* 18 */
7442 { Bad_Opcode },
7443 { Bad_Opcode },
7444 { Bad_Opcode },
7445 { Bad_Opcode },
7446 { Bad_Opcode },
7447 { Bad_Opcode },
7448 { Bad_Opcode },
7449 { Bad_Opcode },
7450 /* 20 */
7451 { PREFIX_TABLE (PREFIX_0F3A20) },
7452 { PREFIX_TABLE (PREFIX_0F3A21) },
7453 { PREFIX_TABLE (PREFIX_0F3A22) },
7454 { Bad_Opcode },
7455 { Bad_Opcode },
7456 { Bad_Opcode },
7457 { Bad_Opcode },
7458 { Bad_Opcode },
7459 /* 28 */
7460 { Bad_Opcode },
7461 { Bad_Opcode },
7462 { Bad_Opcode },
7463 { Bad_Opcode },
7464 { Bad_Opcode },
7465 { Bad_Opcode },
7466 { Bad_Opcode },
7467 { Bad_Opcode },
7468 /* 30 */
7469 { Bad_Opcode },
7470 { Bad_Opcode },
7471 { Bad_Opcode },
7472 { Bad_Opcode },
7473 { Bad_Opcode },
7474 { Bad_Opcode },
7475 { Bad_Opcode },
7476 { Bad_Opcode },
7477 /* 38 */
7478 { Bad_Opcode },
7479 { Bad_Opcode },
7480 { Bad_Opcode },
7481 { Bad_Opcode },
7482 { Bad_Opcode },
7483 { Bad_Opcode },
7484 { Bad_Opcode },
7485 { Bad_Opcode },
7486 /* 40 */
7487 { PREFIX_TABLE (PREFIX_0F3A40) },
7488 { PREFIX_TABLE (PREFIX_0F3A41) },
7489 { PREFIX_TABLE (PREFIX_0F3A42) },
7490 { Bad_Opcode },
7491 { PREFIX_TABLE (PREFIX_0F3A44) },
7492 { Bad_Opcode },
7493 { Bad_Opcode },
7494 { Bad_Opcode },
7495 /* 48 */
7496 { Bad_Opcode },
7497 { Bad_Opcode },
7498 { Bad_Opcode },
7499 { Bad_Opcode },
7500 { Bad_Opcode },
7501 { Bad_Opcode },
7502 { Bad_Opcode },
7503 { Bad_Opcode },
7504 /* 50 */
7505 { Bad_Opcode },
7506 { Bad_Opcode },
7507 { Bad_Opcode },
7508 { Bad_Opcode },
7509 { Bad_Opcode },
7510 { Bad_Opcode },
7511 { Bad_Opcode },
7512 { Bad_Opcode },
7513 /* 58 */
7514 { Bad_Opcode },
7515 { Bad_Opcode },
7516 { Bad_Opcode },
7517 { Bad_Opcode },
7518 { Bad_Opcode },
7519 { Bad_Opcode },
7520 { Bad_Opcode },
7521 { Bad_Opcode },
7522 /* 60 */
7523 { PREFIX_TABLE (PREFIX_0F3A60) },
7524 { PREFIX_TABLE (PREFIX_0F3A61) },
7525 { PREFIX_TABLE (PREFIX_0F3A62) },
7526 { PREFIX_TABLE (PREFIX_0F3A63) },
7527 { Bad_Opcode },
7528 { Bad_Opcode },
7529 { Bad_Opcode },
7530 { Bad_Opcode },
7531 /* 68 */
7532 { Bad_Opcode },
7533 { Bad_Opcode },
7534 { Bad_Opcode },
7535 { Bad_Opcode },
7536 { Bad_Opcode },
7537 { Bad_Opcode },
7538 { Bad_Opcode },
7539 { Bad_Opcode },
7540 /* 70 */
7541 { Bad_Opcode },
7542 { Bad_Opcode },
7543 { Bad_Opcode },
7544 { Bad_Opcode },
7545 { Bad_Opcode },
7546 { Bad_Opcode },
7547 { Bad_Opcode },
7548 { Bad_Opcode },
7549 /* 78 */
7550 { Bad_Opcode },
7551 { Bad_Opcode },
7552 { Bad_Opcode },
7553 { Bad_Opcode },
7554 { Bad_Opcode },
7555 { Bad_Opcode },
7556 { Bad_Opcode },
7557 { Bad_Opcode },
7558 /* 80 */
7559 { Bad_Opcode },
7560 { Bad_Opcode },
7561 { Bad_Opcode },
7562 { Bad_Opcode },
7563 { Bad_Opcode },
7564 { Bad_Opcode },
7565 { Bad_Opcode },
7566 { Bad_Opcode },
7567 /* 88 */
7568 { Bad_Opcode },
7569 { Bad_Opcode },
7570 { Bad_Opcode },
7571 { Bad_Opcode },
7572 { Bad_Opcode },
7573 { Bad_Opcode },
7574 { Bad_Opcode },
7575 { Bad_Opcode },
7576 /* 90 */
7577 { Bad_Opcode },
7578 { Bad_Opcode },
7579 { Bad_Opcode },
7580 { Bad_Opcode },
7581 { Bad_Opcode },
7582 { Bad_Opcode },
7583 { Bad_Opcode },
7584 { Bad_Opcode },
7585 /* 98 */
7586 { Bad_Opcode },
7587 { Bad_Opcode },
7588 { Bad_Opcode },
7589 { Bad_Opcode },
7590 { Bad_Opcode },
7591 { Bad_Opcode },
7592 { Bad_Opcode },
7593 { Bad_Opcode },
7594 /* a0 */
7595 { Bad_Opcode },
7596 { Bad_Opcode },
7597 { Bad_Opcode },
7598 { Bad_Opcode },
7599 { Bad_Opcode },
7600 { Bad_Opcode },
7601 { Bad_Opcode },
7602 { Bad_Opcode },
7603 /* a8 */
7604 { Bad_Opcode },
7605 { Bad_Opcode },
7606 { Bad_Opcode },
7607 { Bad_Opcode },
7608 { Bad_Opcode },
7609 { Bad_Opcode },
7610 { Bad_Opcode },
7611 { Bad_Opcode },
7612 /* b0 */
7613 { Bad_Opcode },
7614 { Bad_Opcode },
7615 { Bad_Opcode },
7616 { Bad_Opcode },
7617 { Bad_Opcode },
7618 { Bad_Opcode },
7619 { Bad_Opcode },
7620 { Bad_Opcode },
7621 /* b8 */
7622 { Bad_Opcode },
7623 { Bad_Opcode },
7624 { Bad_Opcode },
7625 { Bad_Opcode },
7626 { Bad_Opcode },
7627 { Bad_Opcode },
7628 { Bad_Opcode },
7629 { Bad_Opcode },
7630 /* c0 */
7631 { Bad_Opcode },
7632 { Bad_Opcode },
7633 { Bad_Opcode },
7634 { Bad_Opcode },
7635 { Bad_Opcode },
7636 { Bad_Opcode },
7637 { Bad_Opcode },
7638 { Bad_Opcode },
7639 /* c8 */
7640 { Bad_Opcode },
7641 { Bad_Opcode },
7642 { Bad_Opcode },
7643 { Bad_Opcode },
7644 { PREFIX_TABLE (PREFIX_0F3ACC) },
7645 { Bad_Opcode },
7646 { PREFIX_TABLE (PREFIX_0F3ACE) },
7647 { PREFIX_TABLE (PREFIX_0F3ACF) },
7648 /* d0 */
7649 { Bad_Opcode },
7650 { Bad_Opcode },
7651 { Bad_Opcode },
7652 { Bad_Opcode },
7653 { Bad_Opcode },
7654 { Bad_Opcode },
7655 { Bad_Opcode },
7656 { Bad_Opcode },
7657 /* d8 */
7658 { Bad_Opcode },
7659 { Bad_Opcode },
7660 { Bad_Opcode },
7661 { Bad_Opcode },
7662 { Bad_Opcode },
7663 { Bad_Opcode },
7664 { Bad_Opcode },
7665 { PREFIX_TABLE (PREFIX_0F3ADF) },
7666 /* e0 */
7667 { Bad_Opcode },
7668 { Bad_Opcode },
7669 { Bad_Opcode },
7670 { Bad_Opcode },
7671 { Bad_Opcode },
7672 { Bad_Opcode },
7673 { Bad_Opcode },
7674 { Bad_Opcode },
7675 /* e8 */
7676 { Bad_Opcode },
7677 { Bad_Opcode },
7678 { Bad_Opcode },
7679 { Bad_Opcode },
7680 { Bad_Opcode },
7681 { Bad_Opcode },
7682 { Bad_Opcode },
7683 { Bad_Opcode },
7684 /* f0 */
7685 { Bad_Opcode },
7686 { Bad_Opcode },
7687 { Bad_Opcode },
7688 { Bad_Opcode },
7689 { Bad_Opcode },
7690 { Bad_Opcode },
7691 { Bad_Opcode },
7692 { Bad_Opcode },
7693 /* f8 */
7694 { Bad_Opcode },
7695 { Bad_Opcode },
7696 { Bad_Opcode },
7697 { Bad_Opcode },
7698 { Bad_Opcode },
7699 { Bad_Opcode },
7700 { Bad_Opcode },
7701 { Bad_Opcode },
7702 },
7703};
7704
7705static const struct dis386 xop_table[][256] = {
7706 /* XOP_08 */
7707 {
7708 /* 00 */
7709 { Bad_Opcode },
7710 { Bad_Opcode },
7711 { Bad_Opcode },
7712 { Bad_Opcode },
7713 { Bad_Opcode },
7714 { Bad_Opcode },
7715 { Bad_Opcode },
7716 { Bad_Opcode },
7717 /* 08 */
7718 { Bad_Opcode },
7719 { Bad_Opcode },
7720 { Bad_Opcode },
7721 { Bad_Opcode },
7722 { Bad_Opcode },
7723 { Bad_Opcode },
7724 { Bad_Opcode },
7725 { Bad_Opcode },
7726 /* 10 */
7727 { Bad_Opcode },
7728 { Bad_Opcode },
7729 { Bad_Opcode },
7730 { Bad_Opcode },
7731 { Bad_Opcode },
7732 { Bad_Opcode },
7733 { Bad_Opcode },
7734 { Bad_Opcode },
7735 /* 18 */
7736 { Bad_Opcode },
7737 { Bad_Opcode },
7738 { Bad_Opcode },
7739 { Bad_Opcode },
7740 { Bad_Opcode },
7741 { Bad_Opcode },
7742 { Bad_Opcode },
7743 { Bad_Opcode },
7744 /* 20 */
7745 { Bad_Opcode },
7746 { Bad_Opcode },
7747 { Bad_Opcode },
7748 { Bad_Opcode },
7749 { Bad_Opcode },
7750 { Bad_Opcode },
7751 { Bad_Opcode },
7752 { Bad_Opcode },
7753 /* 28 */
7754 { Bad_Opcode },
7755 { Bad_Opcode },
7756 { Bad_Opcode },
7757 { Bad_Opcode },
7758 { Bad_Opcode },
7759 { Bad_Opcode },
7760 { Bad_Opcode },
7761 { Bad_Opcode },
7762 /* 30 */
7763 { Bad_Opcode },
7764 { Bad_Opcode },
7765 { Bad_Opcode },
7766 { Bad_Opcode },
7767 { Bad_Opcode },
7768 { Bad_Opcode },
7769 { Bad_Opcode },
7770 { Bad_Opcode },
7771 /* 38 */
7772 { Bad_Opcode },
7773 { Bad_Opcode },
7774 { Bad_Opcode },
7775 { Bad_Opcode },
7776 { Bad_Opcode },
7777 { Bad_Opcode },
7778 { Bad_Opcode },
7779 { Bad_Opcode },
7780 /* 40 */
7781 { Bad_Opcode },
7782 { Bad_Opcode },
7783 { Bad_Opcode },
7784 { Bad_Opcode },
7785 { Bad_Opcode },
7786 { Bad_Opcode },
7787 { Bad_Opcode },
7788 { Bad_Opcode },
7789 /* 48 */
7790 { Bad_Opcode },
7791 { Bad_Opcode },
7792 { Bad_Opcode },
7793 { Bad_Opcode },
7794 { Bad_Opcode },
7795 { Bad_Opcode },
7796 { Bad_Opcode },
7797 { Bad_Opcode },
7798 /* 50 */
7799 { Bad_Opcode },
7800 { Bad_Opcode },
7801 { Bad_Opcode },
7802 { Bad_Opcode },
7803 { Bad_Opcode },
7804 { Bad_Opcode },
7805 { Bad_Opcode },
7806 { Bad_Opcode },
7807 /* 58 */
7808 { Bad_Opcode },
7809 { Bad_Opcode },
7810 { Bad_Opcode },
7811 { Bad_Opcode },
7812 { Bad_Opcode },
7813 { Bad_Opcode },
7814 { Bad_Opcode },
7815 { Bad_Opcode },
7816 /* 60 */
7817 { Bad_Opcode },
7818 { Bad_Opcode },
7819 { Bad_Opcode },
7820 { Bad_Opcode },
7821 { Bad_Opcode },
7822 { Bad_Opcode },
7823 { Bad_Opcode },
7824 { Bad_Opcode },
7825 /* 68 */
7826 { Bad_Opcode },
7827 { Bad_Opcode },
7828 { Bad_Opcode },
7829 { Bad_Opcode },
7830 { Bad_Opcode },
7831 { Bad_Opcode },
7832 { Bad_Opcode },
7833 { Bad_Opcode },
7834 /* 70 */
7835 { Bad_Opcode },
7836 { Bad_Opcode },
7837 { Bad_Opcode },
7838 { Bad_Opcode },
7839 { Bad_Opcode },
7840 { Bad_Opcode },
7841 { Bad_Opcode },
7842 { Bad_Opcode },
7843 /* 78 */
7844 { Bad_Opcode },
7845 { Bad_Opcode },
7846 { Bad_Opcode },
7847 { Bad_Opcode },
7848 { Bad_Opcode },
7849 { Bad_Opcode },
7850 { Bad_Opcode },
7851 { Bad_Opcode },
7852 /* 80 */
7853 { Bad_Opcode },
7854 { Bad_Opcode },
7855 { Bad_Opcode },
7856 { Bad_Opcode },
7857 { Bad_Opcode },
7858 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7859 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7860 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7861 /* 88 */
7862 { Bad_Opcode },
7863 { Bad_Opcode },
7864 { Bad_Opcode },
7865 { Bad_Opcode },
7866 { Bad_Opcode },
7867 { Bad_Opcode },
7868 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7869 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7870 /* 90 */
7871 { Bad_Opcode },
7872 { Bad_Opcode },
7873 { Bad_Opcode },
7874 { Bad_Opcode },
7875 { Bad_Opcode },
7876 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7877 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7878 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7879 /* 98 */
7880 { Bad_Opcode },
7881 { Bad_Opcode },
7882 { Bad_Opcode },
7883 { Bad_Opcode },
7884 { Bad_Opcode },
7885 { Bad_Opcode },
7886 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7887 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7888 /* a0 */
7889 { Bad_Opcode },
7890 { Bad_Opcode },
7891 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7892 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7893 { Bad_Opcode },
7894 { Bad_Opcode },
7895 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7896 { Bad_Opcode },
7897 /* a8 */
7898 { Bad_Opcode },
7899 { Bad_Opcode },
7900 { Bad_Opcode },
7901 { Bad_Opcode },
7902 { Bad_Opcode },
7903 { Bad_Opcode },
7904 { Bad_Opcode },
7905 { Bad_Opcode },
7906 /* b0 */
7907 { Bad_Opcode },
7908 { Bad_Opcode },
7909 { Bad_Opcode },
7910 { Bad_Opcode },
7911 { Bad_Opcode },
7912 { Bad_Opcode },
7913 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7914 { Bad_Opcode },
7915 /* b8 */
7916 { Bad_Opcode },
7917 { Bad_Opcode },
7918 { Bad_Opcode },
7919 { Bad_Opcode },
7920 { Bad_Opcode },
7921 { Bad_Opcode },
7922 { Bad_Opcode },
7923 { Bad_Opcode },
7924 /* c0 */
7925 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7926 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7927 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7928 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7929 { Bad_Opcode },
7930 { Bad_Opcode },
7931 { Bad_Opcode },
7932 { Bad_Opcode },
7933 /* c8 */
7934 { Bad_Opcode },
7935 { Bad_Opcode },
7936 { Bad_Opcode },
7937 { Bad_Opcode },
7938 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7939 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7940 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7941 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7942 /* d0 */
7943 { Bad_Opcode },
7944 { Bad_Opcode },
7945 { Bad_Opcode },
7946 { Bad_Opcode },
7947 { Bad_Opcode },
7948 { Bad_Opcode },
7949 { Bad_Opcode },
7950 { Bad_Opcode },
7951 /* d8 */
7952 { Bad_Opcode },
7953 { Bad_Opcode },
7954 { Bad_Opcode },
7955 { Bad_Opcode },
7956 { Bad_Opcode },
7957 { Bad_Opcode },
7958 { Bad_Opcode },
7959 { Bad_Opcode },
7960 /* e0 */
7961 { Bad_Opcode },
7962 { Bad_Opcode },
7963 { Bad_Opcode },
7964 { Bad_Opcode },
7965 { Bad_Opcode },
7966 { Bad_Opcode },
7967 { Bad_Opcode },
7968 { Bad_Opcode },
7969 /* e8 */
7970 { Bad_Opcode },
7971 { Bad_Opcode },
7972 { Bad_Opcode },
7973 { Bad_Opcode },
7974 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7975 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7976 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7977 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7978 /* f0 */
7979 { Bad_Opcode },
7980 { Bad_Opcode },
7981 { Bad_Opcode },
7982 { Bad_Opcode },
7983 { Bad_Opcode },
7984 { Bad_Opcode },
7985 { Bad_Opcode },
7986 { Bad_Opcode },
7987 /* f8 */
7988 { Bad_Opcode },
7989 { Bad_Opcode },
7990 { Bad_Opcode },
7991 { Bad_Opcode },
7992 { Bad_Opcode },
7993 { Bad_Opcode },
7994 { Bad_Opcode },
7995 { Bad_Opcode },
7996 },
7997 /* XOP_09 */
7998 {
7999 /* 00 */
8000 { Bad_Opcode },
8001 { REG_TABLE (REG_XOP_TBM_01) },
8002 { REG_TABLE (REG_XOP_TBM_02) },
8003 { Bad_Opcode },
8004 { Bad_Opcode },
8005 { Bad_Opcode },
8006 { Bad_Opcode },
8007 { Bad_Opcode },
8008 /* 08 */
8009 { Bad_Opcode },
8010 { Bad_Opcode },
8011 { Bad_Opcode },
8012 { Bad_Opcode },
8013 { Bad_Opcode },
8014 { Bad_Opcode },
8015 { Bad_Opcode },
8016 { Bad_Opcode },
8017 /* 10 */
8018 { Bad_Opcode },
8019 { Bad_Opcode },
8020 { REG_TABLE (REG_XOP_LWPCB) },
8021 { Bad_Opcode },
8022 { Bad_Opcode },
8023 { Bad_Opcode },
8024 { Bad_Opcode },
8025 { Bad_Opcode },
8026 /* 18 */
8027 { Bad_Opcode },
8028 { Bad_Opcode },
8029 { Bad_Opcode },
8030 { Bad_Opcode },
8031 { Bad_Opcode },
8032 { Bad_Opcode },
8033 { Bad_Opcode },
8034 { Bad_Opcode },
8035 /* 20 */
8036 { Bad_Opcode },
8037 { Bad_Opcode },
8038 { Bad_Opcode },
8039 { Bad_Opcode },
8040 { Bad_Opcode },
8041 { Bad_Opcode },
8042 { Bad_Opcode },
8043 { Bad_Opcode },
8044 /* 28 */
8045 { Bad_Opcode },
8046 { Bad_Opcode },
8047 { Bad_Opcode },
8048 { Bad_Opcode },
8049 { Bad_Opcode },
8050 { Bad_Opcode },
8051 { Bad_Opcode },
8052 { Bad_Opcode },
8053 /* 30 */
8054 { Bad_Opcode },
8055 { Bad_Opcode },
8056 { Bad_Opcode },
8057 { Bad_Opcode },
8058 { Bad_Opcode },
8059 { Bad_Opcode },
8060 { Bad_Opcode },
8061 { Bad_Opcode },
8062 /* 38 */
8063 { Bad_Opcode },
8064 { Bad_Opcode },
8065 { Bad_Opcode },
8066 { Bad_Opcode },
8067 { Bad_Opcode },
8068 { Bad_Opcode },
8069 { Bad_Opcode },
8070 { Bad_Opcode },
8071 /* 40 */
8072 { Bad_Opcode },
8073 { Bad_Opcode },
8074 { Bad_Opcode },
8075 { Bad_Opcode },
8076 { Bad_Opcode },
8077 { Bad_Opcode },
8078 { Bad_Opcode },
8079 { Bad_Opcode },
8080 /* 48 */
8081 { Bad_Opcode },
8082 { Bad_Opcode },
8083 { Bad_Opcode },
8084 { Bad_Opcode },
8085 { Bad_Opcode },
8086 { Bad_Opcode },
8087 { Bad_Opcode },
8088 { Bad_Opcode },
8089 /* 50 */
8090 { Bad_Opcode },
8091 { Bad_Opcode },
8092 { Bad_Opcode },
8093 { Bad_Opcode },
8094 { Bad_Opcode },
8095 { Bad_Opcode },
8096 { Bad_Opcode },
8097 { Bad_Opcode },
8098 /* 58 */
8099 { Bad_Opcode },
8100 { Bad_Opcode },
8101 { Bad_Opcode },
8102 { Bad_Opcode },
8103 { Bad_Opcode },
8104 { Bad_Opcode },
8105 { Bad_Opcode },
8106 { Bad_Opcode },
8107 /* 60 */
8108 { Bad_Opcode },
8109 { Bad_Opcode },
8110 { Bad_Opcode },
8111 { Bad_Opcode },
8112 { Bad_Opcode },
8113 { Bad_Opcode },
8114 { Bad_Opcode },
8115 { Bad_Opcode },
8116 /* 68 */
8117 { Bad_Opcode },
8118 { Bad_Opcode },
8119 { Bad_Opcode },
8120 { Bad_Opcode },
8121 { Bad_Opcode },
8122 { Bad_Opcode },
8123 { Bad_Opcode },
8124 { Bad_Opcode },
8125 /* 70 */
8126 { Bad_Opcode },
8127 { Bad_Opcode },
8128 { Bad_Opcode },
8129 { Bad_Opcode },
8130 { Bad_Opcode },
8131 { Bad_Opcode },
8132 { Bad_Opcode },
8133 { Bad_Opcode },
8134 /* 78 */
8135 { Bad_Opcode },
8136 { Bad_Opcode },
8137 { Bad_Opcode },
8138 { Bad_Opcode },
8139 { Bad_Opcode },
8140 { Bad_Opcode },
8141 { Bad_Opcode },
8142 { Bad_Opcode },
8143 /* 80 */
8144 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8145 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8146 { "vfrczss", { XM, EXd }, 0 },
8147 { "vfrczsd", { XM, EXq }, 0 },
8148 { Bad_Opcode },
8149 { Bad_Opcode },
8150 { Bad_Opcode },
8151 { Bad_Opcode },
8152 /* 88 */
8153 { Bad_Opcode },
8154 { Bad_Opcode },
8155 { Bad_Opcode },
8156 { Bad_Opcode },
8157 { Bad_Opcode },
8158 { Bad_Opcode },
8159 { Bad_Opcode },
8160 { Bad_Opcode },
8161 /* 90 */
8162 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8163 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8164 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8165 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8166 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8167 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8168 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8169 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170 /* 98 */
8171 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8172 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8173 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175 { Bad_Opcode },
8176 { Bad_Opcode },
8177 { Bad_Opcode },
8178 { Bad_Opcode },
8179 /* a0 */
8180 { Bad_Opcode },
8181 { Bad_Opcode },
8182 { Bad_Opcode },
8183 { Bad_Opcode },
8184 { Bad_Opcode },
8185 { Bad_Opcode },
8186 { Bad_Opcode },
8187 { Bad_Opcode },
8188 /* a8 */
8189 { Bad_Opcode },
8190 { Bad_Opcode },
8191 { Bad_Opcode },
8192 { Bad_Opcode },
8193 { Bad_Opcode },
8194 { Bad_Opcode },
8195 { Bad_Opcode },
8196 { Bad_Opcode },
8197 /* b0 */
8198 { Bad_Opcode },
8199 { Bad_Opcode },
8200 { Bad_Opcode },
8201 { Bad_Opcode },
8202 { Bad_Opcode },
8203 { Bad_Opcode },
8204 { Bad_Opcode },
8205 { Bad_Opcode },
8206 /* b8 */
8207 { Bad_Opcode },
8208 { Bad_Opcode },
8209 { Bad_Opcode },
8210 { Bad_Opcode },
8211 { Bad_Opcode },
8212 { Bad_Opcode },
8213 { Bad_Opcode },
8214 { Bad_Opcode },
8215 /* c0 */
8216 { Bad_Opcode },
8217 { "vphaddbw", { XM, EXxmm }, 0 },
8218 { "vphaddbd", { XM, EXxmm }, 0 },
8219 { "vphaddbq", { XM, EXxmm }, 0 },
8220 { Bad_Opcode },
8221 { Bad_Opcode },
8222 { "vphaddwd", { XM, EXxmm }, 0 },
8223 { "vphaddwq", { XM, EXxmm }, 0 },
8224 /* c8 */
8225 { Bad_Opcode },
8226 { Bad_Opcode },
8227 { Bad_Opcode },
8228 { "vphadddq", { XM, EXxmm }, 0 },
8229 { Bad_Opcode },
8230 { Bad_Opcode },
8231 { Bad_Opcode },
8232 { Bad_Opcode },
8233 /* d0 */
8234 { Bad_Opcode },
8235 { "vphaddubw", { XM, EXxmm }, 0 },
8236 { "vphaddubd", { XM, EXxmm }, 0 },
8237 { "vphaddubq", { XM, EXxmm }, 0 },
8238 { Bad_Opcode },
8239 { Bad_Opcode },
8240 { "vphadduwd", { XM, EXxmm }, 0 },
8241 { "vphadduwq", { XM, EXxmm }, 0 },
8242 /* d8 */
8243 { Bad_Opcode },
8244 { Bad_Opcode },
8245 { Bad_Opcode },
8246 { "vphaddudq", { XM, EXxmm }, 0 },
8247 { Bad_Opcode },
8248 { Bad_Opcode },
8249 { Bad_Opcode },
8250 { Bad_Opcode },
8251 /* e0 */
8252 { Bad_Opcode },
8253 { "vphsubbw", { XM, EXxmm }, 0 },
8254 { "vphsubwd", { XM, EXxmm }, 0 },
8255 { "vphsubdq", { XM, EXxmm }, 0 },
8256 { Bad_Opcode },
8257 { Bad_Opcode },
8258 { Bad_Opcode },
8259 { Bad_Opcode },
8260 /* e8 */
8261 { Bad_Opcode },
8262 { Bad_Opcode },
8263 { Bad_Opcode },
8264 { Bad_Opcode },
8265 { Bad_Opcode },
8266 { Bad_Opcode },
8267 { Bad_Opcode },
8268 { Bad_Opcode },
8269 /* f0 */
8270 { Bad_Opcode },
8271 { Bad_Opcode },
8272 { Bad_Opcode },
8273 { Bad_Opcode },
8274 { Bad_Opcode },
8275 { Bad_Opcode },
8276 { Bad_Opcode },
8277 { Bad_Opcode },
8278 /* f8 */
8279 { Bad_Opcode },
8280 { Bad_Opcode },
8281 { Bad_Opcode },
8282 { Bad_Opcode },
8283 { Bad_Opcode },
8284 { Bad_Opcode },
8285 { Bad_Opcode },
8286 { Bad_Opcode },
8287 },
8288 /* XOP_0A */
8289 {
8290 /* 00 */
8291 { Bad_Opcode },
8292 { Bad_Opcode },
8293 { Bad_Opcode },
8294 { Bad_Opcode },
8295 { Bad_Opcode },
8296 { Bad_Opcode },
8297 { Bad_Opcode },
8298 { Bad_Opcode },
8299 /* 08 */
8300 { Bad_Opcode },
8301 { Bad_Opcode },
8302 { Bad_Opcode },
8303 { Bad_Opcode },
8304 { Bad_Opcode },
8305 { Bad_Opcode },
8306 { Bad_Opcode },
8307 { Bad_Opcode },
8308 /* 10 */
8309 { "bextr", { Gv, Ev, Iq }, 0 },
8310 { Bad_Opcode },
8311 { REG_TABLE (REG_XOP_LWP) },
8312 { Bad_Opcode },
8313 { Bad_Opcode },
8314 { Bad_Opcode },
8315 { Bad_Opcode },
8316 { Bad_Opcode },
8317 /* 18 */
8318 { Bad_Opcode },
8319 { Bad_Opcode },
8320 { Bad_Opcode },
8321 { Bad_Opcode },
8322 { Bad_Opcode },
8323 { Bad_Opcode },
8324 { Bad_Opcode },
8325 { Bad_Opcode },
8326 /* 20 */
8327 { Bad_Opcode },
8328 { Bad_Opcode },
8329 { Bad_Opcode },
8330 { Bad_Opcode },
8331 { Bad_Opcode },
8332 { Bad_Opcode },
8333 { Bad_Opcode },
8334 { Bad_Opcode },
8335 /* 28 */
8336 { Bad_Opcode },
8337 { Bad_Opcode },
8338 { Bad_Opcode },
8339 { Bad_Opcode },
8340 { Bad_Opcode },
8341 { Bad_Opcode },
8342 { Bad_Opcode },
8343 { Bad_Opcode },
8344 /* 30 */
8345 { Bad_Opcode },
8346 { Bad_Opcode },
8347 { Bad_Opcode },
8348 { Bad_Opcode },
8349 { Bad_Opcode },
8350 { Bad_Opcode },
8351 { Bad_Opcode },
8352 { Bad_Opcode },
8353 /* 38 */
8354 { Bad_Opcode },
8355 { Bad_Opcode },
8356 { Bad_Opcode },
8357 { Bad_Opcode },
8358 { Bad_Opcode },
8359 { Bad_Opcode },
8360 { Bad_Opcode },
8361 { Bad_Opcode },
8362 /* 40 */
8363 { Bad_Opcode },
8364 { Bad_Opcode },
8365 { Bad_Opcode },
8366 { Bad_Opcode },
8367 { Bad_Opcode },
8368 { Bad_Opcode },
8369 { Bad_Opcode },
8370 { Bad_Opcode },
8371 /* 48 */
8372 { Bad_Opcode },
8373 { Bad_Opcode },
8374 { Bad_Opcode },
8375 { Bad_Opcode },
8376 { Bad_Opcode },
8377 { Bad_Opcode },
8378 { Bad_Opcode },
8379 { Bad_Opcode },
8380 /* 50 */
8381 { Bad_Opcode },
8382 { Bad_Opcode },
8383 { Bad_Opcode },
8384 { Bad_Opcode },
8385 { Bad_Opcode },
8386 { Bad_Opcode },
8387 { Bad_Opcode },
8388 { Bad_Opcode },
8389 /* 58 */
8390 { Bad_Opcode },
8391 { Bad_Opcode },
8392 { Bad_Opcode },
8393 { Bad_Opcode },
8394 { Bad_Opcode },
8395 { Bad_Opcode },
8396 { Bad_Opcode },
8397 { Bad_Opcode },
8398 /* 60 */
8399 { Bad_Opcode },
8400 { Bad_Opcode },
8401 { Bad_Opcode },
8402 { Bad_Opcode },
8403 { Bad_Opcode },
8404 { Bad_Opcode },
8405 { Bad_Opcode },
8406 { Bad_Opcode },
8407 /* 68 */
8408 { Bad_Opcode },
8409 { Bad_Opcode },
8410 { Bad_Opcode },
8411 { Bad_Opcode },
8412 { Bad_Opcode },
8413 { Bad_Opcode },
8414 { Bad_Opcode },
8415 { Bad_Opcode },
8416 /* 70 */
8417 { Bad_Opcode },
8418 { Bad_Opcode },
8419 { Bad_Opcode },
8420 { Bad_Opcode },
8421 { Bad_Opcode },
8422 { Bad_Opcode },
8423 { Bad_Opcode },
8424 { Bad_Opcode },
8425 /* 78 */
8426 { Bad_Opcode },
8427 { Bad_Opcode },
8428 { Bad_Opcode },
8429 { Bad_Opcode },
8430 { Bad_Opcode },
8431 { Bad_Opcode },
8432 { Bad_Opcode },
8433 { Bad_Opcode },
8434 /* 80 */
8435 { Bad_Opcode },
8436 { Bad_Opcode },
8437 { Bad_Opcode },
8438 { Bad_Opcode },
8439 { Bad_Opcode },
8440 { Bad_Opcode },
8441 { Bad_Opcode },
8442 { Bad_Opcode },
8443 /* 88 */
8444 { Bad_Opcode },
8445 { Bad_Opcode },
8446 { Bad_Opcode },
8447 { Bad_Opcode },
8448 { Bad_Opcode },
8449 { Bad_Opcode },
8450 { Bad_Opcode },
8451 { Bad_Opcode },
8452 /* 90 */
8453 { Bad_Opcode },
8454 { Bad_Opcode },
8455 { Bad_Opcode },
8456 { Bad_Opcode },
8457 { Bad_Opcode },
8458 { Bad_Opcode },
8459 { Bad_Opcode },
8460 { Bad_Opcode },
8461 /* 98 */
8462 { Bad_Opcode },
8463 { Bad_Opcode },
8464 { Bad_Opcode },
8465 { Bad_Opcode },
8466 { Bad_Opcode },
8467 { Bad_Opcode },
8468 { Bad_Opcode },
8469 { Bad_Opcode },
8470 /* a0 */
8471 { Bad_Opcode },
8472 { Bad_Opcode },
8473 { Bad_Opcode },
8474 { Bad_Opcode },
8475 { Bad_Opcode },
8476 { Bad_Opcode },
8477 { Bad_Opcode },
8478 { Bad_Opcode },
8479 /* a8 */
8480 { Bad_Opcode },
8481 { Bad_Opcode },
8482 { Bad_Opcode },
8483 { Bad_Opcode },
8484 { Bad_Opcode },
8485 { Bad_Opcode },
8486 { Bad_Opcode },
8487 { Bad_Opcode },
8488 /* b0 */
8489 { Bad_Opcode },
8490 { Bad_Opcode },
8491 { Bad_Opcode },
8492 { Bad_Opcode },
8493 { Bad_Opcode },
8494 { Bad_Opcode },
8495 { Bad_Opcode },
8496 { Bad_Opcode },
8497 /* b8 */
8498 { Bad_Opcode },
8499 { Bad_Opcode },
8500 { Bad_Opcode },
8501 { Bad_Opcode },
8502 { Bad_Opcode },
8503 { Bad_Opcode },
8504 { Bad_Opcode },
8505 { Bad_Opcode },
8506 /* c0 */
8507 { Bad_Opcode },
8508 { Bad_Opcode },
8509 { Bad_Opcode },
8510 { Bad_Opcode },
8511 { Bad_Opcode },
8512 { Bad_Opcode },
8513 { Bad_Opcode },
8514 { Bad_Opcode },
8515 /* c8 */
8516 { Bad_Opcode },
8517 { Bad_Opcode },
8518 { Bad_Opcode },
8519 { Bad_Opcode },
8520 { Bad_Opcode },
8521 { Bad_Opcode },
8522 { Bad_Opcode },
8523 { Bad_Opcode },
8524 /* d0 */
8525 { Bad_Opcode },
8526 { Bad_Opcode },
8527 { Bad_Opcode },
8528 { Bad_Opcode },
8529 { Bad_Opcode },
8530 { Bad_Opcode },
8531 { Bad_Opcode },
8532 { Bad_Opcode },
8533 /* d8 */
8534 { Bad_Opcode },
8535 { Bad_Opcode },
8536 { Bad_Opcode },
8537 { Bad_Opcode },
8538 { Bad_Opcode },
8539 { Bad_Opcode },
8540 { Bad_Opcode },
8541 { Bad_Opcode },
8542 /* e0 */
8543 { Bad_Opcode },
8544 { Bad_Opcode },
8545 { Bad_Opcode },
8546 { Bad_Opcode },
8547 { Bad_Opcode },
8548 { Bad_Opcode },
8549 { Bad_Opcode },
8550 { Bad_Opcode },
8551 /* e8 */
8552 { Bad_Opcode },
8553 { Bad_Opcode },
8554 { Bad_Opcode },
8555 { Bad_Opcode },
8556 { Bad_Opcode },
8557 { Bad_Opcode },
8558 { Bad_Opcode },
8559 { Bad_Opcode },
8560 /* f0 */
8561 { Bad_Opcode },
8562 { Bad_Opcode },
8563 { Bad_Opcode },
8564 { Bad_Opcode },
8565 { Bad_Opcode },
8566 { Bad_Opcode },
8567 { Bad_Opcode },
8568 { Bad_Opcode },
8569 /* f8 */
8570 { Bad_Opcode },
8571 { Bad_Opcode },
8572 { Bad_Opcode },
8573 { Bad_Opcode },
8574 { Bad_Opcode },
8575 { Bad_Opcode },
8576 { Bad_Opcode },
8577 { Bad_Opcode },
8578 },
8579};
8580
8581static const struct dis386 vex_table[][256] = {
8582 /* VEX_0F */
8583 {
8584 /* 00 */
8585 { Bad_Opcode },
8586 { Bad_Opcode },
8587 { Bad_Opcode },
8588 { Bad_Opcode },
8589 { Bad_Opcode },
8590 { Bad_Opcode },
8591 { Bad_Opcode },
8592 { Bad_Opcode },
8593 /* 08 */
8594 { Bad_Opcode },
8595 { Bad_Opcode },
8596 { Bad_Opcode },
8597 { Bad_Opcode },
8598 { Bad_Opcode },
8599 { Bad_Opcode },
8600 { Bad_Opcode },
8601 { Bad_Opcode },
8602 /* 10 */
8603 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8606 { MOD_TABLE (MOD_VEX_0F13) },
8607 { VEX_W_TABLE (VEX_W_0F14) },
8608 { VEX_W_TABLE (VEX_W_0F15) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8610 { MOD_TABLE (MOD_VEX_0F17) },
8611 /* 18 */
8612 { Bad_Opcode },
8613 { Bad_Opcode },
8614 { Bad_Opcode },
8615 { Bad_Opcode },
8616 { Bad_Opcode },
8617 { Bad_Opcode },
8618 { Bad_Opcode },
8619 { Bad_Opcode },
8620 /* 20 */
8621 { Bad_Opcode },
8622 { Bad_Opcode },
8623 { Bad_Opcode },
8624 { Bad_Opcode },
8625 { Bad_Opcode },
8626 { Bad_Opcode },
8627 { Bad_Opcode },
8628 { Bad_Opcode },
8629 /* 28 */
8630 { VEX_W_TABLE (VEX_W_0F28) },
8631 { VEX_W_TABLE (VEX_W_0F29) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8633 { MOD_TABLE (MOD_VEX_0F2B) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8638 /* 30 */
8639 { Bad_Opcode },
8640 { Bad_Opcode },
8641 { Bad_Opcode },
8642 { Bad_Opcode },
8643 { Bad_Opcode },
8644 { Bad_Opcode },
8645 { Bad_Opcode },
8646 { Bad_Opcode },
8647 /* 38 */
8648 { Bad_Opcode },
8649 { Bad_Opcode },
8650 { Bad_Opcode },
8651 { Bad_Opcode },
8652 { Bad_Opcode },
8653 { Bad_Opcode },
8654 { Bad_Opcode },
8655 { Bad_Opcode },
8656 /* 40 */
8657 { Bad_Opcode },
8658 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8660 { Bad_Opcode },
8661 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8665 /* 48 */
8666 { Bad_Opcode },
8667 { Bad_Opcode },
8668 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8670 { Bad_Opcode },
8671 { Bad_Opcode },
8672 { Bad_Opcode },
8673 { Bad_Opcode },
8674 /* 50 */
8675 { MOD_TABLE (MOD_VEX_0F50) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8679 { "vandpX", { XM, Vex, EXx }, 0 },
8680 { "vandnpX", { XM, Vex, EXx }, 0 },
8681 { "vorpX", { XM, Vex, EXx }, 0 },
8682 { "vxorpX", { XM, Vex, EXx }, 0 },
8683 /* 58 */
8684 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8692 /* 60 */
8693 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8701 /* 68 */
8702 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8710 /* 70 */
8711 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8712 { REG_TABLE (REG_VEX_0F71) },
8713 { REG_TABLE (REG_VEX_0F72) },
8714 { REG_TABLE (REG_VEX_0F73) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8719 /* 78 */
8720 { Bad_Opcode },
8721 { Bad_Opcode },
8722 { Bad_Opcode },
8723 { Bad_Opcode },
8724 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8728 /* 80 */
8729 { Bad_Opcode },
8730 { Bad_Opcode },
8731 { Bad_Opcode },
8732 { Bad_Opcode },
8733 { Bad_Opcode },
8734 { Bad_Opcode },
8735 { Bad_Opcode },
8736 { Bad_Opcode },
8737 /* 88 */
8738 { Bad_Opcode },
8739 { Bad_Opcode },
8740 { Bad_Opcode },
8741 { Bad_Opcode },
8742 { Bad_Opcode },
8743 { Bad_Opcode },
8744 { Bad_Opcode },
8745 { Bad_Opcode },
8746 /* 90 */
8747 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8751 { Bad_Opcode },
8752 { Bad_Opcode },
8753 { Bad_Opcode },
8754 { Bad_Opcode },
8755 /* 98 */
8756 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8758 { Bad_Opcode },
8759 { Bad_Opcode },
8760 { Bad_Opcode },
8761 { Bad_Opcode },
8762 { Bad_Opcode },
8763 { Bad_Opcode },
8764 /* a0 */
8765 { Bad_Opcode },
8766 { Bad_Opcode },
8767 { Bad_Opcode },
8768 { Bad_Opcode },
8769 { Bad_Opcode },
8770 { Bad_Opcode },
8771 { Bad_Opcode },
8772 { Bad_Opcode },
8773 /* a8 */
8774 { Bad_Opcode },
8775 { Bad_Opcode },
8776 { Bad_Opcode },
8777 { Bad_Opcode },
8778 { Bad_Opcode },
8779 { Bad_Opcode },
8780 { REG_TABLE (REG_VEX_0FAE) },
8781 { Bad_Opcode },
8782 /* b0 */
8783 { Bad_Opcode },
8784 { Bad_Opcode },
8785 { Bad_Opcode },
8786 { Bad_Opcode },
8787 { Bad_Opcode },
8788 { Bad_Opcode },
8789 { Bad_Opcode },
8790 { Bad_Opcode },
8791 /* b8 */
8792 { Bad_Opcode },
8793 { Bad_Opcode },
8794 { Bad_Opcode },
8795 { Bad_Opcode },
8796 { Bad_Opcode },
8797 { Bad_Opcode },
8798 { Bad_Opcode },
8799 { Bad_Opcode },
8800 /* c0 */
8801 { Bad_Opcode },
8802 { Bad_Opcode },
8803 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8804 { Bad_Opcode },
8805 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8806 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8807 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8808 { Bad_Opcode },
8809 /* c8 */
8810 { Bad_Opcode },
8811 { Bad_Opcode },
8812 { Bad_Opcode },
8813 { Bad_Opcode },
8814 { Bad_Opcode },
8815 { Bad_Opcode },
8816 { Bad_Opcode },
8817 { Bad_Opcode },
8818 /* d0 */
8819 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8820 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8821 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8822 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8823 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8824 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8825 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8827 /* d8 */
8828 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8836 /* e0 */
8837 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8845 /* e8 */
8846 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8854 /* f0 */
8855 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8863 /* f8 */
8864 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8871 { Bad_Opcode },
8872 },
8873 /* VEX_0F38 */
8874 {
8875 /* 00 */
8876 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8884 /* 08 */
8885 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8893 /* 10 */
8894 { Bad_Opcode },
8895 { Bad_Opcode },
8896 { Bad_Opcode },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8898 { Bad_Opcode },
8899 { Bad_Opcode },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8902 /* 18 */
8903 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8906 { Bad_Opcode },
8907 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8910 { Bad_Opcode },
8911 /* 20 */
8912 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8918 { Bad_Opcode },
8919 { Bad_Opcode },
8920 /* 28 */
8921 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8929 /* 30 */
8930 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8938 /* 38 */
8939 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8947 /* 40 */
8948 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8950 { Bad_Opcode },
8951 { Bad_Opcode },
8952 { Bad_Opcode },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8956 /* 48 */
8957 { Bad_Opcode },
8958 { Bad_Opcode },
8959 { Bad_Opcode },
8960 { Bad_Opcode },
8961 { Bad_Opcode },
8962 { Bad_Opcode },
8963 { Bad_Opcode },
8964 { Bad_Opcode },
8965 /* 50 */
8966 { Bad_Opcode },
8967 { Bad_Opcode },
8968 { Bad_Opcode },
8969 { Bad_Opcode },
8970 { Bad_Opcode },
8971 { Bad_Opcode },
8972 { Bad_Opcode },
8973 { Bad_Opcode },
8974 /* 58 */
8975 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8978 { Bad_Opcode },
8979 { Bad_Opcode },
8980 { Bad_Opcode },
8981 { Bad_Opcode },
8982 { Bad_Opcode },
8983 /* 60 */
8984 { Bad_Opcode },
8985 { Bad_Opcode },
8986 { Bad_Opcode },
8987 { Bad_Opcode },
8988 { Bad_Opcode },
8989 { Bad_Opcode },
8990 { Bad_Opcode },
8991 { Bad_Opcode },
8992 /* 68 */
8993 { Bad_Opcode },
8994 { Bad_Opcode },
8995 { Bad_Opcode },
8996 { Bad_Opcode },
8997 { Bad_Opcode },
8998 { Bad_Opcode },
8999 { Bad_Opcode },
9000 { Bad_Opcode },
9001 /* 70 */
9002 { Bad_Opcode },
9003 { Bad_Opcode },
9004 { Bad_Opcode },
9005 { Bad_Opcode },
9006 { Bad_Opcode },
9007 { Bad_Opcode },
9008 { Bad_Opcode },
9009 { Bad_Opcode },
9010 /* 78 */
9011 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9013 { Bad_Opcode },
9014 { Bad_Opcode },
9015 { Bad_Opcode },
9016 { Bad_Opcode },
9017 { Bad_Opcode },
9018 { Bad_Opcode },
9019 /* 80 */
9020 { Bad_Opcode },
9021 { Bad_Opcode },
9022 { Bad_Opcode },
9023 { Bad_Opcode },
9024 { Bad_Opcode },
9025 { Bad_Opcode },
9026 { Bad_Opcode },
9027 { Bad_Opcode },
9028 /* 88 */
9029 { Bad_Opcode },
9030 { Bad_Opcode },
9031 { Bad_Opcode },
9032 { Bad_Opcode },
9033 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9034 { Bad_Opcode },
9035 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9036 { Bad_Opcode },
9037 /* 90 */
9038 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9042 { Bad_Opcode },
9043 { Bad_Opcode },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9046 /* 98 */
9047 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9055 /* a0 */
9056 { Bad_Opcode },
9057 { Bad_Opcode },
9058 { Bad_Opcode },
9059 { Bad_Opcode },
9060 { Bad_Opcode },
9061 { Bad_Opcode },
9062 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9064 /* a8 */
9065 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9073 /* b0 */
9074 { Bad_Opcode },
9075 { Bad_Opcode },
9076 { Bad_Opcode },
9077 { Bad_Opcode },
9078 { Bad_Opcode },
9079 { Bad_Opcode },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9082 /* b8 */
9083 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9091 /* c0 */
9092 { Bad_Opcode },
9093 { Bad_Opcode },
9094 { Bad_Opcode },
9095 { Bad_Opcode },
9096 { Bad_Opcode },
9097 { Bad_Opcode },
9098 { Bad_Opcode },
9099 { Bad_Opcode },
9100 /* c8 */
9101 { Bad_Opcode },
9102 { Bad_Opcode },
9103 { Bad_Opcode },
9104 { Bad_Opcode },
9105 { Bad_Opcode },
9106 { Bad_Opcode },
9107 { Bad_Opcode },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9109 /* d0 */
9110 { Bad_Opcode },
9111 { Bad_Opcode },
9112 { Bad_Opcode },
9113 { Bad_Opcode },
9114 { Bad_Opcode },
9115 { Bad_Opcode },
9116 { Bad_Opcode },
9117 { Bad_Opcode },
9118 /* d8 */
9119 { Bad_Opcode },
9120 { Bad_Opcode },
9121 { Bad_Opcode },
9122 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9127 /* e0 */
9128 { Bad_Opcode },
9129 { Bad_Opcode },
9130 { Bad_Opcode },
9131 { Bad_Opcode },
9132 { Bad_Opcode },
9133 { Bad_Opcode },
9134 { Bad_Opcode },
9135 { Bad_Opcode },
9136 /* e8 */
9137 { Bad_Opcode },
9138 { Bad_Opcode },
9139 { Bad_Opcode },
9140 { Bad_Opcode },
9141 { Bad_Opcode },
9142 { Bad_Opcode },
9143 { Bad_Opcode },
9144 { Bad_Opcode },
9145 /* f0 */
9146 { Bad_Opcode },
9147 { Bad_Opcode },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9149 { REG_TABLE (REG_VEX_0F38F3) },
9150 { Bad_Opcode },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9154 /* f8 */
9155 { Bad_Opcode },
9156 { Bad_Opcode },
9157 { Bad_Opcode },
9158 { Bad_Opcode },
9159 { Bad_Opcode },
9160 { Bad_Opcode },
9161 { Bad_Opcode },
9162 { Bad_Opcode },
9163 },
9164 /* VEX_0F3A */
9165 {
9166 /* 00 */
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9170 { Bad_Opcode },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9174 { Bad_Opcode },
9175 /* 08 */
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9184 /* 10 */
9185 { Bad_Opcode },
9186 { Bad_Opcode },
9187 { Bad_Opcode },
9188 { Bad_Opcode },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9193 /* 18 */
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9196 { Bad_Opcode },
9197 { Bad_Opcode },
9198 { Bad_Opcode },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9200 { Bad_Opcode },
9201 { Bad_Opcode },
9202 /* 20 */
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9206 { Bad_Opcode },
9207 { Bad_Opcode },
9208 { Bad_Opcode },
9209 { Bad_Opcode },
9210 { Bad_Opcode },
9211 /* 28 */
9212 { Bad_Opcode },
9213 { Bad_Opcode },
9214 { Bad_Opcode },
9215 { Bad_Opcode },
9216 { Bad_Opcode },
9217 { Bad_Opcode },
9218 { Bad_Opcode },
9219 { Bad_Opcode },
9220 /* 30 */
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9225 { Bad_Opcode },
9226 { Bad_Opcode },
9227 { Bad_Opcode },
9228 { Bad_Opcode },
9229 /* 38 */
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9232 { Bad_Opcode },
9233 { Bad_Opcode },
9234 { Bad_Opcode },
9235 { Bad_Opcode },
9236 { Bad_Opcode },
9237 { Bad_Opcode },
9238 /* 40 */
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9242 { Bad_Opcode },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9244 { Bad_Opcode },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9246 { Bad_Opcode },
9247 /* 48 */
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9253 { Bad_Opcode },
9254 { Bad_Opcode },
9255 { Bad_Opcode },
9256 /* 50 */
9257 { Bad_Opcode },
9258 { Bad_Opcode },
9259 { Bad_Opcode },
9260 { Bad_Opcode },
9261 { Bad_Opcode },
9262 { Bad_Opcode },
9263 { Bad_Opcode },
9264 { Bad_Opcode },
9265 /* 58 */
9266 { Bad_Opcode },
9267 { Bad_Opcode },
9268 { Bad_Opcode },
9269 { Bad_Opcode },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9274 /* 60 */
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9276 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9279 { Bad_Opcode },
9280 { Bad_Opcode },
9281 { Bad_Opcode },
9282 { Bad_Opcode },
9283 /* 68 */
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9292 /* 70 */
9293 { Bad_Opcode },
9294 { Bad_Opcode },
9295 { Bad_Opcode },
9296 { Bad_Opcode },
9297 { Bad_Opcode },
9298 { Bad_Opcode },
9299 { Bad_Opcode },
9300 { Bad_Opcode },
9301 /* 78 */
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9310 /* 80 */
9311 { Bad_Opcode },
9312 { Bad_Opcode },
9313 { Bad_Opcode },
9314 { Bad_Opcode },
9315 { Bad_Opcode },
9316 { Bad_Opcode },
9317 { Bad_Opcode },
9318 { Bad_Opcode },
9319 /* 88 */
9320 { Bad_Opcode },
9321 { Bad_Opcode },
9322 { Bad_Opcode },
9323 { Bad_Opcode },
9324 { Bad_Opcode },
9325 { Bad_Opcode },
9326 { Bad_Opcode },
9327 { Bad_Opcode },
9328 /* 90 */
9329 { Bad_Opcode },
9330 { Bad_Opcode },
9331 { Bad_Opcode },
9332 { Bad_Opcode },
9333 { Bad_Opcode },
9334 { Bad_Opcode },
9335 { Bad_Opcode },
9336 { Bad_Opcode },
9337 /* 98 */
9338 { Bad_Opcode },
9339 { Bad_Opcode },
9340 { Bad_Opcode },
9341 { Bad_Opcode },
9342 { Bad_Opcode },
9343 { Bad_Opcode },
9344 { Bad_Opcode },
9345 { Bad_Opcode },
9346 /* a0 */
9347 { Bad_Opcode },
9348 { Bad_Opcode },
9349 { Bad_Opcode },
9350 { Bad_Opcode },
9351 { Bad_Opcode },
9352 { Bad_Opcode },
9353 { Bad_Opcode },
9354 { Bad_Opcode },
9355 /* a8 */
9356 { Bad_Opcode },
9357 { Bad_Opcode },
9358 { Bad_Opcode },
9359 { Bad_Opcode },
9360 { Bad_Opcode },
9361 { Bad_Opcode },
9362 { Bad_Opcode },
9363 { Bad_Opcode },
9364 /* b0 */
9365 { Bad_Opcode },
9366 { Bad_Opcode },
9367 { Bad_Opcode },
9368 { Bad_Opcode },
9369 { Bad_Opcode },
9370 { Bad_Opcode },
9371 { Bad_Opcode },
9372 { Bad_Opcode },
9373 /* b8 */
9374 { Bad_Opcode },
9375 { Bad_Opcode },
9376 { Bad_Opcode },
9377 { Bad_Opcode },
9378 { Bad_Opcode },
9379 { Bad_Opcode },
9380 { Bad_Opcode },
9381 { Bad_Opcode },
9382 /* c0 */
9383 { Bad_Opcode },
9384 { Bad_Opcode },
9385 { Bad_Opcode },
9386 { Bad_Opcode },
9387 { Bad_Opcode },
9388 { Bad_Opcode },
9389 { Bad_Opcode },
9390 { Bad_Opcode },
9391 /* c8 */
9392 { Bad_Opcode },
9393 { Bad_Opcode },
9394 { Bad_Opcode },
9395 { Bad_Opcode },
9396 { Bad_Opcode },
9397 { Bad_Opcode },
9398 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9399 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9400 /* d0 */
9401 { Bad_Opcode },
9402 { Bad_Opcode },
9403 { Bad_Opcode },
9404 { Bad_Opcode },
9405 { Bad_Opcode },
9406 { Bad_Opcode },
9407 { Bad_Opcode },
9408 { Bad_Opcode },
9409 /* d8 */
9410 { Bad_Opcode },
9411 { Bad_Opcode },
9412 { Bad_Opcode },
9413 { Bad_Opcode },
9414 { Bad_Opcode },
9415 { Bad_Opcode },
9416 { Bad_Opcode },
9417 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9418 /* e0 */
9419 { Bad_Opcode },
9420 { Bad_Opcode },
9421 { Bad_Opcode },
9422 { Bad_Opcode },
9423 { Bad_Opcode },
9424 { Bad_Opcode },
9425 { Bad_Opcode },
9426 { Bad_Opcode },
9427 /* e8 */
9428 { Bad_Opcode },
9429 { Bad_Opcode },
9430 { Bad_Opcode },
9431 { Bad_Opcode },
9432 { Bad_Opcode },
9433 { Bad_Opcode },
9434 { Bad_Opcode },
9435 { Bad_Opcode },
9436 /* f0 */
9437 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9438 { Bad_Opcode },
9439 { Bad_Opcode },
9440 { Bad_Opcode },
9441 { Bad_Opcode },
9442 { Bad_Opcode },
9443 { Bad_Opcode },
9444 { Bad_Opcode },
9445 /* f8 */
9446 { Bad_Opcode },
9447 { Bad_Opcode },
9448 { Bad_Opcode },
9449 { Bad_Opcode },
9450 { Bad_Opcode },
9451 { Bad_Opcode },
9452 { Bad_Opcode },
9453 { Bad_Opcode },
9454 },
9455};
9456
9457#define NEED_OPCODE_TABLE
9458#include "i386-dis-evex.h"
9459#undef NEED_OPCODE_TABLE
9460static const struct dis386 vex_len_table[][2] = {
9461 /* VEX_LEN_0F10_P_1 */
9462 {
9463 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9464 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9465 },
9466
9467 /* VEX_LEN_0F10_P_3 */
9468 {
9469 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9470 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9471 },
9472
9473 /* VEX_LEN_0F11_P_1 */
9474 {
9475 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9476 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9477 },
9478
9479 /* VEX_LEN_0F11_P_3 */
9480 {
9481 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9482 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9483 },
9484
9485 /* VEX_LEN_0F12_P_0_M_0 */
9486 {
9487 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9488 },
9489
9490 /* VEX_LEN_0F12_P_0_M_1 */
9491 {
9492 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9493 },
9494
9495 /* VEX_LEN_0F12_P_2 */
9496 {
9497 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9498 },
9499
9500 /* VEX_LEN_0F13_M_0 */
9501 {
9502 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9503 },
9504
9505 /* VEX_LEN_0F16_P_0_M_0 */
9506 {
9507 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9508 },
9509
9510 /* VEX_LEN_0F16_P_0_M_1 */
9511 {
9512 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9513 },
9514
9515 /* VEX_LEN_0F16_P_2 */
9516 {
9517 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9518 },
9519
9520 /* VEX_LEN_0F17_M_0 */
9521 {
9522 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9523 },
9524
9525 /* VEX_LEN_0F2A_P_1 */
9526 {
9527 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9528 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9529 },
9530
9531 /* VEX_LEN_0F2A_P_3 */
9532 {
9533 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9534 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9535 },
9536
9537 /* VEX_LEN_0F2C_P_1 */
9538 {
9539 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9540 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9541 },
9542
9543 /* VEX_LEN_0F2C_P_3 */
9544 {
9545 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9546 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9547 },
9548
9549 /* VEX_LEN_0F2D_P_1 */
9550 {
9551 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9552 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9553 },
9554
9555 /* VEX_LEN_0F2D_P_3 */
9556 {
9557 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9558 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9559 },
9560
9561 /* VEX_LEN_0F2E_P_0 */
9562 {
9563 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9564 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9565 },
9566
9567 /* VEX_LEN_0F2E_P_2 */
9568 {
9569 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9570 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9571 },
9572
9573 /* VEX_LEN_0F2F_P_0 */
9574 {
9575 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9576 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9577 },
9578
9579 /* VEX_LEN_0F2F_P_2 */
9580 {
9581 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9582 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9583 },
9584
9585 /* VEX_LEN_0F41_P_0 */
9586 {
9587 { Bad_Opcode },
9588 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9589 },
9590 /* VEX_LEN_0F41_P_2 */
9591 {
9592 { Bad_Opcode },
9593 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9594 },
9595 /* VEX_LEN_0F42_P_0 */
9596 {
9597 { Bad_Opcode },
9598 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9599 },
9600 /* VEX_LEN_0F42_P_2 */
9601 {
9602 { Bad_Opcode },
9603 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9604 },
9605 /* VEX_LEN_0F44_P_0 */
9606 {
9607 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9608 },
9609 /* VEX_LEN_0F44_P_2 */
9610 {
9611 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9612 },
9613 /* VEX_LEN_0F45_P_0 */
9614 {
9615 { Bad_Opcode },
9616 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9617 },
9618 /* VEX_LEN_0F45_P_2 */
9619 {
9620 { Bad_Opcode },
9621 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9622 },
9623 /* VEX_LEN_0F46_P_0 */
9624 {
9625 { Bad_Opcode },
9626 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9627 },
9628 /* VEX_LEN_0F46_P_2 */
9629 {
9630 { Bad_Opcode },
9631 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9632 },
9633 /* VEX_LEN_0F47_P_0 */
9634 {
9635 { Bad_Opcode },
9636 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9637 },
9638 /* VEX_LEN_0F47_P_2 */
9639 {
9640 { Bad_Opcode },
9641 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9642 },
9643 /* VEX_LEN_0F4A_P_0 */
9644 {
9645 { Bad_Opcode },
9646 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9647 },
9648 /* VEX_LEN_0F4A_P_2 */
9649 {
9650 { Bad_Opcode },
9651 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9652 },
9653 /* VEX_LEN_0F4B_P_0 */
9654 {
9655 { Bad_Opcode },
9656 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9657 },
9658 /* VEX_LEN_0F4B_P_2 */
9659 {
9660 { Bad_Opcode },
9661 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9662 },
9663
9664 /* VEX_LEN_0F51_P_1 */
9665 {
9666 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9667 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9668 },
9669
9670 /* VEX_LEN_0F51_P_3 */
9671 {
9672 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9673 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9674 },
9675
9676 /* VEX_LEN_0F52_P_1 */
9677 {
9678 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9679 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9680 },
9681
9682 /* VEX_LEN_0F53_P_1 */
9683 {
9684 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9685 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9686 },
9687
9688 /* VEX_LEN_0F58_P_1 */
9689 {
9690 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9691 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9692 },
9693
9694 /* VEX_LEN_0F58_P_3 */
9695 {
9696 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9697 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9698 },
9699
9700 /* VEX_LEN_0F59_P_1 */
9701 {
9702 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9703 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9704 },
9705
9706 /* VEX_LEN_0F59_P_3 */
9707 {
9708 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9709 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9710 },
9711
9712 /* VEX_LEN_0F5A_P_1 */
9713 {
9714 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9715 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9716 },
9717
9718 /* VEX_LEN_0F5A_P_3 */
9719 {
9720 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9721 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9722 },
9723
9724 /* VEX_LEN_0F5C_P_1 */
9725 {
9726 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9727 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9728 },
9729
9730 /* VEX_LEN_0F5C_P_3 */
9731 {
9732 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9733 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9734 },
9735
9736 /* VEX_LEN_0F5D_P_1 */
9737 {
9738 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9739 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9740 },
9741
9742 /* VEX_LEN_0F5D_P_3 */
9743 {
9744 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9745 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9746 },
9747
9748 /* VEX_LEN_0F5E_P_1 */
9749 {
9750 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9751 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9752 },
9753
9754 /* VEX_LEN_0F5E_P_3 */
9755 {
9756 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9757 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9758 },
9759
9760 /* VEX_LEN_0F5F_P_1 */
9761 {
9762 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9763 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9764 },
9765
9766 /* VEX_LEN_0F5F_P_3 */
9767 {
9768 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9769 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9770 },
9771
9772 /* VEX_LEN_0F6E_P_2 */
9773 {
9774 { "vmovK", { XMScalar, Edq }, 0 },
9775 { "vmovK", { XMScalar, Edq }, 0 },
9776 },
9777
9778 /* VEX_LEN_0F7E_P_1 */
9779 {
9780 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9781 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9782 },
9783
9784 /* VEX_LEN_0F7E_P_2 */
9785 {
9786 { "vmovK", { Edq, XMScalar }, 0 },
9787 { "vmovK", { Edq, XMScalar }, 0 },
9788 },
9789
9790 /* VEX_LEN_0F90_P_0 */
9791 {
9792 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9793 },
9794
9795 /* VEX_LEN_0F90_P_2 */
9796 {
9797 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9798 },
9799
9800 /* VEX_LEN_0F91_P_0 */
9801 {
9802 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9803 },
9804
9805 /* VEX_LEN_0F91_P_2 */
9806 {
9807 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9808 },
9809
9810 /* VEX_LEN_0F92_P_0 */
9811 {
9812 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9813 },
9814
9815 /* VEX_LEN_0F92_P_2 */
9816 {
9817 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9818 },
9819
9820 /* VEX_LEN_0F92_P_3 */
9821 {
9822 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9823 },
9824
9825 /* VEX_LEN_0F93_P_0 */
9826 {
9827 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9828 },
9829
9830 /* VEX_LEN_0F93_P_2 */
9831 {
9832 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9833 },
9834
9835 /* VEX_LEN_0F93_P_3 */
9836 {
9837 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9838 },
9839
9840 /* VEX_LEN_0F98_P_0 */
9841 {
9842 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9843 },
9844
9845 /* VEX_LEN_0F98_P_2 */
9846 {
9847 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9848 },
9849
9850 /* VEX_LEN_0F99_P_0 */
9851 {
9852 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9853 },
9854
9855 /* VEX_LEN_0F99_P_2 */
9856 {
9857 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9858 },
9859
9860 /* VEX_LEN_0FAE_R_2_M_0 */
9861 {
9862 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9863 },
9864
9865 /* VEX_LEN_0FAE_R_3_M_0 */
9866 {
9867 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9868 },
9869
9870 /* VEX_LEN_0FC2_P_1 */
9871 {
9872 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9873 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9874 },
9875
9876 /* VEX_LEN_0FC2_P_3 */
9877 {
9878 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9879 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9880 },
9881
9882 /* VEX_LEN_0FC4_P_2 */
9883 {
9884 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9885 },
9886
9887 /* VEX_LEN_0FC5_P_2 */
9888 {
9889 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9890 },
9891
9892 /* VEX_LEN_0FD6_P_2 */
9893 {
9894 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9895 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9896 },
9897
9898 /* VEX_LEN_0FF7_P_2 */
9899 {
9900 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9901 },
9902
9903 /* VEX_LEN_0F3816_P_2 */
9904 {
9905 { Bad_Opcode },
9906 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9907 },
9908
9909 /* VEX_LEN_0F3819_P_2 */
9910 {
9911 { Bad_Opcode },
9912 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9913 },
9914
9915 /* VEX_LEN_0F381A_P_2_M_0 */
9916 {
9917 { Bad_Opcode },
9918 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9919 },
9920
9921 /* VEX_LEN_0F3836_P_2 */
9922 {
9923 { Bad_Opcode },
9924 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9925 },
9926
9927 /* VEX_LEN_0F3841_P_2 */
9928 {
9929 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9930 },
9931
9932 /* VEX_LEN_0F385A_P_2_M_0 */
9933 {
9934 { Bad_Opcode },
9935 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9936 },
9937
9938 /* VEX_LEN_0F38DB_P_2 */
9939 {
9940 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9941 },
9942
9943 /* VEX_LEN_0F38DC_P_2 */
9944 {
9945 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9946 },
9947
9948 /* VEX_LEN_0F38DD_P_2 */
9949 {
9950 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9951 },
9952
9953 /* VEX_LEN_0F38DE_P_2 */
9954 {
9955 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9956 },
9957
9958 /* VEX_LEN_0F38DF_P_2 */
9959 {
9960 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9961 },
9962
9963 /* VEX_LEN_0F38F2_P_0 */
9964 {
9965 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9966 },
9967
9968 /* VEX_LEN_0F38F3_R_1_P_0 */
9969 {
9970 { "blsrS", { VexGdq, Edq }, 0 },
9971 },
9972
9973 /* VEX_LEN_0F38F3_R_2_P_0 */
9974 {
9975 { "blsmskS", { VexGdq, Edq }, 0 },
9976 },
9977
9978 /* VEX_LEN_0F38F3_R_3_P_0 */
9979 {
9980 { "blsiS", { VexGdq, Edq }, 0 },
9981 },
9982
9983 /* VEX_LEN_0F38F5_P_0 */
9984 {
9985 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9986 },
9987
9988 /* VEX_LEN_0F38F5_P_1 */
9989 {
9990 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9991 },
9992
9993 /* VEX_LEN_0F38F5_P_3 */
9994 {
9995 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9996 },
9997
9998 /* VEX_LEN_0F38F6_P_3 */
9999 {
10000 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10001 },
10002
10003 /* VEX_LEN_0F38F7_P_0 */
10004 {
10005 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10006 },
10007
10008 /* VEX_LEN_0F38F7_P_1 */
10009 {
10010 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10011 },
10012
10013 /* VEX_LEN_0F38F7_P_2 */
10014 {
10015 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10016 },
10017
10018 /* VEX_LEN_0F38F7_P_3 */
10019 {
10020 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10021 },
10022
10023 /* VEX_LEN_0F3A00_P_2 */
10024 {
10025 { Bad_Opcode },
10026 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10027 },
10028
10029 /* VEX_LEN_0F3A01_P_2 */
10030 {
10031 { Bad_Opcode },
10032 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10033 },
10034
10035 /* VEX_LEN_0F3A06_P_2 */
10036 {
10037 { Bad_Opcode },
10038 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10039 },
10040
10041 /* VEX_LEN_0F3A0A_P_2 */
10042 {
10043 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10044 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10045 },
10046
10047 /* VEX_LEN_0F3A0B_P_2 */
10048 {
10049 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10050 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10051 },
10052
10053 /* VEX_LEN_0F3A14_P_2 */
10054 {
10055 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10056 },
10057
10058 /* VEX_LEN_0F3A15_P_2 */
10059 {
10060 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10061 },
10062
10063 /* VEX_LEN_0F3A16_P_2 */
10064 {
10065 { "vpextrK", { Edq, XM, Ib }, 0 },
10066 },
10067
10068 /* VEX_LEN_0F3A17_P_2 */
10069 {
10070 { "vextractps", { Edqd, XM, Ib }, 0 },
10071 },
10072
10073 /* VEX_LEN_0F3A18_P_2 */
10074 {
10075 { Bad_Opcode },
10076 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10077 },
10078
10079 /* VEX_LEN_0F3A19_P_2 */
10080 {
10081 { Bad_Opcode },
10082 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10083 },
10084
10085 /* VEX_LEN_0F3A20_P_2 */
10086 {
10087 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10088 },
10089
10090 /* VEX_LEN_0F3A21_P_2 */
10091 {
10092 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10093 },
10094
10095 /* VEX_LEN_0F3A22_P_2 */
10096 {
10097 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10098 },
10099
10100 /* VEX_LEN_0F3A30_P_2 */
10101 {
10102 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10103 },
10104
10105 /* VEX_LEN_0F3A31_P_2 */
10106 {
10107 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10108 },
10109
10110 /* VEX_LEN_0F3A32_P_2 */
10111 {
10112 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10113 },
10114
10115 /* VEX_LEN_0F3A33_P_2 */
10116 {
10117 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10118 },
10119
10120 /* VEX_LEN_0F3A38_P_2 */
10121 {
10122 { Bad_Opcode },
10123 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10124 },
10125
10126 /* VEX_LEN_0F3A39_P_2 */
10127 {
10128 { Bad_Opcode },
10129 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10130 },
10131
10132 /* VEX_LEN_0F3A41_P_2 */
10133 {
10134 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10135 },
10136
10137 /* VEX_LEN_0F3A44_P_2 */
10138 {
10139 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10140 },
10141
10142 /* VEX_LEN_0F3A46_P_2 */
10143 {
10144 { Bad_Opcode },
10145 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10146 },
10147
10148 /* VEX_LEN_0F3A60_P_2 */
10149 {
10150 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10151 },
10152
10153 /* VEX_LEN_0F3A61_P_2 */
10154 {
10155 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10156 },
10157
10158 /* VEX_LEN_0F3A62_P_2 */
10159 {
10160 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10161 },
10162
10163 /* VEX_LEN_0F3A63_P_2 */
10164 {
10165 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10166 },
10167
10168 /* VEX_LEN_0F3A6A_P_2 */
10169 {
10170 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10171 },
10172
10173 /* VEX_LEN_0F3A6B_P_2 */
10174 {
10175 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10176 },
10177
10178 /* VEX_LEN_0F3A6E_P_2 */
10179 {
10180 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10181 },
10182
10183 /* VEX_LEN_0F3A6F_P_2 */
10184 {
10185 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10186 },
10187
10188 /* VEX_LEN_0F3A7A_P_2 */
10189 {
10190 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10191 },
10192
10193 /* VEX_LEN_0F3A7B_P_2 */
10194 {
10195 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10196 },
10197
10198 /* VEX_LEN_0F3A7E_P_2 */
10199 {
10200 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10201 },
10202
10203 /* VEX_LEN_0F3A7F_P_2 */
10204 {
10205 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10206 },
10207
10208 /* VEX_LEN_0F3ADF_P_2 */
10209 {
10210 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10211 },
10212
10213 /* VEX_LEN_0F3AF0_P_3 */
10214 {
10215 { "rorxS", { Gdq, Edq, Ib }, 0 },
10216 },
10217
10218 /* VEX_LEN_0FXOP_08_CC */
10219 {
10220 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10221 },
10222
10223 /* VEX_LEN_0FXOP_08_CD */
10224 {
10225 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10226 },
10227
10228 /* VEX_LEN_0FXOP_08_CE */
10229 {
10230 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10231 },
10232
10233 /* VEX_LEN_0FXOP_08_CF */
10234 {
10235 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10236 },
10237
10238 /* VEX_LEN_0FXOP_08_EC */
10239 {
10240 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10241 },
10242
10243 /* VEX_LEN_0FXOP_08_ED */
10244 {
10245 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10246 },
10247
10248 /* VEX_LEN_0FXOP_08_EE */
10249 {
10250 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10251 },
10252
10253 /* VEX_LEN_0FXOP_08_EF */
10254 {
10255 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10256 },
10257
10258 /* VEX_LEN_0FXOP_09_80 */
10259 {
10260 { "vfrczps", { XM, EXxmm }, 0 },
10261 { "vfrczps", { XM, EXymmq }, 0 },
10262 },
10263
10264 /* VEX_LEN_0FXOP_09_81 */
10265 {
10266 { "vfrczpd", { XM, EXxmm }, 0 },
10267 { "vfrczpd", { XM, EXymmq }, 0 },
10268 },
10269};
10270
10271static const struct dis386 vex_w_table[][2] = {
10272 {
10273 /* VEX_W_0F10_P_0 */
10274 { "vmovups", { XM, EXx }, 0 },
10275 },
10276 {
10277 /* VEX_W_0F10_P_1 */
10278 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10279 },
10280 {
10281 /* VEX_W_0F10_P_2 */
10282 { "vmovupd", { XM, EXx }, 0 },
10283 },
10284 {
10285 /* VEX_W_0F10_P_3 */
10286 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10287 },
10288 {
10289 /* VEX_W_0F11_P_0 */
10290 { "vmovups", { EXxS, XM }, 0 },
10291 },
10292 {
10293 /* VEX_W_0F11_P_1 */
10294 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10295 },
10296 {
10297 /* VEX_W_0F11_P_2 */
10298 { "vmovupd", { EXxS, XM }, 0 },
10299 },
10300 {
10301 /* VEX_W_0F11_P_3 */
10302 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10303 },
10304 {
10305 /* VEX_W_0F12_P_0_M_0 */
10306 { "vmovlps", { XM, Vex128, EXq }, 0 },
10307 },
10308 {
10309 /* VEX_W_0F12_P_0_M_1 */
10310 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10311 },
10312 {
10313 /* VEX_W_0F12_P_1 */
10314 { "vmovsldup", { XM, EXx }, 0 },
10315 },
10316 {
10317 /* VEX_W_0F12_P_2 */
10318 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10319 },
10320 {
10321 /* VEX_W_0F12_P_3 */
10322 { "vmovddup", { XM, EXymmq }, 0 },
10323 },
10324 {
10325 /* VEX_W_0F13_M_0 */
10326 { "vmovlpX", { EXq, XM }, 0 },
10327 },
10328 {
10329 /* VEX_W_0F14 */
10330 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10331 },
10332 {
10333 /* VEX_W_0F15 */
10334 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10335 },
10336 {
10337 /* VEX_W_0F16_P_0_M_0 */
10338 { "vmovhps", { XM, Vex128, EXq }, 0 },
10339 },
10340 {
10341 /* VEX_W_0F16_P_0_M_1 */
10342 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10343 },
10344 {
10345 /* VEX_W_0F16_P_1 */
10346 { "vmovshdup", { XM, EXx }, 0 },
10347 },
10348 {
10349 /* VEX_W_0F16_P_2 */
10350 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10351 },
10352 {
10353 /* VEX_W_0F17_M_0 */
10354 { "vmovhpX", { EXq, XM }, 0 },
10355 },
10356 {
10357 /* VEX_W_0F28 */
10358 { "vmovapX", { XM, EXx }, 0 },
10359 },
10360 {
10361 /* VEX_W_0F29 */
10362 { "vmovapX", { EXxS, XM }, 0 },
10363 },
10364 {
10365 /* VEX_W_0F2B_M_0 */
10366 { "vmovntpX", { Mx, XM }, 0 },
10367 },
10368 {
10369 /* VEX_W_0F2E_P_0 */
10370 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10371 },
10372 {
10373 /* VEX_W_0F2E_P_2 */
10374 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10375 },
10376 {
10377 /* VEX_W_0F2F_P_0 */
10378 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10379 },
10380 {
10381 /* VEX_W_0F2F_P_2 */
10382 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10383 },
10384 {
10385 /* VEX_W_0F41_P_0_LEN_1 */
10386 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10387 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10388 },
10389 {
10390 /* VEX_W_0F41_P_2_LEN_1 */
10391 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10392 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10393 },
10394 {
10395 /* VEX_W_0F42_P_0_LEN_1 */
10396 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10397 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10398 },
10399 {
10400 /* VEX_W_0F42_P_2_LEN_1 */
10401 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10402 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10403 },
10404 {
10405 /* VEX_W_0F44_P_0_LEN_0 */
10406 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10407 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10408 },
10409 {
10410 /* VEX_W_0F44_P_2_LEN_0 */
10411 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10412 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10413 },
10414 {
10415 /* VEX_W_0F45_P_0_LEN_1 */
10416 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10417 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10418 },
10419 {
10420 /* VEX_W_0F45_P_2_LEN_1 */
10421 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10422 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10423 },
10424 {
10425 /* VEX_W_0F46_P_0_LEN_1 */
10426 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10427 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10428 },
10429 {
10430 /* VEX_W_0F46_P_2_LEN_1 */
10431 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10432 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10433 },
10434 {
10435 /* VEX_W_0F47_P_0_LEN_1 */
10436 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10437 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10438 },
10439 {
10440 /* VEX_W_0F47_P_2_LEN_1 */
10441 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10442 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10443 },
10444 {
10445 /* VEX_W_0F4A_P_0_LEN_1 */
10446 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10447 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10448 },
10449 {
10450 /* VEX_W_0F4A_P_2_LEN_1 */
10451 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10452 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10453 },
10454 {
10455 /* VEX_W_0F4B_P_0_LEN_1 */
10456 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10457 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10458 },
10459 {
10460 /* VEX_W_0F4B_P_2_LEN_1 */
10461 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10462 },
10463 {
10464 /* VEX_W_0F50_M_0 */
10465 { "vmovmskpX", { Gdq, XS }, 0 },
10466 },
10467 {
10468 /* VEX_W_0F51_P_0 */
10469 { "vsqrtps", { XM, EXx }, 0 },
10470 },
10471 {
10472 /* VEX_W_0F51_P_1 */
10473 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10474 },
10475 {
10476 /* VEX_W_0F51_P_2 */
10477 { "vsqrtpd", { XM, EXx }, 0 },
10478 },
10479 {
10480 /* VEX_W_0F51_P_3 */
10481 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10482 },
10483 {
10484 /* VEX_W_0F52_P_0 */
10485 { "vrsqrtps", { XM, EXx }, 0 },
10486 },
10487 {
10488 /* VEX_W_0F52_P_1 */
10489 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10490 },
10491 {
10492 /* VEX_W_0F53_P_0 */
10493 { "vrcpps", { XM, EXx }, 0 },
10494 },
10495 {
10496 /* VEX_W_0F53_P_1 */
10497 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10498 },
10499 {
10500 /* VEX_W_0F58_P_0 */
10501 { "vaddps", { XM, Vex, EXx }, 0 },
10502 },
10503 {
10504 /* VEX_W_0F58_P_1 */
10505 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10506 },
10507 {
10508 /* VEX_W_0F58_P_2 */
10509 { "vaddpd", { XM, Vex, EXx }, 0 },
10510 },
10511 {
10512 /* VEX_W_0F58_P_3 */
10513 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10514 },
10515 {
10516 /* VEX_W_0F59_P_0 */
10517 { "vmulps", { XM, Vex, EXx }, 0 },
10518 },
10519 {
10520 /* VEX_W_0F59_P_1 */
10521 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10522 },
10523 {
10524 /* VEX_W_0F59_P_2 */
10525 { "vmulpd", { XM, Vex, EXx }, 0 },
10526 },
10527 {
10528 /* VEX_W_0F59_P_3 */
10529 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10530 },
10531 {
10532 /* VEX_W_0F5A_P_0 */
10533 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10534 },
10535 {
10536 /* VEX_W_0F5A_P_1 */
10537 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10538 },
10539 {
10540 /* VEX_W_0F5A_P_3 */
10541 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10542 },
10543 {
10544 /* VEX_W_0F5B_P_0 */
10545 { "vcvtdq2ps", { XM, EXx }, 0 },
10546 },
10547 {
10548 /* VEX_W_0F5B_P_1 */
10549 { "vcvttps2dq", { XM, EXx }, 0 },
10550 },
10551 {
10552 /* VEX_W_0F5B_P_2 */
10553 { "vcvtps2dq", { XM, EXx }, 0 },
10554 },
10555 {
10556 /* VEX_W_0F5C_P_0 */
10557 { "vsubps", { XM, Vex, EXx }, 0 },
10558 },
10559 {
10560 /* VEX_W_0F5C_P_1 */
10561 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10562 },
10563 {
10564 /* VEX_W_0F5C_P_2 */
10565 { "vsubpd", { XM, Vex, EXx }, 0 },
10566 },
10567 {
10568 /* VEX_W_0F5C_P_3 */
10569 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10570 },
10571 {
10572 /* VEX_W_0F5D_P_0 */
10573 { "vminps", { XM, Vex, EXx }, 0 },
10574 },
10575 {
10576 /* VEX_W_0F5D_P_1 */
10577 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10578 },
10579 {
10580 /* VEX_W_0F5D_P_2 */
10581 { "vminpd", { XM, Vex, EXx }, 0 },
10582 },
10583 {
10584 /* VEX_W_0F5D_P_3 */
10585 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10586 },
10587 {
10588 /* VEX_W_0F5E_P_0 */
10589 { "vdivps", { XM, Vex, EXx }, 0 },
10590 },
10591 {
10592 /* VEX_W_0F5E_P_1 */
10593 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10594 },
10595 {
10596 /* VEX_W_0F5E_P_2 */
10597 { "vdivpd", { XM, Vex, EXx }, 0 },
10598 },
10599 {
10600 /* VEX_W_0F5E_P_3 */
10601 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10602 },
10603 {
10604 /* VEX_W_0F5F_P_0 */
10605 { "vmaxps", { XM, Vex, EXx }, 0 },
10606 },
10607 {
10608 /* VEX_W_0F5F_P_1 */
10609 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10610 },
10611 {
10612 /* VEX_W_0F5F_P_2 */
10613 { "vmaxpd", { XM, Vex, EXx }, 0 },
10614 },
10615 {
10616 /* VEX_W_0F5F_P_3 */
10617 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10618 },
10619 {
10620 /* VEX_W_0F60_P_2 */
10621 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10622 },
10623 {
10624 /* VEX_W_0F61_P_2 */
10625 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10626 },
10627 {
10628 /* VEX_W_0F62_P_2 */
10629 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10630 },
10631 {
10632 /* VEX_W_0F63_P_2 */
10633 { "vpacksswb", { XM, Vex, EXx }, 0 },
10634 },
10635 {
10636 /* VEX_W_0F64_P_2 */
10637 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10638 },
10639 {
10640 /* VEX_W_0F65_P_2 */
10641 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10642 },
10643 {
10644 /* VEX_W_0F66_P_2 */
10645 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10646 },
10647 {
10648 /* VEX_W_0F67_P_2 */
10649 { "vpackuswb", { XM, Vex, EXx }, 0 },
10650 },
10651 {
10652 /* VEX_W_0F68_P_2 */
10653 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10654 },
10655 {
10656 /* VEX_W_0F69_P_2 */
10657 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10658 },
10659 {
10660 /* VEX_W_0F6A_P_2 */
10661 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10662 },
10663 {
10664 /* VEX_W_0F6B_P_2 */
10665 { "vpackssdw", { XM, Vex, EXx }, 0 },
10666 },
10667 {
10668 /* VEX_W_0F6C_P_2 */
10669 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10670 },
10671 {
10672 /* VEX_W_0F6D_P_2 */
10673 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10674 },
10675 {
10676 /* VEX_W_0F6F_P_1 */
10677 { "vmovdqu", { XM, EXx }, 0 },
10678 },
10679 {
10680 /* VEX_W_0F6F_P_2 */
10681 { "vmovdqa", { XM, EXx }, 0 },
10682 },
10683 {
10684 /* VEX_W_0F70_P_1 */
10685 { "vpshufhw", { XM, EXx, Ib }, 0 },
10686 },
10687 {
10688 /* VEX_W_0F70_P_2 */
10689 { "vpshufd", { XM, EXx, Ib }, 0 },
10690 },
10691 {
10692 /* VEX_W_0F70_P_3 */
10693 { "vpshuflw", { XM, EXx, Ib }, 0 },
10694 },
10695 {
10696 /* VEX_W_0F71_R_2_P_2 */
10697 { "vpsrlw", { Vex, XS, Ib }, 0 },
10698 },
10699 {
10700 /* VEX_W_0F71_R_4_P_2 */
10701 { "vpsraw", { Vex, XS, Ib }, 0 },
10702 },
10703 {
10704 /* VEX_W_0F71_R_6_P_2 */
10705 { "vpsllw", { Vex, XS, Ib }, 0 },
10706 },
10707 {
10708 /* VEX_W_0F72_R_2_P_2 */
10709 { "vpsrld", { Vex, XS, Ib }, 0 },
10710 },
10711 {
10712 /* VEX_W_0F72_R_4_P_2 */
10713 { "vpsrad", { Vex, XS, Ib }, 0 },
10714 },
10715 {
10716 /* VEX_W_0F72_R_6_P_2 */
10717 { "vpslld", { Vex, XS, Ib }, 0 },
10718 },
10719 {
10720 /* VEX_W_0F73_R_2_P_2 */
10721 { "vpsrlq", { Vex, XS, Ib }, 0 },
10722 },
10723 {
10724 /* VEX_W_0F73_R_3_P_2 */
10725 { "vpsrldq", { Vex, XS, Ib }, 0 },
10726 },
10727 {
10728 /* VEX_W_0F73_R_6_P_2 */
10729 { "vpsllq", { Vex, XS, Ib }, 0 },
10730 },
10731 {
10732 /* VEX_W_0F73_R_7_P_2 */
10733 { "vpslldq", { Vex, XS, Ib }, 0 },
10734 },
10735 {
10736 /* VEX_W_0F74_P_2 */
10737 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10738 },
10739 {
10740 /* VEX_W_0F75_P_2 */
10741 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10742 },
10743 {
10744 /* VEX_W_0F76_P_2 */
10745 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10746 },
10747 {
10748 /* VEX_W_0F77_P_0 */
10749 { "", { VZERO }, 0 },
10750 },
10751 {
10752 /* VEX_W_0F7C_P_2 */
10753 { "vhaddpd", { XM, Vex, EXx }, 0 },
10754 },
10755 {
10756 /* VEX_W_0F7C_P_3 */
10757 { "vhaddps", { XM, Vex, EXx }, 0 },
10758 },
10759 {
10760 /* VEX_W_0F7D_P_2 */
10761 { "vhsubpd", { XM, Vex, EXx }, 0 },
10762 },
10763 {
10764 /* VEX_W_0F7D_P_3 */
10765 { "vhsubps", { XM, Vex, EXx }, 0 },
10766 },
10767 {
10768 /* VEX_W_0F7E_P_1 */
10769 { "vmovq", { XMScalar, EXqScalar }, 0 },
10770 },
10771 {
10772 /* VEX_W_0F7F_P_1 */
10773 { "vmovdqu", { EXxS, XM }, 0 },
10774 },
10775 {
10776 /* VEX_W_0F7F_P_2 */
10777 { "vmovdqa", { EXxS, XM }, 0 },
10778 },
10779 {
10780 /* VEX_W_0F90_P_0_LEN_0 */
10781 { "kmovw", { MaskG, MaskE }, 0 },
10782 { "kmovq", { MaskG, MaskE }, 0 },
10783 },
10784 {
10785 /* VEX_W_0F90_P_2_LEN_0 */
10786 { "kmovb", { MaskG, MaskBDE }, 0 },
10787 { "kmovd", { MaskG, MaskBDE }, 0 },
10788 },
10789 {
10790 /* VEX_W_0F91_P_0_LEN_0 */
10791 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10792 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10793 },
10794 {
10795 /* VEX_W_0F91_P_2_LEN_0 */
10796 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10797 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10798 },
10799 {
10800 /* VEX_W_0F92_P_0_LEN_0 */
10801 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10802 },
10803 {
10804 /* VEX_W_0F92_P_2_LEN_0 */
10805 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10806 },
10807 {
10808 /* VEX_W_0F92_P_3_LEN_0 */
10809 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10810 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10811 },
10812 {
10813 /* VEX_W_0F93_P_0_LEN_0 */
10814 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10815 },
10816 {
10817 /* VEX_W_0F93_P_2_LEN_0 */
10818 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10819 },
10820 {
10821 /* VEX_W_0F93_P_3_LEN_0 */
10822 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10823 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10824 },
10825 {
10826 /* VEX_W_0F98_P_0_LEN_0 */
10827 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10828 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10829 },
10830 {
10831 /* VEX_W_0F98_P_2_LEN_0 */
10832 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10833 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10834 },
10835 {
10836 /* VEX_W_0F99_P_0_LEN_0 */
10837 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10838 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10839 },
10840 {
10841 /* VEX_W_0F99_P_2_LEN_0 */
10842 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10843 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10844 },
10845 {
10846 /* VEX_W_0FAE_R_2_M_0 */
10847 { "vldmxcsr", { Md }, 0 },
10848 },
10849 {
10850 /* VEX_W_0FAE_R_3_M_0 */
10851 { "vstmxcsr", { Md }, 0 },
10852 },
10853 {
10854 /* VEX_W_0FC2_P_0 */
10855 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10856 },
10857 {
10858 /* VEX_W_0FC2_P_1 */
10859 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10860 },
10861 {
10862 /* VEX_W_0FC2_P_2 */
10863 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10864 },
10865 {
10866 /* VEX_W_0FC2_P_3 */
10867 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10868 },
10869 {
10870 /* VEX_W_0FC4_P_2 */
10871 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10872 },
10873 {
10874 /* VEX_W_0FC5_P_2 */
10875 { "vpextrw", { Gdq, XS, Ib }, 0 },
10876 },
10877 {
10878 /* VEX_W_0FD0_P_2 */
10879 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10880 },
10881 {
10882 /* VEX_W_0FD0_P_3 */
10883 { "vaddsubps", { XM, Vex, EXx }, 0 },
10884 },
10885 {
10886 /* VEX_W_0FD1_P_2 */
10887 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10888 },
10889 {
10890 /* VEX_W_0FD2_P_2 */
10891 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10892 },
10893 {
10894 /* VEX_W_0FD3_P_2 */
10895 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10896 },
10897 {
10898 /* VEX_W_0FD4_P_2 */
10899 { "vpaddq", { XM, Vex, EXx }, 0 },
10900 },
10901 {
10902 /* VEX_W_0FD5_P_2 */
10903 { "vpmullw", { XM, Vex, EXx }, 0 },
10904 },
10905 {
10906 /* VEX_W_0FD6_P_2 */
10907 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10908 },
10909 {
10910 /* VEX_W_0FD7_P_2_M_1 */
10911 { "vpmovmskb", { Gdq, XS }, 0 },
10912 },
10913 {
10914 /* VEX_W_0FD8_P_2 */
10915 { "vpsubusb", { XM, Vex, EXx }, 0 },
10916 },
10917 {
10918 /* VEX_W_0FD9_P_2 */
10919 { "vpsubusw", { XM, Vex, EXx }, 0 },
10920 },
10921 {
10922 /* VEX_W_0FDA_P_2 */
10923 { "vpminub", { XM, Vex, EXx }, 0 },
10924 },
10925 {
10926 /* VEX_W_0FDB_P_2 */
10927 { "vpand", { XM, Vex, EXx }, 0 },
10928 },
10929 {
10930 /* VEX_W_0FDC_P_2 */
10931 { "vpaddusb", { XM, Vex, EXx }, 0 },
10932 },
10933 {
10934 /* VEX_W_0FDD_P_2 */
10935 { "vpaddusw", { XM, Vex, EXx }, 0 },
10936 },
10937 {
10938 /* VEX_W_0FDE_P_2 */
10939 { "vpmaxub", { XM, Vex, EXx }, 0 },
10940 },
10941 {
10942 /* VEX_W_0FDF_P_2 */
10943 { "vpandn", { XM, Vex, EXx }, 0 },
10944 },
10945 {
10946 /* VEX_W_0FE0_P_2 */
10947 { "vpavgb", { XM, Vex, EXx }, 0 },
10948 },
10949 {
10950 /* VEX_W_0FE1_P_2 */
10951 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10952 },
10953 {
10954 /* VEX_W_0FE2_P_2 */
10955 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10956 },
10957 {
10958 /* VEX_W_0FE3_P_2 */
10959 { "vpavgw", { XM, Vex, EXx }, 0 },
10960 },
10961 {
10962 /* VEX_W_0FE4_P_2 */
10963 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10964 },
10965 {
10966 /* VEX_W_0FE5_P_2 */
10967 { "vpmulhw", { XM, Vex, EXx }, 0 },
10968 },
10969 {
10970 /* VEX_W_0FE6_P_1 */
10971 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10972 },
10973 {
10974 /* VEX_W_0FE6_P_2 */
10975 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10976 },
10977 {
10978 /* VEX_W_0FE6_P_3 */
10979 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10980 },
10981 {
10982 /* VEX_W_0FE7_P_2_M_0 */
10983 { "vmovntdq", { Mx, XM }, 0 },
10984 },
10985 {
10986 /* VEX_W_0FE8_P_2 */
10987 { "vpsubsb", { XM, Vex, EXx }, 0 },
10988 },
10989 {
10990 /* VEX_W_0FE9_P_2 */
10991 { "vpsubsw", { XM, Vex, EXx }, 0 },
10992 },
10993 {
10994 /* VEX_W_0FEA_P_2 */
10995 { "vpminsw", { XM, Vex, EXx }, 0 },
10996 },
10997 {
10998 /* VEX_W_0FEB_P_2 */
10999 { "vpor", { XM, Vex, EXx }, 0 },
11000 },
11001 {
11002 /* VEX_W_0FEC_P_2 */
11003 { "vpaddsb", { XM, Vex, EXx }, 0 },
11004 },
11005 {
11006 /* VEX_W_0FED_P_2 */
11007 { "vpaddsw", { XM, Vex, EXx }, 0 },
11008 },
11009 {
11010 /* VEX_W_0FEE_P_2 */
11011 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11012 },
11013 {
11014 /* VEX_W_0FEF_P_2 */
11015 { "vpxor", { XM, Vex, EXx }, 0 },
11016 },
11017 {
11018 /* VEX_W_0FF0_P_3_M_0 */
11019 { "vlddqu", { XM, M }, 0 },
11020 },
11021 {
11022 /* VEX_W_0FF1_P_2 */
11023 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11024 },
11025 {
11026 /* VEX_W_0FF2_P_2 */
11027 { "vpslld", { XM, Vex, EXxmm }, 0 },
11028 },
11029 {
11030 /* VEX_W_0FF3_P_2 */
11031 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11032 },
11033 {
11034 /* VEX_W_0FF4_P_2 */
11035 { "vpmuludq", { XM, Vex, EXx }, 0 },
11036 },
11037 {
11038 /* VEX_W_0FF5_P_2 */
11039 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11040 },
11041 {
11042 /* VEX_W_0FF6_P_2 */
11043 { "vpsadbw", { XM, Vex, EXx }, 0 },
11044 },
11045 {
11046 /* VEX_W_0FF7_P_2 */
11047 { "vmaskmovdqu", { XM, XS }, 0 },
11048 },
11049 {
11050 /* VEX_W_0FF8_P_2 */
11051 { "vpsubb", { XM, Vex, EXx }, 0 },
11052 },
11053 {
11054 /* VEX_W_0FF9_P_2 */
11055 { "vpsubw", { XM, Vex, EXx }, 0 },
11056 },
11057 {
11058 /* VEX_W_0FFA_P_2 */
11059 { "vpsubd", { XM, Vex, EXx }, 0 },
11060 },
11061 {
11062 /* VEX_W_0FFB_P_2 */
11063 { "vpsubq", { XM, Vex, EXx }, 0 },
11064 },
11065 {
11066 /* VEX_W_0FFC_P_2 */
11067 { "vpaddb", { XM, Vex, EXx }, 0 },
11068 },
11069 {
11070 /* VEX_W_0FFD_P_2 */
11071 { "vpaddw", { XM, Vex, EXx }, 0 },
11072 },
11073 {
11074 /* VEX_W_0FFE_P_2 */
11075 { "vpaddd", { XM, Vex, EXx }, 0 },
11076 },
11077 {
11078 /* VEX_W_0F3800_P_2 */
11079 { "vpshufb", { XM, Vex, EXx }, 0 },
11080 },
11081 {
11082 /* VEX_W_0F3801_P_2 */
11083 { "vphaddw", { XM, Vex, EXx }, 0 },
11084 },
11085 {
11086 /* VEX_W_0F3802_P_2 */
11087 { "vphaddd", { XM, Vex, EXx }, 0 },
11088 },
11089 {
11090 /* VEX_W_0F3803_P_2 */
11091 { "vphaddsw", { XM, Vex, EXx }, 0 },
11092 },
11093 {
11094 /* VEX_W_0F3804_P_2 */
11095 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11096 },
11097 {
11098 /* VEX_W_0F3805_P_2 */
11099 { "vphsubw", { XM, Vex, EXx }, 0 },
11100 },
11101 {
11102 /* VEX_W_0F3806_P_2 */
11103 { "vphsubd", { XM, Vex, EXx }, 0 },
11104 },
11105 {
11106 /* VEX_W_0F3807_P_2 */
11107 { "vphsubsw", { XM, Vex, EXx }, 0 },
11108 },
11109 {
11110 /* VEX_W_0F3808_P_2 */
11111 { "vpsignb", { XM, Vex, EXx }, 0 },
11112 },
11113 {
11114 /* VEX_W_0F3809_P_2 */
11115 { "vpsignw", { XM, Vex, EXx }, 0 },
11116 },
11117 {
11118 /* VEX_W_0F380A_P_2 */
11119 { "vpsignd", { XM, Vex, EXx }, 0 },
11120 },
11121 {
11122 /* VEX_W_0F380B_P_2 */
11123 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11124 },
11125 {
11126 /* VEX_W_0F380C_P_2 */
11127 { "vpermilps", { XM, Vex, EXx }, 0 },
11128 },
11129 {
11130 /* VEX_W_0F380D_P_2 */
11131 { "vpermilpd", { XM, Vex, EXx }, 0 },
11132 },
11133 {
11134 /* VEX_W_0F380E_P_2 */
11135 { "vtestps", { XM, EXx }, 0 },
11136 },
11137 {
11138 /* VEX_W_0F380F_P_2 */
11139 { "vtestpd", { XM, EXx }, 0 },
11140 },
11141 {
11142 /* VEX_W_0F3816_P_2 */
11143 { "vpermps", { XM, Vex, EXx }, 0 },
11144 },
11145 {
11146 /* VEX_W_0F3817_P_2 */
11147 { "vptest", { XM, EXx }, 0 },
11148 },
11149 {
11150 /* VEX_W_0F3818_P_2 */
11151 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11152 },
11153 {
11154 /* VEX_W_0F3819_P_2 */
11155 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11156 },
11157 {
11158 /* VEX_W_0F381A_P_2_M_0 */
11159 { "vbroadcastf128", { XM, Mxmm }, 0 },
11160 },
11161 {
11162 /* VEX_W_0F381C_P_2 */
11163 { "vpabsb", { XM, EXx }, 0 },
11164 },
11165 {
11166 /* VEX_W_0F381D_P_2 */
11167 { "vpabsw", { XM, EXx }, 0 },
11168 },
11169 {
11170 /* VEX_W_0F381E_P_2 */
11171 { "vpabsd", { XM, EXx }, 0 },
11172 },
11173 {
11174 /* VEX_W_0F3820_P_2 */
11175 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11176 },
11177 {
11178 /* VEX_W_0F3821_P_2 */
11179 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11180 },
11181 {
11182 /* VEX_W_0F3822_P_2 */
11183 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11184 },
11185 {
11186 /* VEX_W_0F3823_P_2 */
11187 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11188 },
11189 {
11190 /* VEX_W_0F3824_P_2 */
11191 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11192 },
11193 {
11194 /* VEX_W_0F3825_P_2 */
11195 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11196 },
11197 {
11198 /* VEX_W_0F3828_P_2 */
11199 { "vpmuldq", { XM, Vex, EXx }, 0 },
11200 },
11201 {
11202 /* VEX_W_0F3829_P_2 */
11203 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11204 },
11205 {
11206 /* VEX_W_0F382A_P_2_M_0 */
11207 { "vmovntdqa", { XM, Mx }, 0 },
11208 },
11209 {
11210 /* VEX_W_0F382B_P_2 */
11211 { "vpackusdw", { XM, Vex, EXx }, 0 },
11212 },
11213 {
11214 /* VEX_W_0F382C_P_2_M_0 */
11215 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11216 },
11217 {
11218 /* VEX_W_0F382D_P_2_M_0 */
11219 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11220 },
11221 {
11222 /* VEX_W_0F382E_P_2_M_0 */
11223 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11224 },
11225 {
11226 /* VEX_W_0F382F_P_2_M_0 */
11227 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11228 },
11229 {
11230 /* VEX_W_0F3830_P_2 */
11231 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11232 },
11233 {
11234 /* VEX_W_0F3831_P_2 */
11235 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11236 },
11237 {
11238 /* VEX_W_0F3832_P_2 */
11239 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11240 },
11241 {
11242 /* VEX_W_0F3833_P_2 */
11243 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11244 },
11245 {
11246 /* VEX_W_0F3834_P_2 */
11247 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11248 },
11249 {
11250 /* VEX_W_0F3835_P_2 */
11251 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11252 },
11253 {
11254 /* VEX_W_0F3836_P_2 */
11255 { "vpermd", { XM, Vex, EXx }, 0 },
11256 },
11257 {
11258 /* VEX_W_0F3837_P_2 */
11259 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11260 },
11261 {
11262 /* VEX_W_0F3838_P_2 */
11263 { "vpminsb", { XM, Vex, EXx }, 0 },
11264 },
11265 {
11266 /* VEX_W_0F3839_P_2 */
11267 { "vpminsd", { XM, Vex, EXx }, 0 },
11268 },
11269 {
11270 /* VEX_W_0F383A_P_2 */
11271 { "vpminuw", { XM, Vex, EXx }, 0 },
11272 },
11273 {
11274 /* VEX_W_0F383B_P_2 */
11275 { "vpminud", { XM, Vex, EXx }, 0 },
11276 },
11277 {
11278 /* VEX_W_0F383C_P_2 */
11279 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11280 },
11281 {
11282 /* VEX_W_0F383D_P_2 */
11283 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11284 },
11285 {
11286 /* VEX_W_0F383E_P_2 */
11287 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11288 },
11289 {
11290 /* VEX_W_0F383F_P_2 */
11291 { "vpmaxud", { XM, Vex, EXx }, 0 },
11292 },
11293 {
11294 /* VEX_W_0F3840_P_2 */
11295 { "vpmulld", { XM, Vex, EXx }, 0 },
11296 },
11297 {
11298 /* VEX_W_0F3841_P_2 */
11299 { "vphminposuw", { XM, EXx }, 0 },
11300 },
11301 {
11302 /* VEX_W_0F3846_P_2 */
11303 { "vpsravd", { XM, Vex, EXx }, 0 },
11304 },
11305 {
11306 /* VEX_W_0F3858_P_2 */
11307 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11308 },
11309 {
11310 /* VEX_W_0F3859_P_2 */
11311 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11312 },
11313 {
11314 /* VEX_W_0F385A_P_2_M_0 */
11315 { "vbroadcasti128", { XM, Mxmm }, 0 },
11316 },
11317 {
11318 /* VEX_W_0F3878_P_2 */
11319 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11320 },
11321 {
11322 /* VEX_W_0F3879_P_2 */
11323 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11324 },
11325 {
11326 /* VEX_W_0F38CF_P_2 */
11327 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11328 },
11329 {
11330 /* VEX_W_0F38DB_P_2 */
11331 { "vaesimc", { XM, EXx }, 0 },
11332 },
11333 {
11334 /* VEX_W_0F38DC_P_2 */
11335 { "vaesenc", { XM, Vex128, EXx }, 0 },
11336 },
11337 {
11338 /* VEX_W_0F38DD_P_2 */
11339 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11340 },
11341 {
11342 /* VEX_W_0F38DE_P_2 */
11343 { "vaesdec", { XM, Vex128, EXx }, 0 },
11344 },
11345 {
11346 /* VEX_W_0F38DF_P_2 */
11347 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11348 },
11349 {
11350 /* VEX_W_0F3A00_P_2 */
11351 { Bad_Opcode },
11352 { "vpermq", { XM, EXx, Ib }, 0 },
11353 },
11354 {
11355 /* VEX_W_0F3A01_P_2 */
11356 { Bad_Opcode },
11357 { "vpermpd", { XM, EXx, Ib }, 0 },
11358 },
11359 {
11360 /* VEX_W_0F3A02_P_2 */
11361 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11362 },
11363 {
11364 /* VEX_W_0F3A04_P_2 */
11365 { "vpermilps", { XM, EXx, Ib }, 0 },
11366 },
11367 {
11368 /* VEX_W_0F3A05_P_2 */
11369 { "vpermilpd", { XM, EXx, Ib }, 0 },
11370 },
11371 {
11372 /* VEX_W_0F3A06_P_2 */
11373 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11374 },
11375 {
11376 /* VEX_W_0F3A08_P_2 */
11377 { "vroundps", { XM, EXx, Ib }, 0 },
11378 },
11379 {
11380 /* VEX_W_0F3A09_P_2 */
11381 { "vroundpd", { XM, EXx, Ib }, 0 },
11382 },
11383 {
11384 /* VEX_W_0F3A0A_P_2 */
11385 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11386 },
11387 {
11388 /* VEX_W_0F3A0B_P_2 */
11389 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11390 },
11391 {
11392 /* VEX_W_0F3A0C_P_2 */
11393 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11394 },
11395 {
11396 /* VEX_W_0F3A0D_P_2 */
11397 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11398 },
11399 {
11400 /* VEX_W_0F3A0E_P_2 */
11401 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11402 },
11403 {
11404 /* VEX_W_0F3A0F_P_2 */
11405 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11406 },
11407 {
11408 /* VEX_W_0F3A14_P_2 */
11409 { "vpextrb", { Edqb, XM, Ib }, 0 },
11410 },
11411 {
11412 /* VEX_W_0F3A15_P_2 */
11413 { "vpextrw", { Edqw, XM, Ib }, 0 },
11414 },
11415 {
11416 /* VEX_W_0F3A18_P_2 */
11417 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11418 },
11419 {
11420 /* VEX_W_0F3A19_P_2 */
11421 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11422 },
11423 {
11424 /* VEX_W_0F3A20_P_2 */
11425 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11426 },
11427 {
11428 /* VEX_W_0F3A21_P_2 */
11429 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11430 },
11431 {
11432 /* VEX_W_0F3A30_P_2_LEN_0 */
11433 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11434 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11435 },
11436 {
11437 /* VEX_W_0F3A31_P_2_LEN_0 */
11438 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11439 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11440 },
11441 {
11442 /* VEX_W_0F3A32_P_2_LEN_0 */
11443 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11444 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11445 },
11446 {
11447 /* VEX_W_0F3A33_P_2_LEN_0 */
11448 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11449 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11450 },
11451 {
11452 /* VEX_W_0F3A38_P_2 */
11453 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11454 },
11455 {
11456 /* VEX_W_0F3A39_P_2 */
11457 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11458 },
11459 {
11460 /* VEX_W_0F3A40_P_2 */
11461 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11462 },
11463 {
11464 /* VEX_W_0F3A41_P_2 */
11465 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11466 },
11467 {
11468 /* VEX_W_0F3A42_P_2 */
11469 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11470 },
11471 {
11472 /* VEX_W_0F3A44_P_2 */
11473 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11474 },
11475 {
11476 /* VEX_W_0F3A46_P_2 */
11477 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11478 },
11479 {
11480 /* VEX_W_0F3A48_P_2 */
11481 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11482 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11483 },
11484 {
11485 /* VEX_W_0F3A49_P_2 */
11486 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11487 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11488 },
11489 {
11490 /* VEX_W_0F3A4A_P_2 */
11491 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11492 },
11493 {
11494 /* VEX_W_0F3A4B_P_2 */
11495 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11496 },
11497 {
11498 /* VEX_W_0F3A4C_P_2 */
11499 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11500 },
11501 {
11502 /* VEX_W_0F3A62_P_2 */
11503 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11504 },
11505 {
11506 /* VEX_W_0F3A63_P_2 */
11507 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11508 },
11509 {
11510 /* VEX_W_0F3ACE_P_2 */
11511 { Bad_Opcode },
11512 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11513 },
11514 {
11515 /* VEX_W_0F3ACF_P_2 */
11516 { Bad_Opcode },
11517 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11518 },
11519 {
11520 /* VEX_W_0F3ADF_P_2 */
11521 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11522 },
11523#define NEED_VEX_W_TABLE
11524#include "i386-dis-evex.h"
11525#undef NEED_VEX_W_TABLE
11526};
11527
11528static const struct dis386 mod_table[][2] = {
11529 {
11530 /* MOD_8D */
11531 { "leaS", { Gv, M }, 0 },
11532 },
11533 {
11534 /* MOD_C6_REG_7 */
11535 { Bad_Opcode },
11536 { RM_TABLE (RM_C6_REG_7) },
11537 },
11538 {
11539 /* MOD_C7_REG_7 */
11540 { Bad_Opcode },
11541 { RM_TABLE (RM_C7_REG_7) },
11542 },
11543 {
11544 /* MOD_FF_REG_3 */
11545 { "Jcall^", { indirEp }, 0 },
11546 },
11547 {
11548 /* MOD_FF_REG_5 */
11549 { "Jjmp^", { indirEp }, 0 },
11550 },
11551 {
11552 /* MOD_0F01_REG_0 */
11553 { X86_64_TABLE (X86_64_0F01_REG_0) },
11554 { RM_TABLE (RM_0F01_REG_0) },
11555 },
11556 {
11557 /* MOD_0F01_REG_1 */
11558 { X86_64_TABLE (X86_64_0F01_REG_1) },
11559 { RM_TABLE (RM_0F01_REG_1) },
11560 },
11561 {
11562 /* MOD_0F01_REG_2 */
11563 { X86_64_TABLE (X86_64_0F01_REG_2) },
11564 { RM_TABLE (RM_0F01_REG_2) },
11565 },
11566 {
11567 /* MOD_0F01_REG_3 */
11568 { X86_64_TABLE (X86_64_0F01_REG_3) },
11569 { RM_TABLE (RM_0F01_REG_3) },
11570 },
11571 {
11572 /* MOD_0F01_REG_5 */
11573 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11574 { RM_TABLE (RM_0F01_REG_5) },
11575 },
11576 {
11577 /* MOD_0F01_REG_7 */
11578 { "invlpg", { Mb }, 0 },
11579 { RM_TABLE (RM_0F01_REG_7) },
11580 },
11581 {
11582 /* MOD_0F12_PREFIX_0 */
11583 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11584 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11585 },
11586 {
11587 /* MOD_0F13 */
11588 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11589 },
11590 {
11591 /* MOD_0F16_PREFIX_0 */
11592 { "movhps", { XM, EXq }, 0 },
11593 { "movlhps", { XM, EXq }, 0 },
11594 },
11595 {
11596 /* MOD_0F17 */
11597 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11598 },
11599 {
11600 /* MOD_0F18_REG_0 */
11601 { "prefetchnta", { Mb }, 0 },
11602 },
11603 {
11604 /* MOD_0F18_REG_1 */
11605 { "prefetcht0", { Mb }, 0 },
11606 },
11607 {
11608 /* MOD_0F18_REG_2 */
11609 { "prefetcht1", { Mb }, 0 },
11610 },
11611 {
11612 /* MOD_0F18_REG_3 */
11613 { "prefetcht2", { Mb }, 0 },
11614 },
11615 {
11616 /* MOD_0F18_REG_4 */
11617 { "nop/reserved", { Mb }, 0 },
11618 },
11619 {
11620 /* MOD_0F18_REG_5 */
11621 { "nop/reserved", { Mb }, 0 },
11622 },
11623 {
11624 /* MOD_0F18_REG_6 */
11625 { "nop/reserved", { Mb }, 0 },
11626 },
11627 {
11628 /* MOD_0F18_REG_7 */
11629 { "nop/reserved", { Mb }, 0 },
11630 },
11631 {
11632 /* MOD_0F1A_PREFIX_0 */
11633 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11634 { "nopQ", { Ev }, 0 },
11635 },
11636 {
11637 /* MOD_0F1B_PREFIX_0 */
11638 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11639 { "nopQ", { Ev }, 0 },
11640 },
11641 {
11642 /* MOD_0F1B_PREFIX_1 */
11643 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11644 { "nopQ", { Ev }, 0 },
11645 },
11646 {
11647 /* MOD_0F1E_PREFIX_1 */
11648 { "nopQ", { Ev }, 0 },
11649 { REG_TABLE (REG_0F1E_MOD_3) },
11650 },
11651 {
11652 /* MOD_0F24 */
11653 { Bad_Opcode },
11654 { "movL", { Rd, Td }, 0 },
11655 },
11656 {
11657 /* MOD_0F26 */
11658 { Bad_Opcode },
11659 { "movL", { Td, Rd }, 0 },
11660 },
11661 {
11662 /* MOD_0F2B_PREFIX_0 */
11663 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11664 },
11665 {
11666 /* MOD_0F2B_PREFIX_1 */
11667 {"movntss", { Md, XM }, PREFIX_OPCODE },
11668 },
11669 {
11670 /* MOD_0F2B_PREFIX_2 */
11671 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11672 },
11673 {
11674 /* MOD_0F2B_PREFIX_3 */
11675 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11676 },
11677 {
11678 /* MOD_0F51 */
11679 { Bad_Opcode },
11680 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11681 },
11682 {
11683 /* MOD_0F71_REG_2 */
11684 { Bad_Opcode },
11685 { "psrlw", { MS, Ib }, 0 },
11686 },
11687 {
11688 /* MOD_0F71_REG_4 */
11689 { Bad_Opcode },
11690 { "psraw", { MS, Ib }, 0 },
11691 },
11692 {
11693 /* MOD_0F71_REG_6 */
11694 { Bad_Opcode },
11695 { "psllw", { MS, Ib }, 0 },
11696 },
11697 {
11698 /* MOD_0F72_REG_2 */
11699 { Bad_Opcode },
11700 { "psrld", { MS, Ib }, 0 },
11701 },
11702 {
11703 /* MOD_0F72_REG_4 */
11704 { Bad_Opcode },
11705 { "psrad", { MS, Ib }, 0 },
11706 },
11707 {
11708 /* MOD_0F72_REG_6 */
11709 { Bad_Opcode },
11710 { "pslld", { MS, Ib }, 0 },
11711 },
11712 {
11713 /* MOD_0F73_REG_2 */
11714 { Bad_Opcode },
11715 { "psrlq", { MS, Ib }, 0 },
11716 },
11717 {
11718 /* MOD_0F73_REG_3 */
11719 { Bad_Opcode },
11720 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11721 },
11722 {
11723 /* MOD_0F73_REG_6 */
11724 { Bad_Opcode },
11725 { "psllq", { MS, Ib }, 0 },
11726 },
11727 {
11728 /* MOD_0F73_REG_7 */
11729 { Bad_Opcode },
11730 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11731 },
11732 {
11733 /* MOD_0FAE_REG_0 */
11734 { "fxsave", { FXSAVE }, 0 },
11735 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11736 },
11737 {
11738 /* MOD_0FAE_REG_1 */
11739 { "fxrstor", { FXSAVE }, 0 },
11740 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11741 },
11742 {
11743 /* MOD_0FAE_REG_2 */
11744 { "ldmxcsr", { Md }, 0 },
11745 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11746 },
11747 {
11748 /* MOD_0FAE_REG_3 */
11749 { "stmxcsr", { Md }, 0 },
11750 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11751 },
11752 {
11753 /* MOD_0FAE_REG_4 */
11754 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11755 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11756 },
11757 {
11758 /* MOD_0FAE_REG_5 */
11759 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11760 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11761 },
11762 {
11763 /* MOD_0FAE_REG_6 */
11764 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11765 { RM_TABLE (RM_0FAE_REG_6) },
11766 },
11767 {
11768 /* MOD_0FAE_REG_7 */
11769 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11770 { RM_TABLE (RM_0FAE_REG_7) },
11771 },
11772 {
11773 /* MOD_0FB2 */
11774 { "lssS", { Gv, Mp }, 0 },
11775 },
11776 {
11777 /* MOD_0FB4 */
11778 { "lfsS", { Gv, Mp }, 0 },
11779 },
11780 {
11781 /* MOD_0FB5 */
11782 { "lgsS", { Gv, Mp }, 0 },
11783 },
11784 {
11785 /* MOD_0FC3 */
11786 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11787 },
11788 {
11789 /* MOD_0FC7_REG_3 */
11790 { "xrstors", { FXSAVE }, 0 },
11791 },
11792 {
11793 /* MOD_0FC7_REG_4 */
11794 { "xsavec", { FXSAVE }, 0 },
11795 },
11796 {
11797 /* MOD_0FC7_REG_5 */
11798 { "xsaves", { FXSAVE }, 0 },
11799 },
11800 {
11801 /* MOD_0FC7_REG_6 */
11802 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11803 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11804 },
11805 {
11806 /* MOD_0FC7_REG_7 */
11807 { "vmptrst", { Mq }, 0 },
11808 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11809 },
11810 {
11811 /* MOD_0FD7 */
11812 { Bad_Opcode },
11813 { "pmovmskb", { Gdq, MS }, 0 },
11814 },
11815 {
11816 /* MOD_0FE7_PREFIX_2 */
11817 { "movntdq", { Mx, XM }, 0 },
11818 },
11819 {
11820 /* MOD_0FF0_PREFIX_3 */
11821 { "lddqu", { XM, M }, 0 },
11822 },
11823 {
11824 /* MOD_0F382A_PREFIX_2 */
11825 { "movntdqa", { XM, Mx }, 0 },
11826 },
11827 {
11828 /* MOD_0F38F5_PREFIX_2 */
11829 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11830 },
11831 {
11832 /* MOD_0F38F6_PREFIX_0 */
11833 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11834 },
11835 {
11836 /* MOD_62_32BIT */
11837 { "bound{S|}", { Gv, Ma }, 0 },
11838 { EVEX_TABLE (EVEX_0F) },
11839 },
11840 {
11841 /* MOD_C4_32BIT */
11842 { "lesS", { Gv, Mp }, 0 },
11843 { VEX_C4_TABLE (VEX_0F) },
11844 },
11845 {
11846 /* MOD_C5_32BIT */
11847 { "ldsS", { Gv, Mp }, 0 },
11848 { VEX_C5_TABLE (VEX_0F) },
11849 },
11850 {
11851 /* MOD_VEX_0F12_PREFIX_0 */
11852 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11853 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11854 },
11855 {
11856 /* MOD_VEX_0F13 */
11857 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11858 },
11859 {
11860 /* MOD_VEX_0F16_PREFIX_0 */
11861 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11862 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11863 },
11864 {
11865 /* MOD_VEX_0F17 */
11866 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11867 },
11868 {
11869 /* MOD_VEX_0F2B */
11870 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11871 },
11872 {
11873 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11874 { Bad_Opcode },
11875 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11876 },
11877 {
11878 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11879 { Bad_Opcode },
11880 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11881 },
11882 {
11883 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11884 { Bad_Opcode },
11885 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11886 },
11887 {
11888 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11889 { Bad_Opcode },
11890 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11891 },
11892 {
11893 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11894 { Bad_Opcode },
11895 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11896 },
11897 {
11898 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11899 { Bad_Opcode },
11900 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11901 },
11902 {
11903 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11904 { Bad_Opcode },
11905 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11906 },
11907 {
11908 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11909 { Bad_Opcode },
11910 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11911 },
11912 {
11913 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11914 { Bad_Opcode },
11915 { "knotw", { MaskG, MaskR }, 0 },
11916 },
11917 {
11918 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11919 { Bad_Opcode },
11920 { "knotq", { MaskG, MaskR }, 0 },
11921 },
11922 {
11923 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11924 { Bad_Opcode },
11925 { "knotb", { MaskG, MaskR }, 0 },
11926 },
11927 {
11928 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11929 { Bad_Opcode },
11930 { "knotd", { MaskG, MaskR }, 0 },
11931 },
11932 {
11933 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11934 { Bad_Opcode },
11935 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11936 },
11937 {
11938 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11939 { Bad_Opcode },
11940 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11941 },
11942 {
11943 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11944 { Bad_Opcode },
11945 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11946 },
11947 {
11948 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11949 { Bad_Opcode },
11950 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11951 },
11952 {
11953 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11954 { Bad_Opcode },
11955 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11956 },
11957 {
11958 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11959 { Bad_Opcode },
11960 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11961 },
11962 {
11963 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11964 { Bad_Opcode },
11965 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11966 },
11967 {
11968 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11969 { Bad_Opcode },
11970 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11971 },
11972 {
11973 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11974 { Bad_Opcode },
11975 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11976 },
11977 {
11978 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11979 { Bad_Opcode },
11980 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11981 },
11982 {
11983 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11984 { Bad_Opcode },
11985 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11986 },
11987 {
11988 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11989 { Bad_Opcode },
11990 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11991 },
11992 {
11993 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11994 { Bad_Opcode },
11995 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11996 },
11997 {
11998 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11999 { Bad_Opcode },
12000 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
12001 },
12002 {
12003 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12004 { Bad_Opcode },
12005 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
12006 },
12007 {
12008 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12009 { Bad_Opcode },
12010 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
12011 },
12012 {
12013 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12014 { Bad_Opcode },
12015 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
12016 },
12017 {
12018 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12019 { Bad_Opcode },
12020 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
12021 },
12022 {
12023 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12024 { Bad_Opcode },
12025 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
12026 },
12027 {
12028 /* MOD_VEX_0F50 */
12029 { Bad_Opcode },
12030 { VEX_W_TABLE (VEX_W_0F50_M_0) },
12031 },
12032 {
12033 /* MOD_VEX_0F71_REG_2 */
12034 { Bad_Opcode },
12035 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12036 },
12037 {
12038 /* MOD_VEX_0F71_REG_4 */
12039 { Bad_Opcode },
12040 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12041 },
12042 {
12043 /* MOD_VEX_0F71_REG_6 */
12044 { Bad_Opcode },
12045 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12046 },
12047 {
12048 /* MOD_VEX_0F72_REG_2 */
12049 { Bad_Opcode },
12050 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12051 },
12052 {
12053 /* MOD_VEX_0F72_REG_4 */
12054 { Bad_Opcode },
12055 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12056 },
12057 {
12058 /* MOD_VEX_0F72_REG_6 */
12059 { Bad_Opcode },
12060 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12061 },
12062 {
12063 /* MOD_VEX_0F73_REG_2 */
12064 { Bad_Opcode },
12065 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12066 },
12067 {
12068 /* MOD_VEX_0F73_REG_3 */
12069 { Bad_Opcode },
12070 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12071 },
12072 {
12073 /* MOD_VEX_0F73_REG_6 */
12074 { Bad_Opcode },
12075 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12076 },
12077 {
12078 /* MOD_VEX_0F73_REG_7 */
12079 { Bad_Opcode },
12080 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12081 },
12082 {
12083 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12084 { "kmovw", { Ew, MaskG }, 0 },
12085 { Bad_Opcode },
12086 },
12087 {
12088 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12089 { "kmovq", { Eq, MaskG }, 0 },
12090 { Bad_Opcode },
12091 },
12092 {
12093 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12094 { "kmovb", { Eb, MaskG }, 0 },
12095 { Bad_Opcode },
12096 },
12097 {
12098 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12099 { "kmovd", { Ed, MaskG }, 0 },
12100 { Bad_Opcode },
12101 },
12102 {
12103 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12104 { Bad_Opcode },
12105 { "kmovw", { MaskG, Rdq }, 0 },
12106 },
12107 {
12108 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12109 { Bad_Opcode },
12110 { "kmovb", { MaskG, Rdq }, 0 },
12111 },
12112 {
12113 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12114 { Bad_Opcode },
12115 { "kmovd", { MaskG, Rdq }, 0 },
12116 },
12117 {
12118 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12119 { Bad_Opcode },
12120 { "kmovq", { MaskG, Rdq }, 0 },
12121 },
12122 {
12123 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12124 { Bad_Opcode },
12125 { "kmovw", { Gdq, MaskR }, 0 },
12126 },
12127 {
12128 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12129 { Bad_Opcode },
12130 { "kmovb", { Gdq, MaskR }, 0 },
12131 },
12132 {
12133 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12134 { Bad_Opcode },
12135 { "kmovd", { Gdq, MaskR }, 0 },
12136 },
12137 {
12138 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12139 { Bad_Opcode },
12140 { "kmovq", { Gdq, MaskR }, 0 },
12141 },
12142 {
12143 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12144 { Bad_Opcode },
12145 { "kortestw", { MaskG, MaskR }, 0 },
12146 },
12147 {
12148 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12149 { Bad_Opcode },
12150 { "kortestq", { MaskG, MaskR }, 0 },
12151 },
12152 {
12153 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12154 { Bad_Opcode },
12155 { "kortestb", { MaskG, MaskR }, 0 },
12156 },
12157 {
12158 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12159 { Bad_Opcode },
12160 { "kortestd", { MaskG, MaskR }, 0 },
12161 },
12162 {
12163 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12164 { Bad_Opcode },
12165 { "ktestw", { MaskG, MaskR }, 0 },
12166 },
12167 {
12168 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12169 { Bad_Opcode },
12170 { "ktestq", { MaskG, MaskR }, 0 },
12171 },
12172 {
12173 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12174 { Bad_Opcode },
12175 { "ktestb", { MaskG, MaskR }, 0 },
12176 },
12177 {
12178 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12179 { Bad_Opcode },
12180 { "ktestd", { MaskG, MaskR }, 0 },
12181 },
12182 {
12183 /* MOD_VEX_0FAE_REG_2 */
12184 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12185 },
12186 {
12187 /* MOD_VEX_0FAE_REG_3 */
12188 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12189 },
12190 {
12191 /* MOD_VEX_0FD7_PREFIX_2 */
12192 { Bad_Opcode },
12193 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12194 },
12195 {
12196 /* MOD_VEX_0FE7_PREFIX_2 */
12197 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12198 },
12199 {
12200 /* MOD_VEX_0FF0_PREFIX_3 */
12201 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12202 },
12203 {
12204 /* MOD_VEX_0F381A_PREFIX_2 */
12205 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12206 },
12207 {
12208 /* MOD_VEX_0F382A_PREFIX_2 */
12209 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12210 },
12211 {
12212 /* MOD_VEX_0F382C_PREFIX_2 */
12213 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12214 },
12215 {
12216 /* MOD_VEX_0F382D_PREFIX_2 */
12217 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12218 },
12219 {
12220 /* MOD_VEX_0F382E_PREFIX_2 */
12221 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12222 },
12223 {
12224 /* MOD_VEX_0F382F_PREFIX_2 */
12225 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12226 },
12227 {
12228 /* MOD_VEX_0F385A_PREFIX_2 */
12229 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12230 },
12231 {
12232 /* MOD_VEX_0F388C_PREFIX_2 */
12233 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12234 },
12235 {
12236 /* MOD_VEX_0F388E_PREFIX_2 */
12237 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12238 },
12239 {
12240 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12241 { Bad_Opcode },
12242 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12243 },
12244 {
12245 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12246 { Bad_Opcode },
12247 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12248 },
12249 {
12250 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12251 { Bad_Opcode },
12252 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12253 },
12254 {
12255 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12256 { Bad_Opcode },
12257 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12258 },
12259 {
12260 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12261 { Bad_Opcode },
12262 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12263 },
12264 {
12265 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12266 { Bad_Opcode },
12267 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12268 },
12269 {
12270 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12271 { Bad_Opcode },
12272 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12273 },
12274 {
12275 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12276 { Bad_Opcode },
12277 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12278 },
12279#define NEED_MOD_TABLE
12280#include "i386-dis-evex.h"
12281#undef NEED_MOD_TABLE
12282};
12283
12284static const struct dis386 rm_table[][8] = {
12285 {
12286 /* RM_C6_REG_7 */
12287 { "xabort", { Skip_MODRM, Ib }, 0 },
12288 },
12289 {
12290 /* RM_C7_REG_7 */
12291 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12292 },
12293 {
12294 /* RM_0F01_REG_0 */
12295 { Bad_Opcode },
12296 { "vmcall", { Skip_MODRM }, 0 },
12297 { "vmlaunch", { Skip_MODRM }, 0 },
12298 { "vmresume", { Skip_MODRM }, 0 },
12299 { "vmxoff", { Skip_MODRM }, 0 },
12300 },
12301 {
12302 /* RM_0F01_REG_1 */
12303 { "monitor", { { OP_Monitor, 0 } }, 0 },
12304 { "mwait", { { OP_Mwait, 0 } }, 0 },
12305 { "clac", { Skip_MODRM }, 0 },
12306 { "stac", { Skip_MODRM }, 0 },
12307 { Bad_Opcode },
12308 { Bad_Opcode },
12309 { Bad_Opcode },
12310 { "encls", { Skip_MODRM }, 0 },
12311 },
12312 {
12313 /* RM_0F01_REG_2 */
12314 { "xgetbv", { Skip_MODRM }, 0 },
12315 { "xsetbv", { Skip_MODRM }, 0 },
12316 { Bad_Opcode },
12317 { Bad_Opcode },
12318 { "vmfunc", { Skip_MODRM }, 0 },
12319 { "xend", { Skip_MODRM }, 0 },
12320 { "xtest", { Skip_MODRM }, 0 },
12321 { "enclu", { Skip_MODRM }, 0 },
12322 },
12323 {
12324 /* RM_0F01_REG_3 */
12325 { "vmrun", { Skip_MODRM }, 0 },
12326 { "vmmcall", { Skip_MODRM }, 0 },
12327 { "vmload", { Skip_MODRM }, 0 },
12328 { "vmsave", { Skip_MODRM }, 0 },
12329 { "stgi", { Skip_MODRM }, 0 },
12330 { "clgi", { Skip_MODRM }, 0 },
12331 { "skinit", { Skip_MODRM }, 0 },
12332 { "invlpga", { Skip_MODRM }, 0 },
12333 },
12334 {
12335 /* RM_0F01_REG_5 */
12336 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12337 { Bad_Opcode },
12338 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12339 { Bad_Opcode },
12340 { Bad_Opcode },
12341 { Bad_Opcode },
12342 { "rdpkru", { Skip_MODRM }, 0 },
12343 { "wrpkru", { Skip_MODRM }, 0 },
12344 },
12345 {
12346 /* RM_0F01_REG_7 */
12347 { "swapgs", { Skip_MODRM }, 0 },
12348 { "rdtscp", { Skip_MODRM }, 0 },
12349 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12350 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12351 { "clzero", { Skip_MODRM }, 0 },
12352 },
12353 {
12354 /* RM_0F1E_MOD_3_REG_7 */
12355 { "nopQ", { Ev }, 0 },
12356 { "nopQ", { Ev }, 0 },
12357 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12358 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12359 { "nopQ", { Ev }, 0 },
12360 { "nopQ", { Ev }, 0 },
12361 { "nopQ", { Ev }, 0 },
12362 { "nopQ", { Ev }, 0 },
12363 },
12364 {
12365 /* RM_0FAE_REG_6 */
12366 { "mfence", { Skip_MODRM }, 0 },
12367 },
12368 {
12369 /* RM_0FAE_REG_7 */
12370 { "sfence", { Skip_MODRM }, 0 },
12371
12372 },
12373};
12374
12375#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12376
12377/* We use the high bit to indicate different name for the same
12378 prefix. */
12379#define REP_PREFIX (0xf3 | 0x100)
12380#define XACQUIRE_PREFIX (0xf2 | 0x200)
12381#define XRELEASE_PREFIX (0xf3 | 0x400)
12382#define BND_PREFIX (0xf2 | 0x400)
12383#define NOTRACK_PREFIX (0x3e | 0x100)
12384
12385static int
12386ckprefix (void)
12387{
12388 int newrex, i, length;
12389 rex = 0;
12390 rex_ignored = 0;
12391 prefixes = 0;
12392 used_prefixes = 0;
12393 rex_used = 0;
12394 last_lock_prefix = -1;
12395 last_repz_prefix = -1;
12396 last_repnz_prefix = -1;
12397 last_data_prefix = -1;
12398 last_addr_prefix = -1;
12399 last_rex_prefix = -1;
12400 last_seg_prefix = -1;
12401 fwait_prefix = -1;
12402 active_seg_prefix = 0;
12403 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12404 all_prefixes[i] = 0;
12405 i = 0;
12406 length = 0;
12407 /* The maximum instruction length is 15bytes. */
12408 while (length < MAX_CODE_LENGTH - 1)
12409 {
12410 FETCH_DATA (the_info, codep + 1);
12411 newrex = 0;
12412 switch (*codep)
12413 {
12414 /* REX prefixes family. */
12415 case 0x40:
12416 case 0x41:
12417 case 0x42:
12418 case 0x43:
12419 case 0x44:
12420 case 0x45:
12421 case 0x46:
12422 case 0x47:
12423 case 0x48:
12424 case 0x49:
12425 case 0x4a:
12426 case 0x4b:
12427 case 0x4c:
12428 case 0x4d:
12429 case 0x4e:
12430 case 0x4f:
12431 if (address_mode == mode_64bit)
12432 newrex = *codep;
12433 else
12434 return 1;
12435 last_rex_prefix = i;
12436 break;
12437 case 0xf3:
12438 prefixes |= PREFIX_REPZ;
12439 last_repz_prefix = i;
12440 break;
12441 case 0xf2:
12442 prefixes |= PREFIX_REPNZ;
12443 last_repnz_prefix = i;
12444 break;
12445 case 0xf0:
12446 prefixes |= PREFIX_LOCK;
12447 last_lock_prefix = i;
12448 break;
12449 case 0x2e:
12450 prefixes |= PREFIX_CS;
12451 last_seg_prefix = i;
12452 active_seg_prefix = PREFIX_CS;
12453 break;
12454 case 0x36:
12455 prefixes |= PREFIX_SS;
12456 last_seg_prefix = i;
12457 active_seg_prefix = PREFIX_SS;
12458 break;
12459 case 0x3e:
12460 prefixes |= PREFIX_DS;
12461 last_seg_prefix = i;
12462 active_seg_prefix = PREFIX_DS;
12463 break;
12464 case 0x26:
12465 prefixes |= PREFIX_ES;
12466 last_seg_prefix = i;
12467 active_seg_prefix = PREFIX_ES;
12468 break;
12469 case 0x64:
12470 prefixes |= PREFIX_FS;
12471 last_seg_prefix = i;
12472 active_seg_prefix = PREFIX_FS;
12473 break;
12474 case 0x65:
12475 prefixes |= PREFIX_GS;
12476 last_seg_prefix = i;
12477 active_seg_prefix = PREFIX_GS;
12478 break;
12479 case 0x66:
12480 prefixes |= PREFIX_DATA;
12481 last_data_prefix = i;
12482 break;
12483 case 0x67:
12484 prefixes |= PREFIX_ADDR;
12485 last_addr_prefix = i;
12486 break;
12487 case FWAIT_OPCODE:
12488 /* fwait is really an instruction. If there are prefixes
12489 before the fwait, they belong to the fwait, *not* to the
12490 following instruction. */
12491 fwait_prefix = i;
12492 if (prefixes || rex)
12493 {
12494 prefixes |= PREFIX_FWAIT;
12495 codep++;
12496 /* This ensures that the previous REX prefixes are noticed
12497 as unused prefixes, as in the return case below. */
12498 rex_used = rex;
12499 return 1;
12500 }
12501 prefixes = PREFIX_FWAIT;
12502 break;
12503 default:
12504 return 1;
12505 }
12506 /* Rex is ignored when followed by another prefix. */
12507 if (rex)
12508 {
12509 rex_used = rex;
12510 return 1;
12511 }
12512 if (*codep != FWAIT_OPCODE)
12513 all_prefixes[i++] = *codep;
12514 rex = newrex;
12515 codep++;
12516 length++;
12517 }
12518 return 0;
12519}
12520
12521/* Return the name of the prefix byte PREF, or NULL if PREF is not a
12522 prefix byte. */
12523
12524static const char *
12525prefix_name (int pref, int sizeflag)
12526{
12527 static const char *rexes [16] =
12528 {
12529 "rex", /* 0x40 */
12530 "rex.B", /* 0x41 */
12531 "rex.X", /* 0x42 */
12532 "rex.XB", /* 0x43 */
12533 "rex.R", /* 0x44 */
12534 "rex.RB", /* 0x45 */
12535 "rex.RX", /* 0x46 */
12536 "rex.RXB", /* 0x47 */
12537 "rex.W", /* 0x48 */
12538 "rex.WB", /* 0x49 */
12539 "rex.WX", /* 0x4a */
12540 "rex.WXB", /* 0x4b */
12541 "rex.WR", /* 0x4c */
12542 "rex.WRB", /* 0x4d */
12543 "rex.WRX", /* 0x4e */
12544 "rex.WRXB", /* 0x4f */
12545 };
12546
12547 switch (pref)
12548 {
12549 /* REX prefixes family. */
12550 case 0x40:
12551 case 0x41:
12552 case 0x42:
12553 case 0x43:
12554 case 0x44:
12555 case 0x45:
12556 case 0x46:
12557 case 0x47:
12558 case 0x48:
12559 case 0x49:
12560 case 0x4a:
12561 case 0x4b:
12562 case 0x4c:
12563 case 0x4d:
12564 case 0x4e:
12565 case 0x4f:
12566 return rexes [pref - 0x40];
12567 case 0xf3:
12568 return "repz";
12569 case 0xf2:
12570 return "repnz";
12571 case 0xf0:
12572 return "lock";
12573 case 0x2e:
12574 return "cs";
12575 case 0x36:
12576 return "ss";
12577 case 0x3e:
12578 return "ds";
12579 case 0x26:
12580 return "es";
12581 case 0x64:
12582 return "fs";
12583 case 0x65:
12584 return "gs";
12585 case 0x66:
12586 return (sizeflag & DFLAG) ? "data16" : "data32";
12587 case 0x67:
12588 if (address_mode == mode_64bit)
12589 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12590 else
12591 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12592 case FWAIT_OPCODE:
12593 return "fwait";
12594 case REP_PREFIX:
12595 return "rep";
12596 case XACQUIRE_PREFIX:
12597 return "xacquire";
12598 case XRELEASE_PREFIX:
12599 return "xrelease";
12600 case BND_PREFIX:
12601 return "bnd";
12602 case NOTRACK_PREFIX:
12603 return "notrack";
12604 default:
12605 return NULL;
12606 }
12607}
12608
12609static char op_out[MAX_OPERANDS][100];
12610static int op_ad, op_index[MAX_OPERANDS];
12611static int two_source_ops;
12612static bfd_vma op_address[MAX_OPERANDS];
12613static bfd_vma op_riprel[MAX_OPERANDS];
12614static bfd_vma start_pc;
12615
12616/*
12617 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12618 * (see topic "Redundant prefixes" in the "Differences from 8086"
12619 * section of the "Virtual 8086 Mode" chapter.)
12620 * 'pc' should be the address of this instruction, it will
12621 * be used to print the target address if this is a relative jump or call
12622 * The function returns the length of this instruction in bytes.
12623 */
12624
12625static char intel_syntax;
12626static char intel_mnemonic = !SYSV386_COMPAT;
12627static char open_char;
12628static char close_char;
12629static char separator_char;
12630static char scale_char;
12631
12632enum x86_64_isa
12633{
12634 amd64 = 0,
12635 intel64
12636};
12637
12638static enum x86_64_isa isa64;
12639
12640/* Here for backwards compatibility. When gdb stops using
12641 print_insn_i386_att and print_insn_i386_intel these functions can
12642 disappear, and print_insn_i386 be merged into print_insn. */
12643int
12644print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12645{
12646 intel_syntax = 0;
12647
12648 return print_insn (pc, info);
12649}
12650
12651int
12652print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12653{
12654 intel_syntax = 1;
12655
12656 return print_insn (pc, info);
12657}
12658
12659int
12660print_insn_i386 (bfd_vma pc, disassemble_info *info)
12661{
12662 intel_syntax = -1;
12663
12664 return print_insn (pc, info);
12665}
12666
12667void
12668print_i386_disassembler_options (FILE *stream)
12669{
12670 fprintf (stream, _("\n\
12671The following i386/x86-64 specific disassembler options are supported for use\n\
12672with the -M switch (multiple options should be separated by commas):\n"));
12673
12674 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12675 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12676 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12677 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12678 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12679 fprintf (stream, _(" att-mnemonic\n"
12680 " Display instruction in AT&T mnemonic\n"));
12681 fprintf (stream, _(" intel-mnemonic\n"
12682 " Display instruction in Intel mnemonic\n"));
12683 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12684 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12685 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12686 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12687 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12688 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12689 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12690 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12691}
12692
12693/* Bad opcode. */
12694static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12695
12696/* Get a pointer to struct dis386 with a valid name. */
12697
12698static const struct dis386 *
12699get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12700{
12701 int vindex, vex_table_index;
12702
12703 if (dp->name != NULL)
12704 return dp;
12705
12706 switch (dp->op[0].bytemode)
12707 {
12708 case USE_REG_TABLE:
12709 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12710 break;
12711
12712 case USE_MOD_TABLE:
12713 vindex = modrm.mod == 0x3 ? 1 : 0;
12714 dp = &mod_table[dp->op[1].bytemode][vindex];
12715 break;
12716
12717 case USE_RM_TABLE:
12718 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12719 break;
12720
12721 case USE_PREFIX_TABLE:
12722 if (need_vex)
12723 {
12724 /* The prefix in VEX is implicit. */
12725 switch (vex.prefix)
12726 {
12727 case 0:
12728 vindex = 0;
12729 break;
12730 case REPE_PREFIX_OPCODE:
12731 vindex = 1;
12732 break;
12733 case DATA_PREFIX_OPCODE:
12734 vindex = 2;
12735 break;
12736 case REPNE_PREFIX_OPCODE:
12737 vindex = 3;
12738 break;
12739 default:
12740 abort ();
12741 break;
12742 }
12743 }
12744 else
12745 {
12746 int last_prefix = -1;
12747 int prefix = 0;
12748 vindex = 0;
12749 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12750 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12751 last one wins. */
12752 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12753 {
12754 if (last_repz_prefix > last_repnz_prefix)
12755 {
12756 vindex = 1;
12757 prefix = PREFIX_REPZ;
12758 last_prefix = last_repz_prefix;
12759 }
12760 else
12761 {
12762 vindex = 3;
12763 prefix = PREFIX_REPNZ;
12764 last_prefix = last_repnz_prefix;
12765 }
12766
12767 /* Check if prefix should be ignored. */
12768 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12769 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12770 & prefix) != 0)
12771 vindex = 0;
12772 }
12773
12774 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12775 {
12776 vindex = 2;
12777 prefix = PREFIX_DATA;
12778 last_prefix = last_data_prefix;
12779 }
12780
12781 if (vindex != 0)
12782 {
12783 used_prefixes |= prefix;
12784 all_prefixes[last_prefix] = 0;
12785 }
12786 }
12787 dp = &prefix_table[dp->op[1].bytemode][vindex];
12788 break;
12789
12790 case USE_X86_64_TABLE:
12791 vindex = address_mode == mode_64bit ? 1 : 0;
12792 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12793 break;
12794
12795 case USE_3BYTE_TABLE:
12796 FETCH_DATA (info, codep + 2);
12797 vindex = *codep++;
12798 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12799 end_codep = codep;
12800 modrm.mod = (*codep >> 6) & 3;
12801 modrm.reg = (*codep >> 3) & 7;
12802 modrm.rm = *codep & 7;
12803 break;
12804
12805 case USE_VEX_LEN_TABLE:
12806 if (!need_vex)
12807 abort ();
12808
12809 switch (vex.length)
12810 {
12811 case 128:
12812 vindex = 0;
12813 break;
12814 case 256:
12815 vindex = 1;
12816 break;
12817 default:
12818 abort ();
12819 break;
12820 }
12821
12822 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12823 break;
12824
12825 case USE_XOP_8F_TABLE:
12826 FETCH_DATA (info, codep + 3);
12827 /* All bits in the REX prefix are ignored. */
12828 rex_ignored = rex;
12829 rex = ~(*codep >> 5) & 0x7;
12830
12831 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12832 switch ((*codep & 0x1f))
12833 {
12834 default:
12835 dp = &bad_opcode;
12836 return dp;
12837 case 0x8:
12838 vex_table_index = XOP_08;
12839 break;
12840 case 0x9:
12841 vex_table_index = XOP_09;
12842 break;
12843 case 0xa:
12844 vex_table_index = XOP_0A;
12845 break;
12846 }
12847 codep++;
12848 vex.w = *codep & 0x80;
12849 if (vex.w && address_mode == mode_64bit)
12850 rex |= REX_W;
12851
12852 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12853 if (address_mode != mode_64bit)
12854 {
12855 /* In 16/32-bit mode REX_B is silently ignored. */
12856 rex &= ~REX_B;
12857 if (vex.register_specifier > 0x7)
12858 {
12859 dp = &bad_opcode;
12860 return dp;
12861 }
12862 }
12863
12864 vex.length = (*codep & 0x4) ? 256 : 128;
12865 switch ((*codep & 0x3))
12866 {
12867 case 0:
12868 vex.prefix = 0;
12869 break;
12870 case 1:
12871 vex.prefix = DATA_PREFIX_OPCODE;
12872 break;
12873 case 2:
12874 vex.prefix = REPE_PREFIX_OPCODE;
12875 break;
12876 case 3:
12877 vex.prefix = REPNE_PREFIX_OPCODE;
12878 break;
12879 }
12880 need_vex = 1;
12881 need_vex_reg = 1;
12882 codep++;
12883 vindex = *codep++;
12884 dp = &xop_table[vex_table_index][vindex];
12885
12886 end_codep = codep;
12887 FETCH_DATA (info, codep + 1);
12888 modrm.mod = (*codep >> 6) & 3;
12889 modrm.reg = (*codep >> 3) & 7;
12890 modrm.rm = *codep & 7;
12891 break;
12892
12893 case USE_VEX_C4_TABLE:
12894 /* VEX prefix. */
12895 FETCH_DATA (info, codep + 3);
12896 /* All bits in the REX prefix are ignored. */
12897 rex_ignored = rex;
12898 rex = ~(*codep >> 5) & 0x7;
12899 switch ((*codep & 0x1f))
12900 {
12901 default:
12902 dp = &bad_opcode;
12903 return dp;
12904 case 0x1:
12905 vex_table_index = VEX_0F;
12906 break;
12907 case 0x2:
12908 vex_table_index = VEX_0F38;
12909 break;
12910 case 0x3:
12911 vex_table_index = VEX_0F3A;
12912 break;
12913 }
12914 codep++;
12915 vex.w = *codep & 0x80;
12916 if (address_mode == mode_64bit)
12917 {
12918 if (vex.w)
12919 rex |= REX_W;
12920 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12921 }
12922 else
12923 {
12924 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12925 is ignored, other REX bits are 0 and the highest bit in
12926 VEX.vvvv is also ignored. */
12927 rex = 0;
12928 vex.register_specifier = (~(*codep >> 3)) & 0x7;
12929 }
12930 vex.length = (*codep & 0x4) ? 256 : 128;
12931 switch ((*codep & 0x3))
12932 {
12933 case 0:
12934 vex.prefix = 0;
12935 break;
12936 case 1:
12937 vex.prefix = DATA_PREFIX_OPCODE;
12938 break;
12939 case 2:
12940 vex.prefix = REPE_PREFIX_OPCODE;
12941 break;
12942 case 3:
12943 vex.prefix = REPNE_PREFIX_OPCODE;
12944 break;
12945 }
12946 need_vex = 1;
12947 need_vex_reg = 1;
12948 codep++;
12949 vindex = *codep++;
12950 dp = &vex_table[vex_table_index][vindex];
12951 end_codep = codep;
12952 /* There is no MODRM byte for VEX0F 77. */
12953 if (vex_table_index != VEX_0F || vindex != 0x77)
12954 {
12955 FETCH_DATA (info, codep + 1);
12956 modrm.mod = (*codep >> 6) & 3;
12957 modrm.reg = (*codep >> 3) & 7;
12958 modrm.rm = *codep & 7;
12959 }
12960 break;
12961
12962 case USE_VEX_C5_TABLE:
12963 /* VEX prefix. */
12964 FETCH_DATA (info, codep + 2);
12965 /* All bits in the REX prefix are ignored. */
12966 rex_ignored = rex;
12967 rex = (*codep & 0x80) ? 0 : REX_R;
12968
12969 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12970 VEX.vvvv is 1. */
12971 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12972 vex.w = 0;
12973 vex.length = (*codep & 0x4) ? 256 : 128;
12974 switch ((*codep & 0x3))
12975 {
12976 case 0:
12977 vex.prefix = 0;
12978 break;
12979 case 1:
12980 vex.prefix = DATA_PREFIX_OPCODE;
12981 break;
12982 case 2:
12983 vex.prefix = REPE_PREFIX_OPCODE;
12984 break;
12985 case 3:
12986 vex.prefix = REPNE_PREFIX_OPCODE;
12987 break;
12988 }
12989 need_vex = 1;
12990 need_vex_reg = 1;
12991 codep++;
12992 vindex = *codep++;
12993 dp = &vex_table[dp->op[1].bytemode][vindex];
12994 end_codep = codep;
12995 /* There is no MODRM byte for VEX 77. */
12996 if (vindex != 0x77)
12997 {
12998 FETCH_DATA (info, codep + 1);
12999 modrm.mod = (*codep >> 6) & 3;
13000 modrm.reg = (*codep >> 3) & 7;
13001 modrm.rm = *codep & 7;
13002 }
13003 break;
13004
13005 case USE_VEX_W_TABLE:
13006 if (!need_vex)
13007 abort ();
13008
13009 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13010 break;
13011
13012 case USE_EVEX_TABLE:
13013 two_source_ops = 0;
13014 /* EVEX prefix. */
13015 vex.evex = 1;
13016 FETCH_DATA (info, codep + 4);
13017 /* All bits in the REX prefix are ignored. */
13018 rex_ignored = rex;
13019 /* The first byte after 0x62. */
13020 rex = ~(*codep >> 5) & 0x7;
13021 vex.r = *codep & 0x10;
13022 switch ((*codep & 0xf))
13023 {
13024 default:
13025 return &bad_opcode;
13026 case 0x1:
13027 vex_table_index = EVEX_0F;
13028 break;
13029 case 0x2:
13030 vex_table_index = EVEX_0F38;
13031 break;
13032 case 0x3:
13033 vex_table_index = EVEX_0F3A;
13034 break;
13035 }
13036
13037 /* The second byte after 0x62. */
13038 codep++;
13039 vex.w = *codep & 0x80;
13040 if (vex.w && address_mode == mode_64bit)
13041 rex |= REX_W;
13042
13043 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13044 if (address_mode != mode_64bit)
13045 {
13046 /* In 16/32-bit mode silently ignore following bits. */
13047 rex &= ~REX_B;
13048 vex.r = 1;
13049 vex.v = 1;
13050 vex.register_specifier &= 0x7;
13051 }
13052
13053 /* The U bit. */
13054 if (!(*codep & 0x4))
13055 return &bad_opcode;
13056
13057 switch ((*codep & 0x3))
13058 {
13059 case 0:
13060 vex.prefix = 0;
13061 break;
13062 case 1:
13063 vex.prefix = DATA_PREFIX_OPCODE;
13064 break;
13065 case 2:
13066 vex.prefix = REPE_PREFIX_OPCODE;
13067 break;
13068 case 3:
13069 vex.prefix = REPNE_PREFIX_OPCODE;
13070 break;
13071 }
13072
13073 /* The third byte after 0x62. */
13074 codep++;
13075
13076 /* Remember the static rounding bits. */
13077 vex.ll = (*codep >> 5) & 3;
13078 vex.b = (*codep & 0x10) != 0;
13079
13080 vex.v = *codep & 0x8;
13081 vex.mask_register_specifier = *codep & 0x7;
13082 vex.zeroing = *codep & 0x80;
13083
13084 need_vex = 1;
13085 need_vex_reg = 1;
13086 codep++;
13087 vindex = *codep++;
13088 dp = &evex_table[vex_table_index][vindex];
13089 end_codep = codep;
13090 FETCH_DATA (info, codep + 1);
13091 modrm.mod = (*codep >> 6) & 3;
13092 modrm.reg = (*codep >> 3) & 7;
13093 modrm.rm = *codep & 7;
13094
13095 /* Set vector length. */
13096 if (modrm.mod == 3 && vex.b)
13097 vex.length = 512;
13098 else
13099 {
13100 switch (vex.ll)
13101 {
13102 case 0x0:
13103 vex.length = 128;
13104 break;
13105 case 0x1:
13106 vex.length = 256;
13107 break;
13108 case 0x2:
13109 vex.length = 512;
13110 break;
13111 default:
13112 return &bad_opcode;
13113 }
13114 }
13115 break;
13116
13117 case 0:
13118 dp = &bad_opcode;
13119 break;
13120
13121 default:
13122 abort ();
13123 }
13124
13125 if (dp->name != NULL)
13126 return dp;
13127 else
13128 return get_valid_dis386 (dp, info);
13129}
13130
13131static void
13132get_sib (disassemble_info *info, int sizeflag)
13133{
13134 /* If modrm.mod == 3, operand must be register. */
13135 if (need_modrm
13136 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13137 && modrm.mod != 3
13138 && modrm.rm == 4)
13139 {
13140 FETCH_DATA (info, codep + 2);
13141 sib.index = (codep [1] >> 3) & 7;
13142 sib.scale = (codep [1] >> 6) & 3;
13143 sib.base = codep [1] & 7;
13144 }
13145}
13146
13147static int
13148print_insn (bfd_vma pc, disassemble_info *info)
13149{
13150 const struct dis386 *dp;
13151 int i;
13152 char *op_txt[MAX_OPERANDS];
13153 int needcomma;
13154 int sizeflag, orig_sizeflag;
13155 const char *p;
13156 struct dis_private priv;
13157 int prefix_length;
13158
13159 priv.orig_sizeflag = AFLAG | DFLAG;
13160 if ((info->mach & bfd_mach_i386_i386) != 0)
13161 address_mode = mode_32bit;
13162 else if (info->mach == bfd_mach_i386_i8086)
13163 {
13164 address_mode = mode_16bit;
13165 priv.orig_sizeflag = 0;
13166 }
13167 else
13168 address_mode = mode_64bit;
13169
13170 if (intel_syntax == (char) -1)
13171 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13172
13173 for (p = info->disassembler_options; p != NULL; )
13174 {
13175 if (CONST_STRNEQ (p, "amd64"))
13176 isa64 = amd64;
13177 else if (CONST_STRNEQ (p, "intel64"))
13178 isa64 = intel64;
13179 else if (CONST_STRNEQ (p, "x86-64"))
13180 {
13181 address_mode = mode_64bit;
13182 priv.orig_sizeflag = AFLAG | DFLAG;
13183 }
13184 else if (CONST_STRNEQ (p, "i386"))
13185 {
13186 address_mode = mode_32bit;
13187 priv.orig_sizeflag = AFLAG | DFLAG;
13188 }
13189 else if (CONST_STRNEQ (p, "i8086"))
13190 {
13191 address_mode = mode_16bit;
13192 priv.orig_sizeflag = 0;
13193 }
13194 else if (CONST_STRNEQ (p, "intel"))
13195 {
13196 intel_syntax = 1;
13197 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13198 intel_mnemonic = 1;
13199 }
13200 else if (CONST_STRNEQ (p, "att"))
13201 {
13202 intel_syntax = 0;
13203 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13204 intel_mnemonic = 0;
13205 }
13206 else if (CONST_STRNEQ (p, "addr"))
13207 {
13208 if (address_mode == mode_64bit)
13209 {
13210 if (p[4] == '3' && p[5] == '2')
13211 priv.orig_sizeflag &= ~AFLAG;
13212 else if (p[4] == '6' && p[5] == '4')
13213 priv.orig_sizeflag |= AFLAG;
13214 }
13215 else
13216 {
13217 if (p[4] == '1' && p[5] == '6')
13218 priv.orig_sizeflag &= ~AFLAG;
13219 else if (p[4] == '3' && p[5] == '2')
13220 priv.orig_sizeflag |= AFLAG;
13221 }
13222 }
13223 else if (CONST_STRNEQ (p, "data"))
13224 {
13225 if (p[4] == '1' && p[5] == '6')
13226 priv.orig_sizeflag &= ~DFLAG;
13227 else if (p[4] == '3' && p[5] == '2')
13228 priv.orig_sizeflag |= DFLAG;
13229 }
13230 else if (CONST_STRNEQ (p, "suffix"))
13231 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13232
13233 p = strchr (p, ',');
13234 if (p != NULL)
13235 p++;
13236 }
13237
13238 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13239 {
13240 (*info->fprintf_func) (info->stream,
13241 _("64-bit address is disabled"));
13242 return -1;
13243 }
13244
13245 if (intel_syntax)
13246 {
13247 names64 = intel_names64;
13248 names32 = intel_names32;
13249 names16 = intel_names16;
13250 names8 = intel_names8;
13251 names8rex = intel_names8rex;
13252 names_seg = intel_names_seg;
13253 names_mm = intel_names_mm;
13254 names_bnd = intel_names_bnd;
13255 names_xmm = intel_names_xmm;
13256 names_ymm = intel_names_ymm;
13257 names_zmm = intel_names_zmm;
13258 index64 = intel_index64;
13259 index32 = intel_index32;
13260 names_mask = intel_names_mask;
13261 index16 = intel_index16;
13262 open_char = '[';
13263 close_char = ']';
13264 separator_char = '+';
13265 scale_char = '*';
13266 }
13267 else
13268 {
13269 names64 = att_names64;
13270 names32 = att_names32;
13271 names16 = att_names16;
13272 names8 = att_names8;
13273 names8rex = att_names8rex;
13274 names_seg = att_names_seg;
13275 names_mm = att_names_mm;
13276 names_bnd = att_names_bnd;
13277 names_xmm = att_names_xmm;
13278 names_ymm = att_names_ymm;
13279 names_zmm = att_names_zmm;
13280 index64 = att_index64;
13281 index32 = att_index32;
13282 names_mask = att_names_mask;
13283 index16 = att_index16;
13284 open_char = '(';
13285 close_char = ')';
13286 separator_char = ',';
13287 scale_char = ',';
13288 }
13289
13290 /* The output looks better if we put 7 bytes on a line, since that
13291 puts most long word instructions on a single line. Use 8 bytes
13292 for Intel L1OM. */
13293 if ((info->mach & bfd_mach_l1om) != 0)
13294 info->bytes_per_line = 8;
13295 else
13296 info->bytes_per_line = 7;
13297
13298 info->private_data = &priv;
13299 priv.max_fetched = priv.the_buffer;
13300 priv.insn_start = pc;
13301
13302 obuf[0] = 0;
13303 for (i = 0; i < MAX_OPERANDS; ++i)
13304 {
13305 op_out[i][0] = 0;
13306 op_index[i] = -1;
13307 }
13308
13309 the_info = info;
13310 start_pc = pc;
13311 start_codep = priv.the_buffer;
13312 codep = priv.the_buffer;
13313
13314 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13315 {
13316 const char *name;
13317
13318 /* Getting here means we tried for data but didn't get it. That
13319 means we have an incomplete instruction of some sort. Just
13320 print the first byte as a prefix or a .byte pseudo-op. */
13321 if (codep > priv.the_buffer)
13322 {
13323 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13324 if (name != NULL)
13325 (*info->fprintf_func) (info->stream, "%s", name);
13326 else
13327 {
13328 /* Just print the first byte as a .byte instruction. */
13329 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13330 (unsigned int) priv.the_buffer[0]);
13331 }
13332
13333 return 1;
13334 }
13335
13336 return -1;
13337 }
13338
13339 obufp = obuf;
13340 sizeflag = priv.orig_sizeflag;
13341
13342 if (!ckprefix () || rex_used)
13343 {
13344 /* Too many prefixes or unused REX prefixes. */
13345 for (i = 0;
13346 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13347 i++)
13348 (*info->fprintf_func) (info->stream, "%s%s",
13349 i == 0 ? "" : " ",
13350 prefix_name (all_prefixes[i], sizeflag));
13351 return i;
13352 }
13353
13354 insn_codep = codep;
13355
13356 FETCH_DATA (info, codep + 1);
13357 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13358
13359 if (((prefixes & PREFIX_FWAIT)
13360 && ((*codep < 0xd8) || (*codep > 0xdf))))
13361 {
13362 /* Handle prefixes before fwait. */
13363 for (i = 0; i < fwait_prefix && all_prefixes[i];
13364 i++)
13365 (*info->fprintf_func) (info->stream, "%s ",
13366 prefix_name (all_prefixes[i], sizeflag));
13367 (*info->fprintf_func) (info->stream, "fwait");
13368 return i + 1;
13369 }
13370
13371 if (*codep == 0x0f)
13372 {
13373 unsigned char threebyte;
13374
13375 codep++;
13376 FETCH_DATA (info, codep + 1);
13377 threebyte = *codep;
13378 dp = &dis386_twobyte[threebyte];
13379 need_modrm = twobyte_has_modrm[*codep];
13380 codep++;
13381 }
13382 else
13383 {
13384 dp = &dis386[*codep];
13385 need_modrm = onebyte_has_modrm[*codep];
13386 codep++;
13387 }
13388
13389 /* Save sizeflag for printing the extra prefixes later before updating
13390 it for mnemonic and operand processing. The prefix names depend
13391 only on the address mode. */
13392 orig_sizeflag = sizeflag;
13393 if (prefixes & PREFIX_ADDR)
13394 sizeflag ^= AFLAG;
13395 if ((prefixes & PREFIX_DATA))
13396 sizeflag ^= DFLAG;
13397
13398 end_codep = codep;
13399 if (need_modrm)
13400 {
13401 FETCH_DATA (info, codep + 1);
13402 modrm.mod = (*codep >> 6) & 3;
13403 modrm.reg = (*codep >> 3) & 7;
13404 modrm.rm = *codep & 7;
13405 }
13406
13407 need_vex = 0;
13408 need_vex_reg = 0;
13409 vex_w_done = 0;
13410 vex.evex = 0;
13411
13412 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13413 {
13414 get_sib (info, sizeflag);
13415 dofloat (sizeflag);
13416 }
13417 else
13418 {
13419 dp = get_valid_dis386 (dp, info);
13420 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13421 {
13422 get_sib (info, sizeflag);
13423 for (i = 0; i < MAX_OPERANDS; ++i)
13424 {
13425 obufp = op_out[i];
13426 op_ad = MAX_OPERANDS - 1 - i;
13427 if (dp->op[i].rtn)
13428 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13429 /* For EVEX instruction after the last operand masking
13430 should be printed. */
13431 if (i == 0 && vex.evex)
13432 {
13433 /* Don't print {%k0}. */
13434 if (vex.mask_register_specifier)
13435 {
13436 oappend ("{");
13437 oappend (names_mask[vex.mask_register_specifier]);
13438 oappend ("}");
13439 }
13440 if (vex.zeroing)
13441 oappend ("{z}");
13442 }
13443 }
13444 }
13445 }
13446
13447 /* Check if the REX prefix is used. */
13448 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13449 all_prefixes[last_rex_prefix] = 0;
13450
13451 /* Check if the SEG prefix is used. */
13452 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13453 | PREFIX_FS | PREFIX_GS)) != 0
13454 && (used_prefixes & active_seg_prefix) != 0)
13455 all_prefixes[last_seg_prefix] = 0;
13456
13457 /* Check if the ADDR prefix is used. */
13458 if ((prefixes & PREFIX_ADDR) != 0
13459 && (used_prefixes & PREFIX_ADDR) != 0)
13460 all_prefixes[last_addr_prefix] = 0;
13461
13462 /* Check if the DATA prefix is used. */
13463 if ((prefixes & PREFIX_DATA) != 0
13464 && (used_prefixes & PREFIX_DATA) != 0)
13465 all_prefixes[last_data_prefix] = 0;
13466
13467 /* Print the extra prefixes. */
13468 prefix_length = 0;
13469 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13470 if (all_prefixes[i])
13471 {
13472 const char *name;
13473 name = prefix_name (all_prefixes[i], orig_sizeflag);
13474 if (name == NULL)
13475 abort ();
13476 prefix_length += strlen (name) + 1;
13477 (*info->fprintf_func) (info->stream, "%s ", name);
13478 }
13479
13480 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13481 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13482 used by putop and MMX/SSE operand and may be overriden by the
13483 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13484 separately. */
13485 if (dp->prefix_requirement == PREFIX_OPCODE
13486 && dp != &bad_opcode
13487 && (((prefixes
13488 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13489 && (used_prefixes
13490 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13491 || ((((prefixes
13492 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13493 == PREFIX_DATA)
13494 && (used_prefixes & PREFIX_DATA) == 0))))
13495 {
13496 (*info->fprintf_func) (info->stream, "(bad)");
13497 return end_codep - priv.the_buffer;
13498 }
13499
13500 /* Check maximum code length. */
13501 if ((codep - start_codep) > MAX_CODE_LENGTH)
13502 {
13503 (*info->fprintf_func) (info->stream, "(bad)");
13504 return MAX_CODE_LENGTH;
13505 }
13506
13507 obufp = mnemonicendp;
13508 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13509 oappend (" ");
13510 oappend (" ");
13511 (*info->fprintf_func) (info->stream, "%s", obuf);
13512
13513 /* The enter and bound instructions are printed with operands in the same
13514 order as the intel book; everything else is printed in reverse order. */
13515 if (intel_syntax || two_source_ops)
13516 {
13517 bfd_vma riprel;
13518
13519 for (i = 0; i < MAX_OPERANDS; ++i)
13520 op_txt[i] = op_out[i];
13521
13522 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13523 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13524 {
13525 op_txt[2] = op_out[3];
13526 op_txt[3] = op_out[2];
13527 }
13528
13529 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13530 {
13531 op_ad = op_index[i];
13532 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13533 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13534 riprel = op_riprel[i];
13535 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13536 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13537 }
13538 }
13539 else
13540 {
13541 for (i = 0; i < MAX_OPERANDS; ++i)
13542 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13543 }
13544
13545 needcomma = 0;
13546 for (i = 0; i < MAX_OPERANDS; ++i)
13547 if (*op_txt[i])
13548 {
13549 if (needcomma)
13550 (*info->fprintf_func) (info->stream, ",");
13551 if (op_index[i] != -1 && !op_riprel[i])
13552 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13553 else
13554 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13555 needcomma = 1;
13556 }
13557
13558 for (i = 0; i < MAX_OPERANDS; i++)
13559 if (op_index[i] != -1 && op_riprel[i])
13560 {
13561 (*info->fprintf_func) (info->stream, " # ");
13562 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13563 + op_address[op_index[i]]), info);
13564 break;
13565 }
13566 return codep - priv.the_buffer;
13567}
13568
13569static const char *float_mem[] = {
13570 /* d8 */
13571 "fadd{s|}",
13572 "fmul{s|}",
13573 "fcom{s|}",
13574 "fcomp{s|}",
13575 "fsub{s|}",
13576 "fsubr{s|}",
13577 "fdiv{s|}",
13578 "fdivr{s|}",
13579 /* d9 */
13580 "fld{s|}",
13581 "(bad)",
13582 "fst{s|}",
13583 "fstp{s|}",
13584 "fldenvIC",
13585 "fldcw",
13586 "fNstenvIC",
13587 "fNstcw",
13588 /* da */
13589 "fiadd{l|}",
13590 "fimul{l|}",
13591 "ficom{l|}",
13592 "ficomp{l|}",
13593 "fisub{l|}",
13594 "fisubr{l|}",
13595 "fidiv{l|}",
13596 "fidivr{l|}",
13597 /* db */
13598 "fild{l|}",
13599 "fisttp{l|}",
13600 "fist{l|}",
13601 "fistp{l|}",
13602 "(bad)",
13603 "fld{t||t|}",
13604 "(bad)",
13605 "fstp{t||t|}",
13606 /* dc */
13607 "fadd{l|}",
13608 "fmul{l|}",
13609 "fcom{l|}",
13610 "fcomp{l|}",
13611 "fsub{l|}",
13612 "fsubr{l|}",
13613 "fdiv{l|}",
13614 "fdivr{l|}",
13615 /* dd */
13616 "fld{l|}",
13617 "fisttp{ll|}",
13618 "fst{l||}",
13619 "fstp{l|}",
13620 "frstorIC",
13621 "(bad)",
13622 "fNsaveIC",
13623 "fNstsw",
13624 /* de */
13625 "fiadd",
13626 "fimul",
13627 "ficom",
13628 "ficomp",
13629 "fisub",
13630 "fisubr",
13631 "fidiv",
13632 "fidivr",
13633 /* df */
13634 "fild",
13635 "fisttp",
13636 "fist",
13637 "fistp",
13638 "fbld",
13639 "fild{ll|}",
13640 "fbstp",
13641 "fistp{ll|}",
13642};
13643
13644static const unsigned char float_mem_mode[] = {
13645 /* d8 */
13646 d_mode,
13647 d_mode,
13648 d_mode,
13649 d_mode,
13650 d_mode,
13651 d_mode,
13652 d_mode,
13653 d_mode,
13654 /* d9 */
13655 d_mode,
13656 0,
13657 d_mode,
13658 d_mode,
13659 0,
13660 w_mode,
13661 0,
13662 w_mode,
13663 /* da */
13664 d_mode,
13665 d_mode,
13666 d_mode,
13667 d_mode,
13668 d_mode,
13669 d_mode,
13670 d_mode,
13671 d_mode,
13672 /* db */
13673 d_mode,
13674 d_mode,
13675 d_mode,
13676 d_mode,
13677 0,
13678 t_mode,
13679 0,
13680 t_mode,
13681 /* dc */
13682 q_mode,
13683 q_mode,
13684 q_mode,
13685 q_mode,
13686 q_mode,
13687 q_mode,
13688 q_mode,
13689 q_mode,
13690 /* dd */
13691 q_mode,
13692 q_mode,
13693 q_mode,
13694 q_mode,
13695 0,
13696 0,
13697 0,
13698 w_mode,
13699 /* de */
13700 w_mode,
13701 w_mode,
13702 w_mode,
13703 w_mode,
13704 w_mode,
13705 w_mode,
13706 w_mode,
13707 w_mode,
13708 /* df */
13709 w_mode,
13710 w_mode,
13711 w_mode,
13712 w_mode,
13713 t_mode,
13714 q_mode,
13715 t_mode,
13716 q_mode
13717};
13718
13719#define ST { OP_ST, 0 }
13720#define STi { OP_STi, 0 }
13721
13722#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13723#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13724#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13725#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13726#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13727#define FGRPda_5 NULL, { { NULL, 6 } }, 0
13728#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13729#define FGRPde_3 NULL, { { NULL, 8 } }, 0
13730#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13731
13732static const struct dis386 float_reg[][8] = {
13733 /* d8 */
13734 {
13735 { "fadd", { ST, STi }, 0 },
13736 { "fmul", { ST, STi }, 0 },
13737 { "fcom", { STi }, 0 },
13738 { "fcomp", { STi }, 0 },
13739 { "fsub", { ST, STi }, 0 },
13740 { "fsubr", { ST, STi }, 0 },
13741 { "fdiv", { ST, STi }, 0 },
13742 { "fdivr", { ST, STi }, 0 },
13743 },
13744 /* d9 */
13745 {
13746 { "fld", { STi }, 0 },
13747 { "fxch", { STi }, 0 },
13748 { FGRPd9_2 },
13749 { Bad_Opcode },
13750 { FGRPd9_4 },
13751 { FGRPd9_5 },
13752 { FGRPd9_6 },
13753 { FGRPd9_7 },
13754 },
13755 /* da */
13756 {
13757 { "fcmovb", { ST, STi }, 0 },
13758 { "fcmove", { ST, STi }, 0 },
13759 { "fcmovbe",{ ST, STi }, 0 },
13760 { "fcmovu", { ST, STi }, 0 },
13761 { Bad_Opcode },
13762 { FGRPda_5 },
13763 { Bad_Opcode },
13764 { Bad_Opcode },
13765 },
13766 /* db */
13767 {
13768 { "fcmovnb",{ ST, STi }, 0 },
13769 { "fcmovne",{ ST, STi }, 0 },
13770 { "fcmovnbe",{ ST, STi }, 0 },
13771 { "fcmovnu",{ ST, STi }, 0 },
13772 { FGRPdb_4 },
13773 { "fucomi", { ST, STi }, 0 },
13774 { "fcomi", { ST, STi }, 0 },
13775 { Bad_Opcode },
13776 },
13777 /* dc */
13778 {
13779 { "fadd", { STi, ST }, 0 },
13780 { "fmul", { STi, ST }, 0 },
13781 { Bad_Opcode },
13782 { Bad_Opcode },
13783 { "fsub!M", { STi, ST }, 0 },
13784 { "fsubM", { STi, ST }, 0 },
13785 { "fdiv!M", { STi, ST }, 0 },
13786 { "fdivM", { STi, ST }, 0 },
13787 },
13788 /* dd */
13789 {
13790 { "ffree", { STi }, 0 },
13791 { Bad_Opcode },
13792 { "fst", { STi }, 0 },
13793 { "fstp", { STi }, 0 },
13794 { "fucom", { STi }, 0 },
13795 { "fucomp", { STi }, 0 },
13796 { Bad_Opcode },
13797 { Bad_Opcode },
13798 },
13799 /* de */
13800 {
13801 { "faddp", { STi, ST }, 0 },
13802 { "fmulp", { STi, ST }, 0 },
13803 { Bad_Opcode },
13804 { FGRPde_3 },
13805 { "fsub!Mp", { STi, ST }, 0 },
13806 { "fsubMp", { STi, ST }, 0 },
13807 { "fdiv!Mp", { STi, ST }, 0 },
13808 { "fdivMp", { STi, ST }, 0 },
13809 },
13810 /* df */
13811 {
13812 { "ffreep", { STi }, 0 },
13813 { Bad_Opcode },
13814 { Bad_Opcode },
13815 { Bad_Opcode },
13816 { FGRPdf_4 },
13817 { "fucomip", { ST, STi }, 0 },
13818 { "fcomip", { ST, STi }, 0 },
13819 { Bad_Opcode },
13820 },
13821};
13822
13823static char *fgrps[][8] = {
13824 /* Bad opcode 0 */
13825 {
13826 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13827 },
13828
13829 /* d9_2 1 */
13830 {
13831 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13832 },
13833
13834 /* d9_4 2 */
13835 {
13836 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13837 },
13838
13839 /* d9_5 3 */
13840 {
13841 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13842 },
13843
13844 /* d9_6 4 */
13845 {
13846 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13847 },
13848
13849 /* d9_7 5 */
13850 {
13851 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13852 },
13853
13854 /* da_5 6 */
13855 {
13856 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13857 },
13858
13859 /* db_4 7 */
13860 {
13861 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13862 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13863 },
13864
13865 /* de_3 8 */
13866 {
13867 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13868 },
13869
13870 /* df_4 9 */
13871 {
13872 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13873 },
13874};
13875
13876static void
13877swap_operand (void)
13878{
13879 mnemonicendp[0] = '.';
13880 mnemonicendp[1] = 's';
13881 mnemonicendp += 2;
13882}
13883
13884static void
13885OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13886 int sizeflag ATTRIBUTE_UNUSED)
13887{
13888 /* Skip mod/rm byte. */
13889 MODRM_CHECK;
13890 codep++;
13891}
13892
13893static void
13894dofloat (int sizeflag)
13895{
13896 const struct dis386 *dp;
13897 unsigned char floatop;
13898
13899 floatop = codep[-1];
13900
13901 if (modrm.mod != 3)
13902 {
13903 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13904
13905 putop (float_mem[fp_indx], sizeflag);
13906 obufp = op_out[0];
13907 op_ad = 2;
13908 OP_E (float_mem_mode[fp_indx], sizeflag);
13909 return;
13910 }
13911 /* Skip mod/rm byte. */
13912 MODRM_CHECK;
13913 codep++;
13914
13915 dp = &float_reg[floatop - 0xd8][modrm.reg];
13916 if (dp->name == NULL)
13917 {
13918 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13919
13920 /* Instruction fnstsw is only one with strange arg. */
13921 if (floatop == 0xdf && codep[-1] == 0xe0)
13922 strcpy (op_out[0], names16[0]);
13923 }
13924 else
13925 {
13926 putop (dp->name, sizeflag);
13927
13928 obufp = op_out[0];
13929 op_ad = 2;
13930 if (dp->op[0].rtn)
13931 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13932
13933 obufp = op_out[1];
13934 op_ad = 1;
13935 if (dp->op[1].rtn)
13936 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13937 }
13938}
13939
13940/* Like oappend (below), but S is a string starting with '%'.
13941 In Intel syntax, the '%' is elided. */
13942static void
13943oappend_maybe_intel (const char *s)
13944{
13945 oappend (s + intel_syntax);
13946}
13947
13948static void
13949OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13950{
13951 oappend_maybe_intel ("%st");
13952}
13953
13954static void
13955OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13956{
13957 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13958 oappend_maybe_intel (scratchbuf);
13959}
13960
13961/* Capital letters in template are macros. */
13962static int
13963putop (const char *in_template, int sizeflag)
13964{
13965 const char *p;
13966 int alt = 0;
13967 int cond = 1;
13968 unsigned int l = 0, len = 1;
13969 char last[4];
13970
13971#define SAVE_LAST(c) \
13972 if (l < len && l < sizeof (last)) \
13973 last[l++] = c; \
13974 else \
13975 abort ();
13976
13977 for (p = in_template; *p; p++)
13978 {
13979 switch (*p)
13980 {
13981 default:
13982 *obufp++ = *p;
13983 break;
13984 case '%':
13985 len++;
13986 break;
13987 case '!':
13988 cond = 0;
13989 break;
13990 case '{':
13991 if (intel_syntax)
13992 {
13993 while (*++p != '|')
13994 if (*p == '}' || *p == '\0')
13995 abort ();
13996 }
13997 /* Fall through. */
13998 case 'I':
13999 alt = 1;
14000 continue;
14001 case '|':
14002 while (*++p != '}')
14003 {
14004 if (*p == '\0')
14005 abort ();
14006 }
14007 break;
14008 case '}':
14009 break;
14010 case 'A':
14011 if (intel_syntax)
14012 break;
14013 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14014 *obufp++ = 'b';
14015 break;
14016 case 'B':
14017 if (l == 0 && len == 1)
14018 {
14019case_B:
14020 if (intel_syntax)
14021 break;
14022 if (sizeflag & SUFFIX_ALWAYS)
14023 *obufp++ = 'b';
14024 }
14025 else
14026 {
14027 if (l != 1
14028 || len != 2
14029 || last[0] != 'L')
14030 {
14031 SAVE_LAST (*p);
14032 break;
14033 }
14034
14035 if (address_mode == mode_64bit
14036 && !(prefixes & PREFIX_ADDR))
14037 {
14038 *obufp++ = 'a';
14039 *obufp++ = 'b';
14040 *obufp++ = 's';
14041 }
14042
14043 goto case_B;
14044 }
14045 break;
14046 case 'C':
14047 if (intel_syntax && !alt)
14048 break;
14049 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14050 {
14051 if (sizeflag & DFLAG)
14052 *obufp++ = intel_syntax ? 'd' : 'l';
14053 else
14054 *obufp++ = intel_syntax ? 'w' : 's';
14055 used_prefixes |= (prefixes & PREFIX_DATA);
14056 }
14057 break;
14058 case 'D':
14059 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14060 break;
14061 USED_REX (REX_W);
14062 if (modrm.mod == 3)
14063 {
14064 if (rex & REX_W)
14065 *obufp++ = 'q';
14066 else
14067 {
14068 if (sizeflag & DFLAG)
14069 *obufp++ = intel_syntax ? 'd' : 'l';
14070 else
14071 *obufp++ = 'w';
14072 used_prefixes |= (prefixes & PREFIX_DATA);
14073 }
14074 }
14075 else
14076 *obufp++ = 'w';
14077 break;
14078 case 'E': /* For jcxz/jecxz */
14079 if (address_mode == mode_64bit)
14080 {
14081 if (sizeflag & AFLAG)
14082 *obufp++ = 'r';
14083 else
14084 *obufp++ = 'e';
14085 }
14086 else
14087 if (sizeflag & AFLAG)
14088 *obufp++ = 'e';
14089 used_prefixes |= (prefixes & PREFIX_ADDR);
14090 break;
14091 case 'F':
14092 if (intel_syntax)
14093 break;
14094 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14095 {
14096 if (sizeflag & AFLAG)
14097 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14098 else
14099 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14100 used_prefixes |= (prefixes & PREFIX_ADDR);
14101 }
14102 break;
14103 case 'G':
14104 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14105 break;
14106 if ((rex & REX_W) || (sizeflag & DFLAG))
14107 *obufp++ = 'l';
14108 else
14109 *obufp++ = 'w';
14110 if (!(rex & REX_W))
14111 used_prefixes |= (prefixes & PREFIX_DATA);
14112 break;
14113 case 'H':
14114 if (intel_syntax)
14115 break;
14116 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14117 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14118 {
14119 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14120 *obufp++ = ',';
14121 *obufp++ = 'p';
14122 if (prefixes & PREFIX_DS)
14123 *obufp++ = 't';
14124 else
14125 *obufp++ = 'n';
14126 }
14127 break;
14128 case 'J':
14129 if (intel_syntax)
14130 break;
14131 *obufp++ = 'l';
14132 break;
14133 case 'K':
14134 USED_REX (REX_W);
14135 if (rex & REX_W)
14136 *obufp++ = 'q';
14137 else
14138 *obufp++ = 'd';
14139 break;
14140 case 'Z':
14141 if (l != 0 || len != 1)
14142 {
14143 if (l != 1 || len != 2 || last[0] != 'X')
14144 {
14145 SAVE_LAST (*p);
14146 break;
14147 }
14148 if (!need_vex || !vex.evex)
14149 abort ();
14150 if (intel_syntax
14151 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14152 break;
14153 switch (vex.length)
14154 {
14155 case 128:
14156 *obufp++ = 'x';
14157 break;
14158 case 256:
14159 *obufp++ = 'y';
14160 break;
14161 case 512:
14162 *obufp++ = 'z';
14163 break;
14164 default:
14165 abort ();
14166 }
14167 break;
14168 }
14169 if (intel_syntax)
14170 break;
14171 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14172 {
14173 *obufp++ = 'q';
14174 break;
14175 }
14176 /* Fall through. */
14177 goto case_L;
14178 case 'L':
14179 if (l != 0 || len != 1)
14180 {
14181 SAVE_LAST (*p);
14182 break;
14183 }
14184case_L:
14185 if (intel_syntax)
14186 break;
14187 if (sizeflag & SUFFIX_ALWAYS)
14188 *obufp++ = 'l';
14189 break;
14190 case 'M':
14191 if (intel_mnemonic != cond)
14192 *obufp++ = 'r';
14193 break;
14194 case 'N':
14195 if ((prefixes & PREFIX_FWAIT) == 0)
14196 *obufp++ = 'n';
14197 else
14198 used_prefixes |= PREFIX_FWAIT;
14199 break;
14200 case 'O':
14201 USED_REX (REX_W);
14202 if (rex & REX_W)
14203 *obufp++ = 'o';
14204 else if (intel_syntax && (sizeflag & DFLAG))
14205 *obufp++ = 'q';
14206 else
14207 *obufp++ = 'd';
14208 if (!(rex & REX_W))
14209 used_prefixes |= (prefixes & PREFIX_DATA);
14210 break;
14211 case '&':
14212 if (!intel_syntax
14213 && address_mode == mode_64bit
14214 && isa64 == intel64)
14215 {
14216 *obufp++ = 'q';
14217 break;
14218 }
14219 /* Fall through. */
14220 case 'T':
14221 if (!intel_syntax
14222 && address_mode == mode_64bit
14223 && ((sizeflag & DFLAG) || (rex & REX_W)))
14224 {
14225 *obufp++ = 'q';
14226 break;
14227 }
14228 /* Fall through. */
14229 goto case_P;
14230 case 'P':
14231 if (l == 0 && len == 1)
14232 {
14233case_P:
14234 if (intel_syntax)
14235 {
14236 if ((rex & REX_W) == 0
14237 && (prefixes & PREFIX_DATA))
14238 {
14239 if ((sizeflag & DFLAG) == 0)
14240 *obufp++ = 'w';
14241 used_prefixes |= (prefixes & PREFIX_DATA);
14242 }
14243 break;
14244 }
14245 if ((prefixes & PREFIX_DATA)
14246 || (rex & REX_W)
14247 || (sizeflag & SUFFIX_ALWAYS))
14248 {
14249 USED_REX (REX_W);
14250 if (rex & REX_W)
14251 *obufp++ = 'q';
14252 else
14253 {
14254 if (sizeflag & DFLAG)
14255 *obufp++ = 'l';
14256 else
14257 *obufp++ = 'w';
14258 used_prefixes |= (prefixes & PREFIX_DATA);
14259 }
14260 }
14261 }
14262 else
14263 {
14264 if (l != 1 || len != 2 || last[0] != 'L')
14265 {
14266 SAVE_LAST (*p);
14267 break;
14268 }
14269
14270 if ((prefixes & PREFIX_DATA)
14271 || (rex & REX_W)
14272 || (sizeflag & SUFFIX_ALWAYS))
14273 {
14274 USED_REX (REX_W);
14275 if (rex & REX_W)
14276 *obufp++ = 'q';
14277 else
14278 {
14279 if (sizeflag & DFLAG)
14280 *obufp++ = intel_syntax ? 'd' : 'l';
14281 else
14282 *obufp++ = 'w';
14283 used_prefixes |= (prefixes & PREFIX_DATA);
14284 }
14285 }
14286 }
14287 break;
14288 case 'U':
14289 if (intel_syntax)
14290 break;
14291 if (address_mode == mode_64bit
14292 && ((sizeflag & DFLAG) || (rex & REX_W)))
14293 {
14294 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14295 *obufp++ = 'q';
14296 break;
14297 }
14298 /* Fall through. */
14299 goto case_Q;
14300 case 'Q':
14301 if (l == 0 && len == 1)
14302 {
14303case_Q:
14304 if (intel_syntax && !alt)
14305 break;
14306 USED_REX (REX_W);
14307 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14308 {
14309 if (rex & REX_W)
14310 *obufp++ = 'q';
14311 else
14312 {
14313 if (sizeflag & DFLAG)
14314 *obufp++ = intel_syntax ? 'd' : 'l';
14315 else
14316 *obufp++ = 'w';
14317 used_prefixes |= (prefixes & PREFIX_DATA);
14318 }
14319 }
14320 }
14321 else
14322 {
14323 if (l != 1 || len != 2 || last[0] != 'L')
14324 {
14325 SAVE_LAST (*p);
14326 break;
14327 }
14328 if (intel_syntax
14329 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14330 break;
14331 if ((rex & REX_W))
14332 {
14333 USED_REX (REX_W);
14334 *obufp++ = 'q';
14335 }
14336 else
14337 *obufp++ = 'l';
14338 }
14339 break;
14340 case 'R':
14341 USED_REX (REX_W);
14342 if (rex & REX_W)
14343 *obufp++ = 'q';
14344 else if (sizeflag & DFLAG)
14345 {
14346 if (intel_syntax)
14347 *obufp++ = 'd';
14348 else
14349 *obufp++ = 'l';
14350 }
14351 else
14352 *obufp++ = 'w';
14353 if (intel_syntax && !p[1]
14354 && ((rex & REX_W) || (sizeflag & DFLAG)))
14355 *obufp++ = 'e';
14356 if (!(rex & REX_W))
14357 used_prefixes |= (prefixes & PREFIX_DATA);
14358 break;
14359 case 'V':
14360 if (l == 0 && len == 1)
14361 {
14362 if (intel_syntax)
14363 break;
14364 if (address_mode == mode_64bit
14365 && ((sizeflag & DFLAG) || (rex & REX_W)))
14366 {
14367 if (sizeflag & SUFFIX_ALWAYS)
14368 *obufp++ = 'q';
14369 break;
14370 }
14371 }
14372 else
14373 {
14374 if (l != 1
14375 || len != 2
14376 || last[0] != 'L')
14377 {
14378 SAVE_LAST (*p);
14379 break;
14380 }
14381
14382 if (rex & REX_W)
14383 {
14384 *obufp++ = 'a';
14385 *obufp++ = 'b';
14386 *obufp++ = 's';
14387 }
14388 }
14389 /* Fall through. */
14390 goto case_S;
14391 case 'S':
14392 if (l == 0 && len == 1)
14393 {
14394case_S:
14395 if (intel_syntax)
14396 break;
14397 if (sizeflag & SUFFIX_ALWAYS)
14398 {
14399 if (rex & REX_W)
14400 *obufp++ = 'q';
14401 else
14402 {
14403 if (sizeflag & DFLAG)
14404 *obufp++ = 'l';
14405 else
14406 *obufp++ = 'w';
14407 used_prefixes |= (prefixes & PREFIX_DATA);
14408 }
14409 }
14410 }
14411 else
14412 {
14413 if (l != 1
14414 || len != 2
14415 || last[0] != 'L')
14416 {
14417 SAVE_LAST (*p);
14418 break;
14419 }
14420
14421 if (address_mode == mode_64bit
14422 && !(prefixes & PREFIX_ADDR))
14423 {
14424 *obufp++ = 'a';
14425 *obufp++ = 'b';
14426 *obufp++ = 's';
14427 }
14428
14429 goto case_S;
14430 }
14431 break;
14432 case 'X':
14433 if (l != 0 || len != 1)
14434 {
14435 SAVE_LAST (*p);
14436 break;
14437 }
14438 if (need_vex && vex.prefix)
14439 {
14440 if (vex.prefix == DATA_PREFIX_OPCODE)
14441 *obufp++ = 'd';
14442 else
14443 *obufp++ = 's';
14444 }
14445 else
14446 {
14447 if (prefixes & PREFIX_DATA)
14448 *obufp++ = 'd';
14449 else
14450 *obufp++ = 's';
14451 used_prefixes |= (prefixes & PREFIX_DATA);
14452 }
14453 break;
14454 case 'Y':
14455 if (l == 0 && len == 1)
14456 {
14457 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14458 break;
14459 if (rex & REX_W)
14460 {
14461 USED_REX (REX_W);
14462 *obufp++ = 'q';
14463 }
14464 break;
14465 }
14466 else
14467 {
14468 if (l != 1 || len != 2 || last[0] != 'X')
14469 {
14470 SAVE_LAST (*p);
14471 break;
14472 }
14473 if (!need_vex)
14474 abort ();
14475 if (intel_syntax
14476 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14477 break;
14478 switch (vex.length)
14479 {
14480 case 128:
14481 *obufp++ = 'x';
14482 break;
14483 case 256:
14484 *obufp++ = 'y';
14485 break;
14486 case 512:
14487 if (!vex.evex)
14488 default:
14489 abort ();
14490 }
14491 }
14492 break;
14493 case 'W':
14494 if (l == 0 && len == 1)
14495 {
14496 /* operand size flag for cwtl, cbtw */
14497 USED_REX (REX_W);
14498 if (rex & REX_W)
14499 {
14500 if (intel_syntax)
14501 *obufp++ = 'd';
14502 else
14503 *obufp++ = 'l';
14504 }
14505 else if (sizeflag & DFLAG)
14506 *obufp++ = 'w';
14507 else
14508 *obufp++ = 'b';
14509 if (!(rex & REX_W))
14510 used_prefixes |= (prefixes & PREFIX_DATA);
14511 }
14512 else
14513 {
14514 if (l != 1
14515 || len != 2
14516 || (last[0] != 'X'
14517 && last[0] != 'L'))
14518 {
14519 SAVE_LAST (*p);
14520 break;
14521 }
14522 if (!need_vex)
14523 abort ();
14524 if (last[0] == 'X')
14525 *obufp++ = vex.w ? 'd': 's';
14526 else
14527 *obufp++ = vex.w ? 'q': 'd';
14528 }
14529 break;
14530 case '^':
14531 if (intel_syntax)
14532 break;
14533 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14534 {
14535 if (sizeflag & DFLAG)
14536 *obufp++ = 'l';
14537 else
14538 *obufp++ = 'w';
14539 used_prefixes |= (prefixes & PREFIX_DATA);
14540 }
14541 break;
14542 case '@':
14543 if (intel_syntax)
14544 break;
14545 if (address_mode == mode_64bit
14546 && (isa64 == intel64
14547 || ((sizeflag & DFLAG) || (rex & REX_W))))
14548 *obufp++ = 'q';
14549 else if ((prefixes & PREFIX_DATA))
14550 {
14551 if (!(sizeflag & DFLAG))
14552 *obufp++ = 'w';
14553 used_prefixes |= (prefixes & PREFIX_DATA);
14554 }
14555 break;
14556 }
14557 alt = 0;
14558 }
14559 *obufp = 0;
14560 mnemonicendp = obufp;
14561 return 0;
14562}
14563
14564static void
14565oappend (const char *s)
14566{
14567 obufp = stpcpy (obufp, s);
14568}
14569
14570static void
14571append_seg (void)
14572{
14573 /* Only print the active segment register. */
14574 if (!active_seg_prefix)
14575 return;
14576
14577 used_prefixes |= active_seg_prefix;
14578 switch (active_seg_prefix)
14579 {
14580 case PREFIX_CS:
14581 oappend_maybe_intel ("%cs:");
14582 break;
14583 case PREFIX_DS:
14584 oappend_maybe_intel ("%ds:");
14585 break;
14586 case PREFIX_SS:
14587 oappend_maybe_intel ("%ss:");
14588 break;
14589 case PREFIX_ES:
14590 oappend_maybe_intel ("%es:");
14591 break;
14592 case PREFIX_FS:
14593 oappend_maybe_intel ("%fs:");
14594 break;
14595 case PREFIX_GS:
14596 oappend_maybe_intel ("%gs:");
14597 break;
14598 default:
14599 break;
14600 }
14601}
14602
14603static void
14604OP_indirE (int bytemode, int sizeflag)
14605{
14606 if (!intel_syntax)
14607 oappend ("*");
14608 OP_E (bytemode, sizeflag);
14609}
14610
14611static void
14612print_operand_value (char *buf, int hex, bfd_vma disp)
14613{
14614 if (address_mode == mode_64bit)
14615 {
14616 if (hex)
14617 {
14618 char tmp[30];
14619 int i;
14620 buf[0] = '0';
14621 buf[1] = 'x';
14622 sprintf_vma (tmp, disp);
14623 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14624 strcpy (buf + 2, tmp + i);
14625 }
14626 else
14627 {
14628 bfd_signed_vma v = disp;
14629 char tmp[30];
14630 int i;
14631 if (v < 0)
14632 {
14633 *(buf++) = '-';
14634 v = -disp;
14635 /* Check for possible overflow on 0x8000000000000000. */
14636 if (v < 0)
14637 {
14638 strcpy (buf, "9223372036854775808");
14639 return;
14640 }
14641 }
14642 if (!v)
14643 {
14644 strcpy (buf, "0");
14645 return;
14646 }
14647
14648 i = 0;
14649 tmp[29] = 0;
14650 while (v)
14651 {
14652 tmp[28 - i] = (v % 10) + '0';
14653 v /= 10;
14654 i++;
14655 }
14656 strcpy (buf, tmp + 29 - i);
14657 }
14658 }
14659 else
14660 {
14661 if (hex)
14662 sprintf (buf, "0x%x", (unsigned int) disp);
14663 else
14664 sprintf (buf, "%d", (int) disp);
14665 }
14666}
14667
14668/* Put DISP in BUF as signed hex number. */
14669
14670static void
14671print_displacement (char *buf, bfd_vma disp)
14672{
14673 bfd_signed_vma val = disp;
14674 char tmp[30];
14675 int i, j = 0;
14676
14677 if (val < 0)
14678 {
14679 buf[j++] = '-';
14680 val = -disp;
14681
14682 /* Check for possible overflow. */
14683 if (val < 0)
14684 {
14685 switch (address_mode)
14686 {
14687 case mode_64bit:
14688 strcpy (buf + j, "0x8000000000000000");
14689 break;
14690 case mode_32bit:
14691 strcpy (buf + j, "0x80000000");
14692 break;
14693 case mode_16bit:
14694 strcpy (buf + j, "0x8000");
14695 break;
14696 }
14697 return;
14698 }
14699 }
14700
14701 buf[j++] = '0';
14702 buf[j++] = 'x';
14703
14704 sprintf_vma (tmp, (bfd_vma) val);
14705 for (i = 0; tmp[i] == '0'; i++)
14706 continue;
14707 if (tmp[i] == '\0')
14708 i--;
14709 strcpy (buf + j, tmp + i);
14710}
14711
14712static void
14713intel_operand_size (int bytemode, int sizeflag)
14714{
14715 if (vex.evex
14716 && vex.b
14717 && (bytemode == x_mode
14718 || bytemode == evex_half_bcst_xmmq_mode))
14719 {
14720 if (vex.w)
14721 oappend ("QWORD PTR ");
14722 else
14723 oappend ("DWORD PTR ");
14724 return;
14725 }
14726 switch (bytemode)
14727 {
14728 case b_mode:
14729 case b_swap_mode:
14730 case dqb_mode:
14731 case db_mode:
14732 oappend ("BYTE PTR ");
14733 break;
14734 case w_mode:
14735 case dw_mode:
14736 case dqw_mode:
14737 oappend ("WORD PTR ");
14738 break;
14739 case indir_v_mode:
14740 if (address_mode == mode_64bit && isa64 == intel64)
14741 {
14742 oappend ("QWORD PTR ");
14743 break;
14744 }
14745 /* Fall through. */
14746 case stack_v_mode:
14747 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14748 {
14749 oappend ("QWORD PTR ");
14750 break;
14751 }
14752 /* Fall through. */
14753 case v_mode:
14754 case v_swap_mode:
14755 case dq_mode:
14756 USED_REX (REX_W);
14757 if (rex & REX_W)
14758 oappend ("QWORD PTR ");
14759 else
14760 {
14761 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14762 oappend ("DWORD PTR ");
14763 else
14764 oappend ("WORD PTR ");
14765 used_prefixes |= (prefixes & PREFIX_DATA);
14766 }
14767 break;
14768 case z_mode:
14769 if ((rex & REX_W) || (sizeflag & DFLAG))
14770 *obufp++ = 'D';
14771 oappend ("WORD PTR ");
14772 if (!(rex & REX_W))
14773 used_prefixes |= (prefixes & PREFIX_DATA);
14774 break;
14775 case a_mode:
14776 if (sizeflag & DFLAG)
14777 oappend ("QWORD PTR ");
14778 else
14779 oappend ("DWORD PTR ");
14780 used_prefixes |= (prefixes & PREFIX_DATA);
14781 break;
14782 case d_mode:
14783 case d_scalar_mode:
14784 case d_scalar_swap_mode:
14785 case d_swap_mode:
14786 case dqd_mode:
14787 oappend ("DWORD PTR ");
14788 break;
14789 case q_mode:
14790 case q_scalar_mode:
14791 case q_scalar_swap_mode:
14792 case q_swap_mode:
14793 oappend ("QWORD PTR ");
14794 break;
14795 case m_mode:
14796 if (address_mode == mode_64bit)
14797 oappend ("QWORD PTR ");
14798 else
14799 oappend ("DWORD PTR ");
14800 break;
14801 case f_mode:
14802 if (sizeflag & DFLAG)
14803 oappend ("FWORD PTR ");
14804 else
14805 oappend ("DWORD PTR ");
14806 used_prefixes |= (prefixes & PREFIX_DATA);
14807 break;
14808 case t_mode:
14809 oappend ("TBYTE PTR ");
14810 break;
14811 case x_mode:
14812 case x_swap_mode:
14813 case evex_x_gscat_mode:
14814 case evex_x_nobcst_mode:
14815 case b_scalar_mode:
14816 case w_scalar_mode:
14817 if (need_vex)
14818 {
14819 switch (vex.length)
14820 {
14821 case 128:
14822 oappend ("XMMWORD PTR ");
14823 break;
14824 case 256:
14825 oappend ("YMMWORD PTR ");
14826 break;
14827 case 512:
14828 oappend ("ZMMWORD PTR ");
14829 break;
14830 default:
14831 abort ();
14832 }
14833 }
14834 else
14835 oappend ("XMMWORD PTR ");
14836 break;
14837 case xmm_mode:
14838 oappend ("XMMWORD PTR ");
14839 break;
14840 case ymm_mode:
14841 oappend ("YMMWORD PTR ");
14842 break;
14843 case xmmq_mode:
14844 case evex_half_bcst_xmmq_mode:
14845 if (!need_vex)
14846 abort ();
14847
14848 switch (vex.length)
14849 {
14850 case 128:
14851 oappend ("QWORD PTR ");
14852 break;
14853 case 256:
14854 oappend ("XMMWORD PTR ");
14855 break;
14856 case 512:
14857 oappend ("YMMWORD PTR ");
14858 break;
14859 default:
14860 abort ();
14861 }
14862 break;
14863 case xmm_mb_mode:
14864 if (!need_vex)
14865 abort ();
14866
14867 switch (vex.length)
14868 {
14869 case 128:
14870 case 256:
14871 case 512:
14872 oappend ("BYTE PTR ");
14873 break;
14874 default:
14875 abort ();
14876 }
14877 break;
14878 case xmm_mw_mode:
14879 if (!need_vex)
14880 abort ();
14881
14882 switch (vex.length)
14883 {
14884 case 128:
14885 case 256:
14886 case 512:
14887 oappend ("WORD PTR ");
14888 break;
14889 default:
14890 abort ();
14891 }
14892 break;
14893 case xmm_md_mode:
14894 if (!need_vex)
14895 abort ();
14896
14897 switch (vex.length)
14898 {
14899 case 128:
14900 case 256:
14901 case 512:
14902 oappend ("DWORD PTR ");
14903 break;
14904 default:
14905 abort ();
14906 }
14907 break;
14908 case xmm_mq_mode:
14909 if (!need_vex)
14910 abort ();
14911
14912 switch (vex.length)
14913 {
14914 case 128:
14915 case 256:
14916 case 512:
14917 oappend ("QWORD PTR ");
14918 break;
14919 default:
14920 abort ();
14921 }
14922 break;
14923 case xmmdw_mode:
14924 if (!need_vex)
14925 abort ();
14926
14927 switch (vex.length)
14928 {
14929 case 128:
14930 oappend ("WORD PTR ");
14931 break;
14932 case 256:
14933 oappend ("DWORD PTR ");
14934 break;
14935 case 512:
14936 oappend ("QWORD PTR ");
14937 break;
14938 default:
14939 abort ();
14940 }
14941 break;
14942 case xmmqd_mode:
14943 if (!need_vex)
14944 abort ();
14945
14946 switch (vex.length)
14947 {
14948 case 128:
14949 oappend ("DWORD PTR ");
14950 break;
14951 case 256:
14952 oappend ("QWORD PTR ");
14953 break;
14954 case 512:
14955 oappend ("XMMWORD PTR ");
14956 break;
14957 default:
14958 abort ();
14959 }
14960 break;
14961 case ymmq_mode:
14962 if (!need_vex)
14963 abort ();
14964
14965 switch (vex.length)
14966 {
14967 case 128:
14968 oappend ("QWORD PTR ");
14969 break;
14970 case 256:
14971 oappend ("YMMWORD PTR ");
14972 break;
14973 case 512:
14974 oappend ("ZMMWORD PTR ");
14975 break;
14976 default:
14977 abort ();
14978 }
14979 break;
14980 case ymmxmm_mode:
14981 if (!need_vex)
14982 abort ();
14983
14984 switch (vex.length)
14985 {
14986 case 128:
14987 case 256:
14988 oappend ("XMMWORD PTR ");
14989 break;
14990 default:
14991 abort ();
14992 }
14993 break;
14994 case o_mode:
14995 oappend ("OWORD PTR ");
14996 break;
14997 case xmm_mdq_mode:
14998 case vex_w_dq_mode:
14999 case vex_scalar_w_dq_mode:
15000 if (!need_vex)
15001 abort ();
15002
15003 if (vex.w)
15004 oappend ("QWORD PTR ");
15005 else
15006 oappend ("DWORD PTR ");
15007 break;
15008 case vex_vsib_d_w_dq_mode:
15009 case vex_vsib_q_w_dq_mode:
15010 if (!need_vex)
15011 abort ();
15012
15013 if (!vex.evex)
15014 {
15015 if (vex.w)
15016 oappend ("QWORD PTR ");
15017 else
15018 oappend ("DWORD PTR ");
15019 }
15020 else
15021 {
15022 switch (vex.length)
15023 {
15024 case 128:
15025 oappend ("XMMWORD PTR ");
15026 break;
15027 case 256:
15028 oappend ("YMMWORD PTR ");
15029 break;
15030 case 512:
15031 oappend ("ZMMWORD PTR ");
15032 break;
15033 default:
15034 abort ();
15035 }
15036 }
15037 break;
15038 case vex_vsib_q_w_d_mode:
15039 case vex_vsib_d_w_d_mode:
15040 if (!need_vex || !vex.evex)
15041 abort ();
15042
15043 switch (vex.length)
15044 {
15045 case 128:
15046 oappend ("QWORD PTR ");
15047 break;
15048 case 256:
15049 oappend ("XMMWORD PTR ");
15050 break;
15051 case 512:
15052 oappend ("YMMWORD PTR ");
15053 break;
15054 default:
15055 abort ();
15056 }
15057
15058 break;
15059 case mask_bd_mode:
15060 if (!need_vex || vex.length != 128)
15061 abort ();
15062 if (vex.w)
15063 oappend ("DWORD PTR ");
15064 else
15065 oappend ("BYTE PTR ");
15066 break;
15067 case mask_mode:
15068 if (!need_vex)
15069 abort ();
15070 if (vex.w)
15071 oappend ("QWORD PTR ");
15072 else
15073 oappend ("WORD PTR ");
15074 break;
15075 case v_bnd_mode:
15076 default:
15077 break;
15078 }
15079}
15080
15081static void
15082OP_E_register (int bytemode, int sizeflag)
15083{
15084 int reg = modrm.rm;
15085 const char **names;
15086
15087 USED_REX (REX_B);
15088 if ((rex & REX_B))
15089 reg += 8;
15090
15091 if ((sizeflag & SUFFIX_ALWAYS)
15092 && (bytemode == b_swap_mode
15093 || bytemode == v_swap_mode))
15094 swap_operand ();
15095
15096 switch (bytemode)
15097 {
15098 case b_mode:
15099 case b_swap_mode:
15100 USED_REX (0);
15101 if (rex)
15102 names = names8rex;
15103 else
15104 names = names8;
15105 break;
15106 case w_mode:
15107 names = names16;
15108 break;
15109 case d_mode:
15110 case dw_mode:
15111 case db_mode:
15112 names = names32;
15113 break;
15114 case q_mode:
15115 names = names64;
15116 break;
15117 case m_mode:
15118 case v_bnd_mode:
15119 names = address_mode == mode_64bit ? names64 : names32;
15120 break;
15121 case bnd_mode:
15122 if (reg > 0x3)
15123 {
15124 oappend ("(bad)");
15125 return;
15126 }
15127 names = names_bnd;
15128 break;
15129 case indir_v_mode:
15130 if (address_mode == mode_64bit && isa64 == intel64)
15131 {
15132 names = names64;
15133 break;
15134 }
15135 /* Fall through. */
15136 case stack_v_mode:
15137 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15138 {
15139 names = names64;
15140 break;
15141 }
15142 bytemode = v_mode;
15143 /* Fall through. */
15144 case v_mode:
15145 case v_swap_mode:
15146 case dq_mode:
15147 case dqb_mode:
15148 case dqd_mode:
15149 case dqw_mode:
15150 USED_REX (REX_W);
15151 if (rex & REX_W)
15152 names = names64;
15153 else
15154 {
15155 if ((sizeflag & DFLAG)
15156 || (bytemode != v_mode
15157 && bytemode != v_swap_mode))
15158 names = names32;
15159 else
15160 names = names16;
15161 used_prefixes |= (prefixes & PREFIX_DATA);
15162 }
15163 break;
15164 case mask_bd_mode:
15165 case mask_mode:
15166 if (reg > 0x7)
15167 {
15168 oappend ("(bad)");
15169 return;
15170 }
15171 names = names_mask;
15172 break;
15173 case 0:
15174 return;
15175 default:
15176 oappend (INTERNAL_DISASSEMBLER_ERROR);
15177 return;
15178 }
15179 oappend (names[reg]);
15180}
15181
15182static void
15183OP_E_memory (int bytemode, int sizeflag)
15184{
15185 bfd_vma disp = 0;
15186 int add = (rex & REX_B) ? 8 : 0;
15187 int riprel = 0;
15188 int shift;
15189
15190 if (vex.evex)
15191 {
15192 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15193 if (vex.b
15194 && bytemode != x_mode
15195 && bytemode != xmmq_mode
15196 && bytemode != evex_half_bcst_xmmq_mode)
15197 {
15198 BadOp ();
15199 return;
15200 }
15201 switch (bytemode)
15202 {
15203 case dqw_mode:
15204 case dw_mode:
15205 shift = 1;
15206 break;
15207 case dqb_mode:
15208 case db_mode:
15209 shift = 0;
15210 break;
15211 case vex_vsib_d_w_dq_mode:
15212 case vex_vsib_d_w_d_mode:
15213 case vex_vsib_q_w_dq_mode:
15214 case vex_vsib_q_w_d_mode:
15215 case evex_x_gscat_mode:
15216 case xmm_mdq_mode:
15217 shift = vex.w ? 3 : 2;
15218 break;
15219 case x_mode:
15220 case evex_half_bcst_xmmq_mode:
15221 case xmmq_mode:
15222 if (vex.b)
15223 {
15224 shift = vex.w ? 3 : 2;
15225 break;
15226 }
15227 /* Fall through. */
15228 case xmmqd_mode:
15229 case xmmdw_mode:
15230 case ymmq_mode:
15231 case evex_x_nobcst_mode:
15232 case x_swap_mode:
15233 switch (vex.length)
15234 {
15235 case 128:
15236 shift = 4;
15237 break;
15238 case 256:
15239 shift = 5;
15240 break;
15241 case 512:
15242 shift = 6;
15243 break;
15244 default:
15245 abort ();
15246 }
15247 break;
15248 case ymm_mode:
15249 shift = 5;
15250 break;
15251 case xmm_mode:
15252 shift = 4;
15253 break;
15254 case xmm_mq_mode:
15255 case q_mode:
15256 case q_scalar_mode:
15257 case q_swap_mode:
15258 case q_scalar_swap_mode:
15259 shift = 3;
15260 break;
15261 case dqd_mode:
15262 case xmm_md_mode:
15263 case d_mode:
15264 case d_scalar_mode:
15265 case d_swap_mode:
15266 case d_scalar_swap_mode:
15267 shift = 2;
15268 break;
15269 case w_scalar_mode:
15270 case xmm_mw_mode:
15271 shift = 1;
15272 break;
15273 case b_scalar_mode:
15274 case xmm_mb_mode:
15275 shift = 0;
15276 break;
15277 default:
15278 abort ();
15279 }
15280 /* Make necessary corrections to shift for modes that need it.
15281 For these modes we currently have shift 4, 5 or 6 depending on
15282 vex.length (it corresponds to xmmword, ymmword or zmmword
15283 operand). We might want to make it 3, 4 or 5 (e.g. for
15284 xmmq_mode). In case of broadcast enabled the corrections
15285 aren't needed, as element size is always 32 or 64 bits. */
15286 if (!vex.b
15287 && (bytemode == xmmq_mode
15288 || bytemode == evex_half_bcst_xmmq_mode))
15289 shift -= 1;
15290 else if (bytemode == xmmqd_mode)
15291 shift -= 2;
15292 else if (bytemode == xmmdw_mode)
15293 shift -= 3;
15294 else if (bytemode == ymmq_mode && vex.length == 128)
15295 shift -= 1;
15296 }
15297 else
15298 shift = 0;
15299
15300 USED_REX (REX_B);
15301 if (intel_syntax)
15302 intel_operand_size (bytemode, sizeflag);
15303 append_seg ();
15304
15305 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15306 {
15307 /* 32/64 bit address mode */
15308 int havedisp;
15309 int havesib;
15310 int havebase;
15311 int haveindex;
15312 int needindex;
15313 int base, rbase;
15314 int vindex = 0;
15315 int scale = 0;
15316 int addr32flag = !((sizeflag & AFLAG)
15317 || bytemode == v_bnd_mode
15318 || bytemode == bnd_mode);
15319 const char **indexes64 = names64;
15320 const char **indexes32 = names32;
15321
15322 havesib = 0;
15323 havebase = 1;
15324 haveindex = 0;
15325 base = modrm.rm;
15326
15327 if (base == 4)
15328 {
15329 havesib = 1;
15330 vindex = sib.index;
15331 USED_REX (REX_X);
15332 if (rex & REX_X)
15333 vindex += 8;
15334 switch (bytemode)
15335 {
15336 case vex_vsib_d_w_dq_mode:
15337 case vex_vsib_d_w_d_mode:
15338 case vex_vsib_q_w_dq_mode:
15339 case vex_vsib_q_w_d_mode:
15340 if (!need_vex)
15341 abort ();
15342 if (vex.evex)
15343 {
15344 if (!vex.v)
15345 vindex += 16;
15346 }
15347
15348 haveindex = 1;
15349 switch (vex.length)
15350 {
15351 case 128:
15352 indexes64 = indexes32 = names_xmm;
15353 break;
15354 case 256:
15355 if (!vex.w
15356 || bytemode == vex_vsib_q_w_dq_mode
15357 || bytemode == vex_vsib_q_w_d_mode)
15358 indexes64 = indexes32 = names_ymm;
15359 else
15360 indexes64 = indexes32 = names_xmm;
15361 break;
15362 case 512:
15363 if (!vex.w
15364 || bytemode == vex_vsib_q_w_dq_mode
15365 || bytemode == vex_vsib_q_w_d_mode)
15366 indexes64 = indexes32 = names_zmm;
15367 else
15368 indexes64 = indexes32 = names_ymm;
15369 break;
15370 default:
15371 abort ();
15372 }
15373 break;
15374 default:
15375 haveindex = vindex != 4;
15376 break;
15377 }
15378 scale = sib.scale;
15379 base = sib.base;
15380 codep++;
15381 }
15382 rbase = base + add;
15383
15384 switch (modrm.mod)
15385 {
15386 case 0:
15387 if (base == 5)
15388 {
15389 havebase = 0;
15390 if (address_mode == mode_64bit && !havesib)
15391 riprel = 1;
15392 disp = get32s ();
15393 }
15394 break;
15395 case 1:
15396 FETCH_DATA (the_info, codep + 1);
15397 disp = *codep++;
15398 if ((disp & 0x80) != 0)
15399 disp -= 0x100;
15400 if (vex.evex && shift > 0)
15401 disp <<= shift;
15402 break;
15403 case 2:
15404 disp = get32s ();
15405 break;
15406 }
15407
15408 /* In 32bit mode, we need index register to tell [offset] from
15409 [eiz*1 + offset]. */
15410 needindex = (havesib
15411 && !havebase
15412 && !haveindex
15413 && address_mode == mode_32bit);
15414 havedisp = (havebase
15415 || needindex
15416 || (havesib && (haveindex || scale != 0)));
15417
15418 if (!intel_syntax)
15419 if (modrm.mod != 0 || base == 5)
15420 {
15421 if (havedisp || riprel)
15422 print_displacement (scratchbuf, disp);
15423 else
15424 print_operand_value (scratchbuf, 1, disp);
15425 oappend (scratchbuf);
15426 if (riprel)
15427 {
15428 set_op (disp, 1);
15429 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15430 }
15431 }
15432
15433 if ((havebase || haveindex || riprel)
15434 && (bytemode != v_bnd_mode)
15435 && (bytemode != bnd_mode))
15436 used_prefixes |= PREFIX_ADDR;
15437
15438 if (havedisp || (intel_syntax && riprel))
15439 {
15440 *obufp++ = open_char;
15441 if (intel_syntax && riprel)
15442 {
15443 set_op (disp, 1);
15444 oappend (!addr32flag ? "rip" : "eip");
15445 }
15446 *obufp = '\0';
15447 if (havebase)
15448 oappend (address_mode == mode_64bit && !addr32flag
15449 ? names64[rbase] : names32[rbase]);
15450 if (havesib)
15451 {
15452 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15453 print index to tell base + index from base. */
15454 if (scale != 0
15455 || needindex
15456 || haveindex
15457 || (havebase && base != ESP_REG_NUM))
15458 {
15459 if (!intel_syntax || havebase)
15460 {
15461 *obufp++ = separator_char;
15462 *obufp = '\0';
15463 }
15464 if (haveindex)
15465 oappend (address_mode == mode_64bit && !addr32flag
15466 ? indexes64[vindex] : indexes32[vindex]);
15467 else
15468 oappend (address_mode == mode_64bit && !addr32flag
15469 ? index64 : index32);
15470
15471 *obufp++ = scale_char;
15472 *obufp = '\0';
15473 sprintf (scratchbuf, "%d", 1 << scale);
15474 oappend (scratchbuf);
15475 }
15476 }
15477 if (intel_syntax
15478 && (disp || modrm.mod != 0 || base == 5))
15479 {
15480 if (!havedisp || (bfd_signed_vma) disp >= 0)
15481 {
15482 *obufp++ = '+';
15483 *obufp = '\0';
15484 }
15485 else if (modrm.mod != 1 && disp != -disp)
15486 {
15487 *obufp++ = '-';
15488 *obufp = '\0';
15489 disp = - (bfd_signed_vma) disp;
15490 }
15491
15492 if (havedisp)
15493 print_displacement (scratchbuf, disp);
15494 else
15495 print_operand_value (scratchbuf, 1, disp);
15496 oappend (scratchbuf);
15497 }
15498
15499 *obufp++ = close_char;
15500 *obufp = '\0';
15501 }
15502 else if (intel_syntax)
15503 {
15504 if (modrm.mod != 0 || base == 5)
15505 {
15506 if (!active_seg_prefix)
15507 {
15508 oappend (names_seg[ds_reg - es_reg]);
15509 oappend (":");
15510 }
15511 print_operand_value (scratchbuf, 1, disp);
15512 oappend (scratchbuf);
15513 }
15514 }
15515 }
15516 else
15517 {
15518 /* 16 bit address mode */
15519 used_prefixes |= prefixes & PREFIX_ADDR;
15520 switch (modrm.mod)
15521 {
15522 case 0:
15523 if (modrm.rm == 6)
15524 {
15525 disp = get16 ();
15526 if ((disp & 0x8000) != 0)
15527 disp -= 0x10000;
15528 }
15529 break;
15530 case 1:
15531 FETCH_DATA (the_info, codep + 1);
15532 disp = *codep++;
15533 if ((disp & 0x80) != 0)
15534 disp -= 0x100;
15535 break;
15536 case 2:
15537 disp = get16 ();
15538 if ((disp & 0x8000) != 0)
15539 disp -= 0x10000;
15540 break;
15541 }
15542
15543 if (!intel_syntax)
15544 if (modrm.mod != 0 || modrm.rm == 6)
15545 {
15546 print_displacement (scratchbuf, disp);
15547 oappend (scratchbuf);
15548 }
15549
15550 if (modrm.mod != 0 || modrm.rm != 6)
15551 {
15552 *obufp++ = open_char;
15553 *obufp = '\0';
15554 oappend (index16[modrm.rm]);
15555 if (intel_syntax
15556 && (disp || modrm.mod != 0 || modrm.rm == 6))
15557 {
15558 if ((bfd_signed_vma) disp >= 0)
15559 {
15560 *obufp++ = '+';
15561 *obufp = '\0';
15562 }
15563 else if (modrm.mod != 1)
15564 {
15565 *obufp++ = '-';
15566 *obufp = '\0';
15567 disp = - (bfd_signed_vma) disp;
15568 }
15569
15570 print_displacement (scratchbuf, disp);
15571 oappend (scratchbuf);
15572 }
15573
15574 *obufp++ = close_char;
15575 *obufp = '\0';
15576 }
15577 else if (intel_syntax)
15578 {
15579 if (!active_seg_prefix)
15580 {
15581 oappend (names_seg[ds_reg - es_reg]);
15582 oappend (":");
15583 }
15584 print_operand_value (scratchbuf, 1, disp & 0xffff);
15585 oappend (scratchbuf);
15586 }
15587 }
15588 if (vex.evex && vex.b
15589 && (bytemode == x_mode
15590 || bytemode == xmmq_mode
15591 || bytemode == evex_half_bcst_xmmq_mode))
15592 {
15593 if (vex.w
15594 || bytemode == xmmq_mode
15595 || bytemode == evex_half_bcst_xmmq_mode)
15596 {
15597 switch (vex.length)
15598 {
15599 case 128:
15600 oappend ("{1to2}");
15601 break;
15602 case 256:
15603 oappend ("{1to4}");
15604 break;
15605 case 512:
15606 oappend ("{1to8}");
15607 break;
15608 default:
15609 abort ();
15610 }
15611 }
15612 else
15613 {
15614 switch (vex.length)
15615 {
15616 case 128:
15617 oappend ("{1to4}");
15618 break;
15619 case 256:
15620 oappend ("{1to8}");
15621 break;
15622 case 512:
15623 oappend ("{1to16}");
15624 break;
15625 default:
15626 abort ();
15627 }
15628 }
15629 }
15630}
15631
15632static void
15633OP_E (int bytemode, int sizeflag)
15634{
15635 /* Skip mod/rm byte. */
15636 MODRM_CHECK;
15637 codep++;
15638
15639 if (modrm.mod == 3)
15640 OP_E_register (bytemode, sizeflag);
15641 else
15642 OP_E_memory (bytemode, sizeflag);
15643}
15644
15645static void
15646OP_G (int bytemode, int sizeflag)
15647{
15648 int add = 0;
15649 USED_REX (REX_R);
15650 if (rex & REX_R)
15651 add += 8;
15652 switch (bytemode)
15653 {
15654 case b_mode:
15655 USED_REX (0);
15656 if (rex)
15657 oappend (names8rex[modrm.reg + add]);
15658 else
15659 oappend (names8[modrm.reg + add]);
15660 break;
15661 case w_mode:
15662 oappend (names16[modrm.reg + add]);
15663 break;
15664 case d_mode:
15665 case db_mode:
15666 case dw_mode:
15667 oappend (names32[modrm.reg + add]);
15668 break;
15669 case q_mode:
15670 oappend (names64[modrm.reg + add]);
15671 break;
15672 case bnd_mode:
15673 if (modrm.reg > 0x3)
15674 {
15675 oappend ("(bad)");
15676 return;
15677 }
15678 oappend (names_bnd[modrm.reg]);
15679 break;
15680 case v_mode:
15681 case dq_mode:
15682 case dqb_mode:
15683 case dqd_mode:
15684 case dqw_mode:
15685 USED_REX (REX_W);
15686 if (rex & REX_W)
15687 oappend (names64[modrm.reg + add]);
15688 else
15689 {
15690 if ((sizeflag & DFLAG) || bytemode != v_mode)
15691 oappend (names32[modrm.reg + add]);
15692 else
15693 oappend (names16[modrm.reg + add]);
15694 used_prefixes |= (prefixes & PREFIX_DATA);
15695 }
15696 break;
15697 case m_mode:
15698 if (address_mode == mode_64bit)
15699 oappend (names64[modrm.reg + add]);
15700 else
15701 oappend (names32[modrm.reg + add]);
15702 break;
15703 case mask_bd_mode:
15704 case mask_mode:
15705 if ((modrm.reg + add) > 0x7)
15706 {
15707 oappend ("(bad)");
15708 return;
15709 }
15710 oappend (names_mask[modrm.reg + add]);
15711 break;
15712 default:
15713 oappend (INTERNAL_DISASSEMBLER_ERROR);
15714 break;
15715 }
15716}
15717
15718static bfd_vma
15719get64 (void)
15720{
15721 bfd_vma x;
15722#ifdef BFD64
15723 unsigned int a;
15724 unsigned int b;
15725
15726 FETCH_DATA (the_info, codep + 8);
15727 a = *codep++ & 0xff;
15728 a |= (*codep++ & 0xff) << 8;
15729 a |= (*codep++ & 0xff) << 16;
15730 a |= (*codep++ & 0xffu) << 24;
15731 b = *codep++ & 0xff;
15732 b |= (*codep++ & 0xff) << 8;
15733 b |= (*codep++ & 0xff) << 16;
15734 b |= (*codep++ & 0xffu) << 24;
15735 x = a + ((bfd_vma) b << 32);
15736#else
15737 abort ();
15738 x = 0;
15739#endif
15740 return x;
15741}
15742
15743static bfd_signed_vma
15744get32 (void)
15745{
15746 bfd_signed_vma x = 0;
15747
15748 FETCH_DATA (the_info, codep + 4);
15749 x = *codep++ & (bfd_signed_vma) 0xff;
15750 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15751 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15752 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15753 return x;
15754}
15755
15756static bfd_signed_vma
15757get32s (void)
15758{
15759 bfd_signed_vma x = 0;
15760
15761 FETCH_DATA (the_info, codep + 4);
15762 x = *codep++ & (bfd_signed_vma) 0xff;
15763 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15764 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15765 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15766
15767 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15768
15769 return x;
15770}
15771
15772static int
15773get16 (void)
15774{
15775 int x = 0;
15776
15777 FETCH_DATA (the_info, codep + 2);
15778 x = *codep++ & 0xff;
15779 x |= (*codep++ & 0xff) << 8;
15780 return x;
15781}
15782
15783static void
15784set_op (bfd_vma op, int riprel)
15785{
15786 op_index[op_ad] = op_ad;
15787 if (address_mode == mode_64bit)
15788 {
15789 op_address[op_ad] = op;
15790 op_riprel[op_ad] = riprel;
15791 }
15792 else
15793 {
15794 /* Mask to get a 32-bit address. */
15795 op_address[op_ad] = op & 0xffffffff;
15796 op_riprel[op_ad] = riprel & 0xffffffff;
15797 }
15798}
15799
15800static void
15801OP_REG (int code, int sizeflag)
15802{
15803 const char *s;
15804 int add;
15805
15806 switch (code)
15807 {
15808 case es_reg: case ss_reg: case cs_reg:
15809 case ds_reg: case fs_reg: case gs_reg:
15810 oappend (names_seg[code - es_reg]);
15811 return;
15812 }
15813
15814 USED_REX (REX_B);
15815 if (rex & REX_B)
15816 add = 8;
15817 else
15818 add = 0;
15819
15820 switch (code)
15821 {
15822 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15823 case sp_reg: case bp_reg: case si_reg: case di_reg:
15824 s = names16[code - ax_reg + add];
15825 break;
15826 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15827 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15828 USED_REX (0);
15829 if (rex)
15830 s = names8rex[code - al_reg + add];
15831 else
15832 s = names8[code - al_reg];
15833 break;
15834 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15835 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15836 if (address_mode == mode_64bit
15837 && ((sizeflag & DFLAG) || (rex & REX_W)))
15838 {
15839 s = names64[code - rAX_reg + add];
15840 break;
15841 }
15842 code += eAX_reg - rAX_reg;
15843 /* Fall through. */
15844 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15845 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15846 USED_REX (REX_W);
15847 if (rex & REX_W)
15848 s = names64[code - eAX_reg + add];
15849 else
15850 {
15851 if (sizeflag & DFLAG)
15852 s = names32[code - eAX_reg + add];
15853 else
15854 s = names16[code - eAX_reg + add];
15855 used_prefixes |= (prefixes & PREFIX_DATA);
15856 }
15857 break;
15858 default:
15859 s = INTERNAL_DISASSEMBLER_ERROR;
15860 break;
15861 }
15862 oappend (s);
15863}
15864
15865static void
15866OP_IMREG (int code, int sizeflag)
15867{
15868 const char *s;
15869
15870 switch (code)
15871 {
15872 case indir_dx_reg:
15873 if (intel_syntax)
15874 s = "dx";
15875 else
15876 s = "(%dx)";
15877 break;
15878 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15879 case sp_reg: case bp_reg: case si_reg: case di_reg:
15880 s = names16[code - ax_reg];
15881 break;
15882 case es_reg: case ss_reg: case cs_reg:
15883 case ds_reg: case fs_reg: case gs_reg:
15884 s = names_seg[code - es_reg];
15885 break;
15886 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15887 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15888 USED_REX (0);
15889 if (rex)
15890 s = names8rex[code - al_reg];
15891 else
15892 s = names8[code - al_reg];
15893 break;
15894 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15895 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15896 USED_REX (REX_W);
15897 if (rex & REX_W)
15898 s = names64[code - eAX_reg];
15899 else
15900 {
15901 if (sizeflag & DFLAG)
15902 s = names32[code - eAX_reg];
15903 else
15904 s = names16[code - eAX_reg];
15905 used_prefixes |= (prefixes & PREFIX_DATA);
15906 }
15907 break;
15908 case z_mode_ax_reg:
15909 if ((rex & REX_W) || (sizeflag & DFLAG))
15910 s = *names32;
15911 else
15912 s = *names16;
15913 if (!(rex & REX_W))
15914 used_prefixes |= (prefixes & PREFIX_DATA);
15915 break;
15916 default:
15917 s = INTERNAL_DISASSEMBLER_ERROR;
15918 break;
15919 }
15920 oappend (s);
15921}
15922
15923static void
15924OP_I (int bytemode, int sizeflag)
15925{
15926 bfd_signed_vma op;
15927 bfd_signed_vma mask = -1;
15928
15929 switch (bytemode)
15930 {
15931 case b_mode:
15932 FETCH_DATA (the_info, codep + 1);
15933 op = *codep++;
15934 mask = 0xff;
15935 break;
15936 case q_mode:
15937 if (address_mode == mode_64bit)
15938 {
15939 op = get32s ();
15940 break;
15941 }
15942 /* Fall through. */
15943 case v_mode:
15944 USED_REX (REX_W);
15945 if (rex & REX_W)
15946 op = get32s ();
15947 else
15948 {
15949 if (sizeflag & DFLAG)
15950 {
15951 op = get32 ();
15952 mask = 0xffffffff;
15953 }
15954 else
15955 {
15956 op = get16 ();
15957 mask = 0xfffff;
15958 }
15959 used_prefixes |= (prefixes & PREFIX_DATA);
15960 }
15961 break;
15962 case w_mode:
15963 mask = 0xfffff;
15964 op = get16 ();
15965 break;
15966 case const_1_mode:
15967 if (intel_syntax)
15968 oappend ("1");
15969 return;
15970 default:
15971 oappend (INTERNAL_DISASSEMBLER_ERROR);
15972 return;
15973 }
15974
15975 op &= mask;
15976 scratchbuf[0] = '$';
15977 print_operand_value (scratchbuf + 1, 1, op);
15978 oappend_maybe_intel (scratchbuf);
15979 scratchbuf[0] = '\0';
15980}
15981
15982static void
15983OP_I64 (int bytemode, int sizeflag)
15984{
15985 bfd_signed_vma op;
15986 bfd_signed_vma mask = -1;
15987
15988 if (address_mode != mode_64bit)
15989 {
15990 OP_I (bytemode, sizeflag);
15991 return;
15992 }
15993
15994 switch (bytemode)
15995 {
15996 case b_mode:
15997 FETCH_DATA (the_info, codep + 1);
15998 op = *codep++;
15999 mask = 0xff;
16000 break;
16001 case v_mode:
16002 USED_REX (REX_W);
16003 if (rex & REX_W)
16004 op = get64 ();
16005 else
16006 {
16007 if (sizeflag & DFLAG)
16008 {
16009 op = get32 ();
16010 mask = 0xffffffff;
16011 }
16012 else
16013 {
16014 op = get16 ();
16015 mask = 0xfffff;
16016 }
16017 used_prefixes |= (prefixes & PREFIX_DATA);
16018 }
16019 break;
16020 case w_mode:
16021 mask = 0xfffff;
16022 op = get16 ();
16023 break;
16024 default:
16025 oappend (INTERNAL_DISASSEMBLER_ERROR);
16026 return;
16027 }
16028
16029 op &= mask;
16030 scratchbuf[0] = '$';
16031 print_operand_value (scratchbuf + 1, 1, op);
16032 oappend_maybe_intel (scratchbuf);
16033 scratchbuf[0] = '\0';
16034}
16035
16036static void
16037OP_sI (int bytemode, int sizeflag)
16038{
16039 bfd_signed_vma op;
16040
16041 switch (bytemode)
16042 {
16043 case b_mode:
16044 case b_T_mode:
16045 FETCH_DATA (the_info, codep + 1);
16046 op = *codep++;
16047 if ((op & 0x80) != 0)
16048 op -= 0x100;
16049 if (bytemode == b_T_mode)
16050 {
16051 if (address_mode != mode_64bit
16052 || !((sizeflag & DFLAG) || (rex & REX_W)))
16053 {
16054 /* The operand-size prefix is overridden by a REX prefix. */
16055 if ((sizeflag & DFLAG) || (rex & REX_W))
16056 op &= 0xffffffff;
16057 else
16058 op &= 0xffff;
16059 }
16060 }
16061 else
16062 {
16063 if (!(rex & REX_W))
16064 {
16065 if (sizeflag & DFLAG)
16066 op &= 0xffffffff;
16067 else
16068 op &= 0xffff;
16069 }
16070 }
16071 break;
16072 case v_mode:
16073 /* The operand-size prefix is overridden by a REX prefix. */
16074 if ((sizeflag & DFLAG) || (rex & REX_W))
16075 op = get32s ();
16076 else
16077 op = get16 ();
16078 break;
16079 default:
16080 oappend (INTERNAL_DISASSEMBLER_ERROR);
16081 return;
16082 }
16083
16084 scratchbuf[0] = '$';
16085 print_operand_value (scratchbuf + 1, 1, op);
16086 oappend_maybe_intel (scratchbuf);
16087}
16088
16089static void
16090OP_J (int bytemode, int sizeflag)
16091{
16092 bfd_vma disp;
16093 bfd_vma mask = -1;
16094 bfd_vma segment = 0;
16095
16096 switch (bytemode)
16097 {
16098 case b_mode:
16099 FETCH_DATA (the_info, codep + 1);
16100 disp = *codep++;
16101 if ((disp & 0x80) != 0)
16102 disp -= 0x100;
16103 break;
16104 case v_mode:
16105 if (isa64 == amd64)
16106 USED_REX (REX_W);
16107 if ((sizeflag & DFLAG)
16108 || (address_mode == mode_64bit
16109 && (isa64 != amd64 || (rex & REX_W))))
16110 disp = get32s ();
16111 else
16112 {
16113 disp = get16 ();
16114 if ((disp & 0x8000) != 0)
16115 disp -= 0x10000;
16116 /* In 16bit mode, address is wrapped around at 64k within
16117 the same segment. Otherwise, a data16 prefix on a jump
16118 instruction means that the pc is masked to 16 bits after
16119 the displacement is added! */
16120 mask = 0xffff;
16121 if ((prefixes & PREFIX_DATA) == 0)
16122 segment = ((start_pc + (codep - start_codep))
16123 & ~((bfd_vma) 0xffff));
16124 }
16125 if (address_mode != mode_64bit
16126 || (isa64 == amd64 && !(rex & REX_W)))
16127 used_prefixes |= (prefixes & PREFIX_DATA);
16128 break;
16129 default:
16130 oappend (INTERNAL_DISASSEMBLER_ERROR);
16131 return;
16132 }
16133 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16134 set_op (disp, 0);
16135 print_operand_value (scratchbuf, 1, disp);
16136 oappend (scratchbuf);
16137}
16138
16139static void
16140OP_SEG (int bytemode, int sizeflag)
16141{
16142 if (bytemode == w_mode)
16143 oappend (names_seg[modrm.reg]);
16144 else
16145 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16146}
16147
16148static void
16149OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16150{
16151 int seg, offset;
16152
16153 if (sizeflag & DFLAG)
16154 {
16155 offset = get32 ();
16156 seg = get16 ();
16157 }
16158 else
16159 {
16160 offset = get16 ();
16161 seg = get16 ();
16162 }
16163 used_prefixes |= (prefixes & PREFIX_DATA);
16164 if (intel_syntax)
16165 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16166 else
16167 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16168 oappend (scratchbuf);
16169}
16170
16171static void
16172OP_OFF (int bytemode, int sizeflag)
16173{
16174 bfd_vma off;
16175
16176 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16177 intel_operand_size (bytemode, sizeflag);
16178 append_seg ();
16179
16180 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16181 off = get32 ();
16182 else
16183 off = get16 ();
16184
16185 if (intel_syntax)
16186 {
16187 if (!active_seg_prefix)
16188 {
16189 oappend (names_seg[ds_reg - es_reg]);
16190 oappend (":");
16191 }
16192 }
16193 print_operand_value (scratchbuf, 1, off);
16194 oappend (scratchbuf);
16195}
16196
16197static void
16198OP_OFF64 (int bytemode, int sizeflag)
16199{
16200 bfd_vma off;
16201
16202 if (address_mode != mode_64bit
16203 || (prefixes & PREFIX_ADDR))
16204 {
16205 OP_OFF (bytemode, sizeflag);
16206 return;
16207 }
16208
16209 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16210 intel_operand_size (bytemode, sizeflag);
16211 append_seg ();
16212
16213 off = get64 ();
16214
16215 if (intel_syntax)
16216 {
16217 if (!active_seg_prefix)
16218 {
16219 oappend (names_seg[ds_reg - es_reg]);
16220 oappend (":");
16221 }
16222 }
16223 print_operand_value (scratchbuf, 1, off);
16224 oappend (scratchbuf);
16225}
16226
16227static void
16228ptr_reg (int code, int sizeflag)
16229{
16230 const char *s;
16231
16232 *obufp++ = open_char;
16233 used_prefixes |= (prefixes & PREFIX_ADDR);
16234 if (address_mode == mode_64bit)
16235 {
16236 if (!(sizeflag & AFLAG))
16237 s = names32[code - eAX_reg];
16238 else
16239 s = names64[code - eAX_reg];
16240 }
16241 else if (sizeflag & AFLAG)
16242 s = names32[code - eAX_reg];
16243 else
16244 s = names16[code - eAX_reg];
16245 oappend (s);
16246 *obufp++ = close_char;
16247 *obufp = 0;
16248}
16249
16250static void
16251OP_ESreg (int code, int sizeflag)
16252{
16253 if (intel_syntax)
16254 {
16255 switch (codep[-1])
16256 {
16257 case 0x6d: /* insw/insl */
16258 intel_operand_size (z_mode, sizeflag);
16259 break;
16260 case 0xa5: /* movsw/movsl/movsq */
16261 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16262 case 0xab: /* stosw/stosl */
16263 case 0xaf: /* scasw/scasl */
16264 intel_operand_size (v_mode, sizeflag);
16265 break;
16266 default:
16267 intel_operand_size (b_mode, sizeflag);
16268 }
16269 }
16270 oappend_maybe_intel ("%es:");
16271 ptr_reg (code, sizeflag);
16272}
16273
16274static void
16275OP_DSreg (int code, int sizeflag)
16276{
16277 if (intel_syntax)
16278 {
16279 switch (codep[-1])
16280 {
16281 case 0x6f: /* outsw/outsl */
16282 intel_operand_size (z_mode, sizeflag);
16283 break;
16284 case 0xa5: /* movsw/movsl/movsq */
16285 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16286 case 0xad: /* lodsw/lodsl/lodsq */
16287 intel_operand_size (v_mode, sizeflag);
16288 break;
16289 default:
16290 intel_operand_size (b_mode, sizeflag);
16291 }
16292 }
16293 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16294 default segment register DS is printed. */
16295 if (!active_seg_prefix)
16296 active_seg_prefix = PREFIX_DS;
16297 append_seg ();
16298 ptr_reg (code, sizeflag);
16299}
16300
16301static void
16302OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16303{
16304 int add;
16305 if (rex & REX_R)
16306 {
16307 USED_REX (REX_R);
16308 add = 8;
16309 }
16310 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16311 {
16312 all_prefixes[last_lock_prefix] = 0;
16313 used_prefixes |= PREFIX_LOCK;
16314 add = 8;
16315 }
16316 else
16317 add = 0;
16318 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16319 oappend_maybe_intel (scratchbuf);
16320}
16321
16322static void
16323OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16324{
16325 int add;
16326 USED_REX (REX_R);
16327 if (rex & REX_R)
16328 add = 8;
16329 else
16330 add = 0;
16331 if (intel_syntax)
16332 sprintf (scratchbuf, "db%d", modrm.reg + add);
16333 else
16334 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16335 oappend (scratchbuf);
16336}
16337
16338static void
16339OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16340{
16341 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16342 oappend_maybe_intel (scratchbuf);
16343}
16344
16345static void
16346OP_R (int bytemode, int sizeflag)
16347{
16348 /* Skip mod/rm byte. */
16349 MODRM_CHECK;
16350 codep++;
16351 OP_E_register (bytemode, sizeflag);
16352}
16353
16354static void
16355OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16356{
16357 int reg = modrm.reg;
16358 const char **names;
16359
16360 used_prefixes |= (prefixes & PREFIX_DATA);
16361 if (prefixes & PREFIX_DATA)
16362 {
16363 names = names_xmm;
16364 USED_REX (REX_R);
16365 if (rex & REX_R)
16366 reg += 8;
16367 }
16368 else
16369 names = names_mm;
16370 oappend (names[reg]);
16371}
16372
16373static void
16374OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16375{
16376 int reg = modrm.reg;
16377 const char **names;
16378
16379 USED_REX (REX_R);
16380 if (rex & REX_R)
16381 reg += 8;
16382 if (vex.evex)
16383 {
16384 if (!vex.r)
16385 reg += 16;
16386 }
16387
16388 if (need_vex
16389 && bytemode != xmm_mode
16390 && bytemode != xmmq_mode
16391 && bytemode != evex_half_bcst_xmmq_mode
16392 && bytemode != ymm_mode
16393 && bytemode != scalar_mode)
16394 {
16395 switch (vex.length)
16396 {
16397 case 128:
16398 names = names_xmm;
16399 break;
16400 case 256:
16401 if (vex.w
16402 || (bytemode != vex_vsib_q_w_dq_mode
16403 && bytemode != vex_vsib_q_w_d_mode))
16404 names = names_ymm;
16405 else
16406 names = names_xmm;
16407 break;
16408 case 512:
16409 names = names_zmm;
16410 break;
16411 default:
16412 abort ();
16413 }
16414 }
16415 else if (bytemode == xmmq_mode
16416 || bytemode == evex_half_bcst_xmmq_mode)
16417 {
16418 switch (vex.length)
16419 {
16420 case 128:
16421 case 256:
16422 names = names_xmm;
16423 break;
16424 case 512:
16425 names = names_ymm;
16426 break;
16427 default:
16428 abort ();
16429 }
16430 }
16431 else if (bytemode == ymm_mode)
16432 names = names_ymm;
16433 else
16434 names = names_xmm;
16435 oappend (names[reg]);
16436}
16437
16438static void
16439OP_EM (int bytemode, int sizeflag)
16440{
16441 int reg;
16442 const char **names;
16443
16444 if (modrm.mod != 3)
16445 {
16446 if (intel_syntax
16447 && (bytemode == v_mode || bytemode == v_swap_mode))
16448 {
16449 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16450 used_prefixes |= (prefixes & PREFIX_DATA);
16451 }
16452 OP_E (bytemode, sizeflag);
16453 return;
16454 }
16455
16456 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16457 swap_operand ();
16458
16459 /* Skip mod/rm byte. */
16460 MODRM_CHECK;
16461 codep++;
16462 used_prefixes |= (prefixes & PREFIX_DATA);
16463 reg = modrm.rm;
16464 if (prefixes & PREFIX_DATA)
16465 {
16466 names = names_xmm;
16467 USED_REX (REX_B);
16468 if (rex & REX_B)
16469 reg += 8;
16470 }
16471 else
16472 names = names_mm;
16473 oappend (names[reg]);
16474}
16475
16476/* cvt* are the only instructions in sse2 which have
16477 both SSE and MMX operands and also have 0x66 prefix
16478 in their opcode. 0x66 was originally used to differentiate
16479 between SSE and MMX instruction(operands). So we have to handle the
16480 cvt* separately using OP_EMC and OP_MXC */
16481static void
16482OP_EMC (int bytemode, int sizeflag)
16483{
16484 if (modrm.mod != 3)
16485 {
16486 if (intel_syntax && bytemode == v_mode)
16487 {
16488 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16489 used_prefixes |= (prefixes & PREFIX_DATA);
16490 }
16491 OP_E (bytemode, sizeflag);
16492 return;
16493 }
16494
16495 /* Skip mod/rm byte. */
16496 MODRM_CHECK;
16497 codep++;
16498 used_prefixes |= (prefixes & PREFIX_DATA);
16499 oappend (names_mm[modrm.rm]);
16500}
16501
16502static void
16503OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16504{
16505 used_prefixes |= (prefixes & PREFIX_DATA);
16506 oappend (names_mm[modrm.reg]);
16507}
16508
16509static void
16510OP_EX (int bytemode, int sizeflag)
16511{
16512 int reg;
16513 const char **names;
16514
16515 /* Skip mod/rm byte. */
16516 MODRM_CHECK;
16517 codep++;
16518
16519 if (modrm.mod != 3)
16520 {
16521 OP_E_memory (bytemode, sizeflag);
16522 return;
16523 }
16524
16525 reg = modrm.rm;
16526 USED_REX (REX_B);
16527 if (rex & REX_B)
16528 reg += 8;
16529 if (vex.evex)
16530 {
16531 USED_REX (REX_X);
16532 if ((rex & REX_X))
16533 reg += 16;
16534 }
16535
16536 if ((sizeflag & SUFFIX_ALWAYS)
16537 && (bytemode == x_swap_mode
16538 || bytemode == d_swap_mode
16539 || bytemode == d_scalar_swap_mode
16540 || bytemode == q_swap_mode
16541 || bytemode == q_scalar_swap_mode))
16542 swap_operand ();
16543
16544 if (need_vex
16545 && bytemode != xmm_mode
16546 && bytemode != xmmdw_mode
16547 && bytemode != xmmqd_mode
16548 && bytemode != xmm_mb_mode
16549 && bytemode != xmm_mw_mode
16550 && bytemode != xmm_md_mode
16551 && bytemode != xmm_mq_mode
16552 && bytemode != xmm_mdq_mode
16553 && bytemode != xmmq_mode
16554 && bytemode != evex_half_bcst_xmmq_mode
16555 && bytemode != ymm_mode
16556 && bytemode != d_scalar_mode
16557 && bytemode != d_scalar_swap_mode
16558 && bytemode != q_scalar_mode
16559 && bytemode != q_scalar_swap_mode
16560 && bytemode != vex_scalar_w_dq_mode)
16561 {
16562 switch (vex.length)
16563 {
16564 case 128:
16565 names = names_xmm;
16566 break;
16567 case 256:
16568 names = names_ymm;
16569 break;
16570 case 512:
16571 names = names_zmm;
16572 break;
16573 default:
16574 abort ();
16575 }
16576 }
16577 else if (bytemode == xmmq_mode
16578 || bytemode == evex_half_bcst_xmmq_mode)
16579 {
16580 switch (vex.length)
16581 {
16582 case 128:
16583 case 256:
16584 names = names_xmm;
16585 break;
16586 case 512:
16587 names = names_ymm;
16588 break;
16589 default:
16590 abort ();
16591 }
16592 }
16593 else if (bytemode == ymm_mode)
16594 names = names_ymm;
16595 else
16596 names = names_xmm;
16597 oappend (names[reg]);
16598}
16599
16600static void
16601OP_MS (int bytemode, int sizeflag)
16602{
16603 if (modrm.mod == 3)
16604 OP_EM (bytemode, sizeflag);
16605 else
16606 BadOp ();
16607}
16608
16609static void
16610OP_XS (int bytemode, int sizeflag)
16611{
16612 if (modrm.mod == 3)
16613 OP_EX (bytemode, sizeflag);
16614 else
16615 BadOp ();
16616}
16617
16618static void
16619OP_M (int bytemode, int sizeflag)
16620{
16621 if (modrm.mod == 3)
16622 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16623 BadOp ();
16624 else
16625 OP_E (bytemode, sizeflag);
16626}
16627
16628static void
16629OP_0f07 (int bytemode, int sizeflag)
16630{
16631 if (modrm.mod != 3 || modrm.rm != 0)
16632 BadOp ();
16633 else
16634 OP_E (bytemode, sizeflag);
16635}
16636
16637/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16638 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16639
16640static void
16641NOP_Fixup1 (int bytemode, int sizeflag)
16642{
16643 if ((prefixes & PREFIX_DATA) != 0
16644 || (rex != 0
16645 && rex != 0x48
16646 && address_mode == mode_64bit))
16647 OP_REG (bytemode, sizeflag);
16648 else
16649 strcpy (obuf, "nop");
16650}
16651
16652static void
16653NOP_Fixup2 (int bytemode, int sizeflag)
16654{
16655 if ((prefixes & PREFIX_DATA) != 0
16656 || (rex != 0
16657 && rex != 0x48
16658 && address_mode == mode_64bit))
16659 OP_IMREG (bytemode, sizeflag);
16660}
16661
16662static const char *const Suffix3DNow[] = {
16663/* 00 */ NULL, NULL, NULL, NULL,
16664/* 04 */ NULL, NULL, NULL, NULL,
16665/* 08 */ NULL, NULL, NULL, NULL,
16666/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16667/* 10 */ NULL, NULL, NULL, NULL,
16668/* 14 */ NULL, NULL, NULL, NULL,
16669/* 18 */ NULL, NULL, NULL, NULL,
16670/* 1C */ "pf2iw", "pf2id", NULL, NULL,
16671/* 20 */ NULL, NULL, NULL, NULL,
16672/* 24 */ NULL, NULL, NULL, NULL,
16673/* 28 */ NULL, NULL, NULL, NULL,
16674/* 2C */ NULL, NULL, NULL, NULL,
16675/* 30 */ NULL, NULL, NULL, NULL,
16676/* 34 */ NULL, NULL, NULL, NULL,
16677/* 38 */ NULL, NULL, NULL, NULL,
16678/* 3C */ NULL, NULL, NULL, NULL,
16679/* 40 */ NULL, NULL, NULL, NULL,
16680/* 44 */ NULL, NULL, NULL, NULL,
16681/* 48 */ NULL, NULL, NULL, NULL,
16682/* 4C */ NULL, NULL, NULL, NULL,
16683/* 50 */ NULL, NULL, NULL, NULL,
16684/* 54 */ NULL, NULL, NULL, NULL,
16685/* 58 */ NULL, NULL, NULL, NULL,
16686/* 5C */ NULL, NULL, NULL, NULL,
16687/* 60 */ NULL, NULL, NULL, NULL,
16688/* 64 */ NULL, NULL, NULL, NULL,
16689/* 68 */ NULL, NULL, NULL, NULL,
16690/* 6C */ NULL, NULL, NULL, NULL,
16691/* 70 */ NULL, NULL, NULL, NULL,
16692/* 74 */ NULL, NULL, NULL, NULL,
16693/* 78 */ NULL, NULL, NULL, NULL,
16694/* 7C */ NULL, NULL, NULL, NULL,
16695/* 80 */ NULL, NULL, NULL, NULL,
16696/* 84 */ NULL, NULL, NULL, NULL,
16697/* 88 */ NULL, NULL, "pfnacc", NULL,
16698/* 8C */ NULL, NULL, "pfpnacc", NULL,
16699/* 90 */ "pfcmpge", NULL, NULL, NULL,
16700/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16701/* 98 */ NULL, NULL, "pfsub", NULL,
16702/* 9C */ NULL, NULL, "pfadd", NULL,
16703/* A0 */ "pfcmpgt", NULL, NULL, NULL,
16704/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16705/* A8 */ NULL, NULL, "pfsubr", NULL,
16706/* AC */ NULL, NULL, "pfacc", NULL,
16707/* B0 */ "pfcmpeq", NULL, NULL, NULL,
16708/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16709/* B8 */ NULL, NULL, NULL, "pswapd",
16710/* BC */ NULL, NULL, NULL, "pavgusb",
16711/* C0 */ NULL, NULL, NULL, NULL,
16712/* C4 */ NULL, NULL, NULL, NULL,
16713/* C8 */ NULL, NULL, NULL, NULL,
16714/* CC */ NULL, NULL, NULL, NULL,
16715/* D0 */ NULL, NULL, NULL, NULL,
16716/* D4 */ NULL, NULL, NULL, NULL,
16717/* D8 */ NULL, NULL, NULL, NULL,
16718/* DC */ NULL, NULL, NULL, NULL,
16719/* E0 */ NULL, NULL, NULL, NULL,
16720/* E4 */ NULL, NULL, NULL, NULL,
16721/* E8 */ NULL, NULL, NULL, NULL,
16722/* EC */ NULL, NULL, NULL, NULL,
16723/* F0 */ NULL, NULL, NULL, NULL,
16724/* F4 */ NULL, NULL, NULL, NULL,
16725/* F8 */ NULL, NULL, NULL, NULL,
16726/* FC */ NULL, NULL, NULL, NULL,
16727};
16728
16729static void
16730OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16731{
16732 const char *mnemonic;
16733
16734 FETCH_DATA (the_info, codep + 1);
16735 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16736 place where an 8-bit immediate would normally go. ie. the last
16737 byte of the instruction. */
16738 obufp = mnemonicendp;
16739 mnemonic = Suffix3DNow[*codep++ & 0xff];
16740 if (mnemonic)
16741 oappend (mnemonic);
16742 else
16743 {
16744 /* Since a variable sized modrm/sib chunk is between the start
16745 of the opcode (0x0f0f) and the opcode suffix, we need to do
16746 all the modrm processing first, and don't know until now that
16747 we have a bad opcode. This necessitates some cleaning up. */
16748 op_out[0][0] = '\0';
16749 op_out[1][0] = '\0';
16750 BadOp ();
16751 }
16752 mnemonicendp = obufp;
16753}
16754
16755static struct op simd_cmp_op[] =
16756{
16757 { STRING_COMMA_LEN ("eq") },
16758 { STRING_COMMA_LEN ("lt") },
16759 { STRING_COMMA_LEN ("le") },
16760 { STRING_COMMA_LEN ("unord") },
16761 { STRING_COMMA_LEN ("neq") },
16762 { STRING_COMMA_LEN ("nlt") },
16763 { STRING_COMMA_LEN ("nle") },
16764 { STRING_COMMA_LEN ("ord") }
16765};
16766
16767static void
16768CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16769{
16770 unsigned int cmp_type;
16771
16772 FETCH_DATA (the_info, codep + 1);
16773 cmp_type = *codep++ & 0xff;
16774 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16775 {
16776 char suffix [3];
16777 char *p = mnemonicendp - 2;
16778 suffix[0] = p[0];
16779 suffix[1] = p[1];
16780 suffix[2] = '\0';
16781 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16782 mnemonicendp += simd_cmp_op[cmp_type].len;
16783 }
16784 else
16785 {
16786 /* We have a reserved extension byte. Output it directly. */
16787 scratchbuf[0] = '$';
16788 print_operand_value (scratchbuf + 1, 1, cmp_type);
16789 oappend_maybe_intel (scratchbuf);
16790 scratchbuf[0] = '\0';
16791 }
16792}
16793
16794static void
16795OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16796 int sizeflag ATTRIBUTE_UNUSED)
16797{
16798 /* mwaitx %eax,%ecx,%ebx */
16799 if (!intel_syntax)
16800 {
16801 const char **names = (address_mode == mode_64bit
16802 ? names64 : names32);
16803 strcpy (op_out[0], names[0]);
16804 strcpy (op_out[1], names[1]);
16805 strcpy (op_out[2], names[3]);
16806 two_source_ops = 1;
16807 }
16808 /* Skip mod/rm byte. */
16809 MODRM_CHECK;
16810 codep++;
16811}
16812
16813static void
16814OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16815 int sizeflag ATTRIBUTE_UNUSED)
16816{
16817 /* mwait %eax,%ecx */
16818 if (!intel_syntax)
16819 {
16820 const char **names = (address_mode == mode_64bit
16821 ? names64 : names32);
16822 strcpy (op_out[0], names[0]);
16823 strcpy (op_out[1], names[1]);
16824 two_source_ops = 1;
16825 }
16826 /* Skip mod/rm byte. */
16827 MODRM_CHECK;
16828 codep++;
16829}
16830
16831static void
16832OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16833 int sizeflag ATTRIBUTE_UNUSED)
16834{
16835 /* monitor %eax,%ecx,%edx" */
16836 if (!intel_syntax)
16837 {
16838 const char **op1_names;
16839 const char **names = (address_mode == mode_64bit
16840 ? names64 : names32);
16841
16842 if (!(prefixes & PREFIX_ADDR))
16843 op1_names = (address_mode == mode_16bit
16844 ? names16 : names);
16845 else
16846 {
16847 /* Remove "addr16/addr32". */
16848 all_prefixes[last_addr_prefix] = 0;
16849 op1_names = (address_mode != mode_32bit
16850 ? names32 : names16);
16851 used_prefixes |= PREFIX_ADDR;
16852 }
16853 strcpy (op_out[0], op1_names[0]);
16854 strcpy (op_out[1], names[1]);
16855 strcpy (op_out[2], names[2]);
16856 two_source_ops = 1;
16857 }
16858 /* Skip mod/rm byte. */
16859 MODRM_CHECK;
16860 codep++;
16861}
16862
16863static void
16864BadOp (void)
16865{
16866 /* Throw away prefixes and 1st. opcode byte. */
16867 codep = insn_codep + 1;
16868 oappend ("(bad)");
16869}
16870
16871static void
16872REP_Fixup (int bytemode, int sizeflag)
16873{
16874 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16875 lods and stos. */
16876 if (prefixes & PREFIX_REPZ)
16877 all_prefixes[last_repz_prefix] = REP_PREFIX;
16878
16879 switch (bytemode)
16880 {
16881 case al_reg:
16882 case eAX_reg:
16883 case indir_dx_reg:
16884 OP_IMREG (bytemode, sizeflag);
16885 break;
16886 case eDI_reg:
16887 OP_ESreg (bytemode, sizeflag);
16888 break;
16889 case eSI_reg:
16890 OP_DSreg (bytemode, sizeflag);
16891 break;
16892 default:
16893 abort ();
16894 break;
16895 }
16896}
16897
16898/* For BND-prefixed instructions 0xF2 prefix should be displayed as
16899 "bnd". */
16900
16901static void
16902BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16903{
16904 if (prefixes & PREFIX_REPNZ)
16905 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16906}
16907
16908/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16909 "notrack". */
16910
16911static void
16912NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16913 int sizeflag ATTRIBUTE_UNUSED)
16914{
16915 if (active_seg_prefix == PREFIX_DS
16916 && (address_mode != mode_64bit || last_data_prefix < 0))
16917 {
16918 /* NOTRACK prefix is only valid on indirect branch instructions.
16919 NB: DATA prefix is unsupported for Intel64. */
16920 active_seg_prefix = 0;
16921 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16922 }
16923}
16924
16925/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16926 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16927 */
16928
16929static void
16930HLE_Fixup1 (int bytemode, int sizeflag)
16931{
16932 if (modrm.mod != 3
16933 && (prefixes & PREFIX_LOCK) != 0)
16934 {
16935 if (prefixes & PREFIX_REPZ)
16936 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16937 if (prefixes & PREFIX_REPNZ)
16938 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16939 }
16940
16941 OP_E (bytemode, sizeflag);
16942}
16943
16944/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16945 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16946 */
16947
16948static void
16949HLE_Fixup2 (int bytemode, int sizeflag)
16950{
16951 if (modrm.mod != 3)
16952 {
16953 if (prefixes & PREFIX_REPZ)
16954 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16955 if (prefixes & PREFIX_REPNZ)
16956 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16957 }
16958
16959 OP_E (bytemode, sizeflag);
16960}
16961
16962/* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16963 "xrelease" for memory operand. No check for LOCK prefix. */
16964
16965static void
16966HLE_Fixup3 (int bytemode, int sizeflag)
16967{
16968 if (modrm.mod != 3
16969 && last_repz_prefix > last_repnz_prefix
16970 && (prefixes & PREFIX_REPZ) != 0)
16971 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16972
16973 OP_E (bytemode, sizeflag);
16974}
16975
16976static void
16977CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16978{
16979 USED_REX (REX_W);
16980 if (rex & REX_W)
16981 {
16982 /* Change cmpxchg8b to cmpxchg16b. */
16983 char *p = mnemonicendp - 2;
16984 mnemonicendp = stpcpy (p, "16b");
16985 bytemode = o_mode;
16986 }
16987 else if ((prefixes & PREFIX_LOCK) != 0)
16988 {
16989 if (prefixes & PREFIX_REPZ)
16990 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16991 if (prefixes & PREFIX_REPNZ)
16992 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16993 }
16994
16995 OP_M (bytemode, sizeflag);
16996}
16997
16998static void
16999XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17000{
17001 const char **names;
17002
17003 if (need_vex)
17004 {
17005 switch (vex.length)
17006 {
17007 case 128:
17008 names = names_xmm;
17009 break;
17010 case 256:
17011 names = names_ymm;
17012 break;
17013 default:
17014 abort ();
17015 }
17016 }
17017 else
17018 names = names_xmm;
17019 oappend (names[reg]);
17020}
17021
17022static void
17023CRC32_Fixup (int bytemode, int sizeflag)
17024{
17025 /* Add proper suffix to "crc32". */
17026 char *p = mnemonicendp;
17027
17028 switch (bytemode)
17029 {
17030 case b_mode:
17031 if (intel_syntax)
17032 goto skip;
17033
17034 *p++ = 'b';
17035 break;
17036 case v_mode:
17037 if (intel_syntax)
17038 goto skip;
17039
17040 USED_REX (REX_W);
17041 if (rex & REX_W)
17042 *p++ = 'q';
17043 else
17044 {
17045 if (sizeflag & DFLAG)
17046 *p++ = 'l';
17047 else
17048 *p++ = 'w';
17049 used_prefixes |= (prefixes & PREFIX_DATA);
17050 }
17051 break;
17052 default:
17053 oappend (INTERNAL_DISASSEMBLER_ERROR);
17054 break;
17055 }
17056 mnemonicendp = p;
17057 *p = '\0';
17058
17059skip:
17060 if (modrm.mod == 3)
17061 {
17062 int add;
17063
17064 /* Skip mod/rm byte. */
17065 MODRM_CHECK;
17066 codep++;
17067
17068 USED_REX (REX_B);
17069 add = (rex & REX_B) ? 8 : 0;
17070 if (bytemode == b_mode)
17071 {
17072 USED_REX (0);
17073 if (rex)
17074 oappend (names8rex[modrm.rm + add]);
17075 else
17076 oappend (names8[modrm.rm + add]);
17077 }
17078 else
17079 {
17080 USED_REX (REX_W);
17081 if (rex & REX_W)
17082 oappend (names64[modrm.rm + add]);
17083 else if ((prefixes & PREFIX_DATA))
17084 oappend (names16[modrm.rm + add]);
17085 else
17086 oappend (names32[modrm.rm + add]);
17087 }
17088 }
17089 else
17090 OP_E (bytemode, sizeflag);
17091}
17092
17093static void
17094FXSAVE_Fixup (int bytemode, int sizeflag)
17095{
17096 /* Add proper suffix to "fxsave" and "fxrstor". */
17097 USED_REX (REX_W);
17098 if (rex & REX_W)
17099 {
17100 char *p = mnemonicendp;
17101 *p++ = '6';
17102 *p++ = '4';
17103 *p = '\0';
17104 mnemonicendp = p;
17105 }
17106 OP_M (bytemode, sizeflag);
17107}
17108
17109static void
17110PCMPESTR_Fixup (int bytemode, int sizeflag)
17111{
17112 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17113 if (!intel_syntax)
17114 {
17115 char *p = mnemonicendp;
17116
17117 USED_REX (REX_W);
17118 if (rex & REX_W)
17119 *p++ = 'q';
17120 else if (sizeflag & SUFFIX_ALWAYS)
17121 *p++ = 'l';
17122
17123 *p = '\0';
17124 mnemonicendp = p;
17125 }
17126
17127 OP_EX (bytemode, sizeflag);
17128}
17129
17130/* Display the destination register operand for instructions with
17131 VEX. */
17132
17133static void
17134OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17135{
17136 int reg;
17137 const char **names;
17138
17139 if (!need_vex)
17140 abort ();
17141
17142 if (!need_vex_reg)
17143 return;
17144
17145 reg = vex.register_specifier;
17146 if (vex.evex)
17147 {
17148 if (!vex.v)
17149 reg += 16;
17150 }
17151
17152 if (bytemode == vex_scalar_mode)
17153 {
17154 oappend (names_xmm[reg]);
17155 return;
17156 }
17157
17158 switch (vex.length)
17159 {
17160 case 128:
17161 switch (bytemode)
17162 {
17163 case vex_mode:
17164 case vex128_mode:
17165 case vex_vsib_q_w_dq_mode:
17166 case vex_vsib_q_w_d_mode:
17167 names = names_xmm;
17168 break;
17169 case dq_mode:
17170 if (vex.w)
17171 names = names64;
17172 else
17173 names = names32;
17174 break;
17175 case mask_bd_mode:
17176 case mask_mode:
17177 if (reg > 0x7)
17178 {
17179 oappend ("(bad)");
17180 return;
17181 }
17182 names = names_mask;
17183 break;
17184 default:
17185 abort ();
17186 return;
17187 }
17188 break;
17189 case 256:
17190 switch (bytemode)
17191 {
17192 case vex_mode:
17193 case vex256_mode:
17194 names = names_ymm;
17195 break;
17196 case vex_vsib_q_w_dq_mode:
17197 case vex_vsib_q_w_d_mode:
17198 names = vex.w ? names_ymm : names_xmm;
17199 break;
17200 case mask_bd_mode:
17201 case mask_mode:
17202 if (reg > 0x7)
17203 {
17204 oappend ("(bad)");
17205 return;
17206 }
17207 names = names_mask;
17208 break;
17209 default:
17210 /* See PR binutils/20893 for a reproducer. */
17211 oappend ("(bad)");
17212 return;
17213 }
17214 break;
17215 case 512:
17216 names = names_zmm;
17217 break;
17218 default:
17219 abort ();
17220 break;
17221 }
17222 oappend (names[reg]);
17223}
17224
17225/* Get the VEX immediate byte without moving codep. */
17226
17227static unsigned char
17228get_vex_imm8 (int sizeflag, int opnum)
17229{
17230 int bytes_before_imm = 0;
17231
17232 if (modrm.mod != 3)
17233 {
17234 /* There are SIB/displacement bytes. */
17235 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17236 {
17237 /* 32/64 bit address mode */
17238 int base = modrm.rm;
17239
17240 /* Check SIB byte. */
17241 if (base == 4)
17242 {
17243 FETCH_DATA (the_info, codep + 1);
17244 base = *codep & 7;
17245 /* When decoding the third source, don't increase
17246 bytes_before_imm as this has already been incremented
17247 by one in OP_E_memory while decoding the second
17248 source operand. */
17249 if (opnum == 0)
17250 bytes_before_imm++;
17251 }
17252
17253 /* Don't increase bytes_before_imm when decoding the third source,
17254 it has already been incremented by OP_E_memory while decoding
17255 the second source operand. */
17256 if (opnum == 0)
17257 {
17258 switch (modrm.mod)
17259 {
17260 case 0:
17261 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17262 SIB == 5, there is a 4 byte displacement. */
17263 if (base != 5)
17264 /* No displacement. */
17265 break;
17266 /* Fall through. */
17267 case 2:
17268 /* 4 byte displacement. */
17269 bytes_before_imm += 4;
17270 break;
17271 case 1:
17272 /* 1 byte displacement. */
17273 bytes_before_imm++;
17274 break;
17275 }
17276 }
17277 }
17278 else
17279 {
17280 /* 16 bit address mode */
17281 /* Don't increase bytes_before_imm when decoding the third source,
17282 it has already been incremented by OP_E_memory while decoding
17283 the second source operand. */
17284 if (opnum == 0)
17285 {
17286 switch (modrm.mod)
17287 {
17288 case 0:
17289 /* When modrm.rm == 6, there is a 2 byte displacement. */
17290 if (modrm.rm != 6)
17291 /* No displacement. */
17292 break;
17293 /* Fall through. */
17294 case 2:
17295 /* 2 byte displacement. */
17296 bytes_before_imm += 2;
17297 break;
17298 case 1:
17299 /* 1 byte displacement: when decoding the third source,
17300 don't increase bytes_before_imm as this has already
17301 been incremented by one in OP_E_memory while decoding
17302 the second source operand. */
17303 if (opnum == 0)
17304 bytes_before_imm++;
17305
17306 break;
17307 }
17308 }
17309 }
17310 }
17311
17312 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17313 return codep [bytes_before_imm];
17314}
17315
17316static void
17317OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17318{
17319 const char **names;
17320
17321 if (reg == -1 && modrm.mod != 3)
17322 {
17323 OP_E_memory (bytemode, sizeflag);
17324 return;
17325 }
17326 else
17327 {
17328 if (reg == -1)
17329 {
17330 reg = modrm.rm;
17331 USED_REX (REX_B);
17332 if (rex & REX_B)
17333 reg += 8;
17334 }
17335 else if (reg > 7 && address_mode != mode_64bit)
17336 BadOp ();
17337 }
17338
17339 switch (vex.length)
17340 {
17341 case 128:
17342 names = names_xmm;
17343 break;
17344 case 256:
17345 names = names_ymm;
17346 break;
17347 default:
17348 abort ();
17349 }
17350 oappend (names[reg]);
17351}
17352
17353static void
17354OP_EX_VexImmW (int bytemode, int sizeflag)
17355{
17356 int reg = -1;
17357 static unsigned char vex_imm8;
17358
17359 if (vex_w_done == 0)
17360 {
17361 vex_w_done = 1;
17362
17363 /* Skip mod/rm byte. */
17364 MODRM_CHECK;
17365 codep++;
17366
17367 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17368
17369 if (vex.w)
17370 reg = vex_imm8 >> 4;
17371
17372 OP_EX_VexReg (bytemode, sizeflag, reg);
17373 }
17374 else if (vex_w_done == 1)
17375 {
17376 vex_w_done = 2;
17377
17378 if (!vex.w)
17379 reg = vex_imm8 >> 4;
17380
17381 OP_EX_VexReg (bytemode, sizeflag, reg);
17382 }
17383 else
17384 {
17385 /* Output the imm8 directly. */
17386 scratchbuf[0] = '$';
17387 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17388 oappend_maybe_intel (scratchbuf);
17389 scratchbuf[0] = '\0';
17390 codep++;
17391 }
17392}
17393
17394static void
17395OP_Vex_2src (int bytemode, int sizeflag)
17396{
17397 if (modrm.mod == 3)
17398 {
17399 int reg = modrm.rm;
17400 USED_REX (REX_B);
17401 if (rex & REX_B)
17402 reg += 8;
17403 oappend (names_xmm[reg]);
17404 }
17405 else
17406 {
17407 if (intel_syntax
17408 && (bytemode == v_mode || bytemode == v_swap_mode))
17409 {
17410 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17411 used_prefixes |= (prefixes & PREFIX_DATA);
17412 }
17413 OP_E (bytemode, sizeflag);
17414 }
17415}
17416
17417static void
17418OP_Vex_2src_1 (int bytemode, int sizeflag)
17419{
17420 if (modrm.mod == 3)
17421 {
17422 /* Skip mod/rm byte. */
17423 MODRM_CHECK;
17424 codep++;
17425 }
17426
17427 if (vex.w)
17428 oappend (names_xmm[vex.register_specifier]);
17429 else
17430 OP_Vex_2src (bytemode, sizeflag);
17431}
17432
17433static void
17434OP_Vex_2src_2 (int bytemode, int sizeflag)
17435{
17436 if (vex.w)
17437 OP_Vex_2src (bytemode, sizeflag);
17438 else
17439 oappend (names_xmm[vex.register_specifier]);
17440}
17441
17442static void
17443OP_EX_VexW (int bytemode, int sizeflag)
17444{
17445 int reg = -1;
17446
17447 if (!vex_w_done)
17448 {
17449 vex_w_done = 1;
17450
17451 /* Skip mod/rm byte. */
17452 MODRM_CHECK;
17453 codep++;
17454
17455 if (vex.w)
17456 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17457 }
17458 else
17459 {
17460 if (!vex.w)
17461 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17462 }
17463
17464 OP_EX_VexReg (bytemode, sizeflag, reg);
17465}
17466
17467static void
17468VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17469 int sizeflag ATTRIBUTE_UNUSED)
17470{
17471 /* Skip the immediate byte and check for invalid bits. */
17472 FETCH_DATA (the_info, codep + 1);
17473 if (*codep++ & 0xf)
17474 BadOp ();
17475}
17476
17477static void
17478OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17479{
17480 int reg;
17481 const char **names;
17482
17483 FETCH_DATA (the_info, codep + 1);
17484 reg = *codep++;
17485
17486 if (bytemode != x_mode)
17487 abort ();
17488
17489 if (reg & 0xf)
17490 BadOp ();
17491
17492 reg >>= 4;
17493 if (reg > 7 && address_mode != mode_64bit)
17494 BadOp ();
17495
17496 switch (vex.length)
17497 {
17498 case 128:
17499 names = names_xmm;
17500 break;
17501 case 256:
17502 names = names_ymm;
17503 break;
17504 default:
17505 abort ();
17506 }
17507 oappend (names[reg]);
17508}
17509
17510static void
17511OP_XMM_VexW (int bytemode, int sizeflag)
17512{
17513 /* Turn off the REX.W bit since it is used for swapping operands
17514 now. */
17515 rex &= ~REX_W;
17516 OP_XMM (bytemode, sizeflag);
17517}
17518
17519static void
17520OP_EX_Vex (int bytemode, int sizeflag)
17521{
17522 if (modrm.mod != 3)
17523 {
17524 if (vex.register_specifier != 0)
17525 BadOp ();
17526 need_vex_reg = 0;
17527 }
17528 OP_EX (bytemode, sizeflag);
17529}
17530
17531static void
17532OP_XMM_Vex (int bytemode, int sizeflag)
17533{
17534 if (modrm.mod != 3)
17535 {
17536 if (vex.register_specifier != 0)
17537 BadOp ();
17538 need_vex_reg = 0;
17539 }
17540 OP_XMM (bytemode, sizeflag);
17541}
17542
17543static void
17544VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17545{
17546 switch (vex.length)
17547 {
17548 case 128:
17549 mnemonicendp = stpcpy (obuf, "vzeroupper");
17550 break;
17551 case 256:
17552 mnemonicendp = stpcpy (obuf, "vzeroall");
17553 break;
17554 default:
17555 abort ();
17556 }
17557}
17558
17559static struct op vex_cmp_op[] =
17560{
17561 { STRING_COMMA_LEN ("eq") },
17562 { STRING_COMMA_LEN ("lt") },
17563 { STRING_COMMA_LEN ("le") },
17564 { STRING_COMMA_LEN ("unord") },
17565 { STRING_COMMA_LEN ("neq") },
17566 { STRING_COMMA_LEN ("nlt") },
17567 { STRING_COMMA_LEN ("nle") },
17568 { STRING_COMMA_LEN ("ord") },
17569 { STRING_COMMA_LEN ("eq_uq") },
17570 { STRING_COMMA_LEN ("nge") },
17571 { STRING_COMMA_LEN ("ngt") },
17572 { STRING_COMMA_LEN ("false") },
17573 { STRING_COMMA_LEN ("neq_oq") },
17574 { STRING_COMMA_LEN ("ge") },
17575 { STRING_COMMA_LEN ("gt") },
17576 { STRING_COMMA_LEN ("true") },
17577 { STRING_COMMA_LEN ("eq_os") },
17578 { STRING_COMMA_LEN ("lt_oq") },
17579 { STRING_COMMA_LEN ("le_oq") },
17580 { STRING_COMMA_LEN ("unord_s") },
17581 { STRING_COMMA_LEN ("neq_us") },
17582 { STRING_COMMA_LEN ("nlt_uq") },
17583 { STRING_COMMA_LEN ("nle_uq") },
17584 { STRING_COMMA_LEN ("ord_s") },
17585 { STRING_COMMA_LEN ("eq_us") },
17586 { STRING_COMMA_LEN ("nge_uq") },
17587 { STRING_COMMA_LEN ("ngt_uq") },
17588 { STRING_COMMA_LEN ("false_os") },
17589 { STRING_COMMA_LEN ("neq_os") },
17590 { STRING_COMMA_LEN ("ge_oq") },
17591 { STRING_COMMA_LEN ("gt_oq") },
17592 { STRING_COMMA_LEN ("true_us") },
17593};
17594
17595static void
17596VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17597{
17598 unsigned int cmp_type;
17599
17600 FETCH_DATA (the_info, codep + 1);
17601 cmp_type = *codep++ & 0xff;
17602 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17603 {
17604 char suffix [3];
17605 char *p = mnemonicendp - 2;
17606 suffix[0] = p[0];
17607 suffix[1] = p[1];
17608 suffix[2] = '\0';
17609 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17610 mnemonicendp += vex_cmp_op[cmp_type].len;
17611 }
17612 else
17613 {
17614 /* We have a reserved extension byte. Output it directly. */
17615 scratchbuf[0] = '$';
17616 print_operand_value (scratchbuf + 1, 1, cmp_type);
17617 oappend_maybe_intel (scratchbuf);
17618 scratchbuf[0] = '\0';
17619 }
17620}
17621
17622static void
17623VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17624 int sizeflag ATTRIBUTE_UNUSED)
17625{
17626 unsigned int cmp_type;
17627
17628 if (!vex.evex)
17629 abort ();
17630
17631 FETCH_DATA (the_info, codep + 1);
17632 cmp_type = *codep++ & 0xff;
17633 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17634 If it's the case, print suffix, otherwise - print the immediate. */
17635 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17636 && cmp_type != 3
17637 && cmp_type != 7)
17638 {
17639 char suffix [3];
17640 char *p = mnemonicendp - 2;
17641
17642 /* vpcmp* can have both one- and two-lettered suffix. */
17643 if (p[0] == 'p')
17644 {
17645 p++;
17646 suffix[0] = p[0];
17647 suffix[1] = '\0';
17648 }
17649 else
17650 {
17651 suffix[0] = p[0];
17652 suffix[1] = p[1];
17653 suffix[2] = '\0';
17654 }
17655
17656 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17657 mnemonicendp += simd_cmp_op[cmp_type].len;
17658 }
17659 else
17660 {
17661 /* We have a reserved extension byte. Output it directly. */
17662 scratchbuf[0] = '$';
17663 print_operand_value (scratchbuf + 1, 1, cmp_type);
17664 oappend_maybe_intel (scratchbuf);
17665 scratchbuf[0] = '\0';
17666 }
17667}
17668
17669static const struct op pclmul_op[] =
17670{
17671 { STRING_COMMA_LEN ("lql") },
17672 { STRING_COMMA_LEN ("hql") },
17673 { STRING_COMMA_LEN ("lqh") },
17674 { STRING_COMMA_LEN ("hqh") }
17675};
17676
17677static void
17678PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17679 int sizeflag ATTRIBUTE_UNUSED)
17680{
17681 unsigned int pclmul_type;
17682
17683 FETCH_DATA (the_info, codep + 1);
17684 pclmul_type = *codep++ & 0xff;
17685 switch (pclmul_type)
17686 {
17687 case 0x10:
17688 pclmul_type = 2;
17689 break;
17690 case 0x11:
17691 pclmul_type = 3;
17692 break;
17693 default:
17694 break;
17695 }
17696 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17697 {
17698 char suffix [4];
17699 char *p = mnemonicendp - 3;
17700 suffix[0] = p[0];
17701 suffix[1] = p[1];
17702 suffix[2] = p[2];
17703 suffix[3] = '\0';
17704 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17705 mnemonicendp += pclmul_op[pclmul_type].len;
17706 }
17707 else
17708 {
17709 /* We have a reserved extension byte. Output it directly. */
17710 scratchbuf[0] = '$';
17711 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17712 oappend_maybe_intel (scratchbuf);
17713 scratchbuf[0] = '\0';
17714 }
17715}
17716
17717static void
17718MOVBE_Fixup (int bytemode, int sizeflag)
17719{
17720 /* Add proper suffix to "movbe". */
17721 char *p = mnemonicendp;
17722
17723 switch (bytemode)
17724 {
17725 case v_mode:
17726 if (intel_syntax)
17727 goto skip;
17728
17729 USED_REX (REX_W);
17730 if (sizeflag & SUFFIX_ALWAYS)
17731 {
17732 if (rex & REX_W)
17733 *p++ = 'q';
17734 else
17735 {
17736 if (sizeflag & DFLAG)
17737 *p++ = 'l';
17738 else
17739 *p++ = 'w';
17740 used_prefixes |= (prefixes & PREFIX_DATA);
17741 }
17742 }
17743 break;
17744 default:
17745 oappend (INTERNAL_DISASSEMBLER_ERROR);
17746 break;
17747 }
17748 mnemonicendp = p;
17749 *p = '\0';
17750
17751skip:
17752 OP_M (bytemode, sizeflag);
17753}
17754
17755static void
17756OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17757{
17758 int reg;
17759 const char **names;
17760
17761 /* Skip mod/rm byte. */
17762 MODRM_CHECK;
17763 codep++;
17764
17765 if (vex.w)
17766 names = names64;
17767 else
17768 names = names32;
17769
17770 reg = modrm.rm;
17771 USED_REX (REX_B);
17772 if (rex & REX_B)
17773 reg += 8;
17774
17775 oappend (names[reg]);
17776}
17777
17778static void
17779OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17780{
17781 const char **names;
17782
17783 if (vex.w)
17784 names = names64;
17785 else
17786 names = names32;
17787
17788 oappend (names[vex.register_specifier]);
17789}
17790
17791static void
17792OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17793{
17794 if (!vex.evex
17795 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17796 abort ();
17797
17798 USED_REX (REX_R);
17799 if ((rex & REX_R) != 0 || !vex.r)
17800 {
17801 BadOp ();
17802 return;
17803 }
17804
17805 oappend (names_mask [modrm.reg]);
17806}
17807
17808static void
17809OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17810{
17811 if (!vex.evex
17812 || (bytemode != evex_rounding_mode
17813 && bytemode != evex_sae_mode))
17814 abort ();
17815 if (modrm.mod == 3 && vex.b)
17816 switch (bytemode)
17817 {
17818 case evex_rounding_mode:
17819 oappend (names_rounding[vex.ll]);
17820 break;
17821 case evex_sae_mode:
17822 oappend ("{sae}");
17823 break;
17824 default:
17825 break;
17826 }
17827}
GDB Binutils - Deliverables
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