| 1 | /* Declarations for Intel 80386 opcode table |
| 2 | Copyright 2007, 2008, 2009, 2010 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of the GNU opcodes library. |
| 6 | |
| 7 | This library is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | It is distributed in the hope that it will be useful, but WITHOUT |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 15 | License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to the Free |
| 19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | 02110-1301, USA. */ |
| 21 | |
| 22 | #include "opcode/i386.h" |
| 23 | #ifdef HAVE_LIMITS_H |
| 24 | #include <limits.h> |
| 25 | #endif |
| 26 | |
| 27 | #ifndef CHAR_BIT |
| 28 | #define CHAR_BIT 8 |
| 29 | #endif |
| 30 | |
| 31 | /* Position of cpu flags bitfiled. */ |
| 32 | |
| 33 | enum |
| 34 | { |
| 35 | /* i186 or better required */ |
| 36 | Cpu186 = 0, |
| 37 | /* i286 or better required */ |
| 38 | Cpu286, |
| 39 | /* i386 or better required */ |
| 40 | Cpu386, |
| 41 | /* i486 or better required */ |
| 42 | Cpu486, |
| 43 | /* i585 or better required */ |
| 44 | Cpu586, |
| 45 | /* i686 or better required */ |
| 46 | Cpu686, |
| 47 | /* CLFLUSH Instruction support required */ |
| 48 | CpuClflush, |
| 49 | /* NOP Instruction support required */ |
| 50 | CpuNop, |
| 51 | /* SYSCALL Instructions support required */ |
| 52 | CpuSYSCALL, |
| 53 | /* Floating point support required */ |
| 54 | Cpu8087, |
| 55 | /* i287 support required */ |
| 56 | Cpu287, |
| 57 | /* i387 support required */ |
| 58 | Cpu387, |
| 59 | /* i686 and floating point support required */ |
| 60 | Cpu687, |
| 61 | /* SSE3 and floating point support required */ |
| 62 | CpuFISTTP, |
| 63 | /* MMX support required */ |
| 64 | CpuMMX, |
| 65 | /* SSE support required */ |
| 66 | CpuSSE, |
| 67 | /* SSE2 support required */ |
| 68 | CpuSSE2, |
| 69 | /* 3dnow! support required */ |
| 70 | Cpu3dnow, |
| 71 | /* 3dnow! Extensions support required */ |
| 72 | Cpu3dnowA, |
| 73 | /* SSE3 support required */ |
| 74 | CpuSSE3, |
| 75 | /* VIA PadLock required */ |
| 76 | CpuPadLock, |
| 77 | /* AMD Secure Virtual Machine Ext-s required */ |
| 78 | CpuSVME, |
| 79 | /* VMX Instructions required */ |
| 80 | CpuVMX, |
| 81 | /* SMX Instructions required */ |
| 82 | CpuSMX, |
| 83 | /* SSSE3 support required */ |
| 84 | CpuSSSE3, |
| 85 | /* SSE4a support required */ |
| 86 | CpuSSE4a, |
| 87 | /* ABM New Instructions required */ |
| 88 | CpuABM, |
| 89 | /* SSE4.1 support required */ |
| 90 | CpuSSE4_1, |
| 91 | /* SSE4.2 support required */ |
| 92 | CpuSSE4_2, |
| 93 | /* AVX support required */ |
| 94 | CpuAVX, |
| 95 | /* AVX2 support required */ |
| 96 | CpuAVX2, |
| 97 | /* Intel L1OM support required */ |
| 98 | CpuL1OM, |
| 99 | /* Intel K1OM support required */ |
| 100 | CpuK1OM, |
| 101 | /* Xsave/xrstor New Instructions support required */ |
| 102 | CpuXsave, |
| 103 | /* Xsaveopt New Instructions support required */ |
| 104 | CpuXsaveopt, |
| 105 | /* AES support required */ |
| 106 | CpuAES, |
| 107 | /* PCLMUL support required */ |
| 108 | CpuPCLMUL, |
| 109 | /* FMA support required */ |
| 110 | CpuFMA, |
| 111 | /* FMA4 support required */ |
| 112 | CpuFMA4, |
| 113 | /* XOP support required */ |
| 114 | CpuXOP, |
| 115 | /* LWP support required */ |
| 116 | CpuLWP, |
| 117 | /* BMI support required */ |
| 118 | CpuBMI, |
| 119 | /* TBM support required */ |
| 120 | CpuTBM, |
| 121 | /* MOVBE Instruction support required */ |
| 122 | CpuMovbe, |
| 123 | /* EPT Instructions required */ |
| 124 | CpuEPT, |
| 125 | /* RDTSCP Instruction support required */ |
| 126 | CpuRdtscp, |
| 127 | /* FSGSBASE Instructions required */ |
| 128 | CpuFSGSBase, |
| 129 | /* RDRND Instructions required */ |
| 130 | CpuRdRnd, |
| 131 | /* F16C Instructions required */ |
| 132 | CpuF16C, |
| 133 | /* Intel BMI2 support required */ |
| 134 | CpuBMI2, |
| 135 | /* LZCNT support required */ |
| 136 | CpuLZCNT, |
| 137 | /* INVPCID Instructions required */ |
| 138 | CpuINVPCID, |
| 139 | /* 64bit support available, used by -march= in assembler. */ |
| 140 | CpuLM, |
| 141 | /* 64bit support required */ |
| 142 | Cpu64, |
| 143 | /* Not supported in the 64bit mode */ |
| 144 | CpuNo64, |
| 145 | /* The last bitfield in i386_cpu_flags. */ |
| 146 | CpuMax = CpuNo64 |
| 147 | }; |
| 148 | |
| 149 | #define CpuNumOfUints \ |
| 150 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) |
| 151 | #define CpuNumOfBits \ |
| 152 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
| 153 | |
| 154 | /* If you get a compiler error for zero width of the unused field, |
| 155 | comment it out. */ |
| 156 | #define CpuUnused (CpuMax + 1) |
| 157 | |
| 158 | /* We can check if an instruction is available with array instead |
| 159 | of bitfield. */ |
| 160 | typedef union i386_cpu_flags |
| 161 | { |
| 162 | struct |
| 163 | { |
| 164 | unsigned int cpui186:1; |
| 165 | unsigned int cpui286:1; |
| 166 | unsigned int cpui386:1; |
| 167 | unsigned int cpui486:1; |
| 168 | unsigned int cpui586:1; |
| 169 | unsigned int cpui686:1; |
| 170 | unsigned int cpuclflush:1; |
| 171 | unsigned int cpunop:1; |
| 172 | unsigned int cpusyscall:1; |
| 173 | unsigned int cpu8087:1; |
| 174 | unsigned int cpu287:1; |
| 175 | unsigned int cpu387:1; |
| 176 | unsigned int cpu687:1; |
| 177 | unsigned int cpufisttp:1; |
| 178 | unsigned int cpummx:1; |
| 179 | unsigned int cpusse:1; |
| 180 | unsigned int cpusse2:1; |
| 181 | unsigned int cpua3dnow:1; |
| 182 | unsigned int cpua3dnowa:1; |
| 183 | unsigned int cpusse3:1; |
| 184 | unsigned int cpupadlock:1; |
| 185 | unsigned int cpusvme:1; |
| 186 | unsigned int cpuvmx:1; |
| 187 | unsigned int cpusmx:1; |
| 188 | unsigned int cpussse3:1; |
| 189 | unsigned int cpusse4a:1; |
| 190 | unsigned int cpuabm:1; |
| 191 | unsigned int cpusse4_1:1; |
| 192 | unsigned int cpusse4_2:1; |
| 193 | unsigned int cpuavx:1; |
| 194 | unsigned int cpuavx2:1; |
| 195 | unsigned int cpul1om:1; |
| 196 | unsigned int cpuk1om:1; |
| 197 | unsigned int cpuxsave:1; |
| 198 | unsigned int cpuxsaveopt:1; |
| 199 | unsigned int cpuaes:1; |
| 200 | unsigned int cpupclmul:1; |
| 201 | unsigned int cpufma:1; |
| 202 | unsigned int cpufma4:1; |
| 203 | unsigned int cpuxop:1; |
| 204 | unsigned int cpulwp:1; |
| 205 | unsigned int cpubmi:1; |
| 206 | unsigned int cputbm:1; |
| 207 | unsigned int cpumovbe:1; |
| 208 | unsigned int cpuept:1; |
| 209 | unsigned int cpurdtscp:1; |
| 210 | unsigned int cpufsgsbase:1; |
| 211 | unsigned int cpurdrnd:1; |
| 212 | unsigned int cpuf16c:1; |
| 213 | unsigned int cpubmi2:1; |
| 214 | unsigned int cpulzcnt:1; |
| 215 | unsigned int cpuinvpcid:1; |
| 216 | unsigned int cpulm:1; |
| 217 | unsigned int cpu64:1; |
| 218 | unsigned int cpuno64:1; |
| 219 | #ifdef CpuUnused |
| 220 | unsigned int unused:(CpuNumOfBits - CpuUnused); |
| 221 | #endif |
| 222 | } bitfield; |
| 223 | unsigned int array[CpuNumOfUints]; |
| 224 | } i386_cpu_flags; |
| 225 | |
| 226 | /* Position of opcode_modifier bits. */ |
| 227 | |
| 228 | enum |
| 229 | { |
| 230 | /* has direction bit. */ |
| 231 | D = 0, |
| 232 | /* set if operands can be words or dwords encoded the canonical way */ |
| 233 | W, |
| 234 | /* Skip the current insn and use the next insn in i386-opc.tbl to swap |
| 235 | operand in encoding. */ |
| 236 | S, |
| 237 | /* insn has a modrm byte. */ |
| 238 | Modrm, |
| 239 | /* register is in low 3 bits of opcode */ |
| 240 | ShortForm, |
| 241 | /* special case for jump insns. */ |
| 242 | Jump, |
| 243 | /* call and jump */ |
| 244 | JumpDword, |
| 245 | /* loop and jecxz */ |
| 246 | JumpByte, |
| 247 | /* special case for intersegment leaps/calls */ |
| 248 | JumpInterSegment, |
| 249 | /* FP insn memory format bit, sized by 0x4 */ |
| 250 | FloatMF, |
| 251 | /* src/dest swap for floats. */ |
| 252 | FloatR, |
| 253 | /* has float insn direction bit. */ |
| 254 | FloatD, |
| 255 | /* needs size prefix if in 32-bit mode */ |
| 256 | Size16, |
| 257 | /* needs size prefix if in 16-bit mode */ |
| 258 | Size32, |
| 259 | /* needs size prefix if in 64-bit mode */ |
| 260 | Size64, |
| 261 | /* check register size. */ |
| 262 | CheckRegSize, |
| 263 | /* instruction ignores operand size prefix and in Intel mode ignores |
| 264 | mnemonic size suffix check. */ |
| 265 | IgnoreSize, |
| 266 | /* default insn size depends on mode */ |
| 267 | DefaultSize, |
| 268 | /* b suffix on instruction illegal */ |
| 269 | No_bSuf, |
| 270 | /* w suffix on instruction illegal */ |
| 271 | No_wSuf, |
| 272 | /* l suffix on instruction illegal */ |
| 273 | No_lSuf, |
| 274 | /* s suffix on instruction illegal */ |
| 275 | No_sSuf, |
| 276 | /* q suffix on instruction illegal */ |
| 277 | No_qSuf, |
| 278 | /* long double suffix on instruction illegal */ |
| 279 | No_ldSuf, |
| 280 | /* instruction needs FWAIT */ |
| 281 | FWait, |
| 282 | /* quick test for string instructions */ |
| 283 | IsString, |
| 284 | /* quick test for lockable instructions */ |
| 285 | IsLockable, |
| 286 | /* fake an extra reg operand for clr, imul and special register |
| 287 | processing for some instructions. */ |
| 288 | RegKludge, |
| 289 | /* The first operand must be xmm0 */ |
| 290 | FirstXmm0, |
| 291 | /* An implicit xmm0 as the first operand */ |
| 292 | Implicit1stXmm0, |
| 293 | /* Convert to DWORD */ |
| 294 | ToDword, |
| 295 | /* Convert to QWORD */ |
| 296 | ToQword, |
| 297 | /* Address prefix changes operand 0 */ |
| 298 | AddrPrefixOp0, |
| 299 | /* opcode is a prefix */ |
| 300 | IsPrefix, |
| 301 | /* instruction has extension in 8 bit imm */ |
| 302 | ImmExt, |
| 303 | /* instruction don't need Rex64 prefix. */ |
| 304 | NoRex64, |
| 305 | /* instruction require Rex64 prefix. */ |
| 306 | Rex64, |
| 307 | /* deprecated fp insn, gets a warning */ |
| 308 | Ugh, |
| 309 | /* insn has VEX prefix: |
| 310 | 1: 128bit VEX prefix. |
| 311 | 2: 256bit VEX prefix. |
| 312 | 3: Scalar VEX prefix. |
| 313 | */ |
| 314 | #define VEX128 1 |
| 315 | #define VEX256 2 |
| 316 | #define VEXScalar 3 |
| 317 | Vex, |
| 318 | /* How to encode VEX.vvvv: |
| 319 | 0: VEX.vvvv must be 1111b. |
| 320 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
| 321 | the content of source registers will be preserved. |
| 322 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
| 323 | where the content of first source register will be overwritten |
| 324 | by the result. |
| 325 | VEX.NDD2. The second destination register operand is encoded in |
| 326 | VEX.vvvv for instructions with 2 destination register operands. |
| 327 | For assembler, there are no difference between VEX.NDS, VEX.DDS |
| 328 | and VEX.NDD2. |
| 329 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for |
| 330 | instructions with 1 destination register operand. |
| 331 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
| 332 | of the operands can access a memory location. |
| 333 | */ |
| 334 | #define VEXXDS 1 |
| 335 | #define VEXNDD 2 |
| 336 | #define VEXLWP 3 |
| 337 | VexVVVV, |
| 338 | /* How the VEX.W bit is used: |
| 339 | 0: Set by the REX.W bit. |
| 340 | 1: VEX.W0. Should always be 0. |
| 341 | 2: VEX.W1. Should always be 1. |
| 342 | */ |
| 343 | #define VEXW0 1 |
| 344 | #define VEXW1 2 |
| 345 | VexW, |
| 346 | /* VEX opcode prefix: |
| 347 | 0: VEX 0x0F opcode prefix. |
| 348 | 1: VEX 0x0F38 opcode prefix. |
| 349 | 2: VEX 0x0F3A opcode prefix |
| 350 | 3: XOP 0x08 opcode prefix. |
| 351 | 4: XOP 0x09 opcode prefix |
| 352 | 5: XOP 0x0A opcode prefix. |
| 353 | */ |
| 354 | #define VEX0F 0 |
| 355 | #define VEX0F38 1 |
| 356 | #define VEX0F3A 2 |
| 357 | #define XOP08 3 |
| 358 | #define XOP09 4 |
| 359 | #define XOP0A 5 |
| 360 | VexOpcode, |
| 361 | /* number of VEX source operands: |
| 362 | 0: <= 2 source operands. |
| 363 | 1: 2 XOP source operands. |
| 364 | 2: 3 source operands. |
| 365 | */ |
| 366 | #define XOP2SOURCES 1 |
| 367 | #define VEX3SOURCES 2 |
| 368 | VexSources, |
| 369 | /* instruction has VEX 8 bit imm */ |
| 370 | VexImmExt, |
| 371 | /* Instruction with vector SIB byte: |
| 372 | 1: 128bit vector register. |
| 373 | 2: 256bit vector register. |
| 374 | */ |
| 375 | #define VecSIB128 1 |
| 376 | #define VecSIB256 2 |
| 377 | VecSIB, |
| 378 | /* SSE to AVX support required */ |
| 379 | SSE2AVX, |
| 380 | /* No AVX equivalent */ |
| 381 | NoAVX, |
| 382 | /* Compatible with old (<= 2.8.1) versions of gcc */ |
| 383 | OldGcc, |
| 384 | /* AT&T mnemonic. */ |
| 385 | ATTMnemonic, |
| 386 | /* AT&T syntax. */ |
| 387 | ATTSyntax, |
| 388 | /* Intel syntax. */ |
| 389 | IntelSyntax, |
| 390 | /* The last bitfield in i386_opcode_modifier. */ |
| 391 | Opcode_Modifier_Max |
| 392 | }; |
| 393 | |
| 394 | typedef struct i386_opcode_modifier |
| 395 | { |
| 396 | unsigned int d:1; |
| 397 | unsigned int w:1; |
| 398 | unsigned int s:1; |
| 399 | unsigned int modrm:1; |
| 400 | unsigned int shortform:1; |
| 401 | unsigned int jump:1; |
| 402 | unsigned int jumpdword:1; |
| 403 | unsigned int jumpbyte:1; |
| 404 | unsigned int jumpintersegment:1; |
| 405 | unsigned int floatmf:1; |
| 406 | unsigned int floatr:1; |
| 407 | unsigned int floatd:1; |
| 408 | unsigned int size16:1; |
| 409 | unsigned int size32:1; |
| 410 | unsigned int size64:1; |
| 411 | unsigned int checkregsize:1; |
| 412 | unsigned int ignoresize:1; |
| 413 | unsigned int defaultsize:1; |
| 414 | unsigned int no_bsuf:1; |
| 415 | unsigned int no_wsuf:1; |
| 416 | unsigned int no_lsuf:1; |
| 417 | unsigned int no_ssuf:1; |
| 418 | unsigned int no_qsuf:1; |
| 419 | unsigned int no_ldsuf:1; |
| 420 | unsigned int fwait:1; |
| 421 | unsigned int isstring:1; |
| 422 | unsigned int islockable:1; |
| 423 | unsigned int regkludge:1; |
| 424 | unsigned int firstxmm0:1; |
| 425 | unsigned int implicit1stxmm0:1; |
| 426 | unsigned int todword:1; |
| 427 | unsigned int toqword:1; |
| 428 | unsigned int addrprefixop0:1; |
| 429 | unsigned int isprefix:1; |
| 430 | unsigned int immext:1; |
| 431 | unsigned int norex64:1; |
| 432 | unsigned int rex64:1; |
| 433 | unsigned int ugh:1; |
| 434 | unsigned int vex:2; |
| 435 | unsigned int vexvvvv:2; |
| 436 | unsigned int vexw:2; |
| 437 | unsigned int vexopcode:3; |
| 438 | unsigned int vexsources:2; |
| 439 | unsigned int veximmext:1; |
| 440 | unsigned int vecsib:2; |
| 441 | unsigned int sse2avx:1; |
| 442 | unsigned int noavx:1; |
| 443 | unsigned int oldgcc:1; |
| 444 | unsigned int attmnemonic:1; |
| 445 | unsigned int attsyntax:1; |
| 446 | unsigned int intelsyntax:1; |
| 447 | } i386_opcode_modifier; |
| 448 | |
| 449 | /* Position of operand_type bits. */ |
| 450 | |
| 451 | enum |
| 452 | { |
| 453 | /* 8bit register */ |
| 454 | Reg8 = 0, |
| 455 | /* 16bit register */ |
| 456 | Reg16, |
| 457 | /* 32bit register */ |
| 458 | Reg32, |
| 459 | /* 64bit register */ |
| 460 | Reg64, |
| 461 | /* Floating pointer stack register */ |
| 462 | FloatReg, |
| 463 | /* MMX register */ |
| 464 | RegMMX, |
| 465 | /* SSE register */ |
| 466 | RegXMM, |
| 467 | /* AVX registers */ |
| 468 | RegYMM, |
| 469 | /* Control register */ |
| 470 | Control, |
| 471 | /* Debug register */ |
| 472 | Debug, |
| 473 | /* Test register */ |
| 474 | Test, |
| 475 | /* 2 bit segment register */ |
| 476 | SReg2, |
| 477 | /* 3 bit segment register */ |
| 478 | SReg3, |
| 479 | /* 1 bit immediate */ |
| 480 | Imm1, |
| 481 | /* 8 bit immediate */ |
| 482 | Imm8, |
| 483 | /* 8 bit immediate sign extended */ |
| 484 | Imm8S, |
| 485 | /* 16 bit immediate */ |
| 486 | Imm16, |
| 487 | /* 32 bit immediate */ |
| 488 | Imm32, |
| 489 | /* 32 bit immediate sign extended */ |
| 490 | Imm32S, |
| 491 | /* 64 bit immediate */ |
| 492 | Imm64, |
| 493 | /* 8bit/16bit/32bit displacements are used in different ways, |
| 494 | depending on the instruction. For jumps, they specify the |
| 495 | size of the PC relative displacement, for instructions with |
| 496 | memory operand, they specify the size of the offset relative |
| 497 | to the base register, and for instructions with memory offset |
| 498 | such as `mov 1234,%al' they specify the size of the offset |
| 499 | relative to the segment base. */ |
| 500 | /* 8 bit displacement */ |
| 501 | Disp8, |
| 502 | /* 16 bit displacement */ |
| 503 | Disp16, |
| 504 | /* 32 bit displacement */ |
| 505 | Disp32, |
| 506 | /* 32 bit signed displacement */ |
| 507 | Disp32S, |
| 508 | /* 64 bit displacement */ |
| 509 | Disp64, |
| 510 | /* Accumulator %al/%ax/%eax/%rax */ |
| 511 | Acc, |
| 512 | /* Floating pointer top stack register %st(0) */ |
| 513 | FloatAcc, |
| 514 | /* Register which can be used for base or index in memory operand. */ |
| 515 | BaseIndex, |
| 516 | /* Register to hold in/out port addr = dx */ |
| 517 | InOutPortReg, |
| 518 | /* Register to hold shift count = cl */ |
| 519 | ShiftCount, |
| 520 | /* Absolute address for jump. */ |
| 521 | JumpAbsolute, |
| 522 | /* String insn operand with fixed es segment */ |
| 523 | EsSeg, |
| 524 | /* RegMem is for instructions with a modrm byte where the register |
| 525 | destination operand should be encoded in the mod and regmem fields. |
| 526 | Normally, it will be encoded in the reg field. We add a RegMem |
| 527 | flag to the destination register operand to indicate that it should |
| 528 | be encoded in the regmem field. */ |
| 529 | RegMem, |
| 530 | /* Memory. */ |
| 531 | Mem, |
| 532 | /* BYTE memory. */ |
| 533 | Byte, |
| 534 | /* WORD memory. 2 byte */ |
| 535 | Word, |
| 536 | /* DWORD memory. 4 byte */ |
| 537 | Dword, |
| 538 | /* FWORD memory. 6 byte */ |
| 539 | Fword, |
| 540 | /* QWORD memory. 8 byte */ |
| 541 | Qword, |
| 542 | /* TBYTE memory. 10 byte */ |
| 543 | Tbyte, |
| 544 | /* XMMWORD memory. */ |
| 545 | Xmmword, |
| 546 | /* YMMWORD memory. */ |
| 547 | Ymmword, |
| 548 | /* Unspecified memory size. */ |
| 549 | Unspecified, |
| 550 | /* Any memory size. */ |
| 551 | Anysize, |
| 552 | |
| 553 | /* Vector 4 bit immediate. */ |
| 554 | Vec_Imm4, |
| 555 | |
| 556 | /* The last bitfield in i386_operand_type. */ |
| 557 | OTMax |
| 558 | }; |
| 559 | |
| 560 | #define OTNumOfUints \ |
| 561 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) |
| 562 | #define OTNumOfBits \ |
| 563 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
| 564 | |
| 565 | /* If you get a compiler error for zero width of the unused field, |
| 566 | comment it out. */ |
| 567 | #define OTUnused (OTMax + 1) |
| 568 | |
| 569 | typedef union i386_operand_type |
| 570 | { |
| 571 | struct |
| 572 | { |
| 573 | unsigned int reg8:1; |
| 574 | unsigned int reg16:1; |
| 575 | unsigned int reg32:1; |
| 576 | unsigned int reg64:1; |
| 577 | unsigned int floatreg:1; |
| 578 | unsigned int regmmx:1; |
| 579 | unsigned int regxmm:1; |
| 580 | unsigned int regymm:1; |
| 581 | unsigned int control:1; |
| 582 | unsigned int debug:1; |
| 583 | unsigned int test:1; |
| 584 | unsigned int sreg2:1; |
| 585 | unsigned int sreg3:1; |
| 586 | unsigned int imm1:1; |
| 587 | unsigned int imm8:1; |
| 588 | unsigned int imm8s:1; |
| 589 | unsigned int imm16:1; |
| 590 | unsigned int imm32:1; |
| 591 | unsigned int imm32s:1; |
| 592 | unsigned int imm64:1; |
| 593 | unsigned int disp8:1; |
| 594 | unsigned int disp16:1; |
| 595 | unsigned int disp32:1; |
| 596 | unsigned int disp32s:1; |
| 597 | unsigned int disp64:1; |
| 598 | unsigned int acc:1; |
| 599 | unsigned int floatacc:1; |
| 600 | unsigned int baseindex:1; |
| 601 | unsigned int inoutportreg:1; |
| 602 | unsigned int shiftcount:1; |
| 603 | unsigned int jumpabsolute:1; |
| 604 | unsigned int esseg:1; |
| 605 | unsigned int regmem:1; |
| 606 | unsigned int mem:1; |
| 607 | unsigned int byte:1; |
| 608 | unsigned int word:1; |
| 609 | unsigned int dword:1; |
| 610 | unsigned int fword:1; |
| 611 | unsigned int qword:1; |
| 612 | unsigned int tbyte:1; |
| 613 | unsigned int xmmword:1; |
| 614 | unsigned int ymmword:1; |
| 615 | unsigned int unspecified:1; |
| 616 | unsigned int anysize:1; |
| 617 | unsigned int vec_imm4:1; |
| 618 | #ifdef OTUnused |
| 619 | unsigned int unused:(OTNumOfBits - OTUnused); |
| 620 | #endif |
| 621 | } bitfield; |
| 622 | unsigned int array[OTNumOfUints]; |
| 623 | } i386_operand_type; |
| 624 | |
| 625 | typedef struct insn_template |
| 626 | { |
| 627 | /* instruction name sans width suffix ("mov" for movl insns) */ |
| 628 | char *name; |
| 629 | |
| 630 | /* how many operands */ |
| 631 | unsigned int operands; |
| 632 | |
| 633 | /* base_opcode is the fundamental opcode byte without optional |
| 634 | prefix(es). */ |
| 635 | unsigned int base_opcode; |
| 636 | #define Opcode_D 0x2 /* Direction bit: |
| 637 | set if Reg --> Regmem; |
| 638 | unset if Regmem --> Reg. */ |
| 639 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ |
| 640 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ |
| 641 | |
| 642 | /* extension_opcode is the 3 bit extension for group <n> insns. |
| 643 | This field is also used to store the 8-bit opcode suffix for the |
| 644 | AMD 3DNow! instructions. |
| 645 | If this template has no extension opcode (the usual case) use None |
| 646 | Instructions */ |
| 647 | unsigned int extension_opcode; |
| 648 | #define None 0xffff /* If no extension_opcode is possible. */ |
| 649 | |
| 650 | /* Opcode length. */ |
| 651 | unsigned char opcode_length; |
| 652 | |
| 653 | /* cpu feature flags */ |
| 654 | i386_cpu_flags cpu_flags; |
| 655 | |
| 656 | /* the bits in opcode_modifier are used to generate the final opcode from |
| 657 | the base_opcode. These bits also are used to detect alternate forms of |
| 658 | the same instruction */ |
| 659 | i386_opcode_modifier opcode_modifier; |
| 660 | |
| 661 | /* operand_types[i] describes the type of operand i. This is made |
| 662 | by OR'ing together all of the possible type masks. (e.g. |
| 663 | 'operand_types[i] = Reg|Imm' specifies that operand i can be |
| 664 | either a register or an immediate operand. */ |
| 665 | i386_operand_type operand_types[MAX_OPERANDS]; |
| 666 | } |
| 667 | insn_template; |
| 668 | |
| 669 | extern const insn_template i386_optab[]; |
| 670 | |
| 671 | /* these are for register name --> number & type hash lookup */ |
| 672 | typedef struct |
| 673 | { |
| 674 | char *reg_name; |
| 675 | i386_operand_type reg_type; |
| 676 | unsigned char reg_flags; |
| 677 | #define RegRex 0x1 /* Extended register. */ |
| 678 | #define RegRex64 0x2 /* Extended 8 bit register. */ |
| 679 | unsigned char reg_num; |
| 680 | #define RegRip ((unsigned char ) ~0) |
| 681 | #define RegEip (RegRip - 1) |
| 682 | /* EIZ and RIZ are fake index registers. */ |
| 683 | #define RegEiz (RegEip - 1) |
| 684 | #define RegRiz (RegEiz - 1) |
| 685 | /* FLAT is a fake segment register (Intel mode). */ |
| 686 | #define RegFlat ((unsigned char) ~0) |
| 687 | signed char dw2_regnum[2]; |
| 688 | #define Dw2Inval (-1) |
| 689 | } |
| 690 | reg_entry; |
| 691 | |
| 692 | /* Entries in i386_regtab. */ |
| 693 | #define REGNAM_AL 1 |
| 694 | #define REGNAM_AX 25 |
| 695 | #define REGNAM_EAX 41 |
| 696 | |
| 697 | extern const reg_entry i386_regtab[]; |
| 698 | extern const unsigned int i386_regtab_size; |
| 699 | |
| 700 | typedef struct |
| 701 | { |
| 702 | char *seg_name; |
| 703 | unsigned int seg_prefix; |
| 704 | } |
| 705 | seg_entry; |
| 706 | |
| 707 | extern const seg_entry cs; |
| 708 | extern const seg_entry ds; |
| 709 | extern const seg_entry ss; |
| 710 | extern const seg_entry es; |
| 711 | extern const seg_entry fs; |
| 712 | extern const seg_entry gs; |