| | 1 | /* Declarations for Intel 80386 opcode table |
| | 2 | Copyright (C) 2007-2017 Free Software Foundation, Inc. |
| | 3 | |
| | 4 | This file is part of the GNU opcodes library. |
| | 5 | |
| | 6 | This library is free software; you can redistribute it and/or modify |
| | 7 | it under the terms of the GNU General Public License as published by |
| | 8 | the Free Software Foundation; either version 3, or (at your option) |
| | 9 | any later version. |
| | 10 | |
| | 11 | It is distributed in the hope that it will be useful, but WITHOUT |
| | 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| | 13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| | 14 | License for more details. |
| | 15 | |
| | 16 | You should have received a copy of the GNU General Public License |
| | 17 | along with GAS; see the file COPYING. If not, write to the Free |
| | 18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| | 19 | 02110-1301, USA. */ |
| | 20 | |
| | 21 | #include "opcode/i386.h" |
| | 22 | #ifdef HAVE_LIMITS_H |
| | 23 | #include <limits.h> |
| | 24 | #endif |
| | 25 | |
| | 26 | #ifndef CHAR_BIT |
| | 27 | #define CHAR_BIT 8 |
| | 28 | #endif |
| | 29 | |
| | 30 | /* Position of cpu flags bitfiled. */ |
| | 31 | |
| | 32 | enum |
| | 33 | { |
| | 34 | /* i186 or better required */ |
| | 35 | Cpu186 = 0, |
| | 36 | /* i286 or better required */ |
| | 37 | Cpu286, |
| | 38 | /* i386 or better required */ |
| | 39 | Cpu386, |
| | 40 | /* i486 or better required */ |
| | 41 | Cpu486, |
| | 42 | /* i585 or better required */ |
| | 43 | Cpu586, |
| | 44 | /* i686 or better required */ |
| | 45 | Cpu686, |
| | 46 | /* CLFLUSH Instruction support required */ |
| | 47 | CpuClflush, |
| | 48 | /* NOP Instruction support required */ |
| | 49 | CpuNop, |
| | 50 | /* SYSCALL Instructions support required */ |
| | 51 | CpuSYSCALL, |
| | 52 | /* Floating point support required */ |
| | 53 | Cpu8087, |
| | 54 | /* i287 support required */ |
| | 55 | Cpu287, |
| | 56 | /* i387 support required */ |
| | 57 | Cpu387, |
| | 58 | /* i686 and floating point support required */ |
| | 59 | Cpu687, |
| | 60 | /* SSE3 and floating point support required */ |
| | 61 | CpuFISTTP, |
| | 62 | /* MMX support required */ |
| | 63 | CpuMMX, |
| | 64 | /* SSE support required */ |
| | 65 | CpuSSE, |
| | 66 | /* SSE2 support required */ |
| | 67 | CpuSSE2, |
| | 68 | /* 3dnow! support required */ |
| | 69 | Cpu3dnow, |
| | 70 | /* 3dnow! Extensions support required */ |
| | 71 | Cpu3dnowA, |
| | 72 | /* SSE3 support required */ |
| | 73 | CpuSSE3, |
| | 74 | /* VIA PadLock required */ |
| | 75 | CpuPadLock, |
| | 76 | /* AMD Secure Virtual Machine Ext-s required */ |
| | 77 | CpuSVME, |
| | 78 | /* VMX Instructions required */ |
| | 79 | CpuVMX, |
| | 80 | /* SMX Instructions required */ |
| | 81 | CpuSMX, |
| | 82 | /* SSSE3 support required */ |
| | 83 | CpuSSSE3, |
| | 84 | /* SSE4a support required */ |
| | 85 | CpuSSE4a, |
| | 86 | /* ABM New Instructions required */ |
| | 87 | CpuABM, |
| | 88 | /* SSE4.1 support required */ |
| | 89 | CpuSSE4_1, |
| | 90 | /* SSE4.2 support required */ |
| | 91 | CpuSSE4_2, |
| | 92 | /* AVX support required */ |
| | 93 | CpuAVX, |
| | 94 | /* AVX2 support required */ |
| | 95 | CpuAVX2, |
| | 96 | /* Intel AVX-512 Foundation Instructions support required */ |
| | 97 | CpuAVX512F, |
| | 98 | /* Intel AVX-512 Conflict Detection Instructions support required */ |
| | 99 | CpuAVX512CD, |
| | 100 | /* Intel AVX-512 Exponential and Reciprocal Instructions support |
| | 101 | required */ |
| | 102 | CpuAVX512ER, |
| | 103 | /* Intel AVX-512 Prefetch Instructions support required */ |
| | 104 | CpuAVX512PF, |
| | 105 | /* Intel AVX-512 VL Instructions support required. */ |
| | 106 | CpuAVX512VL, |
| | 107 | /* Intel AVX-512 DQ Instructions support required. */ |
| | 108 | CpuAVX512DQ, |
| | 109 | /* Intel AVX-512 BW Instructions support required. */ |
| | 110 | CpuAVX512BW, |
| | 111 | /* Intel L1OM support required */ |
| | 112 | CpuL1OM, |
| | 113 | /* Intel K1OM support required */ |
| | 114 | CpuK1OM, |
| | 115 | /* Intel IAMCU support required */ |
| | 116 | CpuIAMCU, |
| | 117 | /* Xsave/xrstor New Instructions support required */ |
| | 118 | CpuXsave, |
| | 119 | /* Xsaveopt New Instructions support required */ |
| | 120 | CpuXsaveopt, |
| | 121 | /* AES support required */ |
| | 122 | CpuAES, |
| | 123 | /* PCLMUL support required */ |
| | 124 | CpuPCLMUL, |
| | 125 | /* FMA support required */ |
| | 126 | CpuFMA, |
| | 127 | /* FMA4 support required */ |
| | 128 | CpuFMA4, |
| | 129 | /* XOP support required */ |
| | 130 | CpuXOP, |
| | 131 | /* LWP support required */ |
| | 132 | CpuLWP, |
| | 133 | /* BMI support required */ |
| | 134 | CpuBMI, |
| | 135 | /* TBM support required */ |
| | 136 | CpuTBM, |
| | 137 | /* MOVBE Instruction support required */ |
| | 138 | CpuMovbe, |
| | 139 | /* CMPXCHG16B instruction support required. */ |
| | 140 | CpuCX16, |
| | 141 | /* EPT Instructions required */ |
| | 142 | CpuEPT, |
| | 143 | /* RDTSCP Instruction support required */ |
| | 144 | CpuRdtscp, |
| | 145 | /* FSGSBASE Instructions required */ |
| | 146 | CpuFSGSBase, |
| | 147 | /* RDRND Instructions required */ |
| | 148 | CpuRdRnd, |
| | 149 | /* F16C Instructions required */ |
| | 150 | CpuF16C, |
| | 151 | /* Intel BMI2 support required */ |
| | 152 | CpuBMI2, |
| | 153 | /* LZCNT support required */ |
| | 154 | CpuLZCNT, |
| | 155 | /* HLE support required */ |
| | 156 | CpuHLE, |
| | 157 | /* RTM support required */ |
| | 158 | CpuRTM, |
| | 159 | /* INVPCID Instructions required */ |
| | 160 | CpuINVPCID, |
| | 161 | /* VMFUNC Instruction required */ |
| | 162 | CpuVMFUNC, |
| | 163 | /* Intel MPX Instructions required */ |
| | 164 | CpuMPX, |
| | 165 | /* 64bit support available, used by -march= in assembler. */ |
| | 166 | CpuLM, |
| | 167 | /* RDRSEED instruction required. */ |
| | 168 | CpuRDSEED, |
| | 169 | /* Multi-presisionn add-carry instructions are required. */ |
| | 170 | CpuADX, |
| | 171 | /* Supports prefetchw and prefetch instructions. */ |
| | 172 | CpuPRFCHW, |
| | 173 | /* SMAP instructions required. */ |
| | 174 | CpuSMAP, |
| | 175 | /* SHA instructions required. */ |
| | 176 | CpuSHA, |
| | 177 | /* VREX support required */ |
| | 178 | CpuVREX, |
| | 179 | /* CLFLUSHOPT instruction required */ |
| | 180 | CpuClflushOpt, |
| | 181 | /* XSAVES/XRSTORS instruction required */ |
| | 182 | CpuXSAVES, |
| | 183 | /* XSAVEC instruction required */ |
| | 184 | CpuXSAVEC, |
| | 185 | /* PREFETCHWT1 instruction required */ |
| | 186 | CpuPREFETCHWT1, |
| | 187 | /* SE1 instruction required */ |
| | 188 | CpuSE1, |
| | 189 | /* CLWB instruction required */ |
| | 190 | CpuCLWB, |
| | 191 | /* Intel AVX-512 IFMA Instructions support required. */ |
| | 192 | CpuAVX512IFMA, |
| | 193 | /* Intel AVX-512 VBMI Instructions support required. */ |
| | 194 | CpuAVX512VBMI, |
| | 195 | /* Intel AVX-512 4FMAPS Instructions support required. */ |
| | 196 | CpuAVX512_4FMAPS, |
| | 197 | /* Intel AVX-512 4VNNIW Instructions support required. */ |
| | 198 | CpuAVX512_4VNNIW, |
| | 199 | /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ |
| | 200 | CpuAVX512_VPOPCNTDQ, |
| | 201 | /* Intel AVX-512 VBMI2 Instructions support required. */ |
| | 202 | CpuAVX512_VBMI2, |
| | 203 | /* mwaitx instruction required */ |
| | 204 | CpuMWAITX, |
| | 205 | /* Clzero instruction required */ |
| | 206 | CpuCLZERO, |
| | 207 | /* OSPKE instruction required */ |
| | 208 | CpuOSPKE, |
| | 209 | /* RDPID instruction required */ |
| | 210 | CpuRDPID, |
| | 211 | /* PTWRITE instruction required */ |
| | 212 | CpuPTWRITE, |
| | 213 | /* CET instruction support required */ |
| | 214 | CpuCET, |
| | 215 | /* MMX register support required */ |
| | 216 | CpuRegMMX, |
| | 217 | /* XMM register support required */ |
| | 218 | CpuRegXMM, |
| | 219 | /* YMM register support required */ |
| | 220 | CpuRegYMM, |
| | 221 | /* ZMM register support required */ |
| | 222 | CpuRegZMM, |
| | 223 | /* Mask register support required */ |
| | 224 | CpuRegMask, |
| | 225 | /* 64bit support required */ |
| | 226 | Cpu64, |
| | 227 | /* Not supported in the 64bit mode */ |
| | 228 | CpuNo64, |
| | 229 | /* The last bitfield in i386_cpu_flags. */ |
| | 230 | CpuMax = CpuNo64 |
| | 231 | }; |
| | 232 | |
| | 233 | #define CpuNumOfUints \ |
| | 234 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) |
| | 235 | #define CpuNumOfBits \ |
| | 236 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
| | 237 | |
| | 238 | /* If you get a compiler error for zero width of the unused field, |
| | 239 | comment it out. */ |
| | 240 | |
| | 241 | #define CpuUnused (CpuMax + 1) |
| | 242 | |
| | 243 | |
| | 244 | /* We can check if an instruction is available with array instead |
| | 245 | of bitfield. */ |
| | 246 | typedef union i386_cpu_flags |
| | 247 | { |
| | 248 | struct |
| | 249 | { |
| | 250 | unsigned int cpui186:1; |
| | 251 | unsigned int cpui286:1; |
| | 252 | unsigned int cpui386:1; |
| | 253 | unsigned int cpui486:1; |
| | 254 | unsigned int cpui586:1; |
| | 255 | unsigned int cpui686:1; |
| | 256 | unsigned int cpuclflush:1; |
| | 257 | unsigned int cpunop:1; |
| | 258 | unsigned int cpusyscall:1; |
| | 259 | unsigned int cpu8087:1; |
| | 260 | unsigned int cpu287:1; |
| | 261 | unsigned int cpu387:1; |
| | 262 | unsigned int cpu687:1; |
| | 263 | unsigned int cpufisttp:1; |
| | 264 | unsigned int cpummx:1; |
| | 265 | unsigned int cpusse:1; |
| | 266 | unsigned int cpusse2:1; |
| | 267 | unsigned int cpua3dnow:1; |
| | 268 | unsigned int cpua3dnowa:1; |
| | 269 | unsigned int cpusse3:1; |
| | 270 | unsigned int cpupadlock:1; |
| | 271 | unsigned int cpusvme:1; |
| | 272 | unsigned int cpuvmx:1; |
| | 273 | unsigned int cpusmx:1; |
| | 274 | unsigned int cpussse3:1; |
| | 275 | unsigned int cpusse4a:1; |
| | 276 | unsigned int cpuabm:1; |
| | 277 | unsigned int cpusse4_1:1; |
| | 278 | unsigned int cpusse4_2:1; |
| | 279 | unsigned int cpuavx:1; |
| | 280 | unsigned int cpuavx2:1; |
| | 281 | unsigned int cpuavx512f:1; |
| | 282 | unsigned int cpuavx512cd:1; |
| | 283 | unsigned int cpuavx512er:1; |
| | 284 | unsigned int cpuavx512pf:1; |
| | 285 | unsigned int cpuavx512vl:1; |
| | 286 | unsigned int cpuavx512dq:1; |
| | 287 | unsigned int cpuavx512bw:1; |
| | 288 | unsigned int cpul1om:1; |
| | 289 | unsigned int cpuk1om:1; |
| | 290 | unsigned int cpuiamcu:1; |
| | 291 | unsigned int cpuxsave:1; |
| | 292 | unsigned int cpuxsaveopt:1; |
| | 293 | unsigned int cpuaes:1; |
| | 294 | unsigned int cpupclmul:1; |
| | 295 | unsigned int cpufma:1; |
| | 296 | unsigned int cpufma4:1; |
| | 297 | unsigned int cpuxop:1; |
| | 298 | unsigned int cpulwp:1; |
| | 299 | unsigned int cpubmi:1; |
| | 300 | unsigned int cputbm:1; |
| | 301 | unsigned int cpumovbe:1; |
| | 302 | unsigned int cpucx16:1; |
| | 303 | unsigned int cpuept:1; |
| | 304 | unsigned int cpurdtscp:1; |
| | 305 | unsigned int cpufsgsbase:1; |
| | 306 | unsigned int cpurdrnd:1; |
| | 307 | unsigned int cpuf16c:1; |
| | 308 | unsigned int cpubmi2:1; |
| | 309 | unsigned int cpulzcnt:1; |
| | 310 | unsigned int cpuhle:1; |
| | 311 | unsigned int cpurtm:1; |
| | 312 | unsigned int cpuinvpcid:1; |
| | 313 | unsigned int cpuvmfunc:1; |
| | 314 | unsigned int cpumpx:1; |
| | 315 | unsigned int cpulm:1; |
| | 316 | unsigned int cpurdseed:1; |
| | 317 | unsigned int cpuadx:1; |
| | 318 | unsigned int cpuprfchw:1; |
| | 319 | unsigned int cpusmap:1; |
| | 320 | unsigned int cpusha:1; |
| | 321 | unsigned int cpuvrex:1; |
| | 322 | unsigned int cpuclflushopt:1; |
| | 323 | unsigned int cpuxsaves:1; |
| | 324 | unsigned int cpuxsavec:1; |
| | 325 | unsigned int cpuprefetchwt1:1; |
| | 326 | unsigned int cpuse1:1; |
| | 327 | unsigned int cpuclwb:1; |
| | 328 | unsigned int cpuavx512ifma:1; |
| | 329 | unsigned int cpuavx512vbmi:1; |
| | 330 | unsigned int cpuavx512_4fmaps:1; |
| | 331 | unsigned int cpuavx512_4vnniw:1; |
| | 332 | unsigned int cpuavx512_vpopcntdq:1; |
| | 333 | unsigned int cpuavx512_vbmi2:1; |
| | 334 | unsigned int cpumwaitx:1; |
| | 335 | unsigned int cpuclzero:1; |
| | 336 | unsigned int cpuospke:1; |
| | 337 | unsigned int cpurdpid:1; |
| | 338 | unsigned int cpuptwrite:1; |
| | 339 | unsigned int cpucet:1; |
| | 340 | unsigned int cpuregmmx:1; |
| | 341 | unsigned int cpuregxmm:1; |
| | 342 | unsigned int cpuregymm:1; |
| | 343 | unsigned int cpuregzmm:1; |
| | 344 | unsigned int cpuregmask:1; |
| | 345 | unsigned int cpu64:1; |
| | 346 | unsigned int cpuno64:1; |
| | 347 | #ifdef CpuUnused |
| | 348 | unsigned int unused:(CpuNumOfBits - CpuUnused); |
| | 349 | #endif |
| | 350 | } bitfield; |
| | 351 | unsigned int array[CpuNumOfUints]; |
| | 352 | } i386_cpu_flags; |
| | 353 | |
| | 354 | /* Position of opcode_modifier bits. */ |
| | 355 | |
| | 356 | enum |
| | 357 | { |
| | 358 | /* has direction bit. */ |
| | 359 | D = 0, |
| | 360 | /* set if operands can be words or dwords encoded the canonical way */ |
| | 361 | W, |
| | 362 | /* load form instruction. Must be placed before store form. */ |
| | 363 | Load, |
| | 364 | /* insn has a modrm byte. */ |
| | 365 | Modrm, |
| | 366 | /* register is in low 3 bits of opcode */ |
| | 367 | ShortForm, |
| | 368 | /* special case for jump insns. */ |
| | 369 | Jump, |
| | 370 | /* call and jump */ |
| | 371 | JumpDword, |
| | 372 | /* loop and jecxz */ |
| | 373 | JumpByte, |
| | 374 | /* special case for intersegment leaps/calls */ |
| | 375 | JumpInterSegment, |
| | 376 | /* FP insn memory format bit, sized by 0x4 */ |
| | 377 | FloatMF, |
| | 378 | /* src/dest swap for floats. */ |
| | 379 | FloatR, |
| | 380 | /* has float insn direction bit. */ |
| | 381 | FloatD, |
| | 382 | /* needs size prefix if in 32-bit mode */ |
| | 383 | Size16, |
| | 384 | /* needs size prefix if in 16-bit mode */ |
| | 385 | Size32, |
| | 386 | /* needs size prefix if in 64-bit mode */ |
| | 387 | Size64, |
| | 388 | /* check register size. */ |
| | 389 | CheckRegSize, |
| | 390 | /* instruction ignores operand size prefix and in Intel mode ignores |
| | 391 | mnemonic size suffix check. */ |
| | 392 | IgnoreSize, |
| | 393 | /* default insn size depends on mode */ |
| | 394 | DefaultSize, |
| | 395 | /* b suffix on instruction illegal */ |
| | 396 | No_bSuf, |
| | 397 | /* w suffix on instruction illegal */ |
| | 398 | No_wSuf, |
| | 399 | /* l suffix on instruction illegal */ |
| | 400 | No_lSuf, |
| | 401 | /* s suffix on instruction illegal */ |
| | 402 | No_sSuf, |
| | 403 | /* q suffix on instruction illegal */ |
| | 404 | No_qSuf, |
| | 405 | /* long double suffix on instruction illegal */ |
| | 406 | No_ldSuf, |
| | 407 | /* instruction needs FWAIT */ |
| | 408 | FWait, |
| | 409 | /* quick test for string instructions */ |
| | 410 | IsString, |
| | 411 | /* quick test if branch instruction is MPX supported */ |
| | 412 | BNDPrefixOk, |
| | 413 | /* quick test if NOTRACK prefix is supported */ |
| | 414 | NoTrackPrefixOk, |
| | 415 | /* quick test for lockable instructions */ |
| | 416 | IsLockable, |
| | 417 | /* fake an extra reg operand for clr, imul and special register |
| | 418 | processing for some instructions. */ |
| | 419 | RegKludge, |
| | 420 | /* The first operand must be xmm0 */ |
| | 421 | FirstXmm0, |
| | 422 | /* An implicit xmm0 as the first operand */ |
| | 423 | Implicit1stXmm0, |
| | 424 | /* The HLE prefix is OK: |
| | 425 | 1. With a LOCK prefix. |
| | 426 | 2. With or without a LOCK prefix. |
| | 427 | 3. With a RELEASE (0xf3) prefix. |
| | 428 | */ |
| | 429 | #define HLEPrefixNone 0 |
| | 430 | #define HLEPrefixLock 1 |
| | 431 | #define HLEPrefixAny 2 |
| | 432 | #define HLEPrefixRelease 3 |
| | 433 | HLEPrefixOk, |
| | 434 | /* An instruction on which a "rep" prefix is acceptable. */ |
| | 435 | RepPrefixOk, |
| | 436 | /* Convert to DWORD */ |
| | 437 | ToDword, |
| | 438 | /* Convert to QWORD */ |
| | 439 | ToQword, |
| | 440 | /* Address prefix changes operand 0 */ |
| | 441 | AddrPrefixOp0, |
| | 442 | /* opcode is a prefix */ |
| | 443 | IsPrefix, |
| | 444 | /* instruction has extension in 8 bit imm */ |
| | 445 | ImmExt, |
| | 446 | /* instruction don't need Rex64 prefix. */ |
| | 447 | NoRex64, |
| | 448 | /* instruction require Rex64 prefix. */ |
| | 449 | Rex64, |
| | 450 | /* deprecated fp insn, gets a warning */ |
| | 451 | Ugh, |
| | 452 | /* insn has VEX prefix: |
| | 453 | 1: 128bit VEX prefix. |
| | 454 | 2: 256bit VEX prefix. |
| | 455 | 3: Scalar VEX prefix. |
| | 456 | */ |
| | 457 | #define VEX128 1 |
| | 458 | #define VEX256 2 |
| | 459 | #define VEXScalar 3 |
| | 460 | Vex, |
| | 461 | /* How to encode VEX.vvvv: |
| | 462 | 0: VEX.vvvv must be 1111b. |
| | 463 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
| | 464 | the content of source registers will be preserved. |
| | 465 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
| | 466 | where the content of first source register will be overwritten |
| | 467 | by the result. |
| | 468 | VEX.NDD2. The second destination register operand is encoded in |
| | 469 | VEX.vvvv for instructions with 2 destination register operands. |
| | 470 | For assembler, there are no difference between VEX.NDS, VEX.DDS |
| | 471 | and VEX.NDD2. |
| | 472 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for |
| | 473 | instructions with 1 destination register operand. |
| | 474 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
| | 475 | of the operands can access a memory location. |
| | 476 | */ |
| | 477 | #define VEXXDS 1 |
| | 478 | #define VEXNDD 2 |
| | 479 | #define VEXLWP 3 |
| | 480 | VexVVVV, |
| | 481 | /* How the VEX.W bit is used: |
| | 482 | 0: Set by the REX.W bit. |
| | 483 | 1: VEX.W0. Should always be 0. |
| | 484 | 2: VEX.W1. Should always be 1. |
| | 485 | */ |
| | 486 | #define VEXW0 1 |
| | 487 | #define VEXW1 2 |
| | 488 | VexW, |
| | 489 | /* VEX opcode prefix: |
| | 490 | 0: VEX 0x0F opcode prefix. |
| | 491 | 1: VEX 0x0F38 opcode prefix. |
| | 492 | 2: VEX 0x0F3A opcode prefix |
| | 493 | 3: XOP 0x08 opcode prefix. |
| | 494 | 4: XOP 0x09 opcode prefix |
| | 495 | 5: XOP 0x0A opcode prefix. |
| | 496 | */ |
| | 497 | #define VEX0F 0 |
| | 498 | #define VEX0F38 1 |
| | 499 | #define VEX0F3A 2 |
| | 500 | #define XOP08 3 |
| | 501 | #define XOP09 4 |
| | 502 | #define XOP0A 5 |
| | 503 | VexOpcode, |
| | 504 | /* number of VEX source operands: |
| | 505 | 0: <= 2 source operands. |
| | 506 | 1: 2 XOP source operands. |
| | 507 | 2: 3 source operands. |
| | 508 | */ |
| | 509 | #define XOP2SOURCES 1 |
| | 510 | #define VEX3SOURCES 2 |
| | 511 | VexSources, |
| | 512 | /* instruction has VEX 8 bit imm */ |
| | 513 | VexImmExt, |
| | 514 | /* Instruction with vector SIB byte: |
| | 515 | 1: 128bit vector register. |
| | 516 | 2: 256bit vector register. |
| | 517 | 3: 512bit vector register. |
| | 518 | */ |
| | 519 | #define VecSIB128 1 |
| | 520 | #define VecSIB256 2 |
| | 521 | #define VecSIB512 3 |
| | 522 | VecSIB, |
| | 523 | /* SSE to AVX support required */ |
| | 524 | SSE2AVX, |
| | 525 | /* No AVX equivalent */ |
| | 526 | NoAVX, |
| | 527 | |
| | 528 | /* insn has EVEX prefix: |
| | 529 | 1: 512bit EVEX prefix. |
| | 530 | 2: 128bit EVEX prefix. |
| | 531 | 3: 256bit EVEX prefix. |
| | 532 | 4: Length-ignored (LIG) EVEX prefix. |
| | 533 | */ |
| | 534 | #define EVEX512 1 |
| | 535 | #define EVEX128 2 |
| | 536 | #define EVEX256 3 |
| | 537 | #define EVEXLIG 4 |
| | 538 | EVex, |
| | 539 | |
| | 540 | /* AVX512 masking support: |
| | 541 | 1: Zeroing-masking. |
| | 542 | 2: Merging-masking. |
| | 543 | 3: Both zeroing and merging masking. |
| | 544 | */ |
| | 545 | #define ZEROING_MASKING 1 |
| | 546 | #define MERGING_MASKING 2 |
| | 547 | #define BOTH_MASKING 3 |
| | 548 | Masking, |
| | 549 | |
| | 550 | /* Input element size of vector insn: |
| | 551 | 0: 32bit. |
| | 552 | 1: 64bit. |
| | 553 | */ |
| | 554 | VecESize, |
| | 555 | |
| | 556 | /* Broadcast factor. |
| | 557 | 0: No broadcast. |
| | 558 | 1: 1to16 broadcast. |
| | 559 | 2: 1to8 broadcast. |
| | 560 | */ |
| | 561 | #define NO_BROADCAST 0 |
| | 562 | #define BROADCAST_1TO16 1 |
| | 563 | #define BROADCAST_1TO8 2 |
| | 564 | #define BROADCAST_1TO4 3 |
| | 565 | #define BROADCAST_1TO2 4 |
| | 566 | Broadcast, |
| | 567 | |
| | 568 | /* Static rounding control is supported. */ |
| | 569 | StaticRounding, |
| | 570 | |
| | 571 | /* Supress All Exceptions is supported. */ |
| | 572 | SAE, |
| | 573 | |
| | 574 | /* Copressed Disp8*N attribute. */ |
| | 575 | Disp8MemShift, |
| | 576 | |
| | 577 | /* Default mask isn't allowed. */ |
| | 578 | NoDefMask, |
| | 579 | |
| | 580 | /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. |
| | 581 | It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). |
| | 582 | */ |
| | 583 | ImplicitQuadGroup, |
| | 584 | |
| | 585 | /* Compatible with old (<= 2.8.1) versions of gcc */ |
| | 586 | OldGcc, |
| | 587 | /* AT&T mnemonic. */ |
| | 588 | ATTMnemonic, |
| | 589 | /* AT&T syntax. */ |
| | 590 | ATTSyntax, |
| | 591 | /* Intel syntax. */ |
| | 592 | IntelSyntax, |
| | 593 | /* AMD64. */ |
| | 594 | AMD64, |
| | 595 | /* Intel64. */ |
| | 596 | Intel64, |
| | 597 | /* The last bitfield in i386_opcode_modifier. */ |
| | 598 | Opcode_Modifier_Max |
| | 599 | }; |
| | 600 | |
| | 601 | typedef struct i386_opcode_modifier |
| | 602 | { |
| | 603 | unsigned int d:1; |
| | 604 | unsigned int w:1; |
| | 605 | unsigned int load:1; |
| | 606 | unsigned int modrm:1; |
| | 607 | unsigned int shortform:1; |
| | 608 | unsigned int jump:1; |
| | 609 | unsigned int jumpdword:1; |
| | 610 | unsigned int jumpbyte:1; |
| | 611 | unsigned int jumpintersegment:1; |
| | 612 | unsigned int floatmf:1; |
| | 613 | unsigned int floatr:1; |
| | 614 | unsigned int floatd:1; |
| | 615 | unsigned int size16:1; |
| | 616 | unsigned int size32:1; |
| | 617 | unsigned int size64:1; |
| | 618 | unsigned int checkregsize:1; |
| | 619 | unsigned int ignoresize:1; |
| | 620 | unsigned int defaultsize:1; |
| | 621 | unsigned int no_bsuf:1; |
| | 622 | unsigned int no_wsuf:1; |
| | 623 | unsigned int no_lsuf:1; |
| | 624 | unsigned int no_ssuf:1; |
| | 625 | unsigned int no_qsuf:1; |
| | 626 | unsigned int no_ldsuf:1; |
| | 627 | unsigned int fwait:1; |
| | 628 | unsigned int isstring:1; |
| | 629 | unsigned int bndprefixok:1; |
| | 630 | unsigned int notrackprefixok:1; |
| | 631 | unsigned int islockable:1; |
| | 632 | unsigned int regkludge:1; |
| | 633 | unsigned int firstxmm0:1; |
| | 634 | unsigned int implicit1stxmm0:1; |
| | 635 | unsigned int hleprefixok:2; |
| | 636 | unsigned int repprefixok:1; |
| | 637 | unsigned int todword:1; |
| | 638 | unsigned int toqword:1; |
| | 639 | unsigned int addrprefixop0:1; |
| | 640 | unsigned int isprefix:1; |
| | 641 | unsigned int immext:1; |
| | 642 | unsigned int norex64:1; |
| | 643 | unsigned int rex64:1; |
| | 644 | unsigned int ugh:1; |
| | 645 | unsigned int vex:2; |
| | 646 | unsigned int vexvvvv:2; |
| | 647 | unsigned int vexw:2; |
| | 648 | unsigned int vexopcode:3; |
| | 649 | unsigned int vexsources:2; |
| | 650 | unsigned int veximmext:1; |
| | 651 | unsigned int vecsib:2; |
| | 652 | unsigned int sse2avx:1; |
| | 653 | unsigned int noavx:1; |
| | 654 | unsigned int evex:3; |
| | 655 | unsigned int masking:2; |
| | 656 | unsigned int vecesize:1; |
| | 657 | unsigned int broadcast:3; |
| | 658 | unsigned int staticrounding:1; |
| | 659 | unsigned int sae:1; |
| | 660 | unsigned int disp8memshift:3; |
| | 661 | unsigned int nodefmask:1; |
| | 662 | unsigned int implicitquadgroup:1; |
| | 663 | unsigned int oldgcc:1; |
| | 664 | unsigned int attmnemonic:1; |
| | 665 | unsigned int attsyntax:1; |
| | 666 | unsigned int intelsyntax:1; |
| | 667 | unsigned int amd64:1; |
| | 668 | unsigned int intel64:1; |
| | 669 | } i386_opcode_modifier; |
| | 670 | |
| | 671 | /* Position of operand_type bits. */ |
| | 672 | |
| | 673 | enum |
| | 674 | { |
| | 675 | /* 8bit register */ |
| | 676 | Reg8 = 0, |
| | 677 | /* 16bit register */ |
| | 678 | Reg16, |
| | 679 | /* 32bit register */ |
| | 680 | Reg32, |
| | 681 | /* 64bit register */ |
| | 682 | Reg64, |
| | 683 | /* Floating pointer stack register */ |
| | 684 | FloatReg, |
| | 685 | /* MMX register */ |
| | 686 | RegMMX, |
| | 687 | /* SSE register */ |
| | 688 | RegXMM, |
| | 689 | /* AVX registers */ |
| | 690 | RegYMM, |
| | 691 | /* AVX512 registers */ |
| | 692 | RegZMM, |
| | 693 | /* Vector Mask registers */ |
| | 694 | RegMask, |
| | 695 | /* Control register */ |
| | 696 | Control, |
| | 697 | /* Debug register */ |
| | 698 | Debug, |
| | 699 | /* Test register */ |
| | 700 | Test, |
| | 701 | /* 2 bit segment register */ |
| | 702 | SReg2, |
| | 703 | /* 3 bit segment register */ |
| | 704 | SReg3, |
| | 705 | /* 1 bit immediate */ |
| | 706 | Imm1, |
| | 707 | /* 8 bit immediate */ |
| | 708 | Imm8, |
| | 709 | /* 8 bit immediate sign extended */ |
| | 710 | Imm8S, |
| | 711 | /* 16 bit immediate */ |
| | 712 | Imm16, |
| | 713 | /* 32 bit immediate */ |
| | 714 | Imm32, |
| | 715 | /* 32 bit immediate sign extended */ |
| | 716 | Imm32S, |
| | 717 | /* 64 bit immediate */ |
| | 718 | Imm64, |
| | 719 | /* 8bit/16bit/32bit displacements are used in different ways, |
| | 720 | depending on the instruction. For jumps, they specify the |
| | 721 | size of the PC relative displacement, for instructions with |
| | 722 | memory operand, they specify the size of the offset relative |
| | 723 | to the base register, and for instructions with memory offset |
| | 724 | such as `mov 1234,%al' they specify the size of the offset |
| | 725 | relative to the segment base. */ |
| | 726 | /* 8 bit displacement */ |
| | 727 | Disp8, |
| | 728 | /* 16 bit displacement */ |
| | 729 | Disp16, |
| | 730 | /* 32 bit displacement */ |
| | 731 | Disp32, |
| | 732 | /* 32 bit signed displacement */ |
| | 733 | Disp32S, |
| | 734 | /* 64 bit displacement */ |
| | 735 | Disp64, |
| | 736 | /* Accumulator %al/%ax/%eax/%rax */ |
| | 737 | Acc, |
| | 738 | /* Floating pointer top stack register %st(0) */ |
| | 739 | FloatAcc, |
| | 740 | /* Register which can be used for base or index in memory operand. */ |
| | 741 | BaseIndex, |
| | 742 | /* Register to hold in/out port addr = dx */ |
| | 743 | InOutPortReg, |
| | 744 | /* Register to hold shift count = cl */ |
| | 745 | ShiftCount, |
| | 746 | /* Absolute address for jump. */ |
| | 747 | JumpAbsolute, |
| | 748 | /* String insn operand with fixed es segment */ |
| | 749 | EsSeg, |
| | 750 | /* RegMem is for instructions with a modrm byte where the register |
| | 751 | destination operand should be encoded in the mod and regmem fields. |
| | 752 | Normally, it will be encoded in the reg field. We add a RegMem |
| | 753 | flag to the destination register operand to indicate that it should |
| | 754 | be encoded in the regmem field. */ |
| | 755 | RegMem, |
| | 756 | /* Memory. */ |
| | 757 | Mem, |
| | 758 | /* BYTE memory. */ |
| | 759 | Byte, |
| | 760 | /* WORD memory. 2 byte */ |
| | 761 | Word, |
| | 762 | /* DWORD memory. 4 byte */ |
| | 763 | Dword, |
| | 764 | /* FWORD memory. 6 byte */ |
| | 765 | Fword, |
| | 766 | /* QWORD memory. 8 byte */ |
| | 767 | Qword, |
| | 768 | /* TBYTE memory. 10 byte */ |
| | 769 | Tbyte, |
| | 770 | /* XMMWORD memory. */ |
| | 771 | Xmmword, |
| | 772 | /* YMMWORD memory. */ |
| | 773 | Ymmword, |
| | 774 | /* ZMMWORD memory. */ |
| | 775 | Zmmword, |
| | 776 | /* Unspecified memory size. */ |
| | 777 | Unspecified, |
| | 778 | /* Any memory size. */ |
| | 779 | Anysize, |
| | 780 | |
| | 781 | /* Vector 4 bit immediate. */ |
| | 782 | Vec_Imm4, |
| | 783 | |
| | 784 | /* Bound register. */ |
| | 785 | RegBND, |
| | 786 | |
| | 787 | /* Vector 8bit displacement */ |
| | 788 | Vec_Disp8, |
| | 789 | |
| | 790 | /* The last bitfield in i386_operand_type. */ |
| | 791 | OTMax |
| | 792 | }; |
| | 793 | |
| | 794 | #define OTNumOfUints \ |
| | 795 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) |
| | 796 | #define OTNumOfBits \ |
| | 797 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
| | 798 | |
| | 799 | /* If you get a compiler error for zero width of the unused field, |
| | 800 | comment it out. */ |
| | 801 | #define OTUnused (OTMax + 1) |
| | 802 | |
| | 803 | typedef union i386_operand_type |
| | 804 | { |
| | 805 | struct |
| | 806 | { |
| | 807 | unsigned int reg8:1; |
| | 808 | unsigned int reg16:1; |
| | 809 | unsigned int reg32:1; |
| | 810 | unsigned int reg64:1; |
| | 811 | unsigned int floatreg:1; |
| | 812 | unsigned int regmmx:1; |
| | 813 | unsigned int regxmm:1; |
| | 814 | unsigned int regymm:1; |
| | 815 | unsigned int regzmm:1; |
| | 816 | unsigned int regmask:1; |
| | 817 | unsigned int control:1; |
| | 818 | unsigned int debug:1; |
| | 819 | unsigned int test:1; |
| | 820 | unsigned int sreg2:1; |
| | 821 | unsigned int sreg3:1; |
| | 822 | unsigned int imm1:1; |
| | 823 | unsigned int imm8:1; |
| | 824 | unsigned int imm8s:1; |
| | 825 | unsigned int imm16:1; |
| | 826 | unsigned int imm32:1; |
| | 827 | unsigned int imm32s:1; |
| | 828 | unsigned int imm64:1; |
| | 829 | unsigned int disp8:1; |
| | 830 | unsigned int disp16:1; |
| | 831 | unsigned int disp32:1; |
| | 832 | unsigned int disp32s:1; |
| | 833 | unsigned int disp64:1; |
| | 834 | unsigned int acc:1; |
| | 835 | unsigned int floatacc:1; |
| | 836 | unsigned int baseindex:1; |
| | 837 | unsigned int inoutportreg:1; |
| | 838 | unsigned int shiftcount:1; |
| | 839 | unsigned int jumpabsolute:1; |
| | 840 | unsigned int esseg:1; |
| | 841 | unsigned int regmem:1; |
| | 842 | unsigned int mem:1; |
| | 843 | unsigned int byte:1; |
| | 844 | unsigned int word:1; |
| | 845 | unsigned int dword:1; |
| | 846 | unsigned int fword:1; |
| | 847 | unsigned int qword:1; |
| | 848 | unsigned int tbyte:1; |
| | 849 | unsigned int xmmword:1; |
| | 850 | unsigned int ymmword:1; |
| | 851 | unsigned int zmmword:1; |
| | 852 | unsigned int unspecified:1; |
| | 853 | unsigned int anysize:1; |
| | 854 | unsigned int vec_imm4:1; |
| | 855 | unsigned int regbnd:1; |
| | 856 | unsigned int vec_disp8:1; |
| | 857 | #ifdef OTUnused |
| | 858 | unsigned int unused:(OTNumOfBits - OTUnused); |
| | 859 | #endif |
| | 860 | } bitfield; |
| | 861 | unsigned int array[OTNumOfUints]; |
| | 862 | } i386_operand_type; |
| | 863 | |
| | 864 | typedef struct insn_template |
| | 865 | { |
| | 866 | /* instruction name sans width suffix ("mov" for movl insns) */ |
| | 867 | char *name; |
| | 868 | |
| | 869 | /* how many operands */ |
| | 870 | unsigned int operands; |
| | 871 | |
| | 872 | /* base_opcode is the fundamental opcode byte without optional |
| | 873 | prefix(es). */ |
| | 874 | unsigned int base_opcode; |
| | 875 | #define Opcode_D 0x2 /* Direction bit: |
| | 876 | set if Reg --> Regmem; |
| | 877 | unset if Regmem --> Reg. */ |
| | 878 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ |
| | 879 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ |
| | 880 | |
| | 881 | /* extension_opcode is the 3 bit extension for group <n> insns. |
| | 882 | This field is also used to store the 8-bit opcode suffix for the |
| | 883 | AMD 3DNow! instructions. |
| | 884 | If this template has no extension opcode (the usual case) use None |
| | 885 | Instructions */ |
| | 886 | unsigned int extension_opcode; |
| | 887 | #define None 0xffff /* If no extension_opcode is possible. */ |
| | 888 | |
| | 889 | /* Opcode length. */ |
| | 890 | unsigned char opcode_length; |
| | 891 | |
| | 892 | /* cpu feature flags */ |
| | 893 | i386_cpu_flags cpu_flags; |
| | 894 | |
| | 895 | /* the bits in opcode_modifier are used to generate the final opcode from |
| | 896 | the base_opcode. These bits also are used to detect alternate forms of |
| | 897 | the same instruction */ |
| | 898 | i386_opcode_modifier opcode_modifier; |
| | 899 | |
| | 900 | /* operand_types[i] describes the type of operand i. This is made |
| | 901 | by OR'ing together all of the possible type masks. (e.g. |
| | 902 | 'operand_types[i] = Reg|Imm' specifies that operand i can be |
| | 903 | either a register or an immediate operand. */ |
| | 904 | i386_operand_type operand_types[MAX_OPERANDS]; |
| | 905 | } |
| | 906 | insn_template; |
| | 907 | |
| | 908 | extern const insn_template i386_optab[]; |
| | 909 | |
| | 910 | /* these are for register name --> number & type hash lookup */ |
| | 911 | typedef struct |
| | 912 | { |
| | 913 | char *reg_name; |
| | 914 | i386_operand_type reg_type; |
| | 915 | unsigned char reg_flags; |
| | 916 | #define RegRex 0x1 /* Extended register. */ |
| | 917 | #define RegRex64 0x2 /* Extended 8 bit register. */ |
| | 918 | #define RegVRex 0x4 /* Extended vector register. */ |
| | 919 | unsigned char reg_num; |
| | 920 | #define RegRip ((unsigned char ) ~0) |
| | 921 | #define RegEip (RegRip - 1) |
| | 922 | /* EIZ and RIZ are fake index registers. */ |
| | 923 | #define RegEiz (RegEip - 1) |
| | 924 | #define RegRiz (RegEiz - 1) |
| | 925 | /* FLAT is a fake segment register (Intel mode). */ |
| | 926 | #define RegFlat ((unsigned char) ~0) |
| | 927 | signed char dw2_regnum[2]; |
| | 928 | #define Dw2Inval (-1) |
| | 929 | } |
| | 930 | reg_entry; |
| | 931 | |
| | 932 | /* Entries in i386_regtab. */ |
| | 933 | #define REGNAM_AL 1 |
| | 934 | #define REGNAM_AX 25 |
| | 935 | #define REGNAM_EAX 41 |
| | 936 | |
| | 937 | extern const reg_entry i386_regtab[]; |
| | 938 | extern const unsigned int i386_regtab_size; |
| | 939 | |
| | 940 | typedef struct |
| | 941 | { |
| | 942 | char *seg_name; |
| | 943 | unsigned int seg_prefix; |
| | 944 | } |
| | 945 | seg_entry; |
| | 946 | |
| | 947 | extern const seg_entry cs; |
| | 948 | extern const seg_entry ds; |
| | 949 | extern const seg_entry ss; |
| | 950 | extern const seg_entry es; |
| | 951 | extern const seg_entry fs; |
| | 952 | extern const seg_entry gs; |
projects / deliverable / binutils-gdb.git / blame_incremental