| 1 | /* Declarations for Intel 80386 opcode table |
| 2 | Copyright 2007 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of the GNU opcodes library. |
| 6 | |
| 7 | This library is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | It is distributed in the hope that it will be useful, but WITHOUT |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 15 | License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to the Free |
| 19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | 02110-1301, USA. */ |
| 21 | |
| 22 | #include "opcode/i386.h" |
| 23 | #ifdef HAVE_LIMITS_H |
| 24 | #include <limits.h> |
| 25 | #endif |
| 26 | |
| 27 | #ifndef CHAR_BIT |
| 28 | #define CHAR_BIT 8 |
| 29 | #endif |
| 30 | |
| 31 | /* Position of cpu flags bitfiled. */ |
| 32 | |
| 33 | /* i186 or better required */ |
| 34 | #define Cpu186 0 |
| 35 | /* i286 or better required */ |
| 36 | #define Cpu286 (Cpu186 + 1) |
| 37 | /* i386 or better required */ |
| 38 | #define Cpu386 (Cpu286 + 1) |
| 39 | /* i486 or better required */ |
| 40 | #define Cpu486 (Cpu386 + 1) |
| 41 | /* i585 or better required */ |
| 42 | #define Cpu586 (Cpu486 + 1) |
| 43 | /* i686 or better required */ |
| 44 | #define Cpu686 (Cpu586 + 1) |
| 45 | /* Pentium4 or better required */ |
| 46 | #define CpuP4 (Cpu686 + 1) |
| 47 | /* AMD K6 or better required*/ |
| 48 | #define CpuK6 (CpuP4 + 1) |
| 49 | /* AMD K8 or better required */ |
| 50 | #define CpuK8 (CpuK6 + 1) |
| 51 | /* MMX support required */ |
| 52 | #define CpuMMX (CpuK8 + 1) |
| 53 | /* extended MMX support (with SSE or 3DNow!Ext) required */ |
| 54 | #define CpuMMX2 (CpuMMX + 1) |
| 55 | /* SSE support required */ |
| 56 | #define CpuSSE (CpuMMX2 + 1) |
| 57 | /* SSE2 support required */ |
| 58 | #define CpuSSE2 (CpuSSE + 1) |
| 59 | /* 3dnow! support required */ |
| 60 | #define Cpu3dnow (CpuSSE2 + 1) |
| 61 | /* 3dnow! Extensions support required */ |
| 62 | #define Cpu3dnowA (Cpu3dnow + 1) |
| 63 | /* SSE3 support required */ |
| 64 | #define CpuSSE3 (Cpu3dnowA + 1) |
| 65 | /* VIA PadLock required */ |
| 66 | #define CpuPadLock (CpuSSE3 + 1) |
| 67 | /* AMD Secure Virtual Machine Ext-s required */ |
| 68 | #define CpuSVME (CpuPadLock + 1) |
| 69 | /* VMX Instructions required */ |
| 70 | #define CpuVMX (CpuSVME + 1) |
| 71 | /* SSSE3 support required */ |
| 72 | #define CpuSSSE3 (CpuVMX + 1) |
| 73 | /* SSE4a support required */ |
| 74 | #define CpuSSE4a (CpuSSSE3 + 1) |
| 75 | /* ABM New Instructions required */ |
| 76 | #define CpuABM (CpuSSE4a + 1) |
| 77 | /* SSE4.1 support required */ |
| 78 | #define CpuSSE4_1 (CpuABM + 1) |
| 79 | /* SSE4.2 support required */ |
| 80 | #define CpuSSE4_2 (CpuSSE4_1 + 1) |
| 81 | /* SSE5 support required */ |
| 82 | #define CpuSSE5 (CpuSSE4_2 + 1) |
| 83 | /* 64bit support available, used by -march= in assembler. */ |
| 84 | #define CpuLM (CpuSSE5 + 1) |
| 85 | /* 64bit support required */ |
| 86 | #define Cpu64 (CpuLM + 1) |
| 87 | /* Not supported in the 64bit mode */ |
| 88 | #define CpuNo64 (Cpu64 + 1) |
| 89 | /* The last bitfield in i386_cpu_flags. */ |
| 90 | #define CpuMax CpuNo64 |
| 91 | |
| 92 | #define CpuNumOfUints \ |
| 93 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) |
| 94 | #define CpuNumOfBits \ |
| 95 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
| 96 | |
| 97 | /* If you get a compiler error for zero width of the unused field, |
| 98 | comment it out. */ |
| 99 | #define CpuUnused (CpuMax + 1) |
| 100 | |
| 101 | /* We can check if an instruction is available with array instead |
| 102 | of bitfield. */ |
| 103 | typedef union i386_cpu_flags |
| 104 | { |
| 105 | struct |
| 106 | { |
| 107 | unsigned int cpui186:1; |
| 108 | unsigned int cpui286:1; |
| 109 | unsigned int cpui386:1; |
| 110 | unsigned int cpui486:1; |
| 111 | unsigned int cpui586:1; |
| 112 | unsigned int cpui686:1; |
| 113 | unsigned int cpup4:1; |
| 114 | unsigned int cpuk6:1; |
| 115 | unsigned int cpuk8:1; |
| 116 | unsigned int cpummx:1; |
| 117 | unsigned int cpummx2:1; |
| 118 | unsigned int cpusse:1; |
| 119 | unsigned int cpusse2:1; |
| 120 | unsigned int cpua3dnow:1; |
| 121 | unsigned int cpua3dnowa:1; |
| 122 | unsigned int cpusse3:1; |
| 123 | unsigned int cpupadlock:1; |
| 124 | unsigned int cpusvme:1; |
| 125 | unsigned int cpuvmx:1; |
| 126 | unsigned int cpussse3:1; |
| 127 | unsigned int cpusse4a:1; |
| 128 | unsigned int cpuabm:1; |
| 129 | unsigned int cpusse4_1:1; |
| 130 | unsigned int cpusse4_2:1; |
| 131 | unsigned int cpusse5:1; |
| 132 | unsigned int cpulm:1; |
| 133 | unsigned int cpu64:1; |
| 134 | unsigned int cpuno64:1; |
| 135 | #ifdef CpuUnused |
| 136 | unsigned int unused:(CpuNumOfBits - CpuUnused); |
| 137 | #endif |
| 138 | } bitfield; |
| 139 | unsigned int array[CpuNumOfUints]; |
| 140 | } i386_cpu_flags; |
| 141 | |
| 142 | /* Position of opcode_modifier bits. */ |
| 143 | |
| 144 | /* has direction bit. */ |
| 145 | #define D 0 |
| 146 | /* set if operands can be words or dwords encoded the canonical way */ |
| 147 | #define W (D + 1) |
| 148 | /* insn has a modrm byte. */ |
| 149 | #define Modrm (W + 1) |
| 150 | /* register is in low 3 bits of opcode */ |
| 151 | #define ShortForm (Modrm + 1) |
| 152 | /* special case for jump insns. */ |
| 153 | #define Jump (ShortForm + 1) |
| 154 | /* call and jump */ |
| 155 | #define JumpDword (Jump + 1) |
| 156 | /* loop and jecxz */ |
| 157 | #define JumpByte (JumpDword + 1) |
| 158 | /* special case for intersegment leaps/calls */ |
| 159 | #define JumpInterSegment (JumpByte + 1) |
| 160 | /* FP insn memory format bit, sized by 0x4 */ |
| 161 | #define FloatMF (JumpInterSegment + 1) |
| 162 | /* src/dest swap for floats. */ |
| 163 | #define FloatR (FloatMF + 1) |
| 164 | /* has float insn direction bit. */ |
| 165 | #define FloatD (FloatR + 1) |
| 166 | /* needs size prefix if in 32-bit mode */ |
| 167 | #define Size16 (FloatD + 1) |
| 168 | /* needs size prefix if in 16-bit mode */ |
| 169 | #define Size32 (Size16 + 1) |
| 170 | /* needs size prefix if in 64-bit mode */ |
| 171 | #define Size64 (Size32 + 1) |
| 172 | /* instruction ignores operand size prefix */ |
| 173 | #define IgnoreSize (Size64 + 1) |
| 174 | /* default insn size depends on mode */ |
| 175 | #define DefaultSize (IgnoreSize + 1) |
| 176 | /* b suffix on instruction illegal */ |
| 177 | #define No_bSuf (DefaultSize + 1) |
| 178 | /* w suffix on instruction illegal */ |
| 179 | #define No_wSuf (No_bSuf + 1) |
| 180 | /* l suffix on instruction illegal */ |
| 181 | #define No_lSuf (No_wSuf + 1) |
| 182 | /* s suffix on instruction illegal */ |
| 183 | #define No_sSuf (No_lSuf + 1) |
| 184 | /* q suffix on instruction illegal */ |
| 185 | #define No_qSuf (No_sSuf + 1) |
| 186 | /* x suffix on instruction illegal */ |
| 187 | #define No_xSuf (No_qSuf + 1) |
| 188 | /* instruction needs FWAIT */ |
| 189 | #define FWait (No_xSuf + 1) |
| 190 | /* quick test for string instructions */ |
| 191 | #define IsString (FWait + 1) |
| 192 | /* fake an extra reg operand for clr, imul and special register |
| 193 | processing for some instructions. */ |
| 194 | #define RegKludge (IsString + 1) |
| 195 | /* opcode is a prefix */ |
| 196 | #define IsPrefix (RegKludge + 1) |
| 197 | /* instruction has extension in 8 bit imm */ |
| 198 | #define ImmExt (IsPrefix + 1) |
| 199 | /* instruction don't need Rex64 prefix. */ |
| 200 | #define NoRex64 (ImmExt + 1) |
| 201 | /* instruction require Rex64 prefix. */ |
| 202 | #define Rex64 (NoRex64 + 1) |
| 203 | /* deprecated fp insn, gets a warning */ |
| 204 | #define Ugh (Rex64 + 1) |
| 205 | #define Drex (Ugh + 1) |
| 206 | /* instruction needs DREX with multiple encodings for memory ops */ |
| 207 | #define Drexv (Drex + 1) |
| 208 | /* special DREX for comparisons */ |
| 209 | #define Drexc (Drexv + 1) |
| 210 | /* The last bitfield in i386_opcode_modifier. */ |
| 211 | #define Opcode_Modifier_Max Drexc |
| 212 | |
| 213 | typedef struct i386_opcode_modifier |
| 214 | { |
| 215 | unsigned int d:1; |
| 216 | unsigned int w:1; |
| 217 | unsigned int modrm:1; |
| 218 | unsigned int shortform:1; |
| 219 | unsigned int jump:1; |
| 220 | unsigned int jumpdword:1; |
| 221 | unsigned int jumpbyte:1; |
| 222 | unsigned int jumpintersegment:1; |
| 223 | unsigned int floatmf:1; |
| 224 | unsigned int floatr:1; |
| 225 | unsigned int floatd:1; |
| 226 | unsigned int size16:1; |
| 227 | unsigned int size32:1; |
| 228 | unsigned int size64:1; |
| 229 | unsigned int ignoresize:1; |
| 230 | unsigned int defaultsize:1; |
| 231 | unsigned int no_bsuf:1; |
| 232 | unsigned int no_wsuf:1; |
| 233 | unsigned int no_lsuf:1; |
| 234 | unsigned int no_ssuf:1; |
| 235 | unsigned int no_qsuf:1; |
| 236 | unsigned int no_xsuf:1; |
| 237 | unsigned int fwait:1; |
| 238 | unsigned int isstring:1; |
| 239 | unsigned int regkludge:1; |
| 240 | unsigned int isprefix:1; |
| 241 | unsigned int immext:1; |
| 242 | unsigned int norex64:1; |
| 243 | unsigned int rex64:1; |
| 244 | unsigned int ugh:1; |
| 245 | unsigned int drex:1; |
| 246 | unsigned int drexv:1; |
| 247 | unsigned int drexc:1; |
| 248 | } i386_opcode_modifier; |
| 249 | |
| 250 | /* Position of operand_type bits. */ |
| 251 | |
| 252 | /* Registers */ |
| 253 | |
| 254 | /* 8 bit reg */ |
| 255 | #define Reg8 0 |
| 256 | /* 16 bit reg */ |
| 257 | #define Reg16 (Reg8 + 1) |
| 258 | /* 32 bit reg */ |
| 259 | #define Reg32 (Reg16 + 1) |
| 260 | /* 64 bit reg */ |
| 261 | #define Reg64 (Reg32 + 1) |
| 262 | |
| 263 | /* immediate */ |
| 264 | |
| 265 | /* 8 bit immediate */ |
| 266 | #define Imm8 (Reg64 + 1) |
| 267 | /* 8 bit immediate sign extended */ |
| 268 | #define Imm8S (Imm8 + 1) |
| 269 | /* 16 bit immediate */ |
| 270 | #define Imm16 (Imm8S + 1) |
| 271 | /* 32 bit immediate */ |
| 272 | #define Imm32 (Imm16 + 1) |
| 273 | /* 32 bit immediate sign extended */ |
| 274 | #define Imm32S (Imm32 + 1) |
| 275 | /* 64 bit immediate */ |
| 276 | #define Imm64 (Imm32S + 1) |
| 277 | /* 1 bit immediate */ |
| 278 | #define Imm1 (Imm64 + 1) |
| 279 | |
| 280 | /* memory */ |
| 281 | |
| 282 | #define BaseIndex (Imm1 + 1) |
| 283 | /* Disp8,16,32 are used in different ways, depending on the |
| 284 | instruction. For jumps, they specify the size of the PC relative |
| 285 | displacement, for baseindex type instructions, they specify the |
| 286 | size of the offset relative to the base register, and for memory |
| 287 | offset instructions such as `mov 1234,%al' they specify the size of |
| 288 | the offset relative to the segment base. */ |
| 289 | /* 8 bit displacement */ |
| 290 | #define Disp8 (BaseIndex + 1) |
| 291 | /* 16 bit displacement */ |
| 292 | #define Disp16 (Disp8 + 1) |
| 293 | /* 32 bit displacement */ |
| 294 | #define Disp32 (Disp16 + 1) |
| 295 | /* 32 bit signed displacement */ |
| 296 | #define Disp32S (Disp32 + 1) |
| 297 | /* 64 bit displacement */ |
| 298 | #define Disp64 (Disp32S + 1) |
| 299 | |
| 300 | /* specials */ |
| 301 | |
| 302 | /* register to hold in/out port addr = dx */ |
| 303 | #define InOutPortReg (Disp64 + 1) |
| 304 | /* register to hold shift count = cl */ |
| 305 | #define ShiftCount (InOutPortReg + 1) |
| 306 | /* Control register */ |
| 307 | #define Control (ShiftCount + 1) |
| 308 | /* Debug register */ |
| 309 | #define Debug (Control + 1) |
| 310 | /* Test register */ |
| 311 | #define Test (Debug + 1) |
| 312 | /* Float register */ |
| 313 | #define FloatReg (Test + 1) |
| 314 | /* Float stack top %st(0) */ |
| 315 | #define FloatAcc (FloatReg + 1) |
| 316 | /* 2 bit segment register */ |
| 317 | #define SReg2 (FloatAcc + 1) |
| 318 | /* 3 bit segment register */ |
| 319 | #define SReg3 (SReg2 + 1) |
| 320 | /* Accumulator %al or %ax or %eax */ |
| 321 | #define Acc (SReg3 + 1) |
| 322 | #define JumpAbsolute (Acc + 1) |
| 323 | /* MMX register */ |
| 324 | #define RegMMX (JumpAbsolute + 1) |
| 325 | /* XMM registers in PIII */ |
| 326 | #define RegXMM (RegMMX + 1) |
| 327 | /* String insn operand with fixed es segment */ |
| 328 | #define EsSeg (RegXMM + 1) |
| 329 | |
| 330 | /* RegMem is for instructions with a modrm byte where the register |
| 331 | destination operand should be encoded in the mod and regmem fields. |
| 332 | Normally, it will be encoded in the reg field. We add a RegMem |
| 333 | flag to the destination register operand to indicate that it should |
| 334 | be encoded in the regmem field. */ |
| 335 | #define RegMem (EsSeg + 1) |
| 336 | |
| 337 | /* The last bitfield in i386_operand_type. */ |
| 338 | #define OTMax RegMem |
| 339 | |
| 340 | #define OTNumOfUints \ |
| 341 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) |
| 342 | #define OTNumOfBits \ |
| 343 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
| 344 | |
| 345 | /* If you get a compiler error for zero width of the unused field, |
| 346 | comment it out. */ |
| 347 | #if 0 |
| 348 | #define OTUnused (OTMax + 1) |
| 349 | #endif |
| 350 | |
| 351 | typedef union i386_operand_type |
| 352 | { |
| 353 | struct |
| 354 | { |
| 355 | unsigned int reg8:1; |
| 356 | unsigned int reg16:1; |
| 357 | unsigned int reg32:1; |
| 358 | unsigned int reg64:1; |
| 359 | unsigned int imm8:1; |
| 360 | unsigned int imm8s:1; |
| 361 | unsigned int imm16:1; |
| 362 | unsigned int imm32:1; |
| 363 | unsigned int imm32s:1; |
| 364 | unsigned int imm64:1; |
| 365 | unsigned int imm1:1; |
| 366 | unsigned int baseindex:1; |
| 367 | unsigned int disp8:1; |
| 368 | unsigned int disp16:1; |
| 369 | unsigned int disp32:1; |
| 370 | unsigned int disp32s:1; |
| 371 | unsigned int disp64:1; |
| 372 | unsigned int inoutportreg:1; |
| 373 | unsigned int shiftcount:1; |
| 374 | unsigned int control:1; |
| 375 | unsigned int debug:1; |
| 376 | unsigned int test:1; |
| 377 | unsigned int floatreg:1; |
| 378 | unsigned int floatacc:1; |
| 379 | unsigned int sreg2:1; |
| 380 | unsigned int sreg3:1; |
| 381 | unsigned int acc:1; |
| 382 | unsigned int jumpabsolute:1; |
| 383 | unsigned int regmmx:1; |
| 384 | unsigned int regxmm:1; |
| 385 | unsigned int esseg:1; |
| 386 | unsigned int regmem:1; |
| 387 | #ifdef OTUnused |
| 388 | unsigned int unused:(OTNumOfBits - OTUnused); |
| 389 | #endif |
| 390 | } bitfield; |
| 391 | unsigned int array[OTNumOfUints]; |
| 392 | } i386_operand_type; |
| 393 | |
| 394 | typedef struct template |
| 395 | { |
| 396 | /* instruction name sans width suffix ("mov" for movl insns) */ |
| 397 | char *name; |
| 398 | |
| 399 | /* how many operands */ |
| 400 | unsigned int operands; |
| 401 | |
| 402 | /* base_opcode is the fundamental opcode byte without optional |
| 403 | prefix(es). */ |
| 404 | unsigned int base_opcode; |
| 405 | #define Opcode_D 0x2 /* Direction bit: |
| 406 | set if Reg --> Regmem; |
| 407 | unset if Regmem --> Reg. */ |
| 408 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ |
| 409 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ |
| 410 | |
| 411 | /* extension_opcode is the 3 bit extension for group <n> insns. |
| 412 | This field is also used to store the 8-bit opcode suffix for the |
| 413 | AMD 3DNow! instructions. |
| 414 | If this template has no extension opcode (the usual case) use None |
| 415 | Instructions with Drex use this to specify 2 bits for OC */ |
| 416 | unsigned int extension_opcode; |
| 417 | #define None 0xffff /* If no extension_opcode is possible. */ |
| 418 | |
| 419 | /* Opcode length. */ |
| 420 | unsigned char opcode_length; |
| 421 | |
| 422 | /* cpu feature flags */ |
| 423 | i386_cpu_flags cpu_flags; |
| 424 | |
| 425 | /* the bits in opcode_modifier are used to generate the final opcode from |
| 426 | the base_opcode. These bits also are used to detect alternate forms of |
| 427 | the same instruction */ |
| 428 | i386_opcode_modifier opcode_modifier; |
| 429 | |
| 430 | /* operand_types[i] describes the type of operand i. This is made |
| 431 | by OR'ing together all of the possible type masks. (e.g. |
| 432 | 'operand_types[i] = Reg|Imm' specifies that operand i can be |
| 433 | either a register or an immediate operand. */ |
| 434 | i386_operand_type operand_types[MAX_OPERANDS]; |
| 435 | } |
| 436 | template; |
| 437 | |
| 438 | extern const template i386_optab[]; |
| 439 | |
| 440 | /* these are for register name --> number & type hash lookup */ |
| 441 | typedef struct |
| 442 | { |
| 443 | char *reg_name; |
| 444 | i386_operand_type reg_type; |
| 445 | unsigned int reg_flags; |
| 446 | #define RegRex 0x1 /* Extended register. */ |
| 447 | #define RegRex64 0x2 /* Extended 8 bit register. */ |
| 448 | unsigned int reg_num; |
| 449 | #define RegRip ((unsigned int ) ~0) |
| 450 | #define RegEip (RegRip - 1) |
| 451 | /* EIZ and RIZ are fake index registers. */ |
| 452 | #define RegEiz (RegEip - 1) |
| 453 | #define RegRiz (RegEiz - 1) |
| 454 | } |
| 455 | reg_entry; |
| 456 | |
| 457 | /* Entries in i386_regtab. */ |
| 458 | #define REGNAM_AL 1 |
| 459 | #define REGNAM_AX 25 |
| 460 | #define REGNAM_EAX 41 |
| 461 | |
| 462 | extern const reg_entry i386_regtab[]; |
| 463 | extern const unsigned int i386_regtab_size; |
| 464 | |
| 465 | typedef struct |
| 466 | { |
| 467 | char *seg_name; |
| 468 | unsigned int seg_prefix; |
| 469 | } |
| 470 | seg_entry; |
| 471 | |
| 472 | extern const seg_entry cs; |
| 473 | extern const seg_entry ds; |
| 474 | extern const seg_entry ss; |
| 475 | extern const seg_entry es; |
| 476 | extern const seg_entry fs; |
| 477 | extern const seg_entry gs; |