| 1 | // i386 opcode table. |
| 2 | |
| 3 | // Move instructions. |
| 4 | // We put the 64bit displacement first and we only mark constants |
| 5 | // larger than 32bit as Disp64. |
| 6 | mov, 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, { Disp64, Acc } |
| 7 | mov, 2, 0xa0, None, CpuNo64, D|W|No_sSuf|No_qSuf|No_xSuf, { Disp16|Disp32, Acc } |
| 8 | mov, 2, 0x88, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 9 | // In the 64bit mode the short form mov immediate is redefined to have |
| 10 | // 64bit value. |
| 11 | mov, 2, 0xb0, None, 0, W|ShortForm|No_sSuf|No_qSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } |
| 12 | mov, 2, 0xc6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 13 | mov, 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { Imm64, Reg64 } |
| 14 | // The segment register moves accept WordReg so that a segment register |
| 15 | // can be copied to a 32 bit register, and vice versa, without using a |
| 16 | // size prefix. When moving to a 32 bit register, the upper 16 bits |
| 17 | // are set to an implementation defined value (on the Pentium Pro, the |
| 18 | // implementation defined value is zero). |
| 19 | mov, 2, 0x8c, None, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, Reg16|Reg32|Reg64|RegMem } |
| 20 | mov, 2, 0x8c, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 21 | mov, 2, 0x8c, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, Reg16|Reg32|Reg64|RegMem } |
| 22 | mov, 2, 0x8c, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 23 | mov, 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, SReg2 } |
| 24 | mov, 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 } |
| 25 | mov, 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, SReg3 } |
| 26 | mov, 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 } |
| 27 | // Move to/from control debug registers. In the 16 or 32bit modes |
| 28 | // they are 32bit. In the 64bit mode they are 64bit. |
| 29 | mov, 2, 0xf20, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Control, Reg32|RegMem } |
| 30 | mov, 2, 0xf20, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Control, Reg64|RegMem } |
| 31 | mov, 2, 0xf21, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Debug, Reg32|RegMem } |
| 32 | mov, 2, 0xf21, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Debug, Reg64|RegMem } |
| 33 | mov, 2, 0xf24, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Test, Reg32|RegMem } |
| 34 | movabs, 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, { Disp64, Acc } |
| 35 | movabs, 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { Imm64, Reg64 } |
| 36 | |
| 37 | // Move with sign extend. |
| 38 | // "movsbl" & "movsbw" must not be unified into "movsb" to avoid |
| 39 | // conflict with the "movs" string move instruction. |
| 40 | movsbl, 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 41 | movsbw, 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } |
| 42 | movswl, 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 43 | movsbq, 2, 0xfbe, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 44 | movswq, 2, 0xfbf, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 45 | movslq, 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 46 | // Intel Syntax next 3 insns |
| 47 | movsx, 2, 0xfbe, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 48 | movsx, 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } |
| 49 | movsx, 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 50 | |
| 51 | // Move with zero extend. We can't remove "movzb" since existing |
| 52 | // assembly codes may use it. |
| 53 | movzb, 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 54 | // "movzbl" & "movzbw" should not be unified into "movzb" for |
| 55 | // consistency with the sign extending moves above. |
| 56 | movzbl, 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 57 | movzbw, 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } |
| 58 | movzwl, 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 59 | // These instructions are not particulary useful, since the zero extend |
| 60 | // 32->64 is implicit, but we can encode them. |
| 61 | movzbq, 2, 0xfb6, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 62 | movzwq, 2, 0xfb7, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 63 | // Intel Syntax next 2 insns (the 64-bit variants are not particulary |
| 64 | // useful since the zero extend 32->64 is implicit, but we can encode them). |
| 65 | movzx, 2, 0xfb6, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 66 | movzx, 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } |
| 67 | |
| 68 | // Push instructions. |
| 69 | push, 1, 0x50, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 70 | push, 1, 0xff, 0x6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 71 | push, 1, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8S } |
| 72 | push, 1, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16|Imm32 } |
| 73 | push, 1, 0x6, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2 } |
| 74 | push, 1, 0xfa0, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3 } |
| 75 | // In 64bit mode, the operand size is implicitly 64bit. |
| 76 | push, 1, 0x50, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64 } |
| 77 | push, 1, 0xff, 0x6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 78 | push, 1, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm8S } |
| 79 | push, 1, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16|Imm32S } |
| 80 | push, 1, 0xfa0, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { SReg3 } |
| 81 | |
| 82 | pusha, 0, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 83 | |
| 84 | // Pop instructions. |
| 85 | pop, 1, 0x58, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 86 | pop, 1, 0x8f, 0x0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 87 | pop, 1, 0x7, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2 } |
| 88 | pop, 1, 0xfa1, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3 } |
| 89 | // In 64bit mode, the operand size is implicitly 64bit. |
| 90 | pop, 1, 0x58, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64 } |
| 91 | pop, 1, 0x8f, 0x0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 92 | pop, 1, 0xfa1, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { SReg3 } |
| 93 | |
| 94 | popa, 0, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 95 | |
| 96 | // Exchange instructions. |
| 97 | // xchg commutes: we allow both operand orders. |
| 98 | |
| 99 | // In the 64bit code, xchg rax, rax is reused for new nop instruction. |
| 100 | xchg, 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Acc } |
| 101 | xchg, 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, { Acc, Reg16|Reg32|Reg64 } |
| 102 | xchg, 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 103 | xchg, 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } |
| 104 | |
| 105 | // In/out from ports. |
| 106 | // XXX should reject %rax |
| 107 | in, 2, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8, Acc } |
| 108 | in, 2, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg, Acc } |
| 109 | in, 1, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8 } |
| 110 | in, 1, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg } |
| 111 | out, 2, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Acc, Imm8 } |
| 112 | out, 2, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Acc, InOutPortReg } |
| 113 | out, 1, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8 } |
| 114 | out, 1, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg } |
| 115 | |
| 116 | // Load effective address. |
| 117 | lea, 2, 0x8d, None, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 118 | |
| 119 | // Load segment registers from memory. |
| 120 | lds, 2, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 121 | les, 2, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 122 | lfs, 2, 0xfb4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 123 | lgs, 2, 0xfb5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 124 | lss, 2, 0xfb2, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 125 | |
| 126 | // Flags register instructions. |
| 127 | clc, 0, 0xf8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 128 | cld, 0, 0xfc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 129 | cli, 0, 0xfa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 130 | clts, 0, 0xf06, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 131 | cmc, 0, 0xf5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 132 | lahf, 0, 0x9f, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 133 | sahf, 0, 0x9e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 134 | pushf, 0, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 135 | pushf, 0, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } |
| 136 | popf, 0, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 137 | popf, 0, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } |
| 138 | stc, 0, 0xf9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 139 | std, 0, 0xfd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 140 | sti, 0, 0xfb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 141 | |
| 142 | // Arithmetic. |
| 143 | add, 2, 0x0, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 144 | add, 2, 0x83, 0x0, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 145 | add, 2, 0x4, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 146 | add, 2, 0x80, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 147 | |
| 148 | inc, 1, 0x40, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 149 | inc, 1, 0xfe, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 150 | |
| 151 | sub, 2, 0x28, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 152 | sub, 2, 0x83, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 153 | sub, 2, 0x2c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 154 | sub, 2, 0x80, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 155 | |
| 156 | dec, 1, 0x48, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 157 | dec, 1, 0xfe, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 158 | |
| 159 | sbb, 2, 0x18, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 160 | sbb, 2, 0x83, 0x3, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 161 | sbb, 2, 0x1c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 162 | sbb, 2, 0x80, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 163 | |
| 164 | cmp, 2, 0x38, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 165 | cmp, 2, 0x83, 0x7, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 166 | cmp, 2, 0x3c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 167 | cmp, 2, 0x80, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 168 | |
| 169 | test, 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 170 | test, 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } |
| 171 | test, 2, 0xa8, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 172 | test, 2, 0xf6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 173 | |
| 174 | and, 2, 0x20, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 175 | and, 2, 0x83, 0x4, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 176 | and, 2, 0x24, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 177 | and, 2, 0x80, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 178 | |
| 179 | or, 2, 0x8, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 180 | or, 2, 0x83, 0x1, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 181 | or, 2, 0xc, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 182 | or, 2, 0x80, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 183 | |
| 184 | xor, 2, 0x30, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 185 | xor, 2, 0x83, 0x6, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 186 | xor, 2, 0x34, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 187 | xor, 2, 0x80, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 188 | |
| 189 | // clr with 1 operand is really xor with 2 operands. |
| 190 | clr, 1, 0x30, None, 0, W|Modrm|No_sSuf|No_xSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 } |
| 191 | |
| 192 | adc, 2, 0x10, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 193 | adc, 2, 0x83, 0x2, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 194 | adc, 2, 0x14, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } |
| 195 | adc, 2, 0x80, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 196 | |
| 197 | neg, 1, 0xf6, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 198 | not, 1, 0xf6, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 199 | |
| 200 | aaa, 0, 0x37, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 201 | aas, 0, 0x3f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 202 | daa, 0, 0x27, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 203 | das, 0, 0x2f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 204 | aad, 0, 0xd50a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 205 | aad, 1, 0xd5, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } |
| 206 | aam, 0, 0xd40a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 207 | aam, 1, 0xd4, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } |
| 208 | |
| 209 | // Conversion insns. |
| 210 | // Intel naming |
| 211 | cbw, 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 212 | cdqe, 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 213 | cwde, 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 214 | cwd, 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 215 | cdq, 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 216 | cqo, 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 217 | // AT&T naming |
| 218 | cbtw, 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 219 | cltq, 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 220 | cwtl, 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 221 | cwtd, 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 222 | cltd, 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 223 | cqto, 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 224 | |
| 225 | // Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are |
| 226 | // expanding 64-bit multiplies, and *cannot* be selected to accomplish |
| 227 | // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) |
| 228 | // These multiplies can only be selected with single operand forms. |
| 229 | mul, 1, 0xf6, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 230 | imul, 1, 0xf6, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 231 | imul, 2, 0xfaf, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 232 | imul, 3, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 233 | imul, 3, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 234 | // imul with 2 operands mimics imul with 3 by putting the register in |
| 235 | // both i.rm.reg & i.rm.regmem fields. RegKludge enables this |
| 236 | // transformation. |
| 237 | imul, 2, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } |
| 238 | imul, 2, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } |
| 239 | |
| 240 | div, 1, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 241 | div, 2, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } |
| 242 | idiv, 1, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 243 | idiv, 2, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } |
| 244 | |
| 245 | rol, 2, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 246 | rol, 2, 0xc0, 0x0, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 247 | rol, 2, 0xd2, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 248 | rol, 1, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 249 | |
| 250 | ror, 2, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 251 | ror, 2, 0xc0, 0x1, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 252 | ror, 2, 0xd2, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 253 | ror, 1, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 254 | |
| 255 | rcl, 2, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 256 | rcl, 2, 0xc0, 0x2, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 257 | rcl, 2, 0xd2, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 258 | rcl, 1, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 259 | |
| 260 | rcr, 2, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 261 | rcr, 2, 0xc0, 0x3, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 262 | rcr, 2, 0xd2, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 263 | rcr, 1, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 264 | |
| 265 | sal, 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 266 | sal, 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 267 | sal, 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 268 | sal, 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 269 | |
| 270 | shl, 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 271 | shl, 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 272 | shl, 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 273 | shl, 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 274 | |
| 275 | shr, 2, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 276 | shr, 2, 0xc0, 0x5, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 277 | shr, 2, 0xd2, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 278 | shr, 1, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 279 | |
| 280 | sar, 2, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 281 | sar, 2, 0xc0, 0x7, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 282 | sar, 2, 0xd2, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 283 | sar, 1, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 284 | |
| 285 | shld, 3, 0xfa4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 286 | shld, 3, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 287 | shld, 2, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 288 | |
| 289 | shrd, 3, 0xfac, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 290 | shrd, 3, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 291 | shrd, 2, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 292 | |
| 293 | // Control transfer instructions. |
| 294 | call, 1, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp16|Disp32 } |
| 295 | call, 1, 0xe8, None, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Disp16|Disp32 } |
| 296 | call, 1, 0xff, 0x2, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 297 | call, 1, 0xff, 0x2, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 298 | // Intel Syntax |
| 299 | call, 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } |
| 300 | // Intel Syntax |
| 301 | call, 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 302 | lcall, 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } |
| 303 | lcall, 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 304 | |
| 305 | jmp, 1, 0xeb, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 306 | jmp, 1, 0xff, 0x4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 307 | jmp, 1, 0xff, 0x4, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 308 | // Intel Syntax. |
| 309 | jmp, 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } |
| 310 | // Intel Syntax. |
| 311 | jmp, 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 312 | ljmp, 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } |
| 313 | ljmp, 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } |
| 314 | |
| 315 | ret, 0, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 316 | ret, 1, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16 } |
| 317 | ret, 0, 0xc3, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } |
| 318 | ret, 1, 0xc2, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16 } |
| 319 | lret, 0, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { 0 } |
| 320 | lret, 1, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { Imm16 } |
| 321 | enter, 2, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm8 } |
| 322 | enter, 2, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16, Imm8 } |
| 323 | leave, 0, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 324 | leave, 0, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } |
| 325 | |
| 326 | // Conditional jumps. |
| 327 | jo, 1, 0x70, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 328 | jno, 1, 0x71, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 329 | jb, 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 330 | jc, 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 331 | jnae, 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 332 | jnb, 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 333 | jnc, 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 334 | jae, 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 335 | je, 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 336 | jz, 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 337 | jne, 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 338 | jnz, 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 339 | jbe, 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 340 | jna, 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 341 | jnbe, 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 342 | ja, 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 343 | js, 1, 0x78, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 344 | jns, 1, 0x79, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 345 | jp, 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 346 | jpe, 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 347 | jnp, 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 348 | jpo, 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 349 | jl, 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 350 | jnge, 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 351 | jnl, 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 352 | jge, 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 353 | jle, 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 354 | jng, 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 355 | jnle, 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 356 | jg, 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 357 | |
| 358 | // jcxz vs. jecxz is chosen on the basis of the address size prefix. |
| 359 | jcxz, 1, 0xe3, None, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 360 | jecxz, 1, 0xe3, None, CpuNo64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 361 | jecxz, 1, 0x67e3, None, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 362 | jrcxz, 1, 0xe3, None, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 363 | |
| 364 | // The loop instructions also use the address size prefix to select |
| 365 | // %cx rather than %ecx for the loop count, so the `w' form of these |
| 366 | // instructions emit an address size prefix rather than a data size |
| 367 | // prefix. |
| 368 | loop, 1, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 369 | loop, 1, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 370 | loopz, 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 371 | loopz, 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 372 | loope, 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 373 | loope, 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 374 | loopnz, 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 375 | loopnz, 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 376 | loopne, 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 377 | loopne, 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } |
| 378 | |
| 379 | // Set byte on flag instructions. |
| 380 | seto, 1, 0xf90, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 381 | setno, 1, 0xf91, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 382 | setb, 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 383 | setc, 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 384 | setnae, 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 385 | setnb, 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 386 | setnc, 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 387 | setae, 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 388 | sete, 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 389 | setz, 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 390 | setne, 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 391 | setnz, 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 392 | setbe, 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 393 | setna, 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 394 | setnbe, 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 395 | seta, 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 396 | sets, 1, 0xf98, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 397 | setns, 1, 0xf99, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 398 | setp, 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 399 | setpe, 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 400 | setnp, 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 401 | setpo, 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 402 | setl, 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 403 | setnge, 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 404 | setnl, 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 405 | setge, 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 406 | setle, 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 407 | setng, 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 408 | setnle, 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 409 | setg, 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 410 | |
| 411 | // String manipulation. |
| 412 | cmps, 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 413 | cmps, 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 414 | scmp, 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 415 | scmp, 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 416 | ins, 0, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } |
| 417 | ins, 2, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { InOutPortReg, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 418 | outs, 0, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } |
| 419 | outs, 2, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, InOutPortReg } |
| 420 | lods, 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 421 | lods, 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 422 | lods, 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } |
| 423 | slod, 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 424 | slod, 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 425 | slod, 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } |
| 426 | movs, 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 427 | movs, 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 428 | smov, 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 429 | smov, 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 430 | scas, 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 431 | scas, 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 432 | scas, 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } |
| 433 | ssca, 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 434 | ssca, 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 435 | ssca, 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } |
| 436 | stos, 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 437 | stos, 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 438 | stos, 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 439 | ssto, 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } |
| 440 | ssto, 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 441 | ssto, 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 442 | xlat, 0, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } |
| 443 | xlat, 1, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 444 | |
| 445 | // Bit manipulation. |
| 446 | bsf, 2, 0xfbc, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 447 | bsr, 2, 0xfbd, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 448 | bt, 2, 0xfa3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 449 | bt, 2, 0xfba, 0x4, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 450 | btc, 2, 0xfbb, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 451 | btc, 2, 0xfba, 0x7, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 452 | btr, 2, 0xfb3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 453 | btr, 2, 0xfba, 0x6, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 454 | bts, 2, 0xfab, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 455 | bts, 2, 0xfba, 0x5, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 456 | |
| 457 | // Interrupts & op. sys insns. |
| 458 | // See gas/config/tc-i386.c for conversion of 'int $3' into the special |
| 459 | // int 3 insn. |
| 460 | int, 1, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } |
| 461 | int3, 0, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 462 | into, 0, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 463 | iret, 0, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { 0 } |
| 464 | // i386sl, i486sl, later 486, and Pentium. |
| 465 | rsm, 0, 0xfaa, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 466 | |
| 467 | bound, 2, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 468 | |
| 469 | hlt, 0, 0xf4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 470 | |
| 471 | nop, 1, 0xf1f, 0x0, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 472 | |
| 473 | // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
| 474 | // 32bit mode and "xchg %rax,%rax" in 64bit mode. |
| 475 | nop, 0, 0x90, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 476 | |
| 477 | // Protection control. |
| 478 | arpl, 2, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16, Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 479 | lar, 2, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 480 | lgdt, 1, 0xf01, 0x2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 481 | lgdt, 1, 0xf01, 0x2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 482 | lidt, 1, 0xf01, 0x3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 483 | lidt, 1, 0xf01, 0x3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 484 | lldt, 1, 0xf00, 0x2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 485 | lmsw, 1, 0xf01, 0x6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 486 | lsl, 2, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 487 | ltr, 1, 0xf00, 0x3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 488 | |
| 489 | sgdt, 1, 0xf01, 0x0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 490 | sgdt, 1, 0xf01, 0x0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 491 | sidt, 1, 0xf01, 0x1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 492 | sidt, 1, 0xf01, 0x1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 493 | sldt, 1, 0xf00, 0x0, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 494 | sldt, 1, 0xf00, 0x0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 495 | smsw, 1, 0xf01, 0x4, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 496 | smsw, 1, 0xf01, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 497 | str, 1, 0xf00, 0x1, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } |
| 498 | str, 1, 0xf00, 0x1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 499 | |
| 500 | verr, 1, 0xf00, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 501 | verw, 1, 0xf00, 0x5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 502 | |
| 503 | // Floating point instructions. |
| 504 | |
| 505 | // load |
| 506 | fld, 1, 0xd9c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 507 | fld, 1, 0xd9, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 508 | fld, 1, 0xd9c0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } |
| 509 | // Intel Syntax |
| 510 | fld, 1, 0xdb, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 511 | fild, 1, 0xdf, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 512 | fild, 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 513 | fildll, 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 514 | fldt, 1, 0xdb, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 515 | fbld, 1, 0xdf, 0x4, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 516 | |
| 517 | // store (no pop) |
| 518 | fst, 1, 0xddd0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 519 | fst, 1, 0xd9, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 520 | fst, 1, 0xddd0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } |
| 521 | fist, 1, 0xdf, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 522 | |
| 523 | // store (with pop) |
| 524 | fstp, 1, 0xddd8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 525 | fstp, 1, 0xd9, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 526 | fstp, 1, 0xddd8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } |
| 527 | // Intel Syntax |
| 528 | fstp, 1, 0xdb, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 529 | fistp, 1, 0xdf, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 530 | fistp, 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 531 | fistpll, 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 532 | fstpt, 1, 0xdb, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 533 | fbstp, 1, 0xdf, 0x6, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 534 | |
| 535 | // exchange %st<n> with %st0 |
| 536 | fxch, 1, 0xd9c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 537 | // alias for fxch %st(1) |
| 538 | fxch, 0, 0xd9c9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 539 | |
| 540 | // comparison (without pop) |
| 541 | fcom, 1, 0xd8d0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 542 | // alias for fcom %st(1) |
| 543 | fcom, 0, 0xd8d1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 544 | fcom, 1, 0xd8, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 545 | fcom, 1, 0xd8d0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } |
| 546 | ficom, 1, 0xde, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 547 | |
| 548 | // comparison (with pop) |
| 549 | fcomp, 1, 0xd8d8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 550 | // alias for fcomp %st(1) |
| 551 | fcomp, 0, 0xd8d9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 552 | fcomp, 1, 0xd8, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 553 | fcomp, 1, 0xd8d8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } |
| 554 | ficomp, 1, 0xde, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 555 | fcompp, 0, 0xded9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 556 | |
| 557 | // unordered comparison (with pop) |
| 558 | fucom, 1, 0xdde0, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 559 | // alias for fucom %st(1) |
| 560 | fucom, 0, 0xdde1, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 561 | fucomp, 1, 0xdde8, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 562 | // alias for fucomp %st(1) |
| 563 | fucomp, 0, 0xdde9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 564 | fucompp, 0, 0xdae9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 565 | |
| 566 | ftst, 0, 0xd9e4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 567 | fxam, 0, 0xd9e5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 568 | |
| 569 | // load constants into %st0 |
| 570 | fld1, 0, 0xd9e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 571 | fldl2t, 0, 0xd9e9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 572 | fldl2e, 0, 0xd9ea, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 573 | fldpi, 0, 0xd9eb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 574 | fldlg2, 0, 0xd9ec, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 575 | fldln2, 0, 0xd9ed, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 576 | fldz, 0, 0xd9ee, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 577 | |
| 578 | // Arithmetic. |
| 579 | |
| 580 | // add |
| 581 | fadd, 2, 0xd8c0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 582 | // alias for fadd %st(i), %st |
| 583 | fadd, 1, 0xd8c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 584 | #if SYSV386_COMPAT |
| 585 | // alias for faddp |
| 586 | fadd, 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } |
| 587 | #endif |
| 588 | fadd, 1, 0xd8, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 589 | fiadd, 1, 0xde, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 590 | |
| 591 | faddp, 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } |
| 592 | faddp, 1, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 593 | // alias for faddp %st, %st(1) |
| 594 | faddp, 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 595 | faddp, 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } |
| 596 | |
| 597 | // subtract |
| 598 | fsub, 1, 0xd8e0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 599 | #if SYSV386_COMPAT |
| 600 | fsub, 2, 0xd8e0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 601 | // alias for fsubp |
| 602 | fsub, 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } |
| 603 | #else |
| 604 | fsub, 2, 0xd8e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } |
| 605 | #endif |
| 606 | fsub, 1, 0xd8, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 607 | fisub, 1, 0xde, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 608 | |
| 609 | #if SYSV386_COMPAT |
| 610 | fsubp, 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } |
| 611 | fsubp, 1, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 612 | fsubp, 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 613 | #if OLDGCC_COMPAT |
| 614 | fsubp, 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } |
| 615 | #endif |
| 616 | #else |
| 617 | fsubp, 2, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } |
| 618 | fsubp, 1, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } |
| 619 | fsubp, 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } |
| 620 | #endif |
| 621 | |
| 622 | // subtract reverse |
| 623 | fsubr, 1, 0xd8e8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 624 | #if SYSV386_COMPAT |
| 625 | fsubr, 2, 0xd8e8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 626 | // alias for fsubrp |
| 627 | fsubr, 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } |
| 628 | #else |
| 629 | fsubr, 2, 0xd8e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } |
| 630 | #endif |
| 631 | fsubr, 1, 0xd8, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 632 | fisubr, 1, 0xde, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 633 | |
| 634 | #if SYSV386_COMPAT |
| 635 | fsubrp, 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } |
| 636 | fsubrp, 1, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 637 | fsubrp, 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 638 | #if OLDGCC_COMPAT |
| 639 | fsubrp, 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } |
| 640 | #endif |
| 641 | #else |
| 642 | fsubrp, 2, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } |
| 643 | fsubrp, 1, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } |
| 644 | fsubrp, 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } |
| 645 | #endif |
| 646 | |
| 647 | // multiply |
| 648 | fmul, 2, 0xd8c8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 649 | fmul, 1, 0xd8c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 650 | #if SYSV386_COMPAT |
| 651 | // alias for fmulp |
| 652 | fmul, 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } |
| 653 | #endif |
| 654 | fmul, 1, 0xd8, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 655 | fimul, 1, 0xde, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 656 | |
| 657 | fmulp, 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } |
| 658 | fmulp, 1, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 659 | fmulp, 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 660 | fmulp, 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } |
| 661 | |
| 662 | // divide |
| 663 | fdiv, 1, 0xd8f0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 664 | #if SYSV386_COMPAT |
| 665 | fdiv, 2, 0xd8f0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 666 | // alias for fdivp |
| 667 | fdiv, 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } |
| 668 | #else |
| 669 | fdiv, 2, 0xd8f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } |
| 670 | #endif |
| 671 | fdiv, 1, 0xd8, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 672 | fidiv, 1, 0xde, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 673 | |
| 674 | #if SYSV386_COMPAT |
| 675 | fdivp, 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } |
| 676 | fdivp, 1, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 677 | fdivp, 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 678 | #if OLDGCC_COMPAT |
| 679 | fdivp, 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } |
| 680 | #endif |
| 681 | #else |
| 682 | fdivp, 2, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } |
| 683 | fdivp, 1, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } |
| 684 | fdivp, 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } |
| 685 | #endif |
| 686 | |
| 687 | // divide reverse |
| 688 | fdivr, 1, 0xd8f8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 689 | #if SYSV386_COMPAT |
| 690 | fdivr, 2, 0xd8f8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 691 | // alias for fdivrp |
| 692 | fdivr, 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } |
| 693 | #else |
| 694 | fdivr, 2, 0xd8f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } |
| 695 | #endif |
| 696 | fdivr, 1, 0xd8, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 697 | fidivr, 1, 0xde, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 698 | |
| 699 | #if SYSV386_COMPAT |
| 700 | fdivrp, 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } |
| 701 | fdivrp, 1, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 702 | fdivrp, 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 703 | #if OLDGCC_COMPAT |
| 704 | fdivrp, 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } |
| 705 | #endif |
| 706 | #else |
| 707 | fdivrp, 2, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } |
| 708 | fdivrp, 1, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } |
| 709 | fdivrp, 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } |
| 710 | #endif |
| 711 | |
| 712 | f2xm1, 0, 0xd9f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 713 | fyl2x, 0, 0xd9f1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 714 | fptan, 0, 0xd9f2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 715 | fpatan, 0, 0xd9f3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 716 | fxtract, 0, 0xd9f4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 717 | fprem1, 0, 0xd9f5, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 718 | fdecstp, 0, 0xd9f6, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 719 | fincstp, 0, 0xd9f7, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 720 | fprem, 0, 0xd9f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 721 | fyl2xp1, 0, 0xd9f9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 722 | fsqrt, 0, 0xd9fa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 723 | fsincos, 0, 0xd9fb, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 724 | frndint, 0, 0xd9fc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 725 | fscale, 0, 0xd9fd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 726 | fsin, 0, 0xd9fe, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 727 | fcos, 0, 0xd9ff, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 728 | fchs, 0, 0xd9e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 729 | fabs, 0, 0xd9e1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 730 | |
| 731 | // processor control |
| 732 | fninit, 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 733 | finit, 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } |
| 734 | fldcw, 1, 0xd9, 0x5, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 735 | fnstcw, 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 736 | fstcw, 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 737 | // XXX should reject %al, %eax, and %rax |
| 738 | fnstsw, 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Acc } |
| 739 | fnstsw, 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 740 | fnstsw, 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 741 | // XXX should reject %al, %eax, and %rax |
| 742 | fstsw, 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { Acc } |
| 743 | fstsw, 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 744 | fstsw, 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } |
| 745 | fnclex, 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 746 | fclex, 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } |
| 747 | // Short forms of fldenv, fstenv use data size prefix. |
| 748 | fnstenv, 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 749 | fstenv, 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 750 | fldenv, 1, 0xd9, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 751 | fnsave, 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 752 | fsave, 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 753 | frstor, 1, 0xdd, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 754 | |
| 755 | ffree, 1, 0xddc0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 756 | // P6:free st(i), pop st |
| 757 | ffreep, 1, 0xdfc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 758 | fnop, 0, 0xd9d0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 759 | fwait, 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 760 | |
| 761 | // Opcode prefixes; we allow them as separate insns too. |
| 762 | |
| 763 | addr16, 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 764 | addr32, 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 765 | aword, 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 766 | adword, 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 767 | data16, 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 768 | data32, 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 769 | word, 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 770 | dword, 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 771 | lock, 0, 0xf0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 772 | wait, 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 773 | cs, 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 774 | ds, 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 775 | es, 0, 0x26, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 776 | fs, 0, 0x64, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 777 | gs, 0, 0x65, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 778 | ss, 0, 0x36, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 779 | rep, 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 780 | repe, 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 781 | repz, 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 782 | repne, 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 783 | repnz, 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 784 | ht, 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 785 | hnt, 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 786 | rex, 0, 0x40, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 787 | rexz, 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 788 | rexy, 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 789 | rexyz, 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 790 | rexx, 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 791 | rexxz, 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 792 | rexxy, 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 793 | rexxyz, 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 794 | rex64, 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 795 | rex64z, 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 796 | rex64y, 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 797 | rex64yz, 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 798 | rex64x, 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 799 | rex64xz, 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 800 | rex64xy, 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 801 | rex64xyz, 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 802 | rex.b, 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 803 | rex.x, 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 804 | rex.xb, 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 805 | rex.r, 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 806 | rex.rb, 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 807 | rex.rx, 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 808 | rex.rxb, 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 809 | rex.w, 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 810 | rex.wb, 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 811 | rex.wx, 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 812 | rex.wxb, 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 813 | rex.wr, 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 814 | rex.wrb, 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 815 | rex.wrx, 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 816 | rex.wrxb, 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } |
| 817 | |
| 818 | // 486 extensions. |
| 819 | |
| 820 | bswap, 1, 0xfc8, None, Cpu486, ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 } |
| 821 | xadd, 2, 0xfc0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 822 | cmpxchg, 2, 0xfb0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 823 | invd, 0, 0xf08, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 824 | wbinvd, 0, 0xf09, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 825 | invlpg, 1, 0xf01, 0x7, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 826 | |
| 827 | // 586 and late 486 extensions. |
| 828 | cpuid, 0, 0xfa2, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 829 | |
| 830 | // Pentium extensions. |
| 831 | wrmsr, 0, 0xf30, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 832 | rdtsc, 0, 0xf31, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 833 | rdmsr, 0, 0xf32, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 834 | cmpxchg8b, 1, 0xfc7, 0x1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 835 | |
| 836 | // Pentium II/Pentium Pro extensions. |
| 837 | sysenter, 0, 0xf34, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 838 | sysexit, 0, 0xf35, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 839 | fxsave, 1, 0xfae, 0x0, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 840 | fxrstor, 1, 0xfae, 0x1, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 841 | rdpmc, 0, 0xf33, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 842 | // official undefined instr. |
| 843 | ud2, 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 844 | // alias for ud2 |
| 845 | ud2a, 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 846 | // 2nd. official undefined instr. |
| 847 | ud2b, 0, 0xfb9, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 848 | |
| 849 | cmovo, 2, 0xf40, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 850 | cmovno, 2, 0xf41, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 851 | cmovb, 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 852 | cmovc, 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 853 | cmovnae, 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 854 | cmovae, 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 855 | cmovnc, 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 856 | cmovnb, 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 857 | cmove, 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 858 | cmovz, 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 859 | cmovne, 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 860 | cmovnz, 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 861 | cmovbe, 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 862 | cmovna, 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 863 | cmova, 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 864 | cmovnbe, 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 865 | cmovs, 2, 0xf48, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 866 | cmovns, 2, 0xf49, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 867 | cmovp, 2, 0xf4a, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 868 | cmovnp, 2, 0xf4b, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 869 | cmovl, 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 870 | cmovnge, 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 871 | cmovge, 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 872 | cmovnl, 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 873 | cmovle, 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 874 | cmovng, 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 875 | cmovg, 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 876 | cmovnle, 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 877 | |
| 878 | fcmovb, 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 879 | fcmovnae, 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 880 | fcmove, 2, 0xdac8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 881 | fcmovbe, 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 882 | fcmovna, 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 883 | fcmovu, 2, 0xdad8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 884 | fcmovae, 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 885 | fcmovnb, 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 886 | fcmovne, 2, 0xdbc8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 887 | fcmova, 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 888 | fcmovnbe, 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 889 | fcmovnu, 2, 0xdbd8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 890 | |
| 891 | fcomi, 2, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 892 | fcomi, 0, 0xdbf1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 893 | fcomi, 1, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 894 | fucomi, 2, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 895 | fucomi, 0, 0xdbe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 896 | fucomi, 1, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 897 | fcomip, 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 898 | fcompi, 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 899 | fcompi, 0, 0xdff1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 900 | fcompi, 1, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 901 | fucomip, 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 902 | fucompi, 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } |
| 903 | fucompi, 0, 0xdfe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 904 | fucompi, 1, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } |
| 905 | |
| 906 | // Pentium4 extensions. |
| 907 | |
| 908 | movnti, 2, 0xfc3, None, CpuP4, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 909 | clflush, 1, 0xfae, 0x7, CpuP4, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 910 | lfence, 0, 0xfae, 0xe8, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 911 | mfence, 0, 0xfae, 0xf0, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 912 | pause, 0, 0xf390, None, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 913 | |
| 914 | // MMX/SSE2 instructions. |
| 915 | |
| 916 | emms, 0, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 917 | // These really shouldn't allow for Reg64 (movq is the right mnemonic for |
| 918 | // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's |
| 919 | // spec). AMD's spec, having been in existence for much longer, failed to |
| 920 | // recognize that and specified movd for 32- and 64-bit operations. |
| 921 | movd, 2, 0xf6e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } |
| 922 | movd, 2, 0xf7e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 923 | movd, 2, 0x660f6e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 924 | movd, 2, 0x660f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 925 | // In the 64bit mode the short form mov immediate is redefined to have |
| 926 | // 64bit displacement value. |
| 927 | movq, 2, 0xf6f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 928 | movq, 2, 0xf7f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } |
| 929 | movq, 2, 0xf30f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 930 | movq, 2, 0x660fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 931 | movq, 2, 0xf6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } |
| 932 | movq, 2, 0xf7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 933 | movq, 2, 0x660f6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 934 | movq, 2, 0x660f7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 935 | // We put the 64bit displacement first and we only mark constants |
| 936 | // larger than 32bit as Disp64. |
| 937 | movq, 2, 0xa0, None, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp64, Acc } |
| 938 | movq, 2, 0x88, None, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 939 | movq, 2, 0xc6, 0x0, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm32S, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 940 | movq, 2, 0xb0, None, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm64, Reg64 } |
| 941 | // The segment register moves accept Reg64 so that a segment register |
| 942 | // can be copied to a 64 bit register, and vice versa. |
| 943 | movq, 2, 0x8c, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2|SReg3, Reg64|RegMem } |
| 944 | movq, 2, 0x8e, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64, SReg2|SReg3 } |
| 945 | // Move to/from control debug registers. In the 16 or 32bit modes they |
| 946 | // are 32bit. In the 64bit mode they are 64bit. |
| 947 | movq, 2, 0xf20, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Control, Reg64|RegMem } |
| 948 | movq, 2, 0xf21, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Debug, Reg64|RegMem } |
| 949 | // Real MMX instructions. |
| 950 | packssdw, 2, 0xf6b, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 951 | packssdw, 2, 0x660f6b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 952 | packsswb, 2, 0xf63, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 953 | packsswb, 2, 0x660f63, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 954 | packuswb, 2, 0xf67, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 955 | packuswb, 2, 0x660f67, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 956 | paddb, 2, 0xffc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 957 | paddb, 2, 0x660ffc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 958 | paddw, 2, 0xffd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 959 | paddw, 2, 0x660ffd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 960 | paddd, 2, 0xffe, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 961 | paddd, 2, 0x660ffe, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 962 | paddq, 2, 0xfd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 963 | paddq, 2, 0x660fd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 964 | paddsb, 2, 0xfec, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 965 | paddsb, 2, 0x660fec, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 966 | paddsw, 2, 0xfed, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 967 | paddsw, 2, 0x660fed, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 968 | paddusb, 2, 0xfdc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 969 | paddusb, 2, 0x660fdc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 970 | paddusw, 2, 0xfdd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 971 | paddusw, 2, 0x660fdd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 972 | pand, 2, 0xfdb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 973 | pand, 2, 0x660fdb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 974 | pandn, 2, 0xfdf, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 975 | pandn, 2, 0x660fdf, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 976 | pcmpeqb, 2, 0xf74, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 977 | pcmpeqb, 2, 0x660f74, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 978 | pcmpeqw, 2, 0xf75, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 979 | pcmpeqw, 2, 0x660f75, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 980 | pcmpeqd, 2, 0xf76, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 981 | pcmpeqd, 2, 0x660f76, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 982 | pcmpgtb, 2, 0xf64, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 983 | pcmpgtb, 2, 0x660f64, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 984 | pcmpgtw, 2, 0xf65, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 985 | pcmpgtw, 2, 0x660f65, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 986 | pcmpgtd, 2, 0xf66, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 987 | pcmpgtd, 2, 0x660f66, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 988 | pmaddwd, 2, 0xff5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 989 | pmaddwd, 2, 0x660ff5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 990 | pmulhw, 2, 0xfe5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 991 | pmulhw, 2, 0x660fe5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 992 | pmullw, 2, 0xfd5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 993 | pmullw, 2, 0x660fd5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 994 | por, 2, 0xfeb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 995 | por, 2, 0x660feb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 996 | psllw, 2, 0xff1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 997 | psllw, 2, 0x660ff1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 998 | psllw, 2, 0xf71, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 999 | psllw, 2, 0x660f71, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1000 | pslld, 2, 0xff2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1001 | pslld, 2, 0x660ff2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1002 | pslld, 2, 0xf72, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1003 | pslld, 2, 0x660f72, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1004 | psllq, 2, 0xff3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1005 | psllq, 2, 0x660ff3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1006 | psllq, 2, 0xf73, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1007 | psllq, 2, 0x660f73, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1008 | psraw, 2, 0xfe1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1009 | psraw, 2, 0x660fe1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1010 | psraw, 2, 0xf71, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1011 | psraw, 2, 0x660f71, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1012 | psrad, 2, 0xfe2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1013 | psrad, 2, 0x660fe2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1014 | psrad, 2, 0xf72, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1015 | psrad, 2, 0x660f72, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1016 | psrlw, 2, 0xfd1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1017 | psrlw, 2, 0x660fd1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1018 | psrlw, 2, 0xf71, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1019 | psrlw, 2, 0x660f71, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1020 | psrld, 2, 0xfd2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1021 | psrld, 2, 0x660fd2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1022 | psrld, 2, 0xf72, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1023 | psrld, 2, 0x660f72, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1024 | psrlq, 2, 0xfd3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1025 | psrlq, 2, 0x660fd3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1026 | psrlq, 2, 0xf73, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } |
| 1027 | psrlq, 2, 0x660f73, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1028 | psubb, 2, 0xff8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1029 | psubb, 2, 0x660ff8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1030 | psubw, 2, 0xff9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1031 | psubw, 2, 0x660ff9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1032 | psubd, 2, 0xffa, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1033 | psubd, 2, 0x660ffa, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1034 | psubq, 2, 0xffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1035 | psubq, 2, 0x660ffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1036 | psubsb, 2, 0xfe8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1037 | psubsb, 2, 0x660fe8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1038 | psubsw, 2, 0xfe9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1039 | psubsw, 2, 0x660fe9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1040 | psubusb, 2, 0xfd8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1041 | psubusb, 2, 0x660fd8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1042 | psubusw, 2, 0xfd9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1043 | psubusw, 2, 0x660fd9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1044 | punpckhbw, 2, 0xf68, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1045 | punpckhbw, 2, 0x660f68, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1046 | punpckhwd, 2, 0xf69, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1047 | punpckhwd, 2, 0x660f69, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1048 | punpckhdq, 2, 0xf6a, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1049 | punpckhdq, 2, 0x660f6a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1050 | punpcklbw, 2, 0xf60, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1051 | punpcklbw, 2, 0x660f60, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1052 | punpcklwd, 2, 0xf61, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1053 | punpcklwd, 2, 0x660f61, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1054 | punpckldq, 2, 0xf62, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1055 | punpckldq, 2, 0x660f62, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1056 | pxor, 2, 0xfef, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1057 | pxor, 2, 0x660fef, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1058 | |
| 1059 | // PIII Katmai New Instructions / SIMD instructions. |
| 1060 | |
| 1061 | addps, 2, 0xf58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1062 | addss, 2, 0xf30f58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1063 | andnps, 2, 0xf55, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1064 | andps, 2, 0xf54, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1065 | cmpeqps, 2, 0xfc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1066 | cmpeqss, 2, 0xf30fc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1067 | cmpleps, 2, 0xfc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1068 | cmpless, 2, 0xf30fc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1069 | cmpltps, 2, 0xfc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1070 | cmpltss, 2, 0xf30fc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1071 | cmpneqps, 2, 0xfc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1072 | cmpneqss, 2, 0xf30fc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1073 | cmpnleps, 2, 0xfc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1074 | cmpnless, 2, 0xf30fc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1075 | cmpnltps, 2, 0xfc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1076 | cmpnltss, 2, 0xf30fc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1077 | cmpordps, 2, 0xfc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1078 | cmpordss, 2, 0xf30fc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1079 | cmpunordps, 2, 0xfc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1080 | cmpunordss, 2, 0xf30fc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1081 | cmpps, 3, 0xfc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1082 | cmpss, 3, 0xf30fc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1083 | comiss, 2, 0xf2f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1084 | cvtpi2ps, 2, 0xf2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } |
| 1085 | cvtps2pi, 2, 0xf2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } |
| 1086 | cvtsi2ss, 2, 0xf30f2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1087 | cvtss2si, 2, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } |
| 1088 | cvttps2pi, 2, 0xf2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } |
| 1089 | cvttss2si, 2, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } |
| 1090 | divps, 2, 0xf5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1091 | divss, 2, 0xf30f5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1092 | ldmxcsr, 1, 0xfae, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1093 | maskmovq, 2, 0xff7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, RegMMX } |
| 1094 | maxps, 2, 0xf5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1095 | maxss, 2, 0xf30f5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1096 | minps, 2, 0xf5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1097 | minss, 2, 0xf30f5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1098 | movaps, 2, 0xf28, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1099 | movaps, 2, 0xf29, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1100 | movhlps, 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } |
| 1101 | movhps, 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1102 | movhps, 2, 0xf17, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1103 | movlhps, 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } |
| 1104 | movlps, 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1105 | movlps, 2, 0xf13, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1106 | movmskps, 2, 0xf50, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } |
| 1107 | movntps, 2, 0xf2b, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1108 | movntq, 2, 0xfe7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1109 | movntdq, 2, 0x660fe7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1110 | movss, 2, 0xf30f10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1111 | movss, 2, 0xf30f11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1112 | movups, 2, 0xf10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1113 | movups, 2, 0xf11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1114 | mulps, 2, 0xf59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1115 | mulss, 2, 0xf30f59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1116 | orps, 2, 0xf56, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1117 | pavgb, 2, 0xfe0, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1118 | pavgb, 2, 0x660fe0, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1119 | pavgw, 2, 0xfe3, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1120 | pavgw, 2, 0x660fe3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1121 | pextrw, 3, 0xfc5, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, RegMMX, Reg32|Reg64 } |
| 1122 | pextrw, 3, 0x660fc5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64 } |
| 1123 | |
| 1124 | // Streaming SIMD extensions 4.1 Instructions. |
| 1125 | pextrw, 3, 0x660f3a15, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1126 | |
| 1127 | pinsrw, 3, 0xfc4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } |
| 1128 | pinsrw, 3, 0x660fc4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1129 | pmaxsw, 2, 0xfee, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1130 | pmaxsw, 2, 0x660fee, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1131 | pmaxub, 2, 0xfde, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1132 | pmaxub, 2, 0x660fde, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1133 | pminsw, 2, 0xfea, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1134 | pminsw, 2, 0x660fea, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1135 | pminub, 2, 0xfda, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1136 | pminub, 2, 0x660fda, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1137 | pmovmskb, 2, 0xfd7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegMMX, Reg32|Reg64 } |
| 1138 | pmovmskb, 2, 0x660fd7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } |
| 1139 | pmulhuw, 2, 0xfe4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1140 | pmulhuw, 2, 0x660fe4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1141 | prefetchnta, 1, 0xf18, 0x0, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1142 | prefetcht0, 1, 0xf18, 0x1, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1143 | prefetcht1, 1, 0xf18, 0x2, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1144 | prefetcht2, 1, 0xf18, 0x3, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1145 | psadbw, 2, 0xff6, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1146 | psadbw, 2, 0x660ff6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1147 | pshufw, 3, 0xf70, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1148 | rcpps, 2, 0xf53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1149 | rcpss, 2, 0xf30f53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1150 | rsqrtps, 2, 0xf52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1151 | rsqrtss, 2, 0xf30f52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1152 | sfence, 0, 0xfae, 0xf8, CpuMMX2, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1153 | shufps, 3, 0xfc6, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1154 | sqrtps, 2, 0xf51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1155 | sqrtss, 2, 0xf30f51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1156 | stmxcsr, 1, 0xfae, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1157 | subps, 2, 0xf5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1158 | subss, 2, 0xf30f5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1159 | ucomiss, 2, 0xf2e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1160 | unpckhps, 2, 0xf15, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1161 | unpcklps, 2, 0xf14, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1162 | xorps, 2, 0xf57, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1163 | |
| 1164 | // SSE-2 instructions. |
| 1165 | |
| 1166 | addpd, 2, 0x660f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1167 | addsd, 2, 0xf20f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1168 | andnpd, 2, 0x660f55, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1169 | andpd, 2, 0x660f54, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1170 | cmpeqpd, 2, 0x660fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1171 | cmpeqsd, 2, 0xf20fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1172 | cmplepd, 2, 0x660fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1173 | cmplesd, 2, 0xf20fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1174 | cmpltpd, 2, 0x660fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1175 | cmpltsd, 2, 0xf20fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1176 | cmpneqpd, 2, 0x660fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1177 | cmpneqsd, 2, 0xf20fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1178 | cmpnlepd, 2, 0x660fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1179 | cmpnlesd, 2, 0xf20fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1180 | cmpnltpd, 2, 0x660fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1181 | cmpnltsd, 2, 0xf20fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1182 | cmpordpd, 2, 0x660fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1183 | cmpordsd, 2, 0xf20fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1184 | cmpunordpd, 2, 0x660fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1185 | cmpunordsd, 2, 0xf20fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1186 | cmppd, 3, 0x660fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1187 | // Intel mode string compare. |
| 1188 | cmpsd, 0, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } |
| 1189 | cmpsd, 2, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 1190 | cmpsd, 3, 0xf20fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1191 | comisd, 2, 0x660f2f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1192 | cvtpi2pd, 2, 0x660f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } |
| 1193 | cvtsi2sd, 2, 0xf20f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1194 | divpd, 2, 0x660f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1195 | divsd, 2, 0xf20f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1196 | maxpd, 2, 0x660f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1197 | maxsd, 2, 0xf20f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1198 | minpd, 2, 0x660f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1199 | minsd, 2, 0xf20f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1200 | movapd, 2, 0x660f28, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1201 | movapd, 2, 0x660f29, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1202 | movhpd, 2, 0x660f16, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1203 | movhpd, 2, 0x660f17, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1204 | movlpd, 2, 0x660f12, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1205 | movlpd, 2, 0x660f13, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1206 | movmskpd, 2, 0x660f50, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } |
| 1207 | movntpd, 2, 0x660f2b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1208 | // Intel mode string move. |
| 1209 | movsd, 0, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } |
| 1210 | movsd, 2, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } |
| 1211 | movsd, 2, 0xf20f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1212 | movsd, 2, 0xf20f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1213 | movupd, 2, 0x660f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1214 | movupd, 2, 0x660f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1215 | mulpd, 2, 0x660f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1216 | mulsd, 2, 0xf20f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1217 | orpd, 2, 0x660f56, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1218 | shufpd, 3, 0x660fc6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1219 | sqrtpd, 2, 0x660f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1220 | sqrtsd, 2, 0xf20f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1221 | subpd, 2, 0x660f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1222 | subsd, 2, 0xf20f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1223 | ucomisd, 2, 0x660f2e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1224 | unpckhpd, 2, 0x660f15, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1225 | unpcklpd, 2, 0x660f14, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1226 | xorpd, 2, 0x660f57, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1227 | cvtdq2pd, 2, 0xf30fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1228 | cvtpd2dq, 2, 0xf20fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1229 | cvtdq2ps, 2, 0xf5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1230 | cvtpd2pi, 2, 0x660f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } |
| 1231 | cvtpd2ps, 2, 0x660f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1232 | cvtps2pd, 2, 0xf5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1233 | cvtps2dq, 2, 0x660f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1234 | cvtsd2si, 2, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } |
| 1235 | cvtsd2ss, 2, 0xf20f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1236 | cvtss2sd, 2, 0xf30f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1237 | cvttpd2pi, 2, 0x660f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } |
| 1238 | cvttsd2si, 2, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } |
| 1239 | cvttpd2dq, 2, 0x660fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1240 | cvttps2dq, 2, 0xf30f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1241 | maskmovdqu, 2, 0x660ff7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } |
| 1242 | movdqa, 2, 0x660f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1243 | movdqa, 2, 0x660f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1244 | movdqu, 2, 0xf30f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1245 | movdqu, 2, 0xf30f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } |
| 1246 | movdq2q, 2, 0xf20fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegMMX } |
| 1247 | movq2dq, 2, 0xf30fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, RegXMM } |
| 1248 | pmuludq, 2, 0xff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1249 | pmuludq, 2, 0x660ff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1250 | pshufd, 3, 0x660f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1251 | pshufhw, 3, 0xf30f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1252 | pshuflw, 3, 0xf20f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1253 | pslldq, 2, 0x660f73, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1254 | psrldq, 2, 0x660f73, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } |
| 1255 | punpckhqdq, 2, 0x660f6d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1256 | punpcklqdq, 2, 0x660f6c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1257 | |
| 1258 | // SSE-3 instructions. |
| 1259 | |
| 1260 | addsubpd, 2, 0x660fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1261 | addsubps, 2, 0xf20fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1262 | cmpxchg16b, 1, 0xfc7, 0x1, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1263 | fisttp, 1, 0xdf, 0x1, CpuSSE3, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1264 | fisttp, 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1265 | fisttpll, 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1266 | haddpd, 2, 0x660f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1267 | haddps, 2, 0xf20f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1268 | hsubpd, 2, 0x660f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1269 | hsubps, 2, 0xf20f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1270 | lddqu, 2, 0xf20ff0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1271 | monitor, 0, 0xf01, 0xc8, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1272 | // monitor is very special. CX and DX are always 64bits with zero upper |
| 1273 | // 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The |
| 1274 | // address size override prefix can be used to overrride the AX size in |
| 1275 | // all modes. |
| 1276 | // Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. |
| 1277 | monitor, 3, 0xf01, 0xc8, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 } |
| 1278 | // Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. |
| 1279 | monitor, 3, 0xf01, 0xc8, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 } |
| 1280 | movddup, 2, 0xf20f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1281 | movshdup, 2, 0xf30f16, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1282 | movsldup, 2, 0xf30f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1283 | mwait, 0, 0xf01, 0xc9, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1284 | // mwait is very special. AX and CX are always 64bits with zero upper |
| 1285 | // 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. |
| 1286 | // Need to ensure only "mwait %eax,%ecx" is accepted. |
| 1287 | mwait, 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32, Reg32 } |
| 1288 | // Need to ensure only "mwait %rax,%rcx" is accepted. |
| 1289 | mwait, 2, 0xf01, 0xc9, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg64 } |
| 1290 | |
| 1291 | // VMX instructions. |
| 1292 | vmcall, 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1293 | vmclear, 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1294 | vmlaunch, 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1295 | vmresume, 0, 0xf01, 0xc3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1296 | vmptrld, 1, 0xfc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1297 | vmptrst, 1, 0xfc7, 0x7, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1298 | vmread, 2, 0xf78, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1299 | vmread, 2, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1300 | vmwrite, 2, 0xf79, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 1301 | vmwrite, 2, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 1302 | vmxoff, 0, 0xf01, 0xc4, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1303 | vmxon, 1, 0xf30fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1304 | |
| 1305 | // Supplemental Streaming SIMD extensions 3 Instructions. |
| 1306 | |
| 1307 | phaddw, 2, 0xf3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1308 | phaddw, 2, 0x660f3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1309 | phaddd, 2, 0xf3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1310 | phaddd, 2, 0x660f3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1311 | phaddsw, 2, 0xf3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1312 | phaddsw, 2, 0x660f3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1313 | phsubw, 2, 0xf3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1314 | phsubw, 2, 0x660f3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1315 | phsubd, 2, 0xf3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1316 | phsubd, 2, 0x660f3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1317 | phsubsw, 2, 0xf3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1318 | phsubsw, 2, 0x660f3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1319 | pmaddubsw, 2, 0xf3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1320 | pmaddubsw, 2, 0x660f3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1321 | pmulhrsw, 2, 0xf380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1322 | pmulhrsw, 2, 0x660f380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1323 | pshufb, 2, 0xf3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1324 | pshufb, 2, 0x660f3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1325 | psignb, 2, 0xf3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1326 | psignb, 2, 0x660f3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1327 | psignw, 2, 0xf3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1328 | psignw, 2, 0x660f3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1329 | psignd, 2, 0xf380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1330 | psignd, 2, 0x660f380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1331 | palignr, 3, 0xf3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1332 | palignr, 3, 0x660f3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1333 | pabsb, 2, 0xf381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1334 | pabsb, 2, 0x660f381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1335 | pabsw, 2, 0xf381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1336 | pabsw, 2, 0x660f381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1337 | pabsd, 2, 0xf381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1338 | pabsd, 2, 0x660f381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1339 | |
| 1340 | // Streaming SIMD extensions 4.1 Instructions. |
| 1341 | |
| 1342 | blendpd, 3, 0x660f3a0d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1343 | blendps, 3, 0x660f3a0c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1344 | blendvpd, 3, 0x660f3815, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1345 | blendvps, 3, 0x660f3814, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1346 | dppd, 3, 0x660f3a41, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1347 | dpps, 3, 0x660f3a40, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1348 | extractps, 3, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1349 | insertps, 3, 0x660f3a21, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1350 | movntdqa, 2, 0x660f382a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1351 | mpsadbw, 3, 0x660f3a42, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1352 | packusdw, 2, 0x660f382b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1353 | pblendvb, 3, 0x660f3810, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1354 | pblendw, 3, 0x660f3a0e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1355 | pcmpeqq, 2, 0x660f3829, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1356 | pextrb, 3, 0x660f3a14, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1357 | pextrd, 3, 0x660f3a16, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1358 | pextrq, 3, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1359 | phminposuw, 2, 0x660f3841, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1360 | pinsrb, 3, 0x660f3a20, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1361 | pinsrd, 3, 0x660f3a22, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1362 | pinsrq, 3, 0x660f3a22, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } |
| 1363 | pmaxsb, 2, 0x660f383c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1364 | pmaxsd, 2, 0x660f383d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1365 | pmaxud, 2, 0x660f383f, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1366 | pmaxuw, 2, 0x660f383e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1367 | pminsb, 2, 0x660f3838, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1368 | pminsd, 2, 0x660f3839, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1369 | pminud, 2, 0x660f383b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1370 | pminuw, 2, 0x660f383a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1371 | pmovsxbw, 2, 0x660f3820, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1372 | pmovsxbd, 2, 0x660f3821, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1373 | pmovsxbq, 2, 0x660f3822, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1374 | pmovsxwd, 2, 0x660f3823, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1375 | pmovsxwq, 2, 0x660f3824, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1376 | pmovsxdq, 2, 0x660f3825, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1377 | pmovzxbw, 2, 0x660f3830, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1378 | pmovzxbd, 2, 0x660f3831, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1379 | pmovzxbq, 2, 0x660f3832, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1380 | pmovzxwd, 2, 0x660f3833, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1381 | pmovzxwq, 2, 0x660f3834, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1382 | pmovzxdq, 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1383 | pmuldq, 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1384 | pmulld, 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1385 | ptest, 2, 0x660f3817, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1386 | roundpd, 3, 0x660f3a09, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1387 | roundps, 3, 0x660f3a08, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1388 | roundsd, 3, 0x660f3a0b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1389 | roundss, 3, 0x660f3a0a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1390 | |
| 1391 | // Streaming SIMD extensions 4.2 Instructions. |
| 1392 | |
| 1393 | pcmpgtq, 2, 0x660f3837, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1394 | pcmpestri, 3, 0x660f3a61, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1395 | pcmpestrm, 3, 0x660f3a60, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1396 | pcmpistri, 3, 0x660f3a63, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1397 | pcmpistrm, 3, 0x660f3a62, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } |
| 1398 | // We put non-8bit version before 8bit so that crc32 with memory operand |
| 1399 | // defaults to non-8bit. |
| 1400 | crc32, 2, 0xf20f38f1, None, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 1401 | crc32, 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 1402 | crc32, 2, 0xf20f38f0, None, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 1403 | crc32, 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } |
| 1404 | |
| 1405 | // AMD 3DNow! instructions. |
| 1406 | |
| 1407 | prefetch, 1, 0xf0d, 0x0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1408 | prefetchw, 1, 0xf0d, 0x1, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1409 | femms, 0, 0xf0e, None, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 1410 | pavgusb, 2, 0xf0f, 0xbf, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1411 | pf2id, 2, 0xf0f, 0x1d, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1412 | pf2iw, 2, 0xf0f, 0x1c, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1413 | pfacc, 2, 0xf0f, 0xae, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1414 | pfadd, 2, 0xf0f, 0x9e, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1415 | pfcmpeq, 2, 0xf0f, 0xb0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1416 | pfcmpge, 2, 0xf0f, 0x90, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1417 | pfcmpgt, 2, 0xf0f, 0xa0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1418 | pfmax, 2, 0xf0f, 0xa4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1419 | pfmin, 2, 0xf0f, 0x94, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1420 | pfmul, 2, 0xf0f, 0xb4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1421 | pfnacc, 2, 0xf0f, 0x8a, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1422 | pfpnacc, 2, 0xf0f, 0x8e, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1423 | pfrcp, 2, 0xf0f, 0x96, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1424 | pfrcpit1, 2, 0xf0f, 0xa6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1425 | pfrcpit2, 2, 0xf0f, 0xb6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1426 | pfrsqit1, 2, 0xf0f, 0xa7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1427 | pfrsqrt, 2, 0xf0f, 0x97, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1428 | pfsub, 2, 0xf0f, 0x9a, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1429 | pfsubr, 2, 0xf0f, 0xaa, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1430 | pi2fd, 2, 0xf0f, 0xd, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1431 | pi2fw, 2, 0xf0f, 0xc, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1432 | pmulhrw, 2, 0xf0f, 0xb7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1433 | pswapd, 2, 0xf0f, 0xbb, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |
| 1434 | |
| 1435 | // AMD extensions. |
| 1436 | syscall, 0, 0xf05, None, CpuK6, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } |
| 1437 | sysret, 0, 0xf07, None, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { 0 } |
| 1438 | swapgs, 0, 0xf01, 0xf8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1439 | rdtscp, 0, 0xf01, 0xf9, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1440 | |
| 1441 | // AMD Pacifica additions. |
| 1442 | clgi, 0, 0xf01, 0xdd, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1443 | invlpga, 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1444 | // Need to ensure only "invlpga ...,%ecx" is accepted. |
| 1445 | invlpga, 2, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } |
| 1446 | skinit, 0, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1447 | skinit, 1, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1448 | stgi, 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1449 | vmload, 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1450 | vmload, 1, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1451 | vmmcall, 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1452 | vmrun, 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1453 | vmrun, 1, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1454 | vmsave, 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } |
| 1455 | vmsave, 1, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1456 | |
| 1457 | |
| 1458 | // SSE4a instructions |
| 1459 | movntsd, 2, 0xf20f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1460 | movntss, 2, 0xf30f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
| 1461 | extrq, 3, 0x660f78, 0x0, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Imm8, RegXMM } |
| 1462 | extrq, 2, 0x660f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } |
| 1463 | insertq, 2, 0xf20f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } |
| 1464 | insertq, 4, 0xf20f78, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Imm8, RegXMM, RegXMM } |
| 1465 | |
| 1466 | // ABM instructions |
| 1467 | popcnt, 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 1468 | lzcnt, 2, 0xf30fbd, None, CpuABM, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } |
| 1469 | |
| 1470 | |
| 1471 | // VIA PadLock extensions. |
| 1472 | xstore-rng, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1473 | xcrypt-ecb, 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1474 | xcrypt-cbc, 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1475 | xcrypt-ctr, 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1476 | xcrypt-cfb, 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1477 | xcrypt-ofb, 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1478 | montmul, 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1479 | xsha1, 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1480 | xsha256, 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1481 | // Aliases without hyphens. |
| 1482 | xstorerng, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1483 | xcryptecb, 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1484 | xcryptcbc, 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1485 | xcryptctr, 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1486 | xcryptcfb, 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1487 | xcryptofb, 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |
| 1488 | // Alias for xstore-rng. |
| 1489 | xstore, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } |