| 1 | // i386 register table. |
| 2 | // Copyright 2007 |
| 3 | // Free Software Foundation, Inc. |
| 4 | // |
| 5 | // This file is part of the GNU opcodes library. |
| 6 | // |
| 7 | // This library is free software; you can redistribute it and/or modify |
| 8 | // it under the terms of the GNU General Public License as published by |
| 9 | // the Free Software Foundation; either version 3, or (at your option) |
| 10 | // any later version. |
| 11 | // |
| 12 | // It is distributed in the hope that it will be useful, but WITHOUT |
| 13 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 14 | // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 15 | // License for more details. |
| 16 | // |
| 17 | // You should have received a copy of the GNU General Public License |
| 18 | // along with GAS; see the file COPYING. If not, write to the Free |
| 19 | // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | // 02110-1301, USA. |
| 21 | |
| 22 | // Make %st first as we test for it. |
| 23 | st, FloatReg|FloatAcc, 0, 0, 11, 33 |
| 24 | // 8 bit regs |
| 25 | al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval |
| 26 | cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval |
| 27 | dl, Reg8, 0, 2, Dw2Inval, Dw2Inval |
| 28 | bl, Reg8, 0, 3, Dw2Inval, Dw2Inval |
| 29 | ah, Reg8, 0, 4, Dw2Inval, Dw2Inval |
| 30 | ch, Reg8, 0, 5, Dw2Inval, Dw2Inval |
| 31 | dh, Reg8, 0, 6, Dw2Inval, Dw2Inval |
| 32 | bh, Reg8, 0, 7, Dw2Inval, Dw2Inval |
| 33 | axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval |
| 34 | cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval |
| 35 | dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval |
| 36 | bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval |
| 37 | spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval |
| 38 | bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval |
| 39 | sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval |
| 40 | dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval |
| 41 | r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval |
| 42 | r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval |
| 43 | r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval |
| 44 | r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval |
| 45 | r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval |
| 46 | r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval |
| 47 | r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval |
| 48 | r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval |
| 49 | // 16 bit regs |
| 50 | ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval |
| 51 | cx, Reg16, 0, 1, Dw2Inval, Dw2Inval |
| 52 | dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval |
| 53 | bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval |
| 54 | sp, Reg16, 0, 4, Dw2Inval, Dw2Inval |
| 55 | bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval |
| 56 | si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval |
| 57 | di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval |
| 58 | r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval |
| 59 | r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval |
| 60 | r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval |
| 61 | r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval |
| 62 | r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval |
| 63 | r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval |
| 64 | r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval |
| 65 | r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval |
| 66 | // 32 bit regs |
| 67 | eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval |
| 68 | ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval |
| 69 | edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval |
| 70 | ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval |
| 71 | esp, Reg32, 0, 4, 4, Dw2Inval |
| 72 | ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval |
| 73 | esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval |
| 74 | edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval |
| 75 | r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval |
| 76 | r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval |
| 77 | r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval |
| 78 | r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval |
| 79 | r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval |
| 80 | r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval |
| 81 | r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval |
| 82 | r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval |
| 83 | rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0 |
| 84 | rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 |
| 85 | rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 |
| 86 | rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 |
| 87 | rsp, Reg64, 0, 4, Dw2Inval, 7 |
| 88 | rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6 |
| 89 | rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4 |
| 90 | rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5 |
| 91 | r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8 |
| 92 | r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9 |
| 93 | r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10 |
| 94 | r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11 |
| 95 | r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12 |
| 96 | r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13 |
| 97 | r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14 |
| 98 | r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15 |
| 99 | // Segment registers. |
| 100 | es, SReg2, 0, 0, 40, 50 |
| 101 | cs, SReg2, 0, 1, 41, 51 |
| 102 | ss, SReg2, 0, 2, 42, 52 |
| 103 | ds, SReg2, 0, 3, 43, 53 |
| 104 | fs, SReg3, 0, 4, 44, 54 |
| 105 | gs, SReg3, 0, 5, 45, 55 |
| 106 | flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval |
| 107 | // Control registers. |
| 108 | cr0, Control, 0, 0, Dw2Inval, Dw2Inval |
| 109 | cr1, Control, 0, 1, Dw2Inval, Dw2Inval |
| 110 | cr2, Control, 0, 2, Dw2Inval, Dw2Inval |
| 111 | cr3, Control, 0, 3, Dw2Inval, Dw2Inval |
| 112 | cr4, Control, 0, 4, Dw2Inval, Dw2Inval |
| 113 | cr5, Control, 0, 5, Dw2Inval, Dw2Inval |
| 114 | cr6, Control, 0, 6, Dw2Inval, Dw2Inval |
| 115 | cr7, Control, 0, 7, Dw2Inval, Dw2Inval |
| 116 | cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval |
| 117 | cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval |
| 118 | cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval |
| 119 | cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval |
| 120 | cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval |
| 121 | cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval |
| 122 | cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval |
| 123 | cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval |
| 124 | // Debug registers. |
| 125 | db0, Debug, 0, 0, Dw2Inval, Dw2Inval |
| 126 | db1, Debug, 0, 1, Dw2Inval, Dw2Inval |
| 127 | db2, Debug, 0, 2, Dw2Inval, Dw2Inval |
| 128 | db3, Debug, 0, 3, Dw2Inval, Dw2Inval |
| 129 | db4, Debug, 0, 4, Dw2Inval, Dw2Inval |
| 130 | db5, Debug, 0, 5, Dw2Inval, Dw2Inval |
| 131 | db6, Debug, 0, 6, Dw2Inval, Dw2Inval |
| 132 | db7, Debug, 0, 7, Dw2Inval, Dw2Inval |
| 133 | db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval |
| 134 | db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval |
| 135 | db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval |
| 136 | db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval |
| 137 | db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval |
| 138 | db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval |
| 139 | db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval |
| 140 | db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval |
| 141 | dr0, Debug, 0, 0, Dw2Inval, Dw2Inval |
| 142 | dr1, Debug, 0, 1, Dw2Inval, Dw2Inval |
| 143 | dr2, Debug, 0, 2, Dw2Inval, Dw2Inval |
| 144 | dr3, Debug, 0, 3, Dw2Inval, Dw2Inval |
| 145 | dr4, Debug, 0, 4, Dw2Inval, Dw2Inval |
| 146 | dr5, Debug, 0, 5, Dw2Inval, Dw2Inval |
| 147 | dr6, Debug, 0, 6, Dw2Inval, Dw2Inval |
| 148 | dr7, Debug, 0, 7, Dw2Inval, Dw2Inval |
| 149 | dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval |
| 150 | dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval |
| 151 | dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval |
| 152 | dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval |
| 153 | dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval |
| 154 | dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval |
| 155 | dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval |
| 156 | dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval |
| 157 | // Test registers. |
| 158 | tr0, Test, 0, 0, Dw2Inval, Dw2Inval |
| 159 | tr1, Test, 0, 1, Dw2Inval, Dw2Inval |
| 160 | tr2, Test, 0, 2, Dw2Inval, Dw2Inval |
| 161 | tr3, Test, 0, 3, Dw2Inval, Dw2Inval |
| 162 | tr4, Test, 0, 4, Dw2Inval, Dw2Inval |
| 163 | tr5, Test, 0, 5, Dw2Inval, Dw2Inval |
| 164 | tr6, Test, 0, 6, Dw2Inval, Dw2Inval |
| 165 | tr7, Test, 0, 7, Dw2Inval, Dw2Inval |
| 166 | // MMX and simd registers. |
| 167 | mm0, RegMMX, 0, 0, 29, 41 |
| 168 | mm1, RegMMX, 0, 1, 30, 42 |
| 169 | mm2, RegMMX, 0, 2, 31, 43 |
| 170 | mm3, RegMMX, 0, 3, 32, 44 |
| 171 | mm4, RegMMX, 0, 4, 33, 45 |
| 172 | mm5, RegMMX, 0, 5, 34, 46 |
| 173 | mm6, RegMMX, 0, 6, 35, 47 |
| 174 | mm7, RegMMX, 0, 7, 36, 48 |
| 175 | xmm0, RegXMM, 0, 0, 21, 17 |
| 176 | xmm1, RegXMM, 0, 1, 22, 18 |
| 177 | xmm2, RegXMM, 0, 2, 23, 19 |
| 178 | xmm3, RegXMM, 0, 3, 24, 20 |
| 179 | xmm4, RegXMM, 0, 4, 25, 21 |
| 180 | xmm5, RegXMM, 0, 5, 26, 22 |
| 181 | xmm6, RegXMM, 0, 6, 27, 23 |
| 182 | xmm7, RegXMM, 0, 7, 28, 24 |
| 183 | xmm8, RegXMM, RegRex, 0, Dw2Inval, 25 |
| 184 | xmm9, RegXMM, RegRex, 1, Dw2Inval, 26 |
| 185 | xmm10, RegXMM, RegRex, 2, Dw2Inval, 27 |
| 186 | xmm11, RegXMM, RegRex, 3, Dw2Inval, 28 |
| 187 | xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 |
| 188 | xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 |
| 189 | xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 |
| 190 | xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 |
| 191 | // AVX registers. |
| 192 | ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval |
| 193 | ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval |
| 194 | ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval |
| 195 | ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval |
| 196 | ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval |
| 197 | ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval |
| 198 | ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval |
| 199 | ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval |
| 200 | ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval |
| 201 | ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval |
| 202 | ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval |
| 203 | ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval |
| 204 | ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval |
| 205 | ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval |
| 206 | ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval |
| 207 | ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval |
| 208 | // No type will make these registers rejected for all purposes except |
| 209 | // for addressing. This saves creating one extra type for RIP/EIP. |
| 210 | rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 |
| 211 | eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval |
| 212 | // No type will make these registers rejected for all purposes except |
| 213 | // for addressing. |
| 214 | eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval |
| 215 | riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval |
| 216 | // fp regs. |
| 217 | st(0), FloatReg|FloatAcc, 0, 0, 11, 33 |
| 218 | st(1), FloatReg, 0, 1, 12, 34 |
| 219 | st(2), FloatReg, 0, 2, 13, 35 |
| 220 | st(3), FloatReg, 0, 3, 14, 36 |
| 221 | st(4), FloatReg, 0, 4, 15, 37 |
| 222 | st(5), FloatReg, 0, 5, 16, 38 |
| 223 | st(6), FloatReg, 0, 6, 17, 39 |
| 224 | st(7), FloatReg, 0, 7, 18, 40 |
| 225 | // Pseudo-register names only used in .cfi_* directives |
| 226 | eflags, 0, 0, 0, 9, 49 |
| 227 | rflags, 0, 0, 0, Dw2Inval, 49 |
| 228 | fs.base, 0, 0, 0, Dw2Inval, 58 |
| 229 | gs.base, 0, 0, 0, Dw2Inval, 59 |
| 230 | tr, 0, 0, 0, 48, 62 |
| 231 | ldtr, 0, 0, 0, 49, 63 |
| 232 | // st0...7 for backward compatibility |
| 233 | st0, 0, 0, 0, 11, 33 |
| 234 | st1, 0, 0, 1, 12, 34 |
| 235 | st2, 0, 0, 2, 13, 35 |
| 236 | st3, 0, 0, 3, 14, 36 |
| 237 | st4, 0, 0, 4, 15, 37 |
| 238 | st5, 0, 0, 5, 16, 38 |
| 239 | st6, 0, 0, 6, 17, 39 |
| 240 | st7, 0, 0, 7, 18, 40 |
| 241 | fcw, 0, 0, 0, 37, 65 |
| 242 | fsw, 0, 0, 0, 38, 66 |
| 243 | mxcsr, 0, 0, 0, 39, 64 |