| 1 | /* CPU data header for m32r. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #ifndef M32R_CPU_H |
| 26 | #define M32R_CPU_H |
| 27 | |
| 28 | #define CGEN_ARCH m32r |
| 29 | |
| 30 | /* Given symbol S, return m32r_cgen_<S>. */ |
| 31 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 32 | #define CGEN_SYM(s) m32r##_cgen_##s |
| 33 | #else |
| 34 | #define CGEN_SYM(s) m32r/**/_cgen_/**/s |
| 35 | #endif |
| 36 | |
| 37 | |
| 38 | /* Selected cpu families. */ |
| 39 | #define HAVE_CPU_M32RBF |
| 40 | #define HAVE_CPU_M32RXF |
| 41 | |
| 42 | #define CGEN_INSN_LSB0_P 0 |
| 43 | |
| 44 | /* Minimum size of any insn (in bytes). */ |
| 45 | #define CGEN_MIN_INSN_SIZE 2 |
| 46 | |
| 47 | /* Maximum size of any insn (in bytes). */ |
| 48 | #define CGEN_MAX_INSN_SIZE 4 |
| 49 | |
| 50 | #define CGEN_INT_INSN_P 1 |
| 51 | |
| 52 | /* Maximum number of syntax elements in an instruction. */ |
| 53 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 |
| 54 | |
| 55 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. |
| 56 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands |
| 57 | we can't hash on everything up to the space. */ |
| 58 | #define CGEN_MNEMONIC_OPERANDS |
| 59 | |
| 60 | /* Maximum number of fields in an instruction. */ |
| 61 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 |
| 62 | |
| 63 | /* Enums. */ |
| 64 | |
| 65 | /* Enum declaration for insn format enums. */ |
| 66 | typedef enum insn_op1 { |
| 67 | OP1_0, OP1_1, OP1_2, OP1_3 |
| 68 | , OP1_4, OP1_5, OP1_6, OP1_7 |
| 69 | , OP1_8, OP1_9, OP1_10, OP1_11 |
| 70 | , OP1_12, OP1_13, OP1_14, OP1_15 |
| 71 | } INSN_OP1; |
| 72 | |
| 73 | /* Enum declaration for op2 enums. */ |
| 74 | typedef enum insn_op2 { |
| 75 | OP2_0, OP2_1, OP2_2, OP2_3 |
| 76 | , OP2_4, OP2_5, OP2_6, OP2_7 |
| 77 | , OP2_8, OP2_9, OP2_10, OP2_11 |
| 78 | , OP2_12, OP2_13, OP2_14, OP2_15 |
| 79 | } INSN_OP2; |
| 80 | |
| 81 | /* Enum declaration for . */ |
| 82 | typedef enum gr_names { |
| 83 | H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 |
| 84 | , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 |
| 85 | , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 |
| 86 | , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 |
| 87 | , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 |
| 88 | } GR_NAMES; |
| 89 | |
| 90 | /* Enum declaration for . */ |
| 91 | typedef enum cr_names { |
| 92 | H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 |
| 93 | , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0 |
| 94 | , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4 |
| 95 | , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8 |
| 96 | , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12 |
| 97 | , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 |
| 98 | } CR_NAMES; |
| 99 | |
| 100 | /* Attributes. */ |
| 101 | |
| 102 | /* Enum declaration for machine type selection. */ |
| 103 | typedef enum mach_attr { |
| 104 | MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX |
| 105 | } MACH_ATTR; |
| 106 | |
| 107 | /* Enum declaration for instruction set selection. */ |
| 108 | typedef enum isa_attr { |
| 109 | ISA_M32R, ISA_MAX |
| 110 | } ISA_ATTR; |
| 111 | |
| 112 | /* Enum declaration for parallel execution pipeline selection. */ |
| 113 | typedef enum pipe_attr { |
| 114 | PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS |
| 115 | } PIPE_ATTR; |
| 116 | |
| 117 | /* Number of architecture variants. */ |
| 118 | #define MAX_ISAS 1 |
| 119 | #define MAX_MACHS ((int) MACH_MAX) |
| 120 | |
| 121 | /* Ifield support. */ |
| 122 | |
| 123 | extern const struct cgen_ifld m32r_cgen_ifld_table[]; |
| 124 | |
| 125 | /* Ifield attribute indices. */ |
| 126 | |
| 127 | /* Enum declaration for cgen_ifld attrs. */ |
| 128 | typedef enum cgen_ifld_attr { |
| 129 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED |
| 130 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS |
| 131 | , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS |
| 132 | } CGEN_IFLD_ATTR; |
| 133 | |
| 134 | /* Number of non-boolean elements in cgen_ifld_attr. */ |
| 135 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) |
| 136 | |
| 137 | /* Enum declaration for m32r ifield types. */ |
| 138 | typedef enum ifield_type { |
| 139 | M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 |
| 140 | , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 |
| 141 | , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5 |
| 142 | , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8 |
| 143 | , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3 |
| 144 | , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67 |
| 145 | , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX |
| 146 | } IFIELD_TYPE; |
| 147 | |
| 148 | #define MAX_IFLD ((int) M32R_F_MAX) |
| 149 | |
| 150 | /* Hardware attribute indices. */ |
| 151 | |
| 152 | /* Enum declaration for cgen_hw attrs. */ |
| 153 | typedef enum cgen_hw_attr { |
| 154 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE |
| 155 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS |
| 156 | } CGEN_HW_ATTR; |
| 157 | |
| 158 | /* Number of non-boolean elements in cgen_hw_attr. */ |
| 159 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) |
| 160 | |
| 161 | /* Enum declaration for m32r hardware types. */ |
| 162 | typedef enum cgen_hw_type { |
| 163 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR |
| 164 | , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 |
| 165 | , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM |
| 166 | , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW |
| 167 | , HW_H_BBPSW, HW_H_LOCK, HW_MAX |
| 168 | } CGEN_HW_TYPE; |
| 169 | |
| 170 | #define MAX_HW ((int) HW_MAX) |
| 171 | |
| 172 | /* Operand attribute indices. */ |
| 173 | |
| 174 | /* Enum declaration for cgen_operand attrs. */ |
| 175 | typedef enum cgen_operand_attr { |
| 176 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT |
| 177 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY |
| 178 | , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31 |
| 179 | , CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS |
| 180 | } CGEN_OPERAND_ATTR; |
| 181 | |
| 182 | /* Number of non-boolean elements in cgen_operand_attr. */ |
| 183 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) |
| 184 | |
| 185 | /* Enum declaration for m32r operand types. */ |
| 186 | typedef enum cgen_operand_type { |
| 187 | M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 |
| 188 | , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 |
| 189 | , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16 |
| 190 | , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC |
| 191 | , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16 |
| 192 | , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24 |
| 193 | , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX |
| 194 | } CGEN_OPERAND_TYPE; |
| 195 | |
| 196 | /* Number of operands types. */ |
| 197 | #define MAX_OPERANDS 26 |
| 198 | |
| 199 | /* Maximum number of operands referenced by any insn. */ |
| 200 | #define MAX_OPERAND_INSTANCES 11 |
| 201 | |
| 202 | /* Insn attribute indices. */ |
| 203 | |
| 204 | /* Enum declaration for cgen_insn attrs. */ |
| 205 | typedef enum cgen_insn_attr { |
| 206 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI |
| 207 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX |
| 208 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL |
| 209 | , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE |
| 210 | , CGEN_INSN_END_NBOOLS |
| 211 | } CGEN_INSN_ATTR; |
| 212 | |
| 213 | /* Number of non-boolean elements in cgen_insn_attr. */ |
| 214 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) |
| 215 | |
| 216 | /* cgen.h uses things we just defined. */ |
| 217 | #include "opcode/cgen.h" |
| 218 | |
| 219 | /* Attributes. */ |
| 220 | extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; |
| 221 | extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; |
| 222 | extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; |
| 223 | extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; |
| 224 | |
| 225 | /* Hardware decls. */ |
| 226 | |
| 227 | extern CGEN_KEYWORD m32r_cgen_opval_gr_names; |
| 228 | extern CGEN_KEYWORD m32r_cgen_opval_cr_names; |
| 229 | extern CGEN_KEYWORD m32r_cgen_opval_h_accums; |
| 230 | |
| 231 | |
| 232 | |
| 233 | |
| 234 | #endif /* M32R_CPU_H */ |