| 1 | /* Instruction opcode table for m32r. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #include "sysdep.h" |
| 26 | #include "ansidecl.h" |
| 27 | #include "bfd.h" |
| 28 | #include "symcat.h" |
| 29 | #include "m32r-desc.h" |
| 30 | #include "m32r-opc.h" |
| 31 | |
| 32 | /* The hash functions are recorded here to help keep assembler code out of |
| 33 | the disassembler and vice versa. */ |
| 34 | |
| 35 | static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); |
| 36 | static unsigned int asm_hash_insn PARAMS ((const char *)); |
| 37 | static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); |
| 38 | static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); |
| 39 | |
| 40 | /* Instruction formats. */ |
| 41 | |
| 42 | #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] |
| 43 | |
| 44 | static const CGEN_IFMT ifmt_empty = { |
| 45 | 0, 0, 0x0, { 0 } |
| 46 | }; |
| 47 | |
| 48 | static const CGEN_IFMT ifmt_add = { |
| 49 | 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 50 | }; |
| 51 | |
| 52 | static const CGEN_IFMT ifmt_add3 = { |
| 53 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } |
| 54 | }; |
| 55 | |
| 56 | static const CGEN_IFMT ifmt_and3 = { |
| 57 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } |
| 58 | }; |
| 59 | |
| 60 | static const CGEN_IFMT ifmt_or3 = { |
| 61 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } |
| 62 | }; |
| 63 | |
| 64 | static const CGEN_IFMT ifmt_addi = { |
| 65 | 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } |
| 66 | }; |
| 67 | |
| 68 | static const CGEN_IFMT ifmt_addv3 = { |
| 69 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } |
| 70 | }; |
| 71 | |
| 72 | static const CGEN_IFMT ifmt_bc8 = { |
| 73 | 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } |
| 74 | }; |
| 75 | |
| 76 | static const CGEN_IFMT ifmt_bc24 = { |
| 77 | 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } |
| 78 | }; |
| 79 | |
| 80 | static const CGEN_IFMT ifmt_beq = { |
| 81 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } |
| 82 | }; |
| 83 | |
| 84 | static const CGEN_IFMT ifmt_beqz = { |
| 85 | 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } |
| 86 | }; |
| 87 | |
| 88 | static const CGEN_IFMT ifmt_cmp = { |
| 89 | 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 90 | }; |
| 91 | |
| 92 | static const CGEN_IFMT ifmt_cmpi = { |
| 93 | 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } |
| 94 | }; |
| 95 | |
| 96 | static const CGEN_IFMT ifmt_div = { |
| 97 | 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } |
| 98 | }; |
| 99 | |
| 100 | static const CGEN_IFMT ifmt_jl = { |
| 101 | 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 102 | }; |
| 103 | |
| 104 | static const CGEN_IFMT ifmt_ld24 = { |
| 105 | 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 } |
| 106 | }; |
| 107 | |
| 108 | static const CGEN_IFMT ifmt_ldi16 = { |
| 109 | 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } |
| 110 | }; |
| 111 | |
| 112 | static const CGEN_IFMT ifmt_mvfachi = { |
| 113 | 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 114 | }; |
| 115 | |
| 116 | static const CGEN_IFMT ifmt_mvfc = { |
| 117 | 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 118 | }; |
| 119 | |
| 120 | static const CGEN_IFMT ifmt_mvtachi = { |
| 121 | 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 122 | }; |
| 123 | |
| 124 | static const CGEN_IFMT ifmt_mvtc = { |
| 125 | 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 126 | }; |
| 127 | |
| 128 | static const CGEN_IFMT ifmt_nop = { |
| 129 | 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 130 | }; |
| 131 | |
| 132 | static const CGEN_IFMT ifmt_seth = { |
| 133 | 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 } |
| 134 | }; |
| 135 | |
| 136 | static const CGEN_IFMT ifmt_slli = { |
| 137 | 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 } |
| 138 | }; |
| 139 | |
| 140 | static const CGEN_IFMT ifmt_st_d = { |
| 141 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } |
| 142 | }; |
| 143 | |
| 144 | static const CGEN_IFMT ifmt_trap = { |
| 145 | 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 } |
| 146 | }; |
| 147 | |
| 148 | #undef F |
| 149 | |
| 150 | #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) |
| 151 | #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ |
| 152 | #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) |
| 153 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) |
| 154 | |
| 155 | /* The instruction table. */ |
| 156 | |
| 157 | static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = |
| 158 | { |
| 159 | /* Special null first entry. |
| 160 | A `num' value of zero is thus invalid. |
| 161 | Also, the special `invalid' insn resides here. */ |
| 162 | { { 0 } }, |
| 163 | /* add $dr,$sr */ |
| 164 | { |
| 165 | { 0, 0, 0, 0 }, |
| 166 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 167 | & ifmt_add, { 0xa0 } |
| 168 | }, |
| 169 | /* add3 $dr,$sr,$hash$slo16 */ |
| 170 | { |
| 171 | { 0, 0, 0, 0 }, |
| 172 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, |
| 173 | & ifmt_add3, { 0x80a00000 } |
| 174 | }, |
| 175 | /* and $dr,$sr */ |
| 176 | { |
| 177 | { 0, 0, 0, 0 }, |
| 178 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 179 | & ifmt_add, { 0xc0 } |
| 180 | }, |
| 181 | /* and3 $dr,$sr,$uimm16 */ |
| 182 | { |
| 183 | { 0, 0, 0, 0 }, |
| 184 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, |
| 185 | & ifmt_and3, { 0x80c00000 } |
| 186 | }, |
| 187 | /* or $dr,$sr */ |
| 188 | { |
| 189 | { 0, 0, 0, 0 }, |
| 190 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 191 | & ifmt_add, { 0xe0 } |
| 192 | }, |
| 193 | /* or3 $dr,$sr,$hash$ulo16 */ |
| 194 | { |
| 195 | { 0, 0, 0, 0 }, |
| 196 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, |
| 197 | & ifmt_or3, { 0x80e00000 } |
| 198 | }, |
| 199 | /* xor $dr,$sr */ |
| 200 | { |
| 201 | { 0, 0, 0, 0 }, |
| 202 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 203 | & ifmt_add, { 0xd0 } |
| 204 | }, |
| 205 | /* xor3 $dr,$sr,$uimm16 */ |
| 206 | { |
| 207 | { 0, 0, 0, 0 }, |
| 208 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, |
| 209 | & ifmt_and3, { 0x80d00000 } |
| 210 | }, |
| 211 | /* addi $dr,$simm8 */ |
| 212 | { |
| 213 | { 0, 0, 0, 0 }, |
| 214 | { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, |
| 215 | & ifmt_addi, { 0x4000 } |
| 216 | }, |
| 217 | /* addv $dr,$sr */ |
| 218 | { |
| 219 | { 0, 0, 0, 0 }, |
| 220 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 221 | & ifmt_add, { 0x80 } |
| 222 | }, |
| 223 | /* addv3 $dr,$sr,$simm16 */ |
| 224 | { |
| 225 | { 0, 0, 0, 0 }, |
| 226 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, |
| 227 | & ifmt_addv3, { 0x80800000 } |
| 228 | }, |
| 229 | /* addx $dr,$sr */ |
| 230 | { |
| 231 | { 0, 0, 0, 0 }, |
| 232 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 233 | & ifmt_add, { 0x90 } |
| 234 | }, |
| 235 | /* bc.s $disp8 */ |
| 236 | { |
| 237 | { 0, 0, 0, 0 }, |
| 238 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 239 | & ifmt_bc8, { 0x7c00 } |
| 240 | }, |
| 241 | /* bc.l $disp24 */ |
| 242 | { |
| 243 | { 0, 0, 0, 0 }, |
| 244 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 245 | & ifmt_bc24, { 0xfc000000 } |
| 246 | }, |
| 247 | /* beq $src1,$src2,$disp16 */ |
| 248 | { |
| 249 | { 0, 0, 0, 0 }, |
| 250 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 251 | & ifmt_beq, { 0xb0000000 } |
| 252 | }, |
| 253 | /* beqz $src2,$disp16 */ |
| 254 | { |
| 255 | { 0, 0, 0, 0 }, |
| 256 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 257 | & ifmt_beqz, { 0xb0800000 } |
| 258 | }, |
| 259 | /* bgez $src2,$disp16 */ |
| 260 | { |
| 261 | { 0, 0, 0, 0 }, |
| 262 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 263 | & ifmt_beqz, { 0xb0b00000 } |
| 264 | }, |
| 265 | /* bgtz $src2,$disp16 */ |
| 266 | { |
| 267 | { 0, 0, 0, 0 }, |
| 268 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 269 | & ifmt_beqz, { 0xb0d00000 } |
| 270 | }, |
| 271 | /* blez $src2,$disp16 */ |
| 272 | { |
| 273 | { 0, 0, 0, 0 }, |
| 274 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 275 | & ifmt_beqz, { 0xb0c00000 } |
| 276 | }, |
| 277 | /* bltz $src2,$disp16 */ |
| 278 | { |
| 279 | { 0, 0, 0, 0 }, |
| 280 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 281 | & ifmt_beqz, { 0xb0a00000 } |
| 282 | }, |
| 283 | /* bnez $src2,$disp16 */ |
| 284 | { |
| 285 | { 0, 0, 0, 0 }, |
| 286 | { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 287 | & ifmt_beqz, { 0xb0900000 } |
| 288 | }, |
| 289 | /* bl.s $disp8 */ |
| 290 | { |
| 291 | { 0, 0, 0, 0 }, |
| 292 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 293 | & ifmt_bc8, { 0x7e00 } |
| 294 | }, |
| 295 | /* bl.l $disp24 */ |
| 296 | { |
| 297 | { 0, 0, 0, 0 }, |
| 298 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 299 | & ifmt_bc24, { 0xfe000000 } |
| 300 | }, |
| 301 | /* bnc.s $disp8 */ |
| 302 | { |
| 303 | { 0, 0, 0, 0 }, |
| 304 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 305 | & ifmt_bc8, { 0x7d00 } |
| 306 | }, |
| 307 | /* bnc.l $disp24 */ |
| 308 | { |
| 309 | { 0, 0, 0, 0 }, |
| 310 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 311 | & ifmt_bc24, { 0xfd000000 } |
| 312 | }, |
| 313 | /* bne $src1,$src2,$disp16 */ |
| 314 | { |
| 315 | { 0, 0, 0, 0 }, |
| 316 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, |
| 317 | & ifmt_beq, { 0xb0100000 } |
| 318 | }, |
| 319 | /* bra.s $disp8 */ |
| 320 | { |
| 321 | { 0, 0, 0, 0 }, |
| 322 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 323 | & ifmt_bc8, { 0x7f00 } |
| 324 | }, |
| 325 | /* bra.l $disp24 */ |
| 326 | { |
| 327 | { 0, 0, 0, 0 }, |
| 328 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 329 | & ifmt_bc24, { 0xff000000 } |
| 330 | }, |
| 331 | /* cmp $src1,$src2 */ |
| 332 | { |
| 333 | { 0, 0, 0, 0 }, |
| 334 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 335 | & ifmt_cmp, { 0x40 } |
| 336 | }, |
| 337 | /* cmpi $src2,$simm16 */ |
| 338 | { |
| 339 | { 0, 0, 0, 0 }, |
| 340 | { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, |
| 341 | & ifmt_cmpi, { 0x80400000 } |
| 342 | }, |
| 343 | /* cmpu $src1,$src2 */ |
| 344 | { |
| 345 | { 0, 0, 0, 0 }, |
| 346 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 347 | & ifmt_cmp, { 0x50 } |
| 348 | }, |
| 349 | /* cmpui $src2,$simm16 */ |
| 350 | { |
| 351 | { 0, 0, 0, 0 }, |
| 352 | { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, |
| 353 | & ifmt_cmpi, { 0x80500000 } |
| 354 | }, |
| 355 | /* div $dr,$sr */ |
| 356 | { |
| 357 | { 0, 0, 0, 0 }, |
| 358 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 359 | & ifmt_div, { 0x90000000 } |
| 360 | }, |
| 361 | /* divu $dr,$sr */ |
| 362 | { |
| 363 | { 0, 0, 0, 0 }, |
| 364 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 365 | & ifmt_div, { 0x90100000 } |
| 366 | }, |
| 367 | /* rem $dr,$sr */ |
| 368 | { |
| 369 | { 0, 0, 0, 0 }, |
| 370 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 371 | & ifmt_div, { 0x90200000 } |
| 372 | }, |
| 373 | /* remu $dr,$sr */ |
| 374 | { |
| 375 | { 0, 0, 0, 0 }, |
| 376 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 377 | & ifmt_div, { 0x90300000 } |
| 378 | }, |
| 379 | /* jl $sr */ |
| 380 | { |
| 381 | { 0, 0, 0, 0 }, |
| 382 | { { MNEM, ' ', OP (SR), 0 } }, |
| 383 | & ifmt_jl, { 0x1ec0 } |
| 384 | }, |
| 385 | /* jmp $sr */ |
| 386 | { |
| 387 | { 0, 0, 0, 0 }, |
| 388 | { { MNEM, ' ', OP (SR), 0 } }, |
| 389 | & ifmt_jl, { 0x1fc0 } |
| 390 | }, |
| 391 | /* ld $dr,@$sr */ |
| 392 | { |
| 393 | { 0, 0, 0, 0 }, |
| 394 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, |
| 395 | & ifmt_add, { 0x20c0 } |
| 396 | }, |
| 397 | /* ld $dr,@($slo16,$sr) */ |
| 398 | { |
| 399 | { 0, 0, 0, 0 }, |
| 400 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, |
| 401 | & ifmt_add3, { 0xa0c00000 } |
| 402 | }, |
| 403 | /* ldb $dr,@$sr */ |
| 404 | { |
| 405 | { 0, 0, 0, 0 }, |
| 406 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, |
| 407 | & ifmt_add, { 0x2080 } |
| 408 | }, |
| 409 | /* ldb $dr,@($slo16,$sr) */ |
| 410 | { |
| 411 | { 0, 0, 0, 0 }, |
| 412 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, |
| 413 | & ifmt_add3, { 0xa0800000 } |
| 414 | }, |
| 415 | /* ldh $dr,@$sr */ |
| 416 | { |
| 417 | { 0, 0, 0, 0 }, |
| 418 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, |
| 419 | & ifmt_add, { 0x20a0 } |
| 420 | }, |
| 421 | /* ldh $dr,@($slo16,$sr) */ |
| 422 | { |
| 423 | { 0, 0, 0, 0 }, |
| 424 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, |
| 425 | & ifmt_add3, { 0xa0a00000 } |
| 426 | }, |
| 427 | /* ldub $dr,@$sr */ |
| 428 | { |
| 429 | { 0, 0, 0, 0 }, |
| 430 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, |
| 431 | & ifmt_add, { 0x2090 } |
| 432 | }, |
| 433 | /* ldub $dr,@($slo16,$sr) */ |
| 434 | { |
| 435 | { 0, 0, 0, 0 }, |
| 436 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, |
| 437 | & ifmt_add3, { 0xa0900000 } |
| 438 | }, |
| 439 | /* lduh $dr,@$sr */ |
| 440 | { |
| 441 | { 0, 0, 0, 0 }, |
| 442 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, |
| 443 | & ifmt_add, { 0x20b0 } |
| 444 | }, |
| 445 | /* lduh $dr,@($slo16,$sr) */ |
| 446 | { |
| 447 | { 0, 0, 0, 0 }, |
| 448 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, |
| 449 | & ifmt_add3, { 0xa0b00000 } |
| 450 | }, |
| 451 | /* ld $dr,@$sr+ */ |
| 452 | { |
| 453 | { 0, 0, 0, 0 }, |
| 454 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, |
| 455 | & ifmt_add, { 0x20e0 } |
| 456 | }, |
| 457 | /* ld24 $dr,$uimm24 */ |
| 458 | { |
| 459 | { 0, 0, 0, 0 }, |
| 460 | { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, |
| 461 | & ifmt_ld24, { 0xe0000000 } |
| 462 | }, |
| 463 | /* ldi8 $dr,$simm8 */ |
| 464 | { |
| 465 | { 0, 0, 0, 0 }, |
| 466 | { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, |
| 467 | & ifmt_addi, { 0x6000 } |
| 468 | }, |
| 469 | /* ldi16 $dr,$hash$slo16 */ |
| 470 | { |
| 471 | { 0, 0, 0, 0 }, |
| 472 | { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, |
| 473 | & ifmt_ldi16, { 0x90f00000 } |
| 474 | }, |
| 475 | /* lock $dr,@$sr */ |
| 476 | { |
| 477 | { 0, 0, 0, 0 }, |
| 478 | { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, |
| 479 | & ifmt_add, { 0x20d0 } |
| 480 | }, |
| 481 | /* machi $src1,$src2 */ |
| 482 | { |
| 483 | { 0, 0, 0, 0 }, |
| 484 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 485 | & ifmt_cmp, { 0x3040 } |
| 486 | }, |
| 487 | /* maclo $src1,$src2 */ |
| 488 | { |
| 489 | { 0, 0, 0, 0 }, |
| 490 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 491 | & ifmt_cmp, { 0x3050 } |
| 492 | }, |
| 493 | /* macwhi $src1,$src2 */ |
| 494 | { |
| 495 | { 0, 0, 0, 0 }, |
| 496 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 497 | & ifmt_cmp, { 0x3060 } |
| 498 | }, |
| 499 | /* macwlo $src1,$src2 */ |
| 500 | { |
| 501 | { 0, 0, 0, 0 }, |
| 502 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 503 | & ifmt_cmp, { 0x3070 } |
| 504 | }, |
| 505 | /* mul $dr,$sr */ |
| 506 | { |
| 507 | { 0, 0, 0, 0 }, |
| 508 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 509 | & ifmt_add, { 0x1060 } |
| 510 | }, |
| 511 | /* mulhi $src1,$src2 */ |
| 512 | { |
| 513 | { 0, 0, 0, 0 }, |
| 514 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 515 | & ifmt_cmp, { 0x3000 } |
| 516 | }, |
| 517 | /* mullo $src1,$src2 */ |
| 518 | { |
| 519 | { 0, 0, 0, 0 }, |
| 520 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 521 | & ifmt_cmp, { 0x3010 } |
| 522 | }, |
| 523 | /* mulwhi $src1,$src2 */ |
| 524 | { |
| 525 | { 0, 0, 0, 0 }, |
| 526 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 527 | & ifmt_cmp, { 0x3020 } |
| 528 | }, |
| 529 | /* mulwlo $src1,$src2 */ |
| 530 | { |
| 531 | { 0, 0, 0, 0 }, |
| 532 | { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, |
| 533 | & ifmt_cmp, { 0x3030 } |
| 534 | }, |
| 535 | /* mv $dr,$sr */ |
| 536 | { |
| 537 | { 0, 0, 0, 0 }, |
| 538 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 539 | & ifmt_add, { 0x1080 } |
| 540 | }, |
| 541 | /* mvfachi $dr */ |
| 542 | { |
| 543 | { 0, 0, 0, 0 }, |
| 544 | { { MNEM, ' ', OP (DR), 0 } }, |
| 545 | & ifmt_mvfachi, { 0x50f0 } |
| 546 | }, |
| 547 | /* mvfaclo $dr */ |
| 548 | { |
| 549 | { 0, 0, 0, 0 }, |
| 550 | { { MNEM, ' ', OP (DR), 0 } }, |
| 551 | & ifmt_mvfachi, { 0x50f1 } |
| 552 | }, |
| 553 | /* mvfacmi $dr */ |
| 554 | { |
| 555 | { 0, 0, 0, 0 }, |
| 556 | { { MNEM, ' ', OP (DR), 0 } }, |
| 557 | & ifmt_mvfachi, { 0x50f2 } |
| 558 | }, |
| 559 | /* mvfc $dr,$scr */ |
| 560 | { |
| 561 | { 0, 0, 0, 0 }, |
| 562 | { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, |
| 563 | & ifmt_mvfc, { 0x1090 } |
| 564 | }, |
| 565 | /* mvtachi $src1 */ |
| 566 | { |
| 567 | { 0, 0, 0, 0 }, |
| 568 | { { MNEM, ' ', OP (SRC1), 0 } }, |
| 569 | & ifmt_mvtachi, { 0x5070 } |
| 570 | }, |
| 571 | /* mvtaclo $src1 */ |
| 572 | { |
| 573 | { 0, 0, 0, 0 }, |
| 574 | { { MNEM, ' ', OP (SRC1), 0 } }, |
| 575 | & ifmt_mvtachi, { 0x5071 } |
| 576 | }, |
| 577 | /* mvtc $sr,$dcr */ |
| 578 | { |
| 579 | { 0, 0, 0, 0 }, |
| 580 | { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, |
| 581 | & ifmt_mvtc, { 0x10a0 } |
| 582 | }, |
| 583 | /* neg $dr,$sr */ |
| 584 | { |
| 585 | { 0, 0, 0, 0 }, |
| 586 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 587 | & ifmt_add, { 0x30 } |
| 588 | }, |
| 589 | /* nop */ |
| 590 | { |
| 591 | { 0, 0, 0, 0 }, |
| 592 | { { MNEM, 0 } }, |
| 593 | & ifmt_nop, { 0x7000 } |
| 594 | }, |
| 595 | /* not $dr,$sr */ |
| 596 | { |
| 597 | { 0, 0, 0, 0 }, |
| 598 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 599 | & ifmt_add, { 0xb0 } |
| 600 | }, |
| 601 | /* rac */ |
| 602 | { |
| 603 | { 0, 0, 0, 0 }, |
| 604 | { { MNEM, 0 } }, |
| 605 | & ifmt_nop, { 0x5090 } |
| 606 | }, |
| 607 | /* rach */ |
| 608 | { |
| 609 | { 0, 0, 0, 0 }, |
| 610 | { { MNEM, 0 } }, |
| 611 | & ifmt_nop, { 0x5080 } |
| 612 | }, |
| 613 | /* rte */ |
| 614 | { |
| 615 | { 0, 0, 0, 0 }, |
| 616 | { { MNEM, 0 } }, |
| 617 | & ifmt_nop, { 0x10d6 } |
| 618 | }, |
| 619 | /* seth $dr,$hash$hi16 */ |
| 620 | { |
| 621 | { 0, 0, 0, 0 }, |
| 622 | { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, |
| 623 | & ifmt_seth, { 0xd0c00000 } |
| 624 | }, |
| 625 | /* sll $dr,$sr */ |
| 626 | { |
| 627 | { 0, 0, 0, 0 }, |
| 628 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 629 | & ifmt_add, { 0x1040 } |
| 630 | }, |
| 631 | /* sll3 $dr,$sr,$simm16 */ |
| 632 | { |
| 633 | { 0, 0, 0, 0 }, |
| 634 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, |
| 635 | & ifmt_addv3, { 0x90c00000 } |
| 636 | }, |
| 637 | /* slli $dr,$uimm5 */ |
| 638 | { |
| 639 | { 0, 0, 0, 0 }, |
| 640 | { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, |
| 641 | & ifmt_slli, { 0x5040 } |
| 642 | }, |
| 643 | /* sra $dr,$sr */ |
| 644 | { |
| 645 | { 0, 0, 0, 0 }, |
| 646 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 647 | & ifmt_add, { 0x1020 } |
| 648 | }, |
| 649 | /* sra3 $dr,$sr,$simm16 */ |
| 650 | { |
| 651 | { 0, 0, 0, 0 }, |
| 652 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, |
| 653 | & ifmt_addv3, { 0x90a00000 } |
| 654 | }, |
| 655 | /* srai $dr,$uimm5 */ |
| 656 | { |
| 657 | { 0, 0, 0, 0 }, |
| 658 | { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, |
| 659 | & ifmt_slli, { 0x5020 } |
| 660 | }, |
| 661 | /* srl $dr,$sr */ |
| 662 | { |
| 663 | { 0, 0, 0, 0 }, |
| 664 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 665 | & ifmt_add, { 0x1000 } |
| 666 | }, |
| 667 | /* srl3 $dr,$sr,$simm16 */ |
| 668 | { |
| 669 | { 0, 0, 0, 0 }, |
| 670 | { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, |
| 671 | & ifmt_addv3, { 0x90800000 } |
| 672 | }, |
| 673 | /* srli $dr,$uimm5 */ |
| 674 | { |
| 675 | { 0, 0, 0, 0 }, |
| 676 | { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, |
| 677 | & ifmt_slli, { 0x5000 } |
| 678 | }, |
| 679 | /* st $src1,@$src2 */ |
| 680 | { |
| 681 | { 0, 0, 0, 0 }, |
| 682 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, |
| 683 | & ifmt_cmp, { 0x2040 } |
| 684 | }, |
| 685 | /* st $src1,@($slo16,$src2) */ |
| 686 | { |
| 687 | { 0, 0, 0, 0 }, |
| 688 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, |
| 689 | & ifmt_st_d, { 0xa0400000 } |
| 690 | }, |
| 691 | /* stb $src1,@$src2 */ |
| 692 | { |
| 693 | { 0, 0, 0, 0 }, |
| 694 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, |
| 695 | & ifmt_cmp, { 0x2000 } |
| 696 | }, |
| 697 | /* stb $src1,@($slo16,$src2) */ |
| 698 | { |
| 699 | { 0, 0, 0, 0 }, |
| 700 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, |
| 701 | & ifmt_st_d, { 0xa0000000 } |
| 702 | }, |
| 703 | /* sth $src1,@$src2 */ |
| 704 | { |
| 705 | { 0, 0, 0, 0 }, |
| 706 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, |
| 707 | & ifmt_cmp, { 0x2020 } |
| 708 | }, |
| 709 | /* sth $src1,@($slo16,$src2) */ |
| 710 | { |
| 711 | { 0, 0, 0, 0 }, |
| 712 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, |
| 713 | & ifmt_st_d, { 0xa0200000 } |
| 714 | }, |
| 715 | /* st $src1,@+$src2 */ |
| 716 | { |
| 717 | { 0, 0, 0, 0 }, |
| 718 | { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, |
| 719 | & ifmt_cmp, { 0x2060 } |
| 720 | }, |
| 721 | /* st $src1,@-$src2 */ |
| 722 | { |
| 723 | { 0, 0, 0, 0 }, |
| 724 | { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, |
| 725 | & ifmt_cmp, { 0x2070 } |
| 726 | }, |
| 727 | /* sub $dr,$sr */ |
| 728 | { |
| 729 | { 0, 0, 0, 0 }, |
| 730 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 731 | & ifmt_add, { 0x20 } |
| 732 | }, |
| 733 | /* subv $dr,$sr */ |
| 734 | { |
| 735 | { 0, 0, 0, 0 }, |
| 736 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 737 | & ifmt_add, { 0x0 } |
| 738 | }, |
| 739 | /* subx $dr,$sr */ |
| 740 | { |
| 741 | { 0, 0, 0, 0 }, |
| 742 | { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, |
| 743 | & ifmt_add, { 0x10 } |
| 744 | }, |
| 745 | /* trap $uimm4 */ |
| 746 | { |
| 747 | { 0, 0, 0, 0 }, |
| 748 | { { MNEM, ' ', OP (UIMM4), 0 } }, |
| 749 | & ifmt_trap, { 0x10f0 } |
| 750 | }, |
| 751 | /* unlock $src1,@$src2 */ |
| 752 | { |
| 753 | { 0, 0, 0, 0 }, |
| 754 | { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, |
| 755 | & ifmt_cmp, { 0x2050 } |
| 756 | }, |
| 757 | }; |
| 758 | |
| 759 | #undef A |
| 760 | #undef MNEM |
| 761 | #undef OPERAND |
| 762 | #undef OP |
| 763 | |
| 764 | /* Formats for ALIAS macro-insns. */ |
| 765 | |
| 766 | #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] |
| 767 | |
| 768 | static const CGEN_IFMT ifmt_bc8r = { |
| 769 | 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } |
| 770 | }; |
| 771 | |
| 772 | static const CGEN_IFMT ifmt_bc24r = { |
| 773 | 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } |
| 774 | }; |
| 775 | |
| 776 | static const CGEN_IFMT ifmt_bl8r = { |
| 777 | 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } |
| 778 | }; |
| 779 | |
| 780 | static const CGEN_IFMT ifmt_bl24r = { |
| 781 | 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } |
| 782 | }; |
| 783 | |
| 784 | static const CGEN_IFMT ifmt_bnc8r = { |
| 785 | 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } |
| 786 | }; |
| 787 | |
| 788 | static const CGEN_IFMT ifmt_bnc24r = { |
| 789 | 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } |
| 790 | }; |
| 791 | |
| 792 | static const CGEN_IFMT ifmt_bra8r = { |
| 793 | 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } |
| 794 | }; |
| 795 | |
| 796 | static const CGEN_IFMT ifmt_bra24r = { |
| 797 | 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } |
| 798 | }; |
| 799 | |
| 800 | static const CGEN_IFMT ifmt_ld_2 = { |
| 801 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 802 | }; |
| 803 | |
| 804 | static const CGEN_IFMT ifmt_ld_d2 = { |
| 805 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 806 | }; |
| 807 | |
| 808 | static const CGEN_IFMT ifmt_ldb_2 = { |
| 809 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 810 | }; |
| 811 | |
| 812 | static const CGEN_IFMT ifmt_ldb_d2 = { |
| 813 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 814 | }; |
| 815 | |
| 816 | static const CGEN_IFMT ifmt_ldh_2 = { |
| 817 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 818 | }; |
| 819 | |
| 820 | static const CGEN_IFMT ifmt_ldh_d2 = { |
| 821 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 822 | }; |
| 823 | |
| 824 | static const CGEN_IFMT ifmt_ldub_2 = { |
| 825 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 826 | }; |
| 827 | |
| 828 | static const CGEN_IFMT ifmt_ldub_d2 = { |
| 829 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 830 | }; |
| 831 | |
| 832 | static const CGEN_IFMT ifmt_lduh_2 = { |
| 833 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 834 | }; |
| 835 | |
| 836 | static const CGEN_IFMT ifmt_lduh_d2 = { |
| 837 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 838 | }; |
| 839 | |
| 840 | static const CGEN_IFMT ifmt_pop = { |
| 841 | 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } |
| 842 | }; |
| 843 | |
| 844 | static const CGEN_IFMT ifmt_ldi8a = { |
| 845 | 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } |
| 846 | }; |
| 847 | |
| 848 | static const CGEN_IFMT ifmt_ldi16a = { |
| 849 | 32, 32, 0xf0ff0000, { F (F_OP1), F (F_OP2), F (F_R2), F (F_R1), F (F_SIMM16), 0 } |
| 850 | }; |
| 851 | |
| 852 | static const CGEN_IFMT ifmt_st_2 = { |
| 853 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 854 | }; |
| 855 | |
| 856 | static const CGEN_IFMT ifmt_st_d2 = { |
| 857 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 858 | }; |
| 859 | |
| 860 | static const CGEN_IFMT ifmt_stb_2 = { |
| 861 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 862 | }; |
| 863 | |
| 864 | static const CGEN_IFMT ifmt_stb_d2 = { |
| 865 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 866 | }; |
| 867 | |
| 868 | static const CGEN_IFMT ifmt_sth_2 = { |
| 869 | 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 870 | }; |
| 871 | |
| 872 | static const CGEN_IFMT ifmt_sth_d2 = { |
| 873 | 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } |
| 874 | }; |
| 875 | |
| 876 | static const CGEN_IFMT ifmt_push = { |
| 877 | 16, 16, 0xf0ff, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } |
| 878 | }; |
| 879 | |
| 880 | #undef F |
| 881 | |
| 882 | /* Each non-simple macro entry points to an array of expansion possibilities. */ |
| 883 | |
| 884 | #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) |
| 885 | #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ |
| 886 | #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) |
| 887 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) |
| 888 | |
| 889 | /* The macro instruction table. */ |
| 890 | |
| 891 | static const CGEN_IBASE m32r_cgen_macro_insn_table[] = |
| 892 | { |
| 893 | /* bc $disp8 */ |
| 894 | { |
| 895 | -1, "bc8r", "bc", 16, |
| 896 | { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 897 | }, |
| 898 | /* bc $disp24 */ |
| 899 | { |
| 900 | -1, "bc24r", "bc", 32, |
| 901 | { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 902 | }, |
| 903 | /* bl $disp8 */ |
| 904 | { |
| 905 | -1, "bl8r", "bl", 16, |
| 906 | { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 907 | }, |
| 908 | /* bl $disp24 */ |
| 909 | { |
| 910 | -1, "bl24r", "bl", 32, |
| 911 | { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 912 | }, |
| 913 | /* bnc $disp8 */ |
| 914 | { |
| 915 | -1, "bnc8r", "bnc", 16, |
| 916 | { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 917 | }, |
| 918 | /* bnc $disp24 */ |
| 919 | { |
| 920 | -1, "bnc24r", "bnc", 32, |
| 921 | { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 922 | }, |
| 923 | /* bra $disp8 */ |
| 924 | { |
| 925 | -1, "bra8r", "bra", 16, |
| 926 | { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 927 | }, |
| 928 | /* bra $disp24 */ |
| 929 | { |
| 930 | -1, "bra24r", "bra", 32, |
| 931 | { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE) } } |
| 932 | }, |
| 933 | /* ld $dr,@($sr) */ |
| 934 | { |
| 935 | -1, "ld-2", "ld", 16, |
| 936 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 937 | }, |
| 938 | /* ld $dr,@($sr,$slo16) */ |
| 939 | { |
| 940 | -1, "ld-d2", "ld", 32, |
| 941 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 942 | }, |
| 943 | /* ldb $dr,@($sr) */ |
| 944 | { |
| 945 | -1, "ldb-2", "ldb", 16, |
| 946 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 947 | }, |
| 948 | /* ldb $dr,@($sr,$slo16) */ |
| 949 | { |
| 950 | -1, "ldb-d2", "ldb", 32, |
| 951 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 952 | }, |
| 953 | /* ldh $dr,@($sr) */ |
| 954 | { |
| 955 | -1, "ldh-2", "ldh", 16, |
| 956 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 957 | }, |
| 958 | /* ldh $dr,@($sr,$slo16) */ |
| 959 | { |
| 960 | -1, "ldh-d2", "ldh", 32, |
| 961 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 962 | }, |
| 963 | /* ldub $dr,@($sr) */ |
| 964 | { |
| 965 | -1, "ldub-2", "ldub", 16, |
| 966 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 967 | }, |
| 968 | /* ldub $dr,@($sr,$slo16) */ |
| 969 | { |
| 970 | -1, "ldub-d2", "ldub", 32, |
| 971 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 972 | }, |
| 973 | /* lduh $dr,@($sr) */ |
| 974 | { |
| 975 | -1, "lduh-2", "lduh", 16, |
| 976 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 977 | }, |
| 978 | /* lduh $dr,@($sr,$slo16) */ |
| 979 | { |
| 980 | -1, "lduh-d2", "lduh", 32, |
| 981 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 982 | }, |
| 983 | /* pop $dr */ |
| 984 | { |
| 985 | -1, "pop", "pop", 16, |
| 986 | { 0|A(ALIAS), { (1<<MACH_BASE) } } |
| 987 | }, |
| 988 | /* ldi $dr,$simm8 */ |
| 989 | { |
| 990 | -1, "ldi8a", "ldi", 16, |
| 991 | { 0|A(ALIAS), { (1<<MACH_BASE) } } |
| 992 | }, |
| 993 | /* ldi $dr,$hash$slo16 */ |
| 994 | { |
| 995 | -1, "ldi16a", "ldi", 32, |
| 996 | { 0|A(ALIAS), { (1<<MACH_BASE) } } |
| 997 | }, |
| 998 | /* st $src1,@($src2) */ |
| 999 | { |
| 1000 | -1, "st-2", "st", 16, |
| 1001 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 1002 | }, |
| 1003 | /* st $src1,@($src2,$slo16) */ |
| 1004 | { |
| 1005 | -1, "st-d2", "st", 32, |
| 1006 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 1007 | }, |
| 1008 | /* stb $src1,@($src2) */ |
| 1009 | { |
| 1010 | -1, "stb-2", "stb", 16, |
| 1011 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 1012 | }, |
| 1013 | /* stb $src1,@($src2,$slo16) */ |
| 1014 | { |
| 1015 | -1, "stb-d2", "stb", 32, |
| 1016 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 1017 | }, |
| 1018 | /* sth $src1,@($src2) */ |
| 1019 | { |
| 1020 | -1, "sth-2", "sth", 16, |
| 1021 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 1022 | }, |
| 1023 | /* sth $src1,@($src2,$slo16) */ |
| 1024 | { |
| 1025 | -1, "sth-d2", "sth", 32, |
| 1026 | { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } |
| 1027 | }, |
| 1028 | /* push $src1 */ |
| 1029 | { |
| 1030 | -1, "push", "push", 16, |
| 1031 | { 0|A(ALIAS), { (1<<MACH_BASE) } } |
| 1032 | }, |
| 1033 | }; |
| 1034 | |
| 1035 | /* The macro instruction opcode table. */ |
| 1036 | |
| 1037 | static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] = |
| 1038 | { |
| 1039 | /* bc $disp8 */ |
| 1040 | { |
| 1041 | { 0, 0, 0, 0 }, |
| 1042 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 1043 | & ifmt_bc8r, { 0x7c00 } |
| 1044 | }, |
| 1045 | /* bc $disp24 */ |
| 1046 | { |
| 1047 | { 0, 0, 0, 0 }, |
| 1048 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 1049 | & ifmt_bc24r, { 0xfc000000 } |
| 1050 | }, |
| 1051 | /* bl $disp8 */ |
| 1052 | { |
| 1053 | { 0, 0, 0, 0 }, |
| 1054 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 1055 | & ifmt_bl8r, { 0x7e00 } |
| 1056 | }, |
| 1057 | /* bl $disp24 */ |
| 1058 | { |
| 1059 | { 0, 0, 0, 0 }, |
| 1060 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 1061 | & ifmt_bl24r, { 0xfe000000 } |
| 1062 | }, |
| 1063 | /* bnc $disp8 */ |
| 1064 | { |
| 1065 | { 0, 0, 0, 0 }, |
| 1066 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 1067 | & ifmt_bnc8r, { 0x7d00 } |
| 1068 | }, |
| 1069 | /* bnc $disp24 */ |
| 1070 | { |
| 1071 | { 0, 0, 0, 0 }, |
| 1072 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 1073 | & ifmt_bnc24r, { 0xfd000000 } |
| 1074 | }, |
| 1075 | /* bra $disp8 */ |
| 1076 | { |
| 1077 | { 0, 0, 0, 0 }, |
| 1078 | { { MNEM, ' ', OP (DISP8), 0 } }, |
| 1079 | & ifmt_bra8r, { 0x7f00 } |
| 1080 | }, |
| 1081 | /* bra $disp24 */ |
| 1082 | { |
| 1083 | { 0, 0, 0, 0 }, |
| 1084 | { { MNEM, ' ', OP (DISP24), 0 } }, |
| 1085 | & ifmt_bra24r, { 0xff000000 } |
| 1086 | }, |
| 1087 | /* ld $dr,@($sr) */ |
| 1088 | { |
| 1089 | { 0, 0, 0, 0 }, |
| 1090 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, |
| 1091 | & ifmt_ld_2, { 0x20c0 } |
| 1092 | }, |
| 1093 | /* ld $dr,@($sr,$slo16) */ |
| 1094 | { |
| 1095 | { 0, 0, 0, 0 }, |
| 1096 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, |
| 1097 | & ifmt_ld_d2, { 0xa0c00000 } |
| 1098 | }, |
| 1099 | /* ldb $dr,@($sr) */ |
| 1100 | { |
| 1101 | { 0, 0, 0, 0 }, |
| 1102 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, |
| 1103 | & ifmt_ldb_2, { 0x2080 } |
| 1104 | }, |
| 1105 | /* ldb $dr,@($sr,$slo16) */ |
| 1106 | { |
| 1107 | { 0, 0, 0, 0 }, |
| 1108 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, |
| 1109 | & ifmt_ldb_d2, { 0xa0800000 } |
| 1110 | }, |
| 1111 | /* ldh $dr,@($sr) */ |
| 1112 | { |
| 1113 | { 0, 0, 0, 0 }, |
| 1114 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, |
| 1115 | & ifmt_ldh_2, { 0x20a0 } |
| 1116 | }, |
| 1117 | /* ldh $dr,@($sr,$slo16) */ |
| 1118 | { |
| 1119 | { 0, 0, 0, 0 }, |
| 1120 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, |
| 1121 | & ifmt_ldh_d2, { 0xa0a00000 } |
| 1122 | }, |
| 1123 | /* ldub $dr,@($sr) */ |
| 1124 | { |
| 1125 | { 0, 0, 0, 0 }, |
| 1126 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, |
| 1127 | & ifmt_ldub_2, { 0x2090 } |
| 1128 | }, |
| 1129 | /* ldub $dr,@($sr,$slo16) */ |
| 1130 | { |
| 1131 | { 0, 0, 0, 0 }, |
| 1132 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, |
| 1133 | & ifmt_ldub_d2, { 0xa0900000 } |
| 1134 | }, |
| 1135 | /* lduh $dr,@($sr) */ |
| 1136 | { |
| 1137 | { 0, 0, 0, 0 }, |
| 1138 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, |
| 1139 | & ifmt_lduh_2, { 0x20b0 } |
| 1140 | }, |
| 1141 | /* lduh $dr,@($sr,$slo16) */ |
| 1142 | { |
| 1143 | { 0, 0, 0, 0 }, |
| 1144 | { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, |
| 1145 | & ifmt_lduh_d2, { 0xa0b00000 } |
| 1146 | }, |
| 1147 | /* pop $dr */ |
| 1148 | { |
| 1149 | { 0, 0, 0, 0 }, |
| 1150 | { { MNEM, ' ', OP (DR), 0 } }, |
| 1151 | & ifmt_pop, { 0x20ef } |
| 1152 | }, |
| 1153 | /* ldi $dr,$simm8 */ |
| 1154 | { |
| 1155 | { 0, 0, 0, 0 }, |
| 1156 | { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, |
| 1157 | & ifmt_ldi8a, { 0x6000 } |
| 1158 | }, |
| 1159 | /* ldi $dr,$hash$slo16 */ |
| 1160 | { |
| 1161 | { 0, 0, 0, 0 }, |
| 1162 | { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, |
| 1163 | & ifmt_ldi16a, { 0x90f00000 } |
| 1164 | }, |
| 1165 | /* st $src1,@($src2) */ |
| 1166 | { |
| 1167 | { 0, 0, 0, 0 }, |
| 1168 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, |
| 1169 | & ifmt_st_2, { 0x2040 } |
| 1170 | }, |
| 1171 | /* st $src1,@($src2,$slo16) */ |
| 1172 | { |
| 1173 | { 0, 0, 0, 0 }, |
| 1174 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, |
| 1175 | & ifmt_st_d2, { 0xa0400000 } |
| 1176 | }, |
| 1177 | /* stb $src1,@($src2) */ |
| 1178 | { |
| 1179 | { 0, 0, 0, 0 }, |
| 1180 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, |
| 1181 | & ifmt_stb_2, { 0x2000 } |
| 1182 | }, |
| 1183 | /* stb $src1,@($src2,$slo16) */ |
| 1184 | { |
| 1185 | { 0, 0, 0, 0 }, |
| 1186 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, |
| 1187 | & ifmt_stb_d2, { 0xa0000000 } |
| 1188 | }, |
| 1189 | /* sth $src1,@($src2) */ |
| 1190 | { |
| 1191 | { 0, 0, 0, 0 }, |
| 1192 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, |
| 1193 | & ifmt_sth_2, { 0x2020 } |
| 1194 | }, |
| 1195 | /* sth $src1,@($src2,$slo16) */ |
| 1196 | { |
| 1197 | { 0, 0, 0, 0 }, |
| 1198 | { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, |
| 1199 | & ifmt_sth_d2, { 0xa0200000 } |
| 1200 | }, |
| 1201 | /* push $src1 */ |
| 1202 | { |
| 1203 | { 0, 0, 0, 0 }, |
| 1204 | { { MNEM, ' ', OP (SRC1), 0 } }, |
| 1205 | & ifmt_push, { 0x207f } |
| 1206 | }, |
| 1207 | }; |
| 1208 | |
| 1209 | #undef A |
| 1210 | #undef MNEM |
| 1211 | #undef OPERAND |
| 1212 | #undef OP |
| 1213 | |
| 1214 | #ifndef CGEN_ASM_HASH_P |
| 1215 | #define CGEN_ASM_HASH_P(insn) 1 |
| 1216 | #endif |
| 1217 | |
| 1218 | #ifndef CGEN_DIS_HASH_P |
| 1219 | #define CGEN_DIS_HASH_P(insn) 1 |
| 1220 | #endif |
| 1221 | |
| 1222 | /* Return non-zero if INSN is to be added to the hash table. |
| 1223 | Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ |
| 1224 | |
| 1225 | static int |
| 1226 | asm_hash_insn_p (insn) |
| 1227 | const CGEN_INSN *insn; |
| 1228 | { |
| 1229 | return CGEN_ASM_HASH_P (insn); |
| 1230 | } |
| 1231 | |
| 1232 | static int |
| 1233 | dis_hash_insn_p (insn) |
| 1234 | const CGEN_INSN *insn; |
| 1235 | { |
| 1236 | /* If building the hash table and the NO-DIS attribute is present, |
| 1237 | ignore. */ |
| 1238 | if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) |
| 1239 | return 0; |
| 1240 | return CGEN_DIS_HASH_P (insn); |
| 1241 | } |
| 1242 | |
| 1243 | #ifndef CGEN_ASM_HASH |
| 1244 | #define CGEN_ASM_HASH_SIZE 127 |
| 1245 | #ifdef CGEN_MNEMONIC_OPERANDS |
| 1246 | #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) |
| 1247 | #else |
| 1248 | #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ |
| 1249 | #endif |
| 1250 | #endif |
| 1251 | |
| 1252 | /* It doesn't make much sense to provide a default here, |
| 1253 | but while this is under development we do. |
| 1254 | BUFFER is a pointer to the bytes of the insn, target order. |
| 1255 | VALUE is the first base_insn_bitsize bits as an int in host order. */ |
| 1256 | |
| 1257 | #ifndef CGEN_DIS_HASH |
| 1258 | #define CGEN_DIS_HASH_SIZE 256 |
| 1259 | #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) |
| 1260 | #endif |
| 1261 | |
| 1262 | /* The result is the hash value of the insn. |
| 1263 | Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ |
| 1264 | |
| 1265 | static unsigned int |
| 1266 | asm_hash_insn (mnem) |
| 1267 | const char * mnem; |
| 1268 | { |
| 1269 | return CGEN_ASM_HASH (mnem); |
| 1270 | } |
| 1271 | |
| 1272 | /* BUF is a pointer to the bytes of the insn, target order. |
| 1273 | VALUE is the first base_insn_bitsize bits as an int in host order. */ |
| 1274 | |
| 1275 | static unsigned int |
| 1276 | dis_hash_insn (buf, value) |
| 1277 | const char * buf; |
| 1278 | CGEN_INSN_INT value; |
| 1279 | { |
| 1280 | return CGEN_DIS_HASH (buf, value); |
| 1281 | } |
| 1282 | |
| 1283 | /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ |
| 1284 | |
| 1285 | static void |
| 1286 | set_fields_bitsize (fields, size) |
| 1287 | CGEN_FIELDS *fields; |
| 1288 | int size; |
| 1289 | { |
| 1290 | CGEN_FIELDS_BITSIZE (fields) = size; |
| 1291 | } |
| 1292 | |
| 1293 | /* Function to call before using the operand instance table. |
| 1294 | This plugs the opcode entries and macro instructions into the cpu table. */ |
| 1295 | |
| 1296 | void |
| 1297 | m32r_cgen_init_opcode_table (cd) |
| 1298 | CGEN_CPU_DESC cd; |
| 1299 | { |
| 1300 | int i; |
| 1301 | int num_macros = (sizeof (m32r_cgen_macro_insn_table) / |
| 1302 | sizeof (m32r_cgen_macro_insn_table[0])); |
| 1303 | const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0]; |
| 1304 | const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0]; |
| 1305 | CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); |
| 1306 | memset (insns, 0, num_macros * sizeof (CGEN_INSN)); |
| 1307 | for (i = 0; i < num_macros; ++i) |
| 1308 | { |
| 1309 | insns[i].base = &ib[i]; |
| 1310 | insns[i].opcode = &oc[i]; |
| 1311 | } |
| 1312 | cd->macro_insn_table.init_entries = insns; |
| 1313 | cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); |
| 1314 | cd->macro_insn_table.num_init_entries = num_macros; |
| 1315 | |
| 1316 | oc = & m32r_cgen_insn_opcode_table[0]; |
| 1317 | insns = (CGEN_INSN *) cd->insn_table.init_entries; |
| 1318 | for (i = 0; i < MAX_INSNS; ++i) |
| 1319 | insns[i].opcode = &oc[i]; |
| 1320 | |
| 1321 | cd->sizeof_fields = sizeof (CGEN_FIELDS); |
| 1322 | cd->set_fields_bitsize = set_fields_bitsize; |
| 1323 | |
| 1324 | cd->asm_hash_p = asm_hash_insn_p; |
| 1325 | cd->asm_hash = asm_hash_insn; |
| 1326 | cd->asm_hash_size = CGEN_ASM_HASH_SIZE; |
| 1327 | |
| 1328 | cd->dis_hash_p = dis_hash_insn_p; |
| 1329 | cd->dis_hash = dis_hash_insn; |
| 1330 | cd->dis_hash_size = CGEN_DIS_HASH_SIZE; |
| 1331 | } |