| 1 | /* Instruction description for m32r. |
| 2 | |
| 3 | This file is machine generated with CGEN. |
| 4 | |
| 5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #ifndef m32r_OPC_H |
| 26 | #define m32r_OPC_H |
| 27 | |
| 28 | #define CGEN_ARCH m32r |
| 29 | |
| 30 | /* Given symbol S, return m32r_cgen_<s>. */ |
| 31 | #define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s) |
| 32 | |
| 33 | /* Selected cpu families. */ |
| 34 | #define HAVE_CPU_M32R |
| 35 | /* start-sanitize-m32rx */ |
| 36 | #define HAVE_CPU_M32RX |
| 37 | /* end-sanitize-m32rx */ |
| 38 | |
| 39 | #define CGEN_WORD_BITSIZE 32 |
| 40 | #define CGEN_DEFAULT_INSN_BITSIZE 32 |
| 41 | #define CGEN_BASE_INSN_BITSIZE 32 |
| 42 | #define CGEN_MAX_INSN_BITSIZE 32 |
| 43 | #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) |
| 44 | #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) |
| 45 | #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) |
| 46 | #define CGEN_INT_INSN |
| 47 | |
| 48 | /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ |
| 49 | |
| 50 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. |
| 51 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands |
| 52 | we can't hash on everything up to the space. */ |
| 53 | #define CGEN_MNEMONIC_OPERANDS |
| 54 | |
| 55 | /* Enums. */ |
| 56 | |
| 57 | /* Enum declaration for insn format enums. */ |
| 58 | typedef enum insn_op1 { |
| 59 | OP1_0, OP1_1, OP1_2, OP1_3 |
| 60 | , OP1_4, OP1_5, OP1_6, OP1_7 |
| 61 | , OP1_8, OP1_9, OP1_10, OP1_11 |
| 62 | , OP1_12, OP1_13, OP1_14, OP1_15 |
| 63 | } INSN_OP1; |
| 64 | |
| 65 | /* Enum declaration for op2 enums. */ |
| 66 | typedef enum insn_op2 { |
| 67 | OP2_0, OP2_1, OP2_2, OP2_3 |
| 68 | , OP2_4, OP2_5, OP2_6, OP2_7 |
| 69 | , OP2_8, OP2_9, OP2_10, OP2_11 |
| 70 | , OP2_12, OP2_13, OP2_14, OP2_15 |
| 71 | } INSN_OP2; |
| 72 | |
| 73 | /* Enum declaration for m32r operand types. */ |
| 74 | typedef enum cgen_operand_type { |
| 75 | M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 |
| 76 | , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 |
| 77 | , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16 |
| 78 | /* start-sanitize-m32rx */ |
| 79 | , M32R_OPERAND_IMM1 |
| 80 | /* end-sanitize-m32rx */ |
| 81 | /* start-sanitize-m32rx */ |
| 82 | , M32R_OPERAND_ACCD |
| 83 | /* end-sanitize-m32rx */ |
| 84 | /* start-sanitize-m32rx */ |
| 85 | , M32R_OPERAND_ACCS |
| 86 | /* end-sanitize-m32rx */ |
| 87 | /* start-sanitize-m32rx */ |
| 88 | , M32R_OPERAND_ACC |
| 89 | /* end-sanitize-m32rx */ |
| 90 | , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24 |
| 91 | , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT |
| 92 | , M32R_OPERAND_ACCUM, M32R_OPERAND_MAX |
| 93 | } CGEN_OPERAND_TYPE; |
| 94 | |
| 95 | /* Non-boolean attributes. */ |
| 96 | |
| 97 | /* Enum declaration for machine type selection. */ |
| 98 | typedef enum mach_attr { |
| 99 | MACH_M32R |
| 100 | /* start-sanitize-m32rx */ |
| 101 | , MACH_M32RX |
| 102 | /* end-sanitize-m32rx */ |
| 103 | , MACH_MAX |
| 104 | } MACH_ATTR; |
| 105 | |
| 106 | /* start-sanitize-m32rx */ |
| 107 | /* Enum declaration for parallel execution pipeline selection. */ |
| 108 | typedef enum pipe_attr { |
| 109 | PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS |
| 110 | } PIPE_ATTR; |
| 111 | |
| 112 | /* end-sanitize-m32rx */ |
| 113 | /* Number of architecture variants. */ |
| 114 | #define MAX_MACHS ((int) MACH_MAX) |
| 115 | |
| 116 | /* Number of operands types. */ |
| 117 | #define MAX_OPERANDS ((int) M32R_OPERAND_MAX) |
| 118 | |
| 119 | /* Maximum number of operands referenced by any insn. */ |
| 120 | #define MAX_OPERAND_INSTANCES 8 |
| 121 | |
| 122 | /* Operand and instruction attribute indices. */ |
| 123 | |
| 124 | /* Enum declaration for cgen_operand attrs. */ |
| 125 | typedef enum cgen_operand_attr { |
| 126 | CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC |
| 127 | , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT |
| 128 | , CGEN_OPERAND_UNSIGNED |
| 129 | } CGEN_OPERAND_ATTR; |
| 130 | |
| 131 | /* Number of non-boolean elements in cgen_operand. */ |
| 132 | #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR) |
| 133 | |
| 134 | /* Enum declaration for cgen_insn attrs. */ |
| 135 | typedef enum cgen_insn_attr { |
| 136 | CGEN_INSN_MACH |
| 137 | /* start-sanitize-m32rx */ |
| 138 | , CGEN_INSN_PIPE |
| 139 | /* end-sanitize-m32rx */ |
| 140 | , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL |
| 141 | , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI |
| 142 | } CGEN_INSN_ATTR; |
| 143 | |
| 144 | /* Number of non-boolean elements in cgen_insn. */ |
| 145 | #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS) |
| 146 | |
| 147 | /* Insn types are used by the simulator. */ |
| 148 | /* Enum declaration for m32r instruction types. */ |
| 149 | typedef enum cgen_insn_type { |
| 150 | M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A |
| 151 | , M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR |
| 152 | , M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3 |
| 153 | , M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV |
| 154 | , M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8 |
| 155 | , M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ |
| 156 | , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ |
| 157 | , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S |
| 158 | , M32R_INSN_BL24, M32R_INSN_BL24_L |
| 159 | /* start-sanitize-m32rx */ |
| 160 | , M32R_INSN_BCL8 |
| 161 | /* end-sanitize-m32rx */ |
| 162 | /* start-sanitize-m32rx */ |
| 163 | , M32R_INSN_BCL8_S |
| 164 | /* end-sanitize-m32rx */ |
| 165 | /* start-sanitize-m32rx */ |
| 166 | , M32R_INSN_BCL24 |
| 167 | /* end-sanitize-m32rx */ |
| 168 | /* start-sanitize-m32rx */ |
| 169 | , M32R_INSN_BCL24_L |
| 170 | /* end-sanitize-m32rx */ |
| 171 | , M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L |
| 172 | , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24 |
| 173 | , M32R_INSN_BRA24_L |
| 174 | /* start-sanitize-m32rx */ |
| 175 | , M32R_INSN_BNCL8 |
| 176 | /* end-sanitize-m32rx */ |
| 177 | /* start-sanitize-m32rx */ |
| 178 | , M32R_INSN_BNCL8_S |
| 179 | /* end-sanitize-m32rx */ |
| 180 | /* start-sanitize-m32rx */ |
| 181 | , M32R_INSN_BNCL24 |
| 182 | /* end-sanitize-m32rx */ |
| 183 | /* start-sanitize-m32rx */ |
| 184 | , M32R_INSN_BNCL24_L |
| 185 | /* end-sanitize-m32rx */ |
| 186 | , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU |
| 187 | , M32R_INSN_CMPUI, M32R_INSN_CMPUI_A |
| 188 | /* start-sanitize-m32rx */ |
| 189 | , M32R_INSN_CMPEQ |
| 190 | /* end-sanitize-m32rx */ |
| 191 | /* start-sanitize-m32rx */ |
| 192 | , M32R_INSN_CMPZ |
| 193 | /* end-sanitize-m32rx */ |
| 194 | , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU |
| 195 | /* start-sanitize-m32rx */ |
| 196 | , M32R_INSN_DIVH |
| 197 | /* end-sanitize-m32rx */ |
| 198 | /* start-sanitize-m32rx */ |
| 199 | , M32R_INSN_JC |
| 200 | /* end-sanitize-m32rx */ |
| 201 | /* start-sanitize-m32rx */ |
| 202 | , M32R_INSN_JNC |
| 203 | /* end-sanitize-m32rx */ |
| 204 | , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2 |
| 205 | , M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2 |
| 206 | , M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2 |
| 207 | , M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2 |
| 208 | , M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2 |
| 209 | , M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24 |
| 210 | , M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A |
| 211 | , M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK |
| 212 | , M32R_INSN_MACHI |
| 213 | /* start-sanitize-m32rx */ |
| 214 | , M32R_INSN_MACHI_A |
| 215 | /* end-sanitize-m32rx */ |
| 216 | , M32R_INSN_MACLO |
| 217 | /* start-sanitize-m32rx */ |
| 218 | , M32R_INSN_MACLO_A |
| 219 | /* end-sanitize-m32rx */ |
| 220 | , M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI |
| 221 | /* start-sanitize-m32rx */ |
| 222 | , M32R_INSN_MULHI_A |
| 223 | /* end-sanitize-m32rx */ |
| 224 | , M32R_INSN_MULLO |
| 225 | /* start-sanitize-m32rx */ |
| 226 | , M32R_INSN_MULLO_A |
| 227 | /* end-sanitize-m32rx */ |
| 228 | , M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI |
| 229 | /* start-sanitize-m32rx */ |
| 230 | , M32R_INSN_MVFACHI_A |
| 231 | /* end-sanitize-m32rx */ |
| 232 | , M32R_INSN_MVFACLO |
| 233 | /* start-sanitize-m32rx */ |
| 234 | , M32R_INSN_MVFACLO_A |
| 235 | /* end-sanitize-m32rx */ |
| 236 | , M32R_INSN_MVFACMI |
| 237 | /* start-sanitize-m32rx */ |
| 238 | , M32R_INSN_MVFACMI_A |
| 239 | /* end-sanitize-m32rx */ |
| 240 | , M32R_INSN_MVFC, M32R_INSN_MVTACHI |
| 241 | /* start-sanitize-m32rx */ |
| 242 | , M32R_INSN_MVTACHI_A |
| 243 | /* end-sanitize-m32rx */ |
| 244 | , M32R_INSN_MVTACLO |
| 245 | /* start-sanitize-m32rx */ |
| 246 | , M32R_INSN_MVTACLO_A |
| 247 | /* end-sanitize-m32rx */ |
| 248 | , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT |
| 249 | , M32R_INSN_RAC |
| 250 | /* start-sanitize-m32rx */ |
| 251 | , M32R_INSN_RAC_D |
| 252 | /* end-sanitize-m32rx */ |
| 253 | /* start-sanitize-m32rx */ |
| 254 | , M32R_INSN_RAC_DS |
| 255 | /* end-sanitize-m32rx */ |
| 256 | /* start-sanitize-m32rx */ |
| 257 | , M32R_INSN_RAC_DSI |
| 258 | /* end-sanitize-m32rx */ |
| 259 | , M32R_INSN_RACH |
| 260 | /* start-sanitize-m32rx */ |
| 261 | , M32R_INSN_RACH_D |
| 262 | /* end-sanitize-m32rx */ |
| 263 | /* start-sanitize-m32rx */ |
| 264 | , M32R_INSN_RACH_DS |
| 265 | /* end-sanitize-m32rx */ |
| 266 | /* start-sanitize-m32rx */ |
| 267 | , M32R_INSN_RACH_DSI |
| 268 | /* end-sanitize-m32rx */ |
| 269 | , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL |
| 270 | , M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A |
| 271 | , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI |
| 272 | , M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A |
| 273 | , M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2 |
| 274 | , M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2 |
| 275 | , M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2 |
| 276 | , M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS |
| 277 | , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP |
| 278 | , M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP |
| 279 | /* start-sanitize-m32rx */ |
| 280 | , M32R_INSN_SATB |
| 281 | /* end-sanitize-m32rx */ |
| 282 | /* start-sanitize-m32rx */ |
| 283 | , M32R_INSN_SATH |
| 284 | /* end-sanitize-m32rx */ |
| 285 | /* start-sanitize-m32rx */ |
| 286 | , M32R_INSN_SAT |
| 287 | /* end-sanitize-m32rx */ |
| 288 | /* start-sanitize-m32rx */ |
| 289 | , M32R_INSN_PCMPBZ |
| 290 | /* end-sanitize-m32rx */ |
| 291 | /* start-sanitize-m32rx */ |
| 292 | , M32R_INSN_SADD |
| 293 | /* end-sanitize-m32rx */ |
| 294 | /* start-sanitize-m32rx */ |
| 295 | , M32R_INSN_MACWU1 |
| 296 | /* end-sanitize-m32rx */ |
| 297 | /* start-sanitize-m32rx */ |
| 298 | , M32R_INSN_MSBLO |
| 299 | /* end-sanitize-m32rx */ |
| 300 | /* start-sanitize-m32rx */ |
| 301 | , M32R_INSN_MULWU1 |
| 302 | /* end-sanitize-m32rx */ |
| 303 | /* start-sanitize-m32rx */ |
| 304 | , M32R_INSN_MACLH1 |
| 305 | /* end-sanitize-m32rx */ |
| 306 | /* start-sanitize-m32rx */ |
| 307 | , M32R_INSN_SC |
| 308 | /* end-sanitize-m32rx */ |
| 309 | /* start-sanitize-m32rx */ |
| 310 | , M32R_INSN_SNC |
| 311 | /* end-sanitize-m32rx */ |
| 312 | , M32R_INSN_MAX |
| 313 | } CGEN_INSN_TYPE; |
| 314 | |
| 315 | /* Index of `illegal' insn place holder. */ |
| 316 | #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL |
| 317 | /* Total number of insns in table. */ |
| 318 | #define MAX_INSNS ((int) M32R_INSN_MAX) |
| 319 | |
| 320 | /* cgen.h uses things we just defined. */ |
| 321 | #include "opcode/cgen.h" |
| 322 | |
| 323 | /* This struct records data prior to insertion or after extraction. */ |
| 324 | struct cgen_fields |
| 325 | { |
| 326 | long f_nil; |
| 327 | long f_op1; |
| 328 | long f_op2; |
| 329 | long f_cond; |
| 330 | long f_r1; |
| 331 | long f_r2; |
| 332 | long f_simm8; |
| 333 | long f_simm16; |
| 334 | long f_shift_op2; |
| 335 | long f_uimm4; |
| 336 | long f_uimm5; |
| 337 | long f_uimm16; |
| 338 | long f_uimm24; |
| 339 | long f_hi16; |
| 340 | long f_disp8; |
| 341 | long f_disp16; |
| 342 | long f_disp24; |
| 343 | /* start-sanitize-m32rx */ |
| 344 | long f_op23; |
| 345 | /* end-sanitize-m32rx */ |
| 346 | /* start-sanitize-m32rx */ |
| 347 | long f_op3; |
| 348 | /* end-sanitize-m32rx */ |
| 349 | /* start-sanitize-m32rx */ |
| 350 | long f_acc; |
| 351 | /* end-sanitize-m32rx */ |
| 352 | /* start-sanitize-m32rx */ |
| 353 | long f_accs; |
| 354 | /* end-sanitize-m32rx */ |
| 355 | /* start-sanitize-m32rx */ |
| 356 | long f_accd; |
| 357 | /* end-sanitize-m32rx */ |
| 358 | /* start-sanitize-m32rx */ |
| 359 | long f_bits67; |
| 360 | /* end-sanitize-m32rx */ |
| 361 | /* start-sanitize-m32rx */ |
| 362 | long f_bit14; |
| 363 | /* end-sanitize-m32rx */ |
| 364 | /* start-sanitize-m32rx */ |
| 365 | long f_imm1; |
| 366 | /* end-sanitize-m32rx */ |
| 367 | int length; |
| 368 | }; |
| 369 | |
| 370 | /* Attributes. */ |
| 371 | extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; |
| 372 | extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; |
| 373 | |
| 374 | /* Enum declaration for m32r hardware types. */ |
| 375 | typedef enum hw_type { |
| 376 | HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT |
| 377 | , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16 |
| 378 | , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM |
| 379 | /* start-sanitize-m32rx */ |
| 380 | , HW_H_ACCUMS |
| 381 | /* end-sanitize-m32rx */ |
| 382 | /* start-sanitize-m32rx */ |
| 383 | , HW_H_ABORT |
| 384 | /* end-sanitize-m32rx */ |
| 385 | , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE |
| 386 | , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK |
| 387 | , HW_MAX |
| 388 | } HW_TYPE; |
| 389 | |
| 390 | #define MAX_HW ((int) HW_MAX) |
| 391 | |
| 392 | /* Hardware decls. */ |
| 393 | |
| 394 | extern CGEN_KEYWORD m32r_cgen_opval_h_gr; |
| 395 | extern CGEN_KEYWORD m32r_cgen_opval_h_cr; |
| 396 | /* start-sanitize-m32rx */ |
| 397 | extern CGEN_KEYWORD m32r_cgen_opval_h_accums; |
| 398 | /* end-sanitize-m32rx */ |
| 399 | |
| 400 | #define CGEN_INIT_PARSE() \ |
| 401 | {\ |
| 402 | } |
| 403 | #define CGEN_INIT_INSERT() \ |
| 404 | {\ |
| 405 | } |
| 406 | #define CGEN_INIT_EXTRACT() \ |
| 407 | {\ |
| 408 | } |
| 409 | #define CGEN_INIT_PRINT() \ |
| 410 | {\ |
| 411 | } |
| 412 | |
| 413 | /* -- opc.h */ |
| 414 | |
| 415 | #undef CGEN_DIS_HASH_SIZE |
| 416 | #define CGEN_DIS_HASH_SIZE 256 |
| 417 | #undef CGEN_DIS_HASH |
| 418 | #define X(b) (((unsigned char *) (b))[0] & 0xf0) |
| 419 | #define CGEN_DIS_HASH(buffer, insn) \ |
| 420 | (X (buffer) | \ |
| 421 | (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ |
| 422 | : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ |
| 423 | : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ |
| 424 | : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) |
| 425 | |
| 426 | /* -- */ |
| 427 | |
| 428 | |
| 429 | #endif /* m32r_OPC_H */ |