projects / deliverable / binutils-gdb.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
2001-11-04 Chris Demetriou <cgd@broadcom.com>
[deliverable/binutils-gdb.git] / opcodes / m32r-opinst.c
... / ...
CommitLineData
1/* Semantic operand instances for m32r.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "m32r-desc.h"
30#include "m32r-opc.h"
31
32/* Operand references. */
33
34#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
35#define OP_ENT(op) M32R_OPERAND_##op
36#else
37#define OP_ENT(op) M32R_OPERAND_/**/op
38#endif
39#define INPUT CGEN_OPINST_INPUT
40#define OUTPUT CGEN_OPINST_OUTPUT
41#define END CGEN_OPINST_END
42#define COND_REF CGEN_OPINST_COND_REF
43
44static const CGEN_OPINST sfmt_empty_ops[] = {
45 { END }
46};
47
48static const CGEN_OPINST sfmt_add_ops[] = {
49 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
50 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
51 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
52 { END }
53};
54
55static const CGEN_OPINST sfmt_add3_ops[] = {
56 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
57 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
58 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
59 { END }
60};
61
62static const CGEN_OPINST sfmt_and3_ops[] = {
63 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
64 { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
65 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
66 { END }
67};
68
69static const CGEN_OPINST sfmt_or3_ops[] = {
70 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
71 { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
72 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
73 { END }
74};
75
76static const CGEN_OPINST sfmt_addi_ops[] = {
77 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
78 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
79 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
80 { END }
81};
82
83static const CGEN_OPINST sfmt_addv_ops[] = {
84 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
85 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
86 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
87 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
88 { END }
89};
90
91static const CGEN_OPINST sfmt_addv3_ops[] = {
92 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
93 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
94 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
95 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
96 { END }
97};
98
99static const CGEN_OPINST sfmt_addx_ops[] = {
100 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
101 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
102 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
103 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
104 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
105 { END }
106};
107
108static const CGEN_OPINST sfmt_bc8_ops[] = {
109 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
110 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
111 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
112 { END }
113};
114
115static const CGEN_OPINST sfmt_bc24_ops[] = {
116 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
117 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
118 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
119 { END }
120};
121
122static const CGEN_OPINST sfmt_beq_ops[] = {
123 { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
124 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
125 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
126 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
127 { END }
128};
129
130static const CGEN_OPINST sfmt_beqz_ops[] = {
131 { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
132 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
133 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
134 { END }
135};
136
137static const CGEN_OPINST sfmt_bl8_ops[] = {
138 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
139 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
140 { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
141 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
142 { END }
143};
144
145static const CGEN_OPINST sfmt_bl24_ops[] = {
146 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
147 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
148 { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
149 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
150 { END }
151};
152
153static const CGEN_OPINST sfmt_bcl8_ops[] = {
154 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
155 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
156 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
157 { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
158 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
159 { END }
160};
161
162static const CGEN_OPINST sfmt_bcl24_ops[] = {
163 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
164 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
165 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
166 { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
167 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
168 { END }
169};
170
171static const CGEN_OPINST sfmt_bra8_ops[] = {
172 { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
173 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
174 { END }
175};
176
177static const CGEN_OPINST sfmt_bra24_ops[] = {
178 { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
179 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
180 { END }
181};
182
183static const CGEN_OPINST sfmt_cmp_ops[] = {
184 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
185 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
186 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
187 { END }
188};
189
190static const CGEN_OPINST sfmt_cmpi_ops[] = {
191 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
192 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
193 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
194 { END }
195};
196
197static const CGEN_OPINST sfmt_cmpz_ops[] = {
198 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
199 { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
200 { END }
201};
202
203static const CGEN_OPINST sfmt_div_ops[] = {
204 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
205 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
206 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
207 { END }
208};
209
210static const CGEN_OPINST sfmt_jc_ops[] = {
211 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
212 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
213 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
214 { END }
215};
216
217static const CGEN_OPINST sfmt_jl_ops[] = {
218 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
219 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
220 { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
221 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
222 { END }
223};
224
225static const CGEN_OPINST sfmt_jmp_ops[] = {
226 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
227 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
228 { END }
229};
230
231static const CGEN_OPINST sfmt_ld_ops[] = {
232 { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
233 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
234 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
235 { END }
236};
237
238static const CGEN_OPINST sfmt_ld_d_ops[] = {
239 { INPUT, "h_memory_SI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
240 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
241 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
242 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
243 { END }
244};
245
246static const CGEN_OPINST sfmt_ldb_ops[] = {
247 { INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
248 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
249 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
250 { END }
251};
252
253static const CGEN_OPINST sfmt_ldb_d_ops[] = {
254 { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
255 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
256 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
257 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
258 { END }
259};
260
261static const CGEN_OPINST sfmt_ldh_ops[] = {
262 { INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
263 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
264 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
265 { END }
266};
267
268static const CGEN_OPINST sfmt_ldh_d_ops[] = {
269 { INPUT, "h_memory_HI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
270 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
271 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
272 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
273 { END }
274};
275
276static const CGEN_OPINST sfmt_ld_plus_ops[] = {
277 { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
278 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
279 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
280 { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
281 { END }
282};
283
284static const CGEN_OPINST sfmt_ld24_ops[] = {
285 { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
286 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
287 { END }
288};
289
290static const CGEN_OPINST sfmt_ldi8_ops[] = {
291 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
292 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
293 { END }
294};
295
296static const CGEN_OPINST sfmt_ldi16_ops[] = {
297 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
298 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
299 { END }
300};
301
302static const CGEN_OPINST sfmt_lock_ops[] = {
303 { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
304 { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
305 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
306 { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
307 { END }
308};
309
310static const CGEN_OPINST sfmt_machi_ops[] = {
311 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
312 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
313 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
314 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
315 { END }
316};
317
318static const CGEN_OPINST sfmt_machi_a_ops[] = {
319 { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
320 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
321 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
322 { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
323 { END }
324};
325
326static const CGEN_OPINST sfmt_mulhi_ops[] = {
327 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
328 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
329 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
330 { END }
331};
332
333static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
334 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
335 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
336 { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
337 { END }
338};
339
340static const CGEN_OPINST sfmt_mv_ops[] = {
341 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
342 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
343 { END }
344};
345
346static const CGEN_OPINST sfmt_mvfachi_ops[] = {
347 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
348 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
349 { END }
350};
351
352static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
353 { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
354 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
355 { END }
356};
357
358static const CGEN_OPINST sfmt_mvfc_ops[] = {
359 { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
360 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
361 { END }
362};
363
364static const CGEN_OPINST sfmt_mvtachi_ops[] = {
365 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
366 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
367 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
368 { END }
369};
370
371static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
372 { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
373 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
374 { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
375 { END }
376};
377
378static const CGEN_OPINST sfmt_mvtc_ops[] = {
379 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
380 { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
381 { END }
382};
383
384static const CGEN_OPINST sfmt_nop_ops[] = {
385 { END }
386};
387
388static const CGEN_OPINST sfmt_rac_ops[] = {
389 { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
390 { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
391 { END }
392};
393
394static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
395 { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
396 { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
397 { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
398 { END }
399};
400
401static const CGEN_OPINST sfmt_rte_ops[] = {
402 { INPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
403 { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
404 { INPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
405 { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
406 { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
407 { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
408 { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
409 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
410 { END }
411};
412
413static const CGEN_OPINST sfmt_seth_ops[] = {
414 { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
415 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
416 { END }
417};
418
419static const CGEN_OPINST sfmt_sll3_ops[] = {
420 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
421 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
422 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
423 { END }
424};
425
426static const CGEN_OPINST sfmt_slli_ops[] = {
427 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
428 { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
429 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
430 { END }
431};
432
433static const CGEN_OPINST sfmt_st_ops[] = {
434 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
435 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
436 { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
437 { END }
438};
439
440static const CGEN_OPINST sfmt_st_d_ops[] = {
441 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
442 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
443 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
444 { OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
445 { END }
446};
447
448static const CGEN_OPINST sfmt_stb_ops[] = {
449 { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
450 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
451 { OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
452 { END }
453};
454
455static const CGEN_OPINST sfmt_stb_d_ops[] = {
456 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
457 { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
458 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
459 { OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
460 { END }
461};
462
463static const CGEN_OPINST sfmt_sth_ops[] = {
464 { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
465 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
466 { OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
467 { END }
468};
469
470static const CGEN_OPINST sfmt_sth_d_ops[] = {
471 { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
472 { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
473 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
474 { OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
475 { END }
476};
477
478static const CGEN_OPINST sfmt_st_plus_ops[] = {
479 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
480 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
481 { OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
482 { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
483 { END }
484};
485
486static const CGEN_OPINST sfmt_trap_ops[] = {
487 { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
488 { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
489 { INPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
490 { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
491 { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
492 { OUTPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
493 { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
494 { OUTPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
495 { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
496 { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
497 { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
498 { END }
499};
500
501static const CGEN_OPINST sfmt_unlock_ops[] = {
502 { INPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
503 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
504 { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
505 { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
506 { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
507 { END }
508};
509
510static const CGEN_OPINST sfmt_satb_ops[] = {
511 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
512 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
513 { END }
514};
515
516static const CGEN_OPINST sfmt_sat_ops[] = {
517 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
518 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
519 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
520 { END }
521};
522
523static const CGEN_OPINST sfmt_sadd_ops[] = {
524 { INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
525 { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
526 { OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
527 { END }
528};
529
530static const CGEN_OPINST sfmt_macwu1_ops[] = {
531 { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
532 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
533 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
534 { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
535 { END }
536};
537
538static const CGEN_OPINST sfmt_mulwu1_ops[] = {
539 { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
540 { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
541 { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
542 { END }
543};
544
545static const CGEN_OPINST sfmt_sc_ops[] = {
546 { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
547 { END }
548};
549
550#undef OP_ENT
551#undef INPUT
552#undef OUTPUT
553#undef END
554#undef COND_REF
555
556/* Operand instance lookup table. */
557
558static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
559 0,
560 & sfmt_add_ops[0],
561 & sfmt_add3_ops[0],
562 & sfmt_add_ops[0],
563 & sfmt_and3_ops[0],
564 & sfmt_add_ops[0],
565 & sfmt_or3_ops[0],
566 & sfmt_add_ops[0],
567 & sfmt_and3_ops[0],
568 & sfmt_addi_ops[0],
569 & sfmt_addv_ops[0],
570 & sfmt_addv3_ops[0],
571 & sfmt_addx_ops[0],
572 & sfmt_bc8_ops[0],
573 & sfmt_bc24_ops[0],
574 & sfmt_beq_ops[0],
575 & sfmt_beqz_ops[0],
576 & sfmt_beqz_ops[0],
577 & sfmt_beqz_ops[0],
578 & sfmt_beqz_ops[0],
579 & sfmt_beqz_ops[0],
580 & sfmt_beqz_ops[0],
581 & sfmt_bl8_ops[0],
582 & sfmt_bl24_ops[0],
583 & sfmt_bcl8_ops[0],
584 & sfmt_bcl24_ops[0],
585 & sfmt_bc8_ops[0],
586 & sfmt_bc24_ops[0],
587 & sfmt_beq_ops[0],
588 & sfmt_bra8_ops[0],
589 & sfmt_bra24_ops[0],
590 & sfmt_bcl8_ops[0],
591 & sfmt_bcl24_ops[0],
592 & sfmt_cmp_ops[0],
593 & sfmt_cmpi_ops[0],
594 & sfmt_cmp_ops[0],
595 & sfmt_cmpi_ops[0],
596 & sfmt_cmp_ops[0],
597 & sfmt_cmpz_ops[0],
598 & sfmt_div_ops[0],
599 & sfmt_div_ops[0],
600 & sfmt_div_ops[0],
601 & sfmt_div_ops[0],
602 & sfmt_div_ops[0],
603 & sfmt_jc_ops[0],
604 & sfmt_jc_ops[0],
605 & sfmt_jl_ops[0],
606 & sfmt_jmp_ops[0],
607 & sfmt_ld_ops[0],
608 & sfmt_ld_d_ops[0],
609 & sfmt_ldb_ops[0],
610 & sfmt_ldb_d_ops[0],
611 & sfmt_ldh_ops[0],
612 & sfmt_ldh_d_ops[0],
613 & sfmt_ldb_ops[0],
614 & sfmt_ldb_d_ops[0],
615 & sfmt_ldh_ops[0],
616 & sfmt_ldh_d_ops[0],
617 & sfmt_ld_plus_ops[0],
618 & sfmt_ld24_ops[0],
619 & sfmt_ldi8_ops[0],
620 & sfmt_ldi16_ops[0],
621 & sfmt_lock_ops[0],
622 & sfmt_machi_ops[0],
623 & sfmt_machi_a_ops[0],
624 & sfmt_machi_ops[0],
625 & sfmt_machi_a_ops[0],
626 & sfmt_machi_ops[0],
627 & sfmt_machi_a_ops[0],
628 & sfmt_machi_ops[0],
629 & sfmt_machi_a_ops[0],
630 & sfmt_add_ops[0],
631 & sfmt_mulhi_ops[0],
632 & sfmt_mulhi_a_ops[0],
633 & sfmt_mulhi_ops[0],
634 & sfmt_mulhi_a_ops[0],
635 & sfmt_mulhi_ops[0],
636 & sfmt_mulhi_a_ops[0],
637 & sfmt_mulhi_ops[0],
638 & sfmt_mulhi_a_ops[0],
639 & sfmt_mv_ops[0],
640 & sfmt_mvfachi_ops[0],
641 & sfmt_mvfachi_a_ops[0],
642 & sfmt_mvfachi_ops[0],
643 & sfmt_mvfachi_a_ops[0],
644 & sfmt_mvfachi_ops[0],
645 & sfmt_mvfachi_a_ops[0],
646 & sfmt_mvfc_ops[0],
647 & sfmt_mvtachi_ops[0],
648 & sfmt_mvtachi_a_ops[0],
649 & sfmt_mvtachi_ops[0],
650 & sfmt_mvtachi_a_ops[0],
651 & sfmt_mvtc_ops[0],
652 & sfmt_mv_ops[0],
653 & sfmt_nop_ops[0],
654 & sfmt_mv_ops[0],
655 & sfmt_rac_ops[0],
656 & sfmt_rac_dsi_ops[0],
657 & sfmt_rac_ops[0],
658 & sfmt_rac_dsi_ops[0],
659 & sfmt_rte_ops[0],
660 & sfmt_seth_ops[0],
661 & sfmt_add_ops[0],
662 & sfmt_sll3_ops[0],
663 & sfmt_slli_ops[0],
664 & sfmt_add_ops[0],
665 & sfmt_sll3_ops[0],
666 & sfmt_slli_ops[0],
667 & sfmt_add_ops[0],
668 & sfmt_sll3_ops[0],
669 & sfmt_slli_ops[0],
670 & sfmt_st_ops[0],
671 & sfmt_st_d_ops[0],
672 & sfmt_stb_ops[0],
673 & sfmt_stb_d_ops[0],
674 & sfmt_sth_ops[0],
675 & sfmt_sth_d_ops[0],
676 & sfmt_st_plus_ops[0],
677 & sfmt_st_plus_ops[0],
678 & sfmt_add_ops[0],
679 & sfmt_addv_ops[0],
680 & sfmt_addx_ops[0],
681 & sfmt_trap_ops[0],
682 & sfmt_unlock_ops[0],
683 & sfmt_satb_ops[0],
684 & sfmt_satb_ops[0],
685 & sfmt_sat_ops[0],
686 & sfmt_cmpz_ops[0],
687 & sfmt_sadd_ops[0],
688 & sfmt_macwu1_ops[0],
689 & sfmt_machi_ops[0],
690 & sfmt_mulwu1_ops[0],
691 & sfmt_macwu1_ops[0],
692 & sfmt_sc_ops[0],
693 & sfmt_sc_ops[0],
694};
695
696/* Function to call before using the operand instance table. */
697
698void
699m32r_cgen_init_opinst_table (cd)
700 CGEN_CPU_DESC cd;
701{
702 int i;
703 const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
704 CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
705 for (i = 0; i < MAX_INSNS; ++i)
706 insns[i].opinst = oi[i];
707}
GDB Binutils - Deliverables
This page took 0.037088 seconds and 4 git commands to generate.