| 1 | /* CPU data header for mep. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright (C) 1996-2014 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #ifndef MEP_CPU_H |
| 26 | #define MEP_CPU_H |
| 27 | |
| 28 | #define CGEN_ARCH mep |
| 29 | |
| 30 | /* Given symbol S, return mep_cgen_<S>. */ |
| 31 | #define CGEN_SYM(s) mep##_cgen_##s |
| 32 | |
| 33 | |
| 34 | /* Selected cpu families. */ |
| 35 | #define HAVE_CPU_MEPF |
| 36 | |
| 37 | #define CGEN_INSN_LSB0_P 0 |
| 38 | |
| 39 | /* Minimum size of any insn (in bytes). */ |
| 40 | #define CGEN_MIN_INSN_SIZE 2 |
| 41 | |
| 42 | /* Maximum size of any insn (in bytes). */ |
| 43 | #define CGEN_MAX_INSN_SIZE 4 |
| 44 | |
| 45 | #define CGEN_INT_INSN_P 1 |
| 46 | |
| 47 | /* Maximum number of syntax elements in an instruction. */ |
| 48 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 |
| 49 | |
| 50 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. |
| 51 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands |
| 52 | we can't hash on everything up to the space. */ |
| 53 | #define CGEN_MNEMONIC_OPERANDS |
| 54 | |
| 55 | /* Maximum number of fields in an instruction. */ |
| 56 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 |
| 57 | |
| 58 | /* Enums. */ |
| 59 | |
| 60 | /* Enum declaration for major opcodes. */ |
| 61 | typedef enum major { |
| 62 | MAJ_0, MAJ_1, MAJ_2, MAJ_3 |
| 63 | , MAJ_4, MAJ_5, MAJ_6, MAJ_7 |
| 64 | , MAJ_8, MAJ_9, MAJ_10, MAJ_11 |
| 65 | , MAJ_12, MAJ_13, MAJ_14, MAJ_15 |
| 66 | } MAJOR; |
| 67 | |
| 68 | /* Attributes. */ |
| 69 | |
| 70 | /* Enum declaration for machine type selection. */ |
| 71 | typedef enum mach_attr { |
| 72 | MACH_BASE, MACH_MEP, MACH_H1, MACH_C5 |
| 73 | , MACH_MAX |
| 74 | } MACH_ATTR; |
| 75 | |
| 76 | /* Enum declaration for instruction set selection. */ |
| 77 | typedef enum isa_attr { |
| 78 | ISA_MEP, ISA_EXT_CORE1, ISA_EXT_COP1_16, ISA_EXT_COP1_32 |
| 79 | , ISA_EXT_COP1_48, ISA_EXT_COP1_64, ISA_MAX |
| 80 | } ISA_ATTR; |
| 81 | |
| 82 | /* Enum declaration for datatype to use for C intrinsics mapping. */ |
| 83 | typedef enum cdata_attr { |
| 84 | CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT |
| 85 | , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT |
| 86 | , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT |
| 87 | } CDATA_ATTR; |
| 88 | |
| 89 | /* Enum declaration for datatype to use for coprocessor values. */ |
| 90 | typedef enum cptype_attr { |
| 91 | CPTYPE_CP_DATA_BUS_INT, CPTYPE_VECT, CPTYPE_V2SI, CPTYPE_V4HI |
| 92 | , CPTYPE_V8QI, CPTYPE_V2USI, CPTYPE_V4UHI, CPTYPE_V8UQI |
| 93 | } CPTYPE_ATTR; |
| 94 | |
| 95 | /* Enum declaration for Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.. */ |
| 96 | typedef enum cret_attr { |
| 97 | CRET_VOID, CRET_FIRST, CRET_FIRSTCOPY |
| 98 | } CRET_ATTR; |
| 99 | |
| 100 | /* Enum declaration for . */ |
| 101 | typedef enum config_attr { |
| 102 | CONFIG_NONE, CONFIG_DEFAULT |
| 103 | } CONFIG_ATTR; |
| 104 | |
| 105 | /* Enum declaration for slots for which this opcode is valid - c3, p0s, p0, p1. */ |
| 106 | typedef enum slots_attr { |
| 107 | SLOTS_CORE, SLOTS_C3, SLOTS_P0S, SLOTS_P0 |
| 108 | , SLOTS_P1 |
| 109 | } SLOTS_ATTR; |
| 110 | |
| 111 | /* Number of architecture variants. */ |
| 112 | #define MAX_ISAS ((int) ISA_MAX) |
| 113 | #define MAX_MACHS ((int) MACH_MAX) |
| 114 | |
| 115 | /* Ifield support. */ |
| 116 | |
| 117 | /* Ifield attribute indices. */ |
| 118 | |
| 119 | /* Enum declaration for cgen_ifld attrs. */ |
| 120 | typedef enum cgen_ifld_attr { |
| 121 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED |
| 122 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 |
| 123 | , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS |
| 124 | } CGEN_IFLD_ATTR; |
| 125 | |
| 126 | /* Number of non-boolean elements in cgen_ifld_attr. */ |
| 127 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) |
| 128 | |
| 129 | /* cgen_ifld attribute accessor macros. */ |
| 130 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) |
| 131 | #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) |
| 132 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) |
| 133 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) |
| 134 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) |
| 135 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) |
| 136 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) |
| 137 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) |
| 138 | |
| 139 | /* Enum declaration for mep ifield types. */ |
| 140 | typedef enum ifield_type { |
| 141 | MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN |
| 142 | , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2 |
| 143 | , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_EXT4 |
| 144 | , MEP_F_EXT62, MEP_F_CRN, MEP_F_CSRN_HI, MEP_F_CSRN_LO |
| 145 | , MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO, MEP_F_CRNX |
| 146 | , MEP_F_0, MEP_F_1, MEP_F_2, MEP_F_3 |
| 147 | , MEP_F_4, MEP_F_5, MEP_F_6, MEP_F_7 |
| 148 | , MEP_F_8, MEP_F_9, MEP_F_10, MEP_F_11 |
| 149 | , MEP_F_12, MEP_F_13, MEP_F_14, MEP_F_15 |
| 150 | , MEP_F_16, MEP_F_17, MEP_F_18, MEP_F_19 |
| 151 | , MEP_F_20, MEP_F_21, MEP_F_22, MEP_F_23 |
| 152 | , MEP_F_24, MEP_F_25, MEP_F_26, MEP_F_27 |
| 153 | , MEP_F_28, MEP_F_29, MEP_F_30, MEP_F_31 |
| 154 | , MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2, MEP_F_24S5A2N_HI |
| 155 | , MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO |
| 156 | , MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9, MEP_F_7U9A2 |
| 157 | , MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10, MEP_F_3U5 |
| 158 | , MEP_F_4U8, MEP_F_5U8, MEP_F_5U24, MEP_F_6S8 |
| 159 | , MEP_F_8S8, MEP_F_16U16, MEP_F_12U16, MEP_F_3U29 |
| 160 | , MEP_F_CDISP10, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N |
| 161 | , MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI |
| 162 | , MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI |
| 163 | , MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5 |
| 164 | , MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20 |
| 165 | , MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20 |
| 166 | , MEP_F_C5_RNMUIMM24, MEP_F_IVC2_2U4, MEP_F_IVC2_3U4, MEP_F_IVC2_8U4 |
| 167 | , MEP_F_IVC2_8S4, MEP_F_IVC2_1U6, MEP_F_IVC2_2U6, MEP_F_IVC2_3U6 |
| 168 | , MEP_F_IVC2_6U6, MEP_F_IVC2_5U7, MEP_F_IVC2_4U8, MEP_F_IVC2_3U9 |
| 169 | , MEP_F_IVC2_5U16, MEP_F_IVC2_5U21, MEP_F_IVC2_5U26, MEP_F_IVC2_1U31 |
| 170 | , MEP_F_IVC2_4U16, MEP_F_IVC2_4U20, MEP_F_IVC2_4U24, MEP_F_IVC2_4U28 |
| 171 | , MEP_F_IVC2_2U0, MEP_F_IVC2_3U0, MEP_F_IVC2_4U0, MEP_F_IVC2_5U0 |
| 172 | , MEP_F_IVC2_8U0, MEP_F_IVC2_8S0, MEP_F_IVC2_6U2, MEP_F_IVC2_5U3 |
| 173 | , MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10 |
| 174 | , MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18 |
| 175 | , MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23 |
| 176 | , MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CCRN_C3HI |
| 177 | , MEP_F_IVC2_CCRN_C3LO, MEP_F_IVC2_CRN, MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1 |
| 178 | , MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO, MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2 |
| 179 | , MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN_C3, MEP_F_IVC2_CCRN, MEP_F_IVC2_CRNX |
| 180 | , MEP_F_MAX |
| 181 | } IFIELD_TYPE; |
| 182 | |
| 183 | #define MAX_IFLD ((int) MEP_F_MAX) |
| 184 | |
| 185 | /* Hardware attribute indices. */ |
| 186 | |
| 187 | /* Enum declaration for cgen_hw attrs. */ |
| 188 | typedef enum cgen_hw_attr { |
| 189 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE |
| 190 | , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH |
| 191 | , CGEN_HW_ISA, CGEN_HW_END_NBOOLS |
| 192 | } CGEN_HW_ATTR; |
| 193 | |
| 194 | /* Number of non-boolean elements in cgen_hw_attr. */ |
| 195 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) |
| 196 | |
| 197 | /* cgen_hw attribute accessor macros. */ |
| 198 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) |
| 199 | #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) |
| 200 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) |
| 201 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) |
| 202 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) |
| 203 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) |
| 204 | #define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_IS_FLOAT)) != 0) |
| 205 | |
| 206 | /* Enum declaration for mep hardware types. */ |
| 207 | typedef enum cgen_hw_type { |
| 208 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR |
| 209 | , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR |
| 210 | , HW_H_CR64, HW_H_CR64_W, HW_H_CR, HW_H_CCR |
| 211 | , HW_H_CCR_W, HW_H_CR_IVC2, HW_H_CCR_IVC2, HW_MAX |
| 212 | } CGEN_HW_TYPE; |
| 213 | |
| 214 | #define MAX_HW ((int) HW_MAX) |
| 215 | |
| 216 | /* Operand attribute indices. */ |
| 217 | |
| 218 | /* Enum declaration for cgen_operand attrs. */ |
| 219 | typedef enum cgen_operand_attr { |
| 220 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT |
| 221 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY |
| 222 | , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH |
| 223 | , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS |
| 224 | } CGEN_OPERAND_ATTR; |
| 225 | |
| 226 | /* Number of non-boolean elements in cgen_operand_attr. */ |
| 227 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) |
| 228 | |
| 229 | /* cgen_operand attribute accessor macros. */ |
| 230 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
| 231 | #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) |
| 232 | #define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
| 233 | #define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
| 234 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) |
| 235 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) |
| 236 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) |
| 237 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) |
| 238 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) |
| 239 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) |
| 240 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) |
| 241 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) |
| 242 | #define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0) |
| 243 | |
| 244 | /* Enum declaration for mep operand types. */ |
| 245 | typedef enum cgen_operand_type { |
| 246 | MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM |
| 247 | , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC |
| 248 | , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL |
| 249 | , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S |
| 250 | , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP |
| 251 | , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0 |
| 252 | , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW |
| 253 | , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG |
| 254 | , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP |
| 255 | , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN |
| 256 | , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64 |
| 257 | , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2 |
| 258 | , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2 |
| 259 | , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16 |
| 260 | , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8 |
| 261 | , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3 |
| 262 | , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2 |
| 263 | , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4 |
| 264 | , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4 |
| 265 | , MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12 |
| 266 | , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_IVC2_CSAR0 |
| 267 | , MEP_OPERAND_IVC2_CC, MEP_OPERAND_IVC2_COFR0, MEP_OPERAND_IVC2_COFR1, MEP_OPERAND_IVC2_COFA0 |
| 268 | , MEP_OPERAND_IVC2_COFA1, MEP_OPERAND_IVC2_CSAR1, MEP_OPERAND_IVC2_ACC0_0, MEP_OPERAND_IVC2_ACC0_1 |
| 269 | , MEP_OPERAND_IVC2_ACC0_2, MEP_OPERAND_IVC2_ACC0_3, MEP_OPERAND_IVC2_ACC0_4, MEP_OPERAND_IVC2_ACC0_5 |
| 270 | , MEP_OPERAND_IVC2_ACC0_6, MEP_OPERAND_IVC2_ACC0_7, MEP_OPERAND_IVC2_ACC1_0, MEP_OPERAND_IVC2_ACC1_1 |
| 271 | , MEP_OPERAND_IVC2_ACC1_2, MEP_OPERAND_IVC2_ACC1_3, MEP_OPERAND_IVC2_ACC1_4, MEP_OPERAND_IVC2_ACC1_5 |
| 272 | , MEP_OPERAND_IVC2_ACC1_6, MEP_OPERAND_IVC2_ACC1_7, MEP_OPERAND_CROC, MEP_OPERAND_CRQC |
| 273 | , MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2, MEP_OPERAND_IVC_X_6_3 |
| 274 | , MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8, MEP_OPERAND_IMM5P7 |
| 275 | , MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4, MEP_OPERAND_IMM3P5 |
| 276 | , MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10, MEP_OPERAND_IMM5P8 |
| 277 | , MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23, MEP_OPERAND_IMM3P25 |
| 278 | , MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20, MEP_OPERAND_IMM8P20 |
| 279 | , MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2 |
| 280 | , MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0 |
| 281 | , MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN |
| 282 | , MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX |
| 283 | } CGEN_OPERAND_TYPE; |
| 284 | |
| 285 | /* Number of operands types. */ |
| 286 | #define MAX_OPERANDS 145 |
| 287 | |
| 288 | /* Maximum number of operands referenced by any insn. */ |
| 289 | #define MAX_OPERAND_INSTANCES 8 |
| 290 | |
| 291 | /* Insn attribute indices. */ |
| 292 | |
| 293 | /* Enum declaration for cgen_insn attrs. */ |
| 294 | typedef enum cgen_insn_attr { |
| 295 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI |
| 296 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED |
| 297 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN |
| 298 | , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN |
| 299 | , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN |
| 300 | , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN |
| 301 | , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP |
| 302 | , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE |
| 303 | , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA |
| 304 | , CGEN_INSN_CPTYPE, CGEN_INSN_CRET, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG |
| 305 | , CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS |
| 306 | } CGEN_INSN_ATTR; |
| 307 | |
| 308 | /* Number of non-boolean elements in cgen_insn_attr. */ |
| 309 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) |
| 310 | |
| 311 | /* cgen_insn attribute accessor macros. */ |
| 312 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 313 | #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) |
| 314 | #define CGEN_ATTR_CGEN_INSN_CPTYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CPTYPE-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 315 | #define CGEN_ATTR_CGEN_INSN_CRET_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CRET-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 316 | #define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 317 | #define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 318 | #define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 319 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) |
| 320 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) |
| 321 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) |
| 322 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) |
| 323 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) |
| 324 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) |
| 325 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) |
| 326 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) |
| 327 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) |
| 328 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) |
| 329 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0) |
| 330 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0) |
| 331 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0) |
| 332 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0) |
| 333 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0) |
| 334 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0) |
| 335 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0) |
| 336 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0) |
| 337 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0) |
| 338 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0) |
| 339 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0) |
| 340 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0) |
| 341 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0) |
| 342 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0) |
| 343 | #define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0) |
| 344 | #define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_MAY_TRAP)) != 0) |
| 345 | #define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW_ALONE)) != 0) |
| 346 | #define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0) |
| 347 | #define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0) |
| 348 | #define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0) |
| 349 | #define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0) |
| 350 | #define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VOLATILE)) != 0) |
| 351 | |
| 352 | /* cgen.h uses things we just defined. */ |
| 353 | #include "opcode/cgen.h" |
| 354 | |
| 355 | extern const struct cgen_ifld mep_cgen_ifld_table[]; |
| 356 | |
| 357 | /* Attributes. */ |
| 358 | extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[]; |
| 359 | extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[]; |
| 360 | extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[]; |
| 361 | extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[]; |
| 362 | |
| 363 | /* Hardware decls. */ |
| 364 | |
| 365 | extern CGEN_KEYWORD mep_cgen_opval_h_gpr; |
| 366 | extern CGEN_KEYWORD mep_cgen_opval_h_csr; |
| 367 | extern CGEN_KEYWORD mep_cgen_opval_h_cr64; |
| 368 | extern CGEN_KEYWORD mep_cgen_opval_h_cr; |
| 369 | extern CGEN_KEYWORD mep_cgen_opval_h_ccr; |
| 370 | extern CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2; |
| 371 | extern CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2; |
| 372 | |
| 373 | extern const CGEN_HW_ENTRY mep_cgen_hw_table[]; |
| 374 | |
| 375 | |
| 376 | |
| 377 | #endif /* MEP_CPU_H */ |