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1/* mips-opc.c -- MIPS opcode list.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
6 Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
7
8This file is part of GDB, GAS, and the GNU binutils.
9
10GDB, GAS, and the GNU binutils are free software; you can redistribute
11them and/or modify them under the terms of the GNU General Public
12License as published by the Free Software Foundation; either version
131, or (at your option) any later version.
14
15GDB, GAS, and the GNU binutils are distributed in the hope that they
16will be useful, but WITHOUT ANY WARRANTY; without even the implied
17warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18the GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this file; see the file COPYING. If not, write to the Free
22Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include <stdio.h>
25#include "sysdep.h"
26#include "opcode/mips.h"
27
28/* Short hand so the lines aren't too long. */
29
30#define LDD INSN_LOAD_MEMORY_DELAY
31#define LCD INSN_LOAD_COPROC_DELAY
32#define UBD INSN_UNCOND_BRANCH_DELAY
33#define CBD INSN_COND_BRANCH_DELAY
34#define COD INSN_COPROC_MOVE_DELAY
35#define CLD INSN_COPROC_MEMORY_DELAY
36#define CBL INSN_COND_BRANCH_LIKELY
37#define TRAP INSN_TRAP
38#define SM INSN_STORE_MEMORY
39
40#define WR_d INSN_WRITE_GPR_D
41#define WR_t INSN_WRITE_GPR_T
42#define WR_31 INSN_WRITE_GPR_31
43#define WR_D INSN_WRITE_FPR_D
44#define WR_T INSN_WRITE_FPR_T
45#define WR_S INSN_WRITE_FPR_S
46#define RD_s INSN_READ_GPR_S
47#define RD_b INSN_READ_GPR_S
48#define RD_t INSN_READ_GPR_T
49#define RD_S INSN_READ_FPR_S
50#define RD_T INSN_READ_FPR_T
51#define RD_R INSN_READ_FPR_R
52#define WR_CC INSN_WRITE_COND_CODE
53#define RD_CC INSN_READ_COND_CODE
54#define RD_C0 INSN_COP
55#define RD_C1 INSN_COP
56#define RD_C2 INSN_COP
57#define RD_C3 INSN_COP
58#define WR_C0 INSN_COP
59#define WR_C1 INSN_COP
60#define WR_C2 INSN_COP
61#define WR_C3 INSN_COP
62
63#define WR_HI INSN_WRITE_HI
64#define RD_HI INSN_READ_HI
65#define MOD_HI WR_HI|RD_HI
66
67#define WR_LO INSN_WRITE_LO
68#define RD_LO INSN_READ_LO
69#define MOD_LO WR_LO|RD_LO
70
71#define WR_HILO WR_HI|WR_LO
72#define RD_HILO RD_HI|RD_LO
73#define MOD_HILO WR_HILO|RD_HILO
74
75#define IS_M INSN_MULT
76
77#define I1 INSN_ISA1
78#define I2 INSN_ISA2
79#define I3 INSN_ISA3
80#define I4 INSN_ISA4
81#define I5 INSN_ISA5
82#define I32 INSN_ISA32
83#define I64 INSN_ISA64
84
85#define P3 INSN_4650
86#define L1 INSN_4010
87#define V1 INSN_4100
88#define T3 INSN_3900
89#define M1 INSN_10000
90
91#define G1 (T3 \
92 )
93
94#define G2 (T3 \
95 )
96
97#define G3 (I4 \
98 )
99
100/* The order of overloaded instructions matters. Label arguments and
101 register arguments look the same. Instructions that can have either
102 for arguments must apear in the correct order in this table for the
103 assembler to pick the right one. In other words, entries with
104 immediate operands must apear after the same instruction with
105 registers.
106
107 Many instructions are short hand for other instructions (i.e., The
108 jal <register> instruction is short for jalr <register>). */
109
110const struct mips_opcode mips_builtin_opcodes[] =
111{
112/* These instructions appear first so that the disassembler will find
113 them first. The assemblers uses a hash table based on the
114 instruction name anyhow. */
115/* name, args, match, mask, pinfo, membership */
116{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I32|G3 },
117{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
118{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
119{"ssnop", "", 0x00000040, 0xffffffff, 0, I32 },
120{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
121{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
122{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
123{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 },
124{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
125{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
126{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
127{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */
128{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
129{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
130
131{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
132{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
133{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
134{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 },
135{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
136{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
137{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
138{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
139{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
140{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
141{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
142{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
143{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
144{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
145{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
146{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
147{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
148/* b is at the top of the table. */
149/* bal is at the top of the table. */
150{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
151{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
152{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
153{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
154{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
155{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
156{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
157{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
158{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
159{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
160{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
161{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
162{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
163{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
164{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
165{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
166{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
167{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
168{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
169{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 },
170{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
171{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
172{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
173{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 },
174{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
175{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 },
176{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 },
177{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 },
178{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 },
179{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 },
180{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 },
181{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 },
182{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 },
183{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 },
184{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
185{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
186{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
187{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 },
188{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 },
189{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 },
190{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 },
191{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 },
192{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 },
193{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 },
194{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 },
195{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 },
196{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
197{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
198{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 },
199{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 },
200{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 },
201{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 },
202{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 },
203{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 },
204{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 },
205{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 },
206{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
207{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
208{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 },
209{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 },
210{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 },
211{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 },
212{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 },
213{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 },
214{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 },
215{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 },
216{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
217{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
218{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
219{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 },
220{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
221{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
222{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
223{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 },
224{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
225{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 },
226{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
227{"break", "B", 0x0000000d, 0xfc00003f, TRAP, I32 },
228{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
229{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
230{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
231{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
232{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
233{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
234{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
235{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
236{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
237{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
238{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
239{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
240{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
241{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
242{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
243{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
244{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
245{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
246{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
247{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
248{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
249{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
250{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
251{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
252{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
253{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
254{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
255{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
256{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
257{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
258{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
259{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
260{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
261{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
262{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
263{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
264{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
265{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
266{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
267{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
268{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
269{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
270{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
271{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
272{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
273{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
274{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
275{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
276{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
277{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
278{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
279{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
280{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
281{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
282{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
283{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
284{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
285{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
286{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
287{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
288{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
289{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
290{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
291{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
292{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
293{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
294{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
295{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
296{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
297{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
298{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
299{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
300{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
301{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
302{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
303{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
304{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
305{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
306{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
307{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
308{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
309{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
310{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
311{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
312{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
313{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
314{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
315{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
316{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
317{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
318{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
319{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
320{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
321{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
322{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
323{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
324{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
325{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
326{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3},
327{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
328{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
329{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
330{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
331{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
332{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
333{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
334{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
335{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
336{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32 },
337{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32 },
338{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
339{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
340{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
341{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
342{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
343{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
344{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
345{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
346{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
347{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
348{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
349{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
350{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
351{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
352{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
353{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
354{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
355{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
356{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
357{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
358{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
359{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
360{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
361{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
362{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
363{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64 },
364{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64 },
365/* dctr and dctw are used on the r5000. */
366{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
367{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
368{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 },
369/* For ddiv, see the comments about div. */
370{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
371{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
372{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
373/* For ddivu, see the comments about div. */
374{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
375{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
376{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
377/* The MIPS assembler treats the div opcode with two operands as
378 though the first operand appeared twice (the first operand is both
379 a source and a destination). To get the div machine instruction,
380 you must use an explicit destination of $0. */
381{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
382{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 },
383{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
384{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
385{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
386{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
387/* For divu, see the comments about div. */
388{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
389{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 },
390{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
391{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
392{"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */
393{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
394{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
395{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
396{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
397
398{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, V1 },
399{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
400{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 },
401{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
402{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 },
403{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
404{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
405{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
406{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
407{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
408{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
409{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
410{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
411{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 },
412{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 },
413{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 },
414{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 },
415{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
416{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
417{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
418{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
419{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
420{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
421{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
422{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
423{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
424{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
425{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
426{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
427{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
428{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
429{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
430{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
431{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
432{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
433{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
434{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
435{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
436{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
437{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
438{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
439{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
440{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
441{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
442{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
443{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
444{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
445{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
446{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
447{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
448{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
449{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
450{"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 },
451{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
452{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
453{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
454{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
455{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
456{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
457{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
458{"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
459{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
460{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
461/* SVR4 PIC code requires special handling for j, so it must be a
462 macro. */
463{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
464/* This form of j is used by the disassembler and internally by the
465 assembler, but will never match user input (because the line above
466 will match first). */
467{"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
468{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
469{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
470/* SVR4 PIC code requires special handling for jal, so it must be a
471 macro. */
472{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
473{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
474{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
475/* This form of jal is used by the disassembler and internally by the
476 assembler, but will never match user input (because the line above
477 will match first). */
478{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
479 /* jalx really should only be avaliable if mips16 is available,
480 but for now make it I1. */
481{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
482{"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */
483{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
484{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
485{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
486{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
487{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
488{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
489{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
490{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
491{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
492{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
493{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
494{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
495{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
496{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
497{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
498{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
499{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
500{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
501{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
502{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
503{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
504{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
505{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
506{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
507{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
508{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
509{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
510{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
511/* li is at the start of the table. */
512{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
513{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
514{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
515{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
516{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
517{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
518{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
519{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
520{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
521{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5 },
522{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
523{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
524{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
525{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
526{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
527{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
528{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
529{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
530{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
531{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
532{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
533{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
534{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
535{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
536{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
537{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
538{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
539{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
540{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
541{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
542{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
543{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
544{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
545{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
546{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
547{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 },
548{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 },
549{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
550{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
551{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
552{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
553{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32},
554{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
555{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
556{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
557{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32},
558{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
559{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
560{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 },
561{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
562{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
563{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
564{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
565{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
566{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
567{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
568{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
569{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
570{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
571{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
572{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
573{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
574{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
575{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
576{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
577{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
578{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
579{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
580{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
581{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
582{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
583{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
584{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 },
585{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
586{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
587{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
588{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
589{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
590{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
591{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
592/* move is at the top of the table. */
593{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
594{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
595{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
596{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
597{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 },
598{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
599{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 },
600{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
601{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
602{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
603{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
604{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
605{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
606{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
607{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
608{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
609{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
610{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
611{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
612{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
613{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
614{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
615{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 },
616{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
617{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
618{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
619{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
620{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
621{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
622{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
623{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
624{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
625{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
626{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
627{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
628{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
629{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
630{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 },
631{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
632{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
633{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
634{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
635{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
636{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
637/* nop is at the start of the table. */
638{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
639{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
640{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
641{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
642{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
643{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
644
645{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
646{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
647
648 /* pref and prefx are at the start of the table. */
649
650{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
651{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
652
653{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
654{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
655{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
656{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
657{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
658{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
659{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
660{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
661{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
662{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
663{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
664{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
665{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 },
666{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
667{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
668{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
669{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
670{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
671{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
672{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
673{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
674{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
675{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 },
676{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
677{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 },
678{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
679{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
680{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
681{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 },
682{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 },
683{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 },
684{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
685{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
686{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
687{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
688{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
689{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
690{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
691{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 },
692{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
693{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 },
694{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
695{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 },
696{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 },
697{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
698{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 },
699{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
700{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 },
701{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
702{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
703{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
704{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 },
705{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 },
706{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 },
707{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 },
708{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 },
709{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 },
710{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 },
711{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 },
712{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 },
713{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 },
714{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
715{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
716{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
717{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
718{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
719{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 },
720{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
721{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
722{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
723{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
724{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
725{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
726{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
727{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
728{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 },
729{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 },
730{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 },
731{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
732{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
733{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
734{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
735{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
736{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
737{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
738{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
739/* ssnop is at the start of the table. */
740{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
741{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
742{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
743{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
744{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
745{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
746{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
747{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
748{"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
749{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5 },
750{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
751{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 },
752{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
753{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 },
754{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
755{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
756{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
757{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
758{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
759{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
760{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
761{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 },
762{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
763{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 },
764{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
765{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 },
766{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
767{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */
768{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
769{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 },
770{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
771{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */
772{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
773{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 },
774{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 },
775{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 },
776{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
777{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
778{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
779{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
780{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
781{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
782{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 },
783{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
784{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
785{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
786{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
787{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 },
788{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
789{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
790{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
791{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
792{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
793{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 },
794{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 },
795{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 },
796{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 },
797{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
798{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
799{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
800{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
801{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 },
802{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
803{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
804{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
805{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
806{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 },
807{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
808{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
809{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
810{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
811{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 },
812{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
813{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
814{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
815{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
816{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 },
817{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
818{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
819{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 },
820{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 },
821{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 },
822{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 },
823{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 },
824{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 },
825{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 },
826{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 },
827{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 },
828{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 },
829{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 },
830{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 },
831{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
832{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
833{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
834{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
835{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
836{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
837{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 },
838{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
839{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
840{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
841/* No hazard protection on coprocessor instructions--they shouldn't
842 change the state of the processor and if they do it's up to the
843 user to put in nops as necessary. These are at the end so that the
844 disassembler recognizes more specific versions first. */
845{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
846{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
847{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
848{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
849{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 },
850{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
851{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
852{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 },
853
854 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
855 4010 any more, so move this insn out of the way. If the object
856 format gave us more info, we could do this right. */
857{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 },
858};
859
860#define MIPS_NUM_OPCODES \
861 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
862const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
863
864/* const removed from the following to allow for dynamic extensions to the
865 * built-in instruction set. */
866struct mips_opcode *mips_opcodes =
867 (struct mips_opcode *) mips_builtin_opcodes;
868int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
869#undef MIPS_NUM_OPCODES
GDB Binutils - Deliverables
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