| 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
| 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. |
| 3 | Contributed by Ralph Campbell and OSF |
| 4 | Commented and modified by Ian Lance Taylor, Cygnus Support |
| 5 | |
| 6 | This file is part of GDB, GAS, and the GNU binutils. |
| 7 | |
| 8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
| 9 | them and/or modify them under the terms of the GNU General Public |
| 10 | License as published by the Free Software Foundation; either version |
| 11 | 1, or (at your option) any later version. |
| 12 | |
| 13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
| 14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 16 | the GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this file; see the file COPYING. If not, write to the Free |
| 20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include <stdio.h> |
| 23 | #include "ansidecl.h" |
| 24 | #include "opcode/mips.h" |
| 25 | |
| 26 | /* Short hand so the lines aren't too long. */ |
| 27 | |
| 28 | #define LDD INSN_LOAD_MEMORY_DELAY |
| 29 | #define LCD INSN_LOAD_COPROC_DELAY |
| 30 | #define UBD INSN_UNCOND_BRANCH_DELAY |
| 31 | #define CBD INSN_COND_BRANCH_DELAY |
| 32 | #define COD INSN_COPROC_MOVE_DELAY |
| 33 | #define CLD INSN_COPROC_MEMORY_DELAY |
| 34 | #define CBL INSN_COND_BRANCH_LIKELY |
| 35 | #define TRAP INSN_TRAP |
| 36 | #define SM INSN_STORE_MEMORY |
| 37 | |
| 38 | #define WR_d INSN_WRITE_GPR_D |
| 39 | #define WR_t INSN_WRITE_GPR_T |
| 40 | #define WR_31 INSN_WRITE_GPR_31 |
| 41 | #define WR_D INSN_WRITE_FPR_D |
| 42 | #define WR_T INSN_WRITE_FPR_T |
| 43 | #define WR_S INSN_WRITE_FPR_S |
| 44 | #define RD_s INSN_READ_GPR_S |
| 45 | #define RD_b INSN_READ_GPR_S |
| 46 | #define RD_t INSN_READ_GPR_T |
| 47 | #define RD_S INSN_READ_FPR_S |
| 48 | #define RD_T INSN_READ_FPR_T |
| 49 | #define RD_R INSN_READ_FPR_R |
| 50 | #define WR_CC INSN_WRITE_COND_CODE |
| 51 | #define RD_CC INSN_READ_COND_CODE |
| 52 | #define RD_C0 INSN_COP |
| 53 | #define RD_C1 INSN_COP |
| 54 | #define RD_C2 INSN_COP |
| 55 | #define RD_C3 INSN_COP |
| 56 | #define WR_C0 INSN_COP |
| 57 | #define WR_C1 INSN_COP |
| 58 | #define WR_C2 INSN_COP |
| 59 | #define WR_C3 INSN_COP |
| 60 | |
| 61 | #define WR_HI INSN_WRITE_HI |
| 62 | #define RD_HI INSN_READ_HI |
| 63 | #define MOD_HI WR_HI|RD_HI |
| 64 | |
| 65 | #define WR_LO INSN_WRITE_LO |
| 66 | #define RD_LO INSN_READ_LO |
| 67 | #define MOD_LO WR_LO|RD_LO |
| 68 | |
| 69 | #define WR_HILO WR_HI|WR_LO |
| 70 | #define RD_HILO RD_HI|RD_LO |
| 71 | #define MOD_HILO WR_HILO|RD_HILO |
| 72 | |
| 73 | #define IS_M INSN_MULT |
| 74 | |
| 75 | #define I1 INSN_ISA1 |
| 76 | #define I2 INSN_ISA2 |
| 77 | #define I3 INSN_ISA3 |
| 78 | #define I4 INSN_ISA4 |
| 79 | #define P3 INSN_4650 |
| 80 | #define L1 INSN_4010 |
| 81 | #define V1 INSN_4100 |
| 82 | #define T3 INSN_3900 |
| 83 | |
| 84 | #define G1 (T3 \ |
| 85 | ) |
| 86 | |
| 87 | #define G2 (T3 \ |
| 88 | ) |
| 89 | |
| 90 | #define G3 (I4 \ |
| 91 | ) |
| 92 | |
| 93 | /* The order of overloaded instructions matters. Label arguments and |
| 94 | register arguments look the same. Instructions that can have either |
| 95 | for arguments must apear in the correct order in this table for the |
| 96 | assembler to pick the right one. In other words, entries with |
| 97 | immediate operands must apear after the same instruction with |
| 98 | registers. |
| 99 | |
| 100 | Many instructions are short hand for other instructions (i.e., The |
| 101 | jal <register> instruction is short for jalr <register>). */ |
| 102 | |
| 103 | const struct mips_opcode mips_builtin_opcodes[] = { |
| 104 | /* These instructions appear first so that the disassembler will find |
| 105 | them first. The assemblers uses a hash table based on the |
| 106 | instruction name anyhow. */ |
| 107 | /* name, args, mask, match, pinfo */ |
| 108 | {"nop", "", 0x00000000, 0xffffffff, 0, I1 }, |
| 109 | {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ |
| 110 | {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ |
| 111 | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, |
| 112 | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ |
| 113 | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ |
| 114 | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ |
| 115 | {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ |
| 116 | {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ |
| 117 | {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ |
| 118 | |
| 119 | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, |
| 120 | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
| 121 | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
| 122 | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 123 | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, |
| 124 | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1}, |
| 125 | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1}, |
| 126 | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 127 | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 128 | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 129 | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, |
| 130 | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 131 | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, |
| 132 | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 133 | /* b is at the top of the table. */ |
| 134 | /* bal is at the top of the table. */ |
| 135 | {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, |
| 136 | {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
| 137 | {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, |
| 138 | {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, |
| 139 | {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, |
| 140 | {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, |
| 141 | {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 }, |
| 142 | {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
| 143 | {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, |
| 144 | {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
| 145 | {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, |
| 146 | {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
| 147 | {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, |
| 148 | {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, |
| 149 | {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, |
| 150 | {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, |
| 151 | {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, |
| 152 | {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
| 153 | {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, |
| 154 | {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
| 155 | {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, |
| 156 | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 157 | {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, |
| 158 | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, |
| 159 | {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, |
| 160 | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 }, |
| 161 | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, |
| 162 | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, |
| 163 | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 }, |
| 164 | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 }, |
| 165 | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, |
| 166 | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, |
| 167 | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 }, |
| 168 | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 }, |
| 169 | {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, |
| 170 | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 171 | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, |
| 172 | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 173 | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, |
| 174 | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, |
| 175 | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 }, |
| 176 | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 }, |
| 177 | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, |
| 178 | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, |
| 179 | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 }, |
| 180 | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 }, |
| 181 | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, |
| 182 | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 183 | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, |
| 184 | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, |
| 185 | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 }, |
| 186 | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 }, |
| 187 | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, |
| 188 | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, |
| 189 | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 }, |
| 190 | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 }, |
| 191 | {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, |
| 192 | {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 193 | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, |
| 194 | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, |
| 195 | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 }, |
| 196 | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 }, |
| 197 | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, |
| 198 | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, |
| 199 | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 }, |
| 200 | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 }, |
| 201 | {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, |
| 202 | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 203 | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, |
| 204 | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 205 | {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, |
| 206 | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
| 207 | {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, |
| 208 | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, |
| 209 | {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, |
| 210 | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 }, |
| 211 | {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, |
| 212 | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, |
| 213 | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, |
| 214 | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 215 | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 216 | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 217 | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 218 | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 219 | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 220 | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 221 | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 222 | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 223 | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 224 | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 225 | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 226 | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 227 | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 228 | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 229 | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 230 | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 231 | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 232 | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 233 | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 234 | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 235 | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 236 | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 237 | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 238 | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 239 | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 240 | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 241 | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 242 | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 243 | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 244 | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 245 | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 246 | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 247 | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 248 | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 249 | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 250 | {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 251 | {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 252 | {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 253 | {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 254 | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 255 | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 256 | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 257 | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 258 | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 259 | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 260 | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 261 | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 262 | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 263 | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 264 | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 265 | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 266 | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 267 | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 268 | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 269 | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 270 | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 271 | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 272 | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 273 | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 274 | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
| 275 | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, |
| 276 | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
| 277 | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, |
| 278 | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3 }, |
| 279 | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
| 280 | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
| 281 | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
| 282 | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
| 283 | {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, |
| 284 | {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, |
| 285 | {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, |
| 286 | {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, |
| 287 | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, |
| 288 | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, |
| 289 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, |
| 290 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, |
| 291 | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, |
| 292 | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, |
| 293 | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
| 294 | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, |
| 295 | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
| 296 | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
| 297 | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
| 298 | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
| 299 | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, |
| 300 | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
| 301 | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
| 302 | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
| 303 | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, |
| 304 | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, |
| 305 | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, |
| 306 | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, |
| 307 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, |
| 308 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, |
| 309 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, |
| 310 | /* dctr and dctw are used on the r5000. */ |
| 311 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, |
| 312 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, |
| 313 | {"deret", "", 0x4200001f, 0xffffffff, 0, G2 }, |
| 314 | /* For ddiv, see the comments about div. */ |
| 315 | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, |
| 316 | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, |
| 317 | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, |
| 318 | /* For ddivu, see the comments about div. */ |
| 319 | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, |
| 320 | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, |
| 321 | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, |
| 322 | /* The MIPS assembler treats the div opcode with two operands as |
| 323 | though the first operand appeared twice (the first operand is both |
| 324 | a source and a destination). To get the div machine instruction, |
| 325 | you must use an explicit destination of $0. */ |
| 326 | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, |
| 327 | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, |
| 328 | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, |
| 329 | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, |
| 330 | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, |
| 331 | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, |
| 332 | /* For divu, see the comments about div. */ |
| 333 | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, |
| 334 | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, |
| 335 | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, |
| 336 | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, |
| 337 | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, |
| 338 | {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ |
| 339 | {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ |
| 340 | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, |
| 341 | |
| 342 | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 }, |
| 343 | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, |
| 344 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, |
| 345 | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, |
| 346 | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, |
| 347 | {"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, |
| 348 | {"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, |
| 349 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, |
| 350 | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, |
| 351 | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, |
| 352 | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, |
| 353 | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, |
| 354 | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, |
| 355 | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, |
| 356 | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, |
| 357 | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ |
| 358 | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ |
| 359 | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, |
| 360 | {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, |
| 361 | {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, |
| 362 | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, |
| 363 | {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, |
| 364 | {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, |
| 365 | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, |
| 366 | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, |
| 367 | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ |
| 368 | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */ |
| 369 | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 }, |
| 370 | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, |
| 371 | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, |
| 372 | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */ |
| 373 | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */ |
| 374 | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 }, |
| 375 | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, |
| 376 | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, |
| 377 | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */ |
| 378 | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */ |
| 379 | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 }, |
| 380 | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, |
| 381 | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 }, |
| 382 | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, |
| 383 | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, |
| 384 | {"eret", "", 0x42000018, 0xffffffff, 0, I3 }, |
| 385 | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
| 386 | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
| 387 | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
| 388 | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
| 389 | {"flushi", "", 0xbc010000, 0xffffffff, 0, L1 }, |
| 390 | {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, |
| 391 | {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, |
| 392 | {"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, |
| 393 | {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, |
| 394 | {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */ |
| 395 | /* SVR4 PIC code requires special handling for j, so it must be a |
| 396 | macro. */ |
| 397 | {"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 }, |
| 398 | /* This form of j is used by the disassembler and internally by the |
| 399 | assembler, but will never match user input (because the line above |
| 400 | will match first). */ |
| 401 | {"j", "a", 0x08000000, 0xfc000000, UBD, I1 }, |
| 402 | {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 }, |
| 403 | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 }, |
| 404 | /* SVR4 PIC code requires special handling for jal, so it must be a |
| 405 | macro. */ |
| 406 | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 }, |
| 407 | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 }, |
| 408 | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 }, |
| 409 | /* This form of jal is used by the disassembler and internally by the |
| 410 | assembler, but will never match user input (because the line above |
| 411 | will match first). */ |
| 412 | {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, |
| 413 | /* jalx really should only be avaliable if mips16 is available, |
| 414 | but for now make it I1. */ |
| 415 | {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, |
| 416 | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, |
| 417 | {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 418 | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, |
| 419 | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 420 | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 }, |
| 421 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 }, |
| 422 | {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 }, |
| 423 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 }, |
| 424 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, |
| 425 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, |
| 426 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, |
| 427 | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, |
| 428 | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */ |
| 429 | {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 }, |
| 430 | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 }, |
| 431 | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, |
| 432 | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 }, |
| 433 | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, |
| 434 | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 }, |
| 435 | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, |
| 436 | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 }, |
| 437 | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, |
| 438 | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 }, |
| 439 | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, |
| 440 | {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 441 | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 }, |
| 442 | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 443 | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 }, |
| 444 | /* li is at the start of the table. */ |
| 445 | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 }, |
| 446 | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 }, |
| 447 | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 }, |
| 448 | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 }, |
| 449 | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, |
| 450 | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 }, |
| 451 | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, |
| 452 | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 }, |
| 453 | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, |
| 454 | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 455 | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 }, |
| 456 | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, |
| 457 | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 }, |
| 458 | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, |
| 459 | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, |
| 460 | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, |
| 461 | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, |
| 462 | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ |
| 463 | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, |
| 464 | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, |
| 465 | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, |
| 466 | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, |
| 467 | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 }, |
| 468 | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 469 | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 }, |
| 470 | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ |
| 471 | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */ |
| 472 | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, |
| 473 | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 }, |
| 474 | {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ |
| 475 | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */ |
| 476 | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, |
| 477 | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 }, |
| 478 | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, |
| 479 | |
| 480 | |
| 481 | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, |
| 482 | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, |
| 483 | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, |
| 484 | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, |
| 485 | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, |
| 486 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1 }, |
| 487 | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 }, |
| 488 | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, |
| 489 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1}, |
| 490 | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, |
| 491 | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 }, |
| 492 | {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, |
| 493 | {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, |
| 494 | {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, |
| 495 | {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, |
| 496 | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, |
| 497 | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, |
| 498 | {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, |
| 499 | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
| 500 | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
| 501 | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4 }, |
| 502 | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 }, |
| 503 | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 }, |
| 504 | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4 }, |
| 505 | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 }, |
| 506 | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, |
| 507 | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, |
| 508 | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4 }, |
| 509 | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 }, |
| 510 | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 }, |
| 511 | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4 }, |
| 512 | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 }, |
| 513 | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, |
| 514 | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, |
| 515 | /* move is at the top of the table. */ |
| 516 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, |
| 517 | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, |
| 518 | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, |
| 519 | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, |
| 520 | {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, |
| 521 | {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, |
| 522 | {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, |
| 523 | {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, |
| 524 | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, |
| 525 | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, |
| 526 | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, |
| 527 | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, |
| 528 | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, |
| 529 | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3}, |
| 530 | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, |
| 531 | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, |
| 532 | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, |
| 533 | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, |
| 534 | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, |
| 535 | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, |
| 536 | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1}, |
| 537 | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, |
| 538 | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1}, |
| 539 | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, |
| 540 | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */ |
| 541 | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */ |
| 542 | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
| 543 | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
| 544 | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, |
| 545 | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, |
| 546 | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, |
| 547 | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, |
| 548 | /* nop is at the start of the table. */ |
| 549 | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 550 | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, |
| 551 | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ |
| 552 | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 553 | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, |
| 554 | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 555 | |
| 556 | |
| 557 | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3 }, |
| 558 | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, |
| 559 | |
| 560 | |
| 561 | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, |
| 562 | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, |
| 563 | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, |
| 564 | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, |
| 565 | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, |
| 566 | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, |
| 567 | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, |
| 568 | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, |
| 569 | {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, |
| 570 | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, |
| 571 | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, |
| 572 | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, |
| 573 | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 }, |
| 574 | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
| 575 | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
| 576 | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
| 577 | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
| 578 | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, |
| 579 | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, |
| 580 | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, |
| 581 | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, |
| 582 | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, |
| 583 | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, |
| 584 | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, |
| 585 | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 }, |
| 586 | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 }, |
| 587 | {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 }, |
| 588 | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 }, |
| 589 | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 }, |
| 590 | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 }, |
| 591 | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 }, |
| 592 | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, |
| 593 | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, |
| 594 | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, |
| 595 | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, |
| 596 | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 }, |
| 597 | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 }, |
| 598 | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 }, |
| 599 | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 }, |
| 600 | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, |
| 601 | {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 }, |
| 602 | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 }, |
| 603 | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 }, |
| 604 | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 }, |
| 605 | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 }, |
| 606 | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 }, |
| 607 | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, |
| 608 | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, |
| 609 | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, |
| 610 | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 }, |
| 611 | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 }, |
| 612 | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 }, |
| 613 | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 }, |
| 614 | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 }, |
| 615 | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 }, |
| 616 | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 }, |
| 617 | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 }, |
| 618 | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 }, |
| 619 | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, |
| 620 | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, |
| 621 | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, |
| 622 | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, |
| 623 | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, |
| 624 | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, |
| 625 | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 }, |
| 626 | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, |
| 627 | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ |
| 628 | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, |
| 629 | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 630 | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, |
| 631 | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 632 | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 633 | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 634 | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 }, |
| 635 | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 }, |
| 636 | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, |
| 637 | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
| 638 | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
| 639 | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, |
| 640 | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ |
| 641 | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, |
| 642 | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, |
| 643 | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ |
| 644 | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, |
| 645 | {"standby", "", 0x42000021, 0xffffffff, 0, V1 }, |
| 646 | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 647 | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, |
| 648 | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, |
| 649 | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, |
| 650 | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 651 | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, |
| 652 | {"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, |
| 653 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 }, |
| 654 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 }, |
| 655 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 }, |
| 656 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 }, |
| 657 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, |
| 658 | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, |
| 659 | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, |
| 660 | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, |
| 661 | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ |
| 662 | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, |
| 663 | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, |
| 664 | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, |
| 665 | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, |
| 666 | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 }, |
| 667 | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, |
| 668 | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 }, |
| 669 | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ |
| 670 | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */ |
| 671 | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, |
| 672 | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 }, |
| 673 | {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ |
| 674 | {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */ |
| 675 | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, |
| 676 | {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 }, |
| 677 | {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 }, |
| 678 | {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 }, |
| 679 | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 }, |
| 680 | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 }, |
| 681 | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, |
| 682 | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, |
| 683 | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, |
| 684 | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */ |
| 685 | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 }, |
| 686 | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, |
| 687 | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, |
| 688 | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, |
| 689 | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */ |
| 690 | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 }, |
| 691 | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, |
| 692 | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, |
| 693 | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, |
| 694 | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */ |
| 695 | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 }, |
| 696 | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 }, |
| 697 | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 }, |
| 698 | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 }, |
| 699 | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 }, |
| 700 | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, |
| 701 | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, |
| 702 | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, |
| 703 | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */ |
| 704 | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 }, |
| 705 | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, |
| 706 | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, |
| 707 | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, |
| 708 | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */ |
| 709 | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 }, |
| 710 | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, |
| 711 | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, |
| 712 | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, |
| 713 | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */ |
| 714 | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 }, |
| 715 | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
| 716 | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
| 717 | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
| 718 | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
| 719 | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 }, |
| 720 | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
| 721 | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
| 722 | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 }, |
| 723 | {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 }, |
| 724 | {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 }, |
| 725 | {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 }, |
| 726 | {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 }, |
| 727 | {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 }, |
| 728 | {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 }, |
| 729 | {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 }, |
| 730 | {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 }, |
| 731 | {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 }, |
| 732 | {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 }, |
| 733 | {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 }, |
| 734 | {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, |
| 735 | {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, |
| 736 | {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, |
| 737 | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
| 738 | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, |
| 739 | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, |
| 740 | {"wait", "", 0x42000020, 0xffffffff, TRAP, I3 }, |
| 741 | {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, |
| 742 | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, |
| 743 | /* No hazard protection on coprocessor instructions--they shouldn't |
| 744 | change the state of the processor and if they do it's up to the |
| 745 | user to put in nops as necessary. These are at the end so that the |
| 746 | disasembler recognizes more specific versions first. */ |
| 747 | {"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, |
| 748 | {"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, |
| 749 | {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, |
| 750 | {"c3", "C", 0x4e000000, 0xfe000000, 0, I1 }, |
| 751 | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 }, |
| 752 | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 }, |
| 753 | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 }, |
| 754 | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 }, |
| 755 | |
| 756 | /* Conflicts with the 4650's "mul" instruction. Nobody's using the |
| 757 | 4010 any more, so move this insn out of the way. If the object |
| 758 | format gave us more info, we could do this right. */ |
| 759 | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 }, |
| 760 | }; |
| 761 | |
| 762 | #define MIPS_NUM_OPCODES \ |
| 763 | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) |
| 764 | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; |
| 765 | |
| 766 | /* const removed from the following to allow for dynamic extensions to the |
| 767 | * built-in instruction set. */ |
| 768 | struct mips_opcode *mips_opcodes = |
| 769 | (struct mips_opcode *) mips_builtin_opcodes; |
| 770 | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; |
| 771 | #undef MIPS_NUM_OPCODES |
| 772 | |