| 1 | /* mips-opc.c -- MIPS opcode list. |
| 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
| 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012 |
| 4 | Free Software Foundation, Inc. |
| 5 | Contributed by Ralph Campbell and OSF |
| 6 | Commented and modified by Ian Lance Taylor, Cygnus Support |
| 7 | Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. |
| 8 | MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom |
| 9 | Corporation (SiByte). |
| 10 | |
| 11 | This file is part of the GNU opcodes library. |
| 12 | |
| 13 | This library is free software; you can redistribute it and/or modify |
| 14 | it under the terms of the GNU General Public License as published by |
| 15 | the Free Software Foundation; either version 3, or (at your option) |
| 16 | any later version. |
| 17 | |
| 18 | It is distributed in the hope that it will be useful, but WITHOUT |
| 19 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 20 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 21 | License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this file; see the file COPYING. If not, write to the |
| 25 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 26 | MA 02110-1301, USA. */ |
| 27 | |
| 28 | #include "sysdep.h" |
| 29 | #include <stdio.h> |
| 30 | #include "opcode/mips.h" |
| 31 | |
| 32 | /* Short hand so the lines aren't too long. */ |
| 33 | |
| 34 | #define LDD INSN_LOAD_MEMORY_DELAY |
| 35 | #define LCD INSN_LOAD_COPROC_DELAY |
| 36 | #define UBD INSN_UNCOND_BRANCH_DELAY |
| 37 | #define CBD INSN_COND_BRANCH_DELAY |
| 38 | #define COD INSN_COPROC_MOVE_DELAY |
| 39 | #define CLD INSN_COPROC_MEMORY_DELAY |
| 40 | #define CBL INSN_COND_BRANCH_LIKELY |
| 41 | #define NODS INSN_NO_DELAY_SLOT |
| 42 | #define TRAP INSN_NO_DELAY_SLOT |
| 43 | #define SM INSN_STORE_MEMORY |
| 44 | |
| 45 | #define WR_d INSN_WRITE_GPR_D |
| 46 | #define WR_t INSN_WRITE_GPR_T |
| 47 | #define WR_31 INSN_WRITE_GPR_31 |
| 48 | #define WR_D INSN_WRITE_FPR_D |
| 49 | #define WR_T INSN_WRITE_FPR_T |
| 50 | #define WR_S INSN_WRITE_FPR_S |
| 51 | #define RD_s INSN_READ_GPR_S |
| 52 | #define RD_b INSN_READ_GPR_S |
| 53 | #define RD_t INSN_READ_GPR_T |
| 54 | #define RD_S INSN_READ_FPR_S |
| 55 | #define RD_T INSN_READ_FPR_T |
| 56 | #define RD_R INSN_READ_FPR_R |
| 57 | #define WR_CC INSN_WRITE_COND_CODE |
| 58 | #define RD_CC INSN_READ_COND_CODE |
| 59 | #define RD_C0 INSN_COP |
| 60 | #define RD_C1 INSN_COP |
| 61 | #define RD_C2 INSN_COP |
| 62 | #define RD_C3 INSN_COP |
| 63 | #define WR_C0 INSN_COP |
| 64 | #define WR_C1 INSN_COP |
| 65 | #define WR_C2 INSN_COP |
| 66 | #define WR_C3 INSN_COP |
| 67 | #define CP INSN_COP |
| 68 | |
| 69 | #define WR_HI INSN_WRITE_HI |
| 70 | #define RD_HI INSN_READ_HI |
| 71 | #define MOD_HI WR_HI|RD_HI |
| 72 | |
| 73 | #define WR_LO INSN_WRITE_LO |
| 74 | #define RD_LO INSN_READ_LO |
| 75 | #define MOD_LO WR_LO|RD_LO |
| 76 | |
| 77 | #define WR_HILO WR_HI|WR_LO |
| 78 | #define RD_HILO RD_HI|RD_LO |
| 79 | #define MOD_HILO WR_HILO|RD_HILO |
| 80 | |
| 81 | #define IS_M INSN_MULT |
| 82 | |
| 83 | #define WR_MACC INSN2_WRITE_MDMX_ACC |
| 84 | #define RD_MACC INSN2_READ_MDMX_ACC |
| 85 | |
| 86 | #define I1 INSN_ISA1 |
| 87 | #define I2 INSN_ISA2 |
| 88 | #define I3 INSN_ISA3 |
| 89 | #define I4 INSN_ISA4 |
| 90 | #define I5 INSN_ISA5 |
| 91 | #define I32 INSN_ISA32 |
| 92 | #define I64 INSN_ISA64 |
| 93 | #define I33 INSN_ISA32R2 |
| 94 | #define I65 INSN_ISA64R2 |
| 95 | #define I3_32 INSN_ISA3_32 |
| 96 | #define I3_33 INSN_ISA3_32R2 |
| 97 | #define I4_32 INSN_ISA4_32 |
| 98 | #define I4_33 INSN_ISA4_32R2 |
| 99 | #define I5_33 INSN_ISA5_32R2 |
| 100 | |
| 101 | /* MIPS64 MIPS-3D ASE support. */ |
| 102 | #define M3D INSN_MIPS3D |
| 103 | |
| 104 | /* MIPS32 SmartMIPS ASE support. */ |
| 105 | #define SMT INSN_SMARTMIPS |
| 106 | |
| 107 | /* MIPS64 MDMX ASE support. */ |
| 108 | #define MX INSN_MDMX |
| 109 | |
| 110 | #define IL2E (INSN_LOONGSON_2E) |
| 111 | #define IL2F (INSN_LOONGSON_2F) |
| 112 | #define IL3A (INSN_LOONGSON_3A) |
| 113 | |
| 114 | #define P3 INSN_4650 |
| 115 | #define L1 INSN_4010 |
| 116 | #define V1 (INSN_4100 | INSN_4111 | INSN_4120) |
| 117 | #define T3 INSN_3900 |
| 118 | /* Emotion Engine MIPS r5900. */ |
| 119 | #define EE INSN_5900 |
| 120 | #define M1 INSN_10000 |
| 121 | #define SB1 INSN_SB1 |
| 122 | #define N411 INSN_4111 |
| 123 | #define N412 INSN_4120 |
| 124 | #define N5 (INSN_5400 | INSN_5500) |
| 125 | #define N54 INSN_5400 |
| 126 | #define N55 INSN_5500 |
| 127 | #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2) |
| 128 | #define IOCTP (INSN_OCTEONP | INSN_OCTEON2) |
| 129 | #define IOCT2 INSN_OCTEON2 |
| 130 | #define XLR INSN_XLR |
| 131 | #define IVIRT INSN_VIRT |
| 132 | #define IVIRT64 INSN_VIRT64 |
| 133 | |
| 134 | #define G1 (T3 \ |
| 135 | |EE \ |
| 136 | ) |
| 137 | |
| 138 | #define G2 (T3 \ |
| 139 | ) |
| 140 | |
| 141 | #define G3 (I4 \ |
| 142 | |EE \ |
| 143 | ) |
| 144 | |
| 145 | /* 64 bit CPU with 32 bit FPU (single float). */ |
| 146 | #define SF EE |
| 147 | |
| 148 | /* Support for 128 bit MMI instructions. */ |
| 149 | #define MMI EE |
| 150 | |
| 151 | /* 64 bit CPU with only 32 bit multiplication/division support. */ |
| 152 | #define M32 EE |
| 153 | |
| 154 | /* MIPS DSP ASE support. |
| 155 | NOTE: |
| 156 | 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair |
| 157 | of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have |
| 158 | the same structure as $ac0 (HI + LO). For DSP instructions that write or |
| 159 | read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a |
| 160 | (RD_HILO) attributes, such that HILO dependencies are maintained |
| 161 | conservatively. |
| 162 | |
| 163 | 2. For some mul. instructions that use integer registers as destinations |
| 164 | but destroy HI+LO as side-effect, we add WR_HILO to their attributes. |
| 165 | |
| 166 | 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields |
| 167 | (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write |
| 168 | certain fields of the DSP control register. For simplicity, we decide not |
| 169 | to track dependencies of these fields. |
| 170 | However, "bposge32" is a branch instruction that depends on the "pos" |
| 171 | field. In order to make sure that GAS does not reorder DSP instructions |
| 172 | that writes the "pos" field and "bposge32", we add DSP_VOLA |
| 173 | (INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos" |
| 174 | field. */ |
| 175 | |
| 176 | #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ |
| 177 | #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ |
| 178 | #define MOD_a WR_a|RD_a |
| 179 | #define DSP_VOLA INSN_NO_DELAY_SLOT |
| 180 | #define D32 INSN_DSP |
| 181 | #define D33 INSN_DSPR2 |
| 182 | #define D64 INSN_DSP64 |
| 183 | |
| 184 | /* MIPS MT ASE support. */ |
| 185 | #define MT32 INSN_MT |
| 186 | |
| 187 | /* Loongson support. */ |
| 188 | #define WR_z INSN2_WRITE_GPR_Z |
| 189 | #define WR_Z INSN2_WRITE_FPR_Z |
| 190 | #define RD_z INSN2_READ_GPR_Z |
| 191 | #define RD_Z INSN2_READ_FPR_Z |
| 192 | #define RD_d INSN2_READ_GPR_D |
| 193 | |
| 194 | /* MIPS MCU (MicroController) ASE support. */ |
| 195 | #define MC INSN_MCU |
| 196 | |
| 197 | /* The order of overloaded instructions matters. Label arguments and |
| 198 | register arguments look the same. Instructions that can have either |
| 199 | for arguments must apear in the correct order in this table for the |
| 200 | assembler to pick the right one. In other words, entries with |
| 201 | immediate operands must apear after the same instruction with |
| 202 | registers. |
| 203 | |
| 204 | Because of the lookup algorithm used, entries with the same opcode |
| 205 | name must be contiguous. |
| 206 | |
| 207 | Many instructions are short hand for other instructions (i.e., The |
| 208 | jal <register> instruction is short for jalr <register>). */ |
| 209 | |
| 210 | const struct mips_opcode mips_builtin_opcodes[] = |
| 211 | { |
| 212 | /* These instructions appear first so that the disassembler will find |
| 213 | them first. The assemblers uses a hash table based on the |
| 214 | instruction name anyhow. */ |
| 215 | /* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */ |
| 216 | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 }, |
| 217 | {"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 }, |
| 218 | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 }, |
| 219 | {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ |
| 220 | {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ |
| 221 | {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ |
| 222 | {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ |
| 223 | {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ |
| 224 | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, |
| 225 | {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, |
| 226 | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ |
| 227 | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ |
| 228 | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ |
| 229 | {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ |
| 230 | {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ |
| 231 | {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ |
| 232 | |
| 233 | /* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 |
| 234 | instructions. Put them here so that disassembler will find them first. |
| 235 | The assemblers uses a hash table based on the instruction name anyhow. */ |
| 236 | {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, |
| 237 | {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, |
| 238 | {"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_s|RD_t, RD_d, IL3A }, |
| 239 | {"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, |
| 240 | {"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_s|RD_t, 0, IL3A }, |
| 241 | {"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_s|RD_t, 0, IL3A }, |
| 242 | {"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 243 | {"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 244 | {"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 245 | {"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 246 | {"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 247 | {"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 248 | {"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 249 | {"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 250 | {"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 251 | {"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 252 | {"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 253 | {"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 254 | {"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 255 | {"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 256 | {"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 257 | {"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, |
| 258 | {"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, |
| 259 | {"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, |
| 260 | {"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, |
| 261 | {"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, |
| 262 | {"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, |
| 263 | {"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, |
| 264 | {"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, |
| 265 | {"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, |
| 266 | {"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, |
| 267 | {"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, |
| 268 | {"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, |
| 269 | {"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, |
| 270 | {"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, |
| 271 | {"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, |
| 272 | {"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, |
| 273 | {"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, |
| 274 | {"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 275 | {"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 276 | {"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 277 | {"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, |
| 278 | {"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, |
| 279 | {"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, |
| 280 | {"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, |
| 281 | {"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, |
| 282 | {"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A }, |
| 283 | {"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A }, |
| 284 | {"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A }, |
| 285 | {"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A }, |
| 286 | {"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_t|RD_b|LDD, WR_z, IL3A }, |
| 287 | {"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_t|RD_b|SM, RD_z, IL3A }, |
| 288 | {"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_T|RD_b|LDD, WR_Z, IL3A }, |
| 289 | {"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_T|RD_b|SM, RD_Z, IL3A }, |
| 290 | |
| 291 | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, |
| 292 | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
| 293 | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, SF }, |
| 294 | {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, |
| 295 | {"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, |
| 296 | {"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, MC }, |
| 297 | {"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC }, |
| 298 | {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC }, |
| 299 | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 300 | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, |
| 301 | {"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 302 | {"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, |
| 303 | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
| 304 | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, SF }, |
| 305 | {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 306 | {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 307 | {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 308 | {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 309 | {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, |
| 310 | {"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, |
| 311 | {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 312 | {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 313 | {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 314 | {"adda.s", "V,T", 0x46000018, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, |
| 315 | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 316 | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 317 | {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 318 | {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 319 | {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
| 320 | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 321 | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, |
| 322 | {"addu", "D,S,T", 0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 323 | {"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, |
| 324 | {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 325 | {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 326 | {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 327 | {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, I5_33 }, |
| 328 | {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, |
| 329 | {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, |
| 330 | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 331 | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, |
| 332 | {"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 333 | {"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 334 | {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 335 | {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 336 | {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 337 | {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 338 | {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 339 | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 340 | {"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, MC }, |
| 341 | {"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC }, |
| 342 | {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC }, |
| 343 | {"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, |
| 344 | /* b is at the top of the table. */ |
| 345 | /* bal is at the top of the table. */ |
| 346 | {"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, |
| 347 | {"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit032 */ |
| 348 | {"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, |
| 349 | {"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, |
| 350 | {"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit132 */ |
| 351 | {"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, |
| 352 | /* bc0[tf]l? are at the bottom of the table. */ |
| 353 | {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
| 354 | {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
| 355 | {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
| 356 | {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, |
| 357 | {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, |
| 358 | {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, |
| 359 | {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, |
| 360 | {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, |
| 361 | {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, |
| 362 | {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, |
| 363 | {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, |
| 364 | {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, |
| 365 | /* bc2* are at the bottom of the table. */ |
| 366 | /* bc3* are at the bottom of the table. */ |
| 367 | {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
| 368 | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
| 369 | {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, |
| 370 | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, |
| 371 | {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, |
| 372 | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, |
| 373 | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, |
| 374 | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, |
| 375 | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, |
| 376 | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, |
| 377 | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, |
| 378 | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, |
| 379 | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, |
| 380 | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, |
| 381 | {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
| 382 | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
| 383 | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, |
| 384 | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, |
| 385 | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, |
| 386 | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, |
| 387 | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, |
| 388 | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, |
| 389 | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, |
| 390 | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, |
| 391 | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, |
| 392 | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, |
| 393 | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
| 394 | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
| 395 | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, |
| 396 | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, |
| 397 | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, |
| 398 | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, |
| 399 | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, |
| 400 | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, |
| 401 | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, |
| 402 | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, |
| 403 | {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
| 404 | {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
| 405 | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, |
| 406 | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, |
| 407 | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, |
| 408 | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, |
| 409 | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, |
| 410 | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, |
| 411 | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, |
| 412 | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, |
| 413 | {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
| 414 | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
| 415 | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, |
| 416 | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, |
| 417 | {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, |
| 418 | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, |
| 419 | {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, |
| 420 | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, |
| 421 | {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, |
| 422 | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, |
| 423 | {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, |
| 424 | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, |
| 425 | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, |
| 426 | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 427 | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 428 | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
| 429 | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 430 | {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 431 | {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 432 | {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 433 | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 434 | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 435 | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 436 | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 437 | {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 438 | {"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 439 | {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 440 | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 441 | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 442 | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, |
| 443 | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 444 | {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 445 | {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 446 | {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 447 | {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 448 | {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 449 | {"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 450 | {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 451 | {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, |
| 452 | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 453 | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 454 | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 455 | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 456 | {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 457 | {"c.ueq.ps","S,T", 0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 458 | {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 459 | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 460 | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 461 | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 462 | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 463 | {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 464 | {"c.olt.ps","S,T", 0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 465 | {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 466 | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 467 | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 468 | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 469 | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 470 | {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 471 | {"c.ult.ps","S,T", 0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 472 | {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 473 | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 474 | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 475 | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 476 | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 477 | {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 478 | {"c.ole.ps","S,T", 0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 479 | {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 480 | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 481 | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 482 | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 483 | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 484 | {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 485 | {"c.ule.ps","S,T", 0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 486 | {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 487 | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 488 | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 489 | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 490 | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 491 | {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 492 | {"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 493 | {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 494 | {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 495 | {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 496 | {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 497 | {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 498 | {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 499 | {"c.ngle.ps","S,T", 0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 500 | {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 501 | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 502 | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 503 | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 504 | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 505 | {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 506 | {"c.seq.ps","S,T", 0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 507 | {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 508 | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 509 | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 510 | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 511 | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 512 | {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 513 | {"c.ngl.ps","S,T", 0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 514 | {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 515 | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 516 | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 517 | {"c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, EE }, |
| 518 | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 519 | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 520 | {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 521 | {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 522 | {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 523 | {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 524 | {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 525 | {"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 526 | {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 527 | {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, |
| 528 | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 529 | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 530 | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 531 | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 532 | {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 533 | {"c.nge.ps","S,T", 0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 534 | {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 535 | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 536 | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 537 | {"c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, EE }, |
| 538 | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 539 | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 540 | {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 541 | {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 542 | {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 543 | {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 544 | {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 545 | {"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 546 | {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 547 | {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, |
| 548 | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1, SF }, |
| 549 | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, |
| 550 | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, EE }, |
| 551 | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, |
| 552 | {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, |
| 553 | {"c.ngt.ps","S,T", 0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 554 | {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, |
| 555 | {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 556 | {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 557 | {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 558 | {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 559 | {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 560 | {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 561 | {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 562 | {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 563 | {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 564 | {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 565 | {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 566 | {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 567 | {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 568 | {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 569 | {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 570 | {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 571 | {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 572 | {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 573 | {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 574 | {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 575 | {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 576 | {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 577 | {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 578 | {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 579 | {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 580 | {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 581 | {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 582 | {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 583 | {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 584 | {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 585 | {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 586 | {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 587 | {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 588 | {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 589 | {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 590 | {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 591 | {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 592 | {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 593 | {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 594 | {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 595 | {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 596 | {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 597 | {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 598 | {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 599 | {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 600 | {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 601 | {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, |
| 602 | {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, |
| 603 | /* CW4010 instructions which are aliases for the cache instruction. */ |
| 604 | {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, |
| 605 | {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, |
| 606 | {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, |
| 607 | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, |
| 608 | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3}, |
| 609 | {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3}, |
| 610 | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, |
| 611 | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, |
| 612 | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, SF }, |
| 613 | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, EE }, |
| 614 | {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 615 | {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, |
| 616 | {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, |
| 617 | /* cfc2 is at the bottom of the table. */ |
| 618 | /* cfc3 is at the bottom of the table. */ |
| 619 | {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, |
| 620 | {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, |
| 621 | {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 }, |
| 622 | {"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, |
| 623 | {"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */ |
| 624 | {"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT }, |
| 625 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, |
| 626 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, |
| 627 | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 628 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, |
| 629 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, |
| 630 | /* ctc2 is at the bottom of the table. */ |
| 631 | /* ctc3 is at the bottom of the table. */ |
| 632 | {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, |
| 633 | {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, |
| 634 | {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 }, |
| 635 | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, |
| 636 | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, SF }, |
| 637 | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, SF }, |
| 638 | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, |
| 639 | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, |
| 640 | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, |
| 641 | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, SF }, |
| 642 | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
| 643 | {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33 }, |
| 644 | {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33 }, |
| 645 | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1, SF }, |
| 646 | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1, EE }, |
| 647 | {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, |
| 648 | {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 }, |
| 649 | {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, |
| 650 | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, |
| 651 | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
| 652 | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, |
| 653 | {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 654 | {"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 655 | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, |
| 656 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, |
| 657 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
| 658 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, |
| 659 | {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR }, |
| 660 | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, |
| 661 | {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, |
| 662 | {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, |
| 663 | /* dctr and dctw are used on the r5000. */ |
| 664 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, |
| 665 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, |
| 666 | {"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2 }, |
| 667 | {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, |
| 668 | {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
| 669 | {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
| 670 | {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
| 671 | /* For ddiv, see the comments about div. */ |
| 672 | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, M32 }, |
| 673 | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, M32 }, |
| 674 | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, M32 }, |
| 675 | /* For ddivu, see the comments about div. */ |
| 676 | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, M32 }, |
| 677 | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, M32 }, |
| 678 | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, M32 }, |
| 679 | {"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE }, |
| 680 | {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, |
| 681 | {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, |
| 682 | {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, |
| 683 | {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
| 684 | {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
| 685 | {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, |
| 686 | /* The MIPS assembler treats the div opcode with two operands as |
| 687 | though the first operand appeared twice (the first operand is both |
| 688 | a source and a destination). To get the div machine instruction, |
| 689 | you must use an explicit destination of $0. */ |
| 690 | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
| 691 | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
| 692 | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, |
| 693 | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, |
| 694 | {"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE }, |
| 695 | {"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, EE }, |
| 696 | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, SF }, |
| 697 | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
| 698 | {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, |
| 699 | /* For divu, see the comments about div. */ |
| 700 | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
| 701 | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
| 702 | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, |
| 703 | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, |
| 704 | {"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE }, |
| 705 | {"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, EE }, |
| 706 | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, |
| 707 | {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, |
| 708 | {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ |
| 709 | {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ |
| 710 | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, |
| 711 | {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 712 | {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 713 | {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 714 | {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 715 | {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 716 | {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 717 | {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 718 | {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, |
| 719 | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, |
| 720 | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3, EE }, |
| 721 | {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, |
| 722 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, |
| 723 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, LCD|WR_t|RD_C0, 0, IVIRT64 }, |
| 724 | {"dmfgc0", "t,+D", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, IVIRT64 }, |
| 725 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, IVIRT64 }, |
| 726 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, |
| 727 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
| 728 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3, EE }, |
| 729 | {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, |
| 730 | {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, |
| 731 | {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, IVIRT64 }, |
| 732 | {"dmtgc0", "t,+D", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, IVIRT64 }, |
| 733 | {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, IVIRT64 }, |
| 734 | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, SF }, |
| 735 | {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, SF }, |
| 736 | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3, SF }, |
| 737 | {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3, SF }, |
| 738 | /* dmfc2 is at the bottom of the table. */ |
| 739 | /* dmtc2 is at the bottom of the table. */ |
| 740 | /* dmfc3 is at the bottom of the table. */ |
| 741 | /* dmtc3 is at the bottom of the table. */ |
| 742 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT }, |
| 743 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, M32 }, |
| 744 | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, M32 }, |
| 745 | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, M32 }, |
| 746 | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, M32 }, |
| 747 | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, M32 }, |
| 748 | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, M32 }, |
| 749 | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, M32 }, |
| 750 | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, M32 }, |
| 751 | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ |
| 752 | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ |
| 753 | {"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_d|RD_s, 0, IOCT }, |
| 754 | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, M32 }, |
| 755 | {"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, M32 }, |
| 756 | {"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, M32 }, |
| 757 | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3, M32 }, |
| 758 | {"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, M32 }, |
| 759 | {"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, M32 }, |
| 760 | {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, |
| 761 | {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, |
| 762 | {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, |
| 763 | {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, |
| 764 | {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, |
| 765 | {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, |
| 766 | {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, |
| 767 | {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, |
| 768 | {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, |
| 769 | {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, |
| 770 | {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, |
| 771 | {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, |
| 772 | {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, |
| 773 | {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, |
| 774 | {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, |
| 775 | {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, |
| 776 | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, |
| 777 | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
| 778 | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ |
| 779 | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ |
| 780 | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
| 781 | {"dsll", "D,S,T", 0x45a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 782 | {"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 783 | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, |
| 784 | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
| 785 | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ |
| 786 | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ |
| 787 | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
| 788 | {"dsra", "D,S,T", 0x45e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 789 | {"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 790 | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, |
| 791 | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
| 792 | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ |
| 793 | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ |
| 794 | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, |
| 795 | {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 796 | {"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 797 | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
| 798 | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, |
| 799 | {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 800 | {"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 801 | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, |
| 802 | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, |
| 803 | {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, |
| 804 | {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
| 805 | {"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE }, |
| 806 | {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, |
| 807 | {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, |
| 808 | {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, |
| 809 | {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
| 810 | {"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 }, |
| 811 | {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, |
| 812 | {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, |
| 813 | {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, |
| 814 | {"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, |
| 815 | {"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */ |
| 816 | {"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT }, |
| 817 | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, |
| 818 | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, |
| 819 | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, SF }, |
| 820 | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
| 821 | {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, |
| 822 | {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, IVIRT }, |
| 823 | {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, IVIRT }, |
| 824 | {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, |
| 825 | {"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC }, |
| 826 | {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, |
| 827 | /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with |
| 828 | the same hazard barrier effect. */ |
| 829 | {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, |
| 830 | {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ |
| 831 | /* SVR4 PIC code requires special handling for j, so it must be a |
| 832 | macro. */ |
| 833 | {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, |
| 834 | /* This form of j is used by the disassembler and internally by the |
| 835 | assembler, but will never match user input (because the line above |
| 836 | will match first). */ |
| 837 | {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, |
| 838 | {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, |
| 839 | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, |
| 840 | /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr |
| 841 | with the same hazard barrier effect. */ |
| 842 | {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, |
| 843 | {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, |
| 844 | /* SVR4 PIC code requires special handling for jal, so it must be a |
| 845 | macro. */ |
| 846 | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, |
| 847 | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, |
| 848 | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, |
| 849 | /* This form of jal is used by the disassembler and internally by the |
| 850 | assembler, but will never match user input (because the line above |
| 851 | will match first). */ |
| 852 | {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, |
| 853 | {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 }, |
| 854 | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, |
| 855 | {"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 856 | {"laad", "d,(b),t", 0x700004df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 857 | {"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 }, |
| 858 | {"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 }, |
| 859 | {"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 860 | {"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 861 | {"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 862 | {"laid", "d,(b)", 0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 863 | {"las", "d,(b)", 0x7000029f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 }, |
| 864 | {"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 }, |
| 865 | {"law", "d,(b),t", 0x7000059f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 866 | {"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 867 | {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 868 | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, |
| 869 | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 870 | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, |
| 871 | {"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 872 | {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32|IOCT2}, |
| 873 | {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64|IOCT2}, |
| 874 | {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32|IOCT2}, |
| 875 | {"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 876 | {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32|IOCT2}, |
| 877 | {"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 }, |
| 878 | {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, |
| 879 | /* The macro has to be first to handle o32 correctly. */ |
| 880 | {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, |
| 881 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, |
| 882 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, |
| 883 | {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, |
| 884 | {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, |
| 885 | {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, |
| 886 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, SF }, |
| 887 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, SF }, |
| 888 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, SF }, |
| 889 | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, SF }, |
| 890 | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, SF }, /* ldc1 */ |
| 891 | {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, |
| 892 | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, |
| 893 | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 894 | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 895 | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 896 | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 897 | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, |
| 898 | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, |
| 899 | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, |
| 900 | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, |
| 901 | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4_33 }, |
| 902 | {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 903 | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, |
| 904 | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 905 | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, |
| 906 | /* li is at the start of the table. */ |
| 907 | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, SF }, |
| 908 | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, SF }, |
| 909 | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 910 | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 911 | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2, EE }, |
| 912 | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, EE }, |
| 913 | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3, EE }, |
| 914 | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, EE }, |
| 915 | {"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, 0, MMI }, |
| 916 | {"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI }, |
| 917 | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, |
| 918 | {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55}, |
| 919 | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 920 | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, |
| 921 | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 922 | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 923 | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, |
| 924 | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, |
| 925 | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 926 | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 927 | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ |
| 928 | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 929 | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 930 | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 931 | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 932 | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 933 | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 934 | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, |
| 935 | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ |
| 936 | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ |
| 937 | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, |
| 938 | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, |
| 939 | {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ |
| 940 | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ |
| 941 | {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, |
| 942 | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, |
| 943 | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, |
| 944 | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0, I4_33 }, |
| 945 | {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, |
| 946 | {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 947 | {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 948 | {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 949 | {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 950 | {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 951 | {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 952 | {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 953 | {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 954 | {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 955 | {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 956 | {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 957 | {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, |
| 958 | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, |
| 959 | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, |
| 960 | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, |
| 961 | {"madd.d", "D,S,T", 0x46200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 962 | {"madd.d", "D,S,T", 0x72200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 963 | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, |
| 964 | {"madd.s", "D,S,T", 0x46000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 965 | {"madd.s", "D,S,T", 0x72000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, |
| 966 | {"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE }, |
| 967 | {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, |
| 968 | {"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 969 | {"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 970 | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
| 971 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
| 972 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, |
| 973 | {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 974 | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
| 975 | {"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE }, |
| 976 | {"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE }, |
| 977 | {"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, |
| 978 | {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, |
| 979 | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
| 980 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
| 981 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, |
| 982 | {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 983 | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
| 984 | {"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE }, |
| 985 | {"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE }, |
| 986 | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, |
| 987 | {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 988 | {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 989 | {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 990 | {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 991 | {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 992 | {"max.s", "D,S,T", 0x46000028, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE }, |
| 993 | {"mfbpc", "t", 0x4000c000, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 994 | {"mfdab", "t", 0x4000c004, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 995 | {"mfdabm", "t", 0x4000c005, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 996 | {"mfdvb", "t", 0x4000c006, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 997 | {"mfdvbm", "t", 0x4000c007, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 998 | {"mfiab", "t", 0x4000c002, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 999 | {"mfiabm", "t", 0x4000c003, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE }, |
| 1000 | {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5|EE }, |
| 1001 | {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5|EE }, |
| 1002 | {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, |
| 1003 | {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, |
| 1004 | {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, |
| 1005 | {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, |
| 1006 | {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, |
| 1007 | {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, |
| 1008 | {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, |
| 1009 | {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 }, |
| 1010 | {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, |
| 1011 | {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, |
| 1012 | {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, |
| 1013 | {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, |
| 1014 | {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 }, |
| 1015 | {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, |
| 1016 | {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, |
| 1017 | {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, |
| 1018 | {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, |
| 1019 | {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, |
| 1020 | {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, |
| 1021 | {"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, |
| 1022 | {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, |
| 1023 | {"mfgc0", "t,G", 0x40600000, 0xffe007ff, LCD|WR_t|RD_C0, 0, IVIRT }, |
| 1024 | {"mfgc0", "t,+D", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, IVIRT }, |
| 1025 | {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, IVIRT }, |
| 1026 | {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, |
| 1027 | {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, |
| 1028 | {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, |
| 1029 | {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, |
| 1030 | /* mfc2 is at the bottom of the table. */ |
| 1031 | /* mfhc2 is at the bottom of the table. */ |
| 1032 | /* mfc3 is at the bottom of the table. */ |
| 1033 | {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, |
| 1034 | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, |
| 1035 | {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, |
| 1036 | {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, 0, EE }, |
| 1037 | {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, |
| 1038 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, |
| 1039 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, 0, EE }, |
| 1040 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, |
| 1041 | {"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR }, |
| 1042 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_d, 0, EE }, |
| 1043 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1044 | {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1045 | {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1046 | {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1047 | {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1048 | {"min.s", "D,S,T", 0x46000029, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE }, |
| 1049 | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, SF }, |
| 1050 | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
| 1051 | {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, |
| 1052 | {"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, |
| 1053 | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, |
| 1054 | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, |
| 1055 | {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
| 1056 | {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
| 1057 | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, |
| 1058 | {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, |
| 1059 | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|EE }, |
| 1060 | {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A }, |
| 1061 | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, |
| 1062 | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, |
| 1063 | {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
| 1064 | {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
| 1065 | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, |
| 1066 | {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33 }, |
| 1067 | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, |
| 1068 | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, |
| 1069 | {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
| 1070 | {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, |
| 1071 | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, |
| 1072 | {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, |
| 1073 | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|EE }, |
| 1074 | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, |
| 1075 | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, |
| 1076 | {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
| 1077 | {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, |
| 1078 | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, |
| 1079 | {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33 }, |
| 1080 | {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1081 | {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1082 | {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1083 | {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1084 | /* move is at the top of the table. */ |
| 1085 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1086 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR }, |
| 1087 | {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR }, |
| 1088 | {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR }, |
| 1089 | {"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR }, |
| 1090 | {"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR }, |
| 1091 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, |
| 1092 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1093 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 1094 | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, |
| 1095 | {"msub.s", "D,S,T", 0x46000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 1096 | {"msub.s", "D,S,T", 0x72000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, |
| 1097 | {"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE }, |
| 1098 | {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, |
| 1099 | {"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1100 | {"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 1101 | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
| 1102 | {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
| 1103 | {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1104 | {"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, |
| 1105 | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, |
| 1106 | {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, |
| 1107 | {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1108 | {"mtbpc", "t", 0x4080c000, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1109 | {"mtdab", "t", 0x4080c004, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1110 | {"mtdabm", "t", 0x4080c005, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1111 | {"mtdvb", "t", 0x4080c006, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1112 | {"mtdvbm", "t", 0x4080c007, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1113 | {"mtiab", "t", 0x4080c002, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1114 | {"mtiabm", "t", 0x4080c003, 0xffe0ffff, COD|RD_t|WR_C0, 0, EE }, |
| 1115 | {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE }, |
| 1116 | {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE }, |
| 1117 | {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, |
| 1118 | {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, |
| 1119 | {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, |
| 1120 | {"mtgc0", "t,G", 0x40600200, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, IVIRT }, |
| 1121 | {"mtgc0", "t,+D", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, IVIRT }, |
| 1122 | {"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, IVIRT }, |
| 1123 | {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, |
| 1124 | {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, |
| 1125 | {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, |
| 1126 | {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, |
| 1127 | /* mtc2 is at the bottom of the table. */ |
| 1128 | /* mthc2 is at the bottom of the table. */ |
| 1129 | /* mtc3 is at the bottom of the table. */ |
| 1130 | {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, |
| 1131 | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, |
| 1132 | {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, |
| 1133 | {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, 0, EE }, |
| 1134 | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, |
| 1135 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, |
| 1136 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, 0, EE }, |
| 1137 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, |
| 1138 | {"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR }, |
| 1139 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT }, |
| 1140 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT }, |
| 1141 | {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT }, |
| 1142 | {"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s, 0, IOCT }, |
| 1143 | {"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s, 0, IOCT }, |
| 1144 | {"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s, 0, IOCT }, |
| 1145 | {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_s, 0, EE }, |
| 1146 | {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, 0, EE }, |
| 1147 | {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, 0, EE }, |
| 1148 | {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, |
| 1149 | {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, |
| 1150 | {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, |
| 1151 | {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, |
| 1152 | {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, |
| 1153 | {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 }, |
| 1154 | {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, |
| 1155 | {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, |
| 1156 | {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, |
| 1157 | {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, |
| 1158 | {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, |
| 1159 | {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, |
| 1160 | {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 }, |
| 1161 | {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, |
| 1162 | {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, |
| 1163 | {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, |
| 1164 | {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, |
| 1165 | {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, |
| 1166 | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, SF }, |
| 1167 | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
| 1168 | {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1169 | {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1170 | {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1171 | {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1172 | {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, |
| 1173 | {"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, |
| 1174 | {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1175 | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, |
| 1176 | {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, |
| 1177 | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, |
| 1178 | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, |
| 1179 | {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1180 | {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1181 | {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1182 | {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1183 | {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1184 | {"mula.s", "V,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, |
| 1185 | {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1186 | {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1187 | {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1188 | {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1189 | {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1190 | {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1191 | {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1192 | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, |
| 1193 | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, |
| 1194 | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, |
| 1195 | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, |
| 1196 | {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
| 1197 | {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1198 | {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1199 | {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1200 | {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1201 | {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1202 | {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1203 | {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1204 | {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1205 | {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1206 | {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1207 | {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1208 | {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1209 | {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, |
| 1210 | {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1211 | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, |
| 1212 | {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D32 }, |
| 1213 | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
| 1214 | {"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE }, |
| 1215 | {"mult1", "d,s,t", 0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE }, |
| 1216 | {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, |
| 1217 | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, |
| 1218 | {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D32 }, |
| 1219 | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, |
| 1220 | {"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE }, |
| 1221 | {"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE }, |
| 1222 | {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, |
| 1223 | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ |
| 1224 | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ |
| 1225 | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, SF }, |
| 1226 | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, |
| 1227 | {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, |
| 1228 | {"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, |
| 1229 | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, |
| 1230 | {"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1231 | {"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 1232 | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, |
| 1233 | {"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 1234 | {"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, |
| 1235 | {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, |
| 1236 | {"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1237 | {"nmadd.ps", "D,S,T", 0x7160001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 1238 | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, |
| 1239 | {"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1240 | {"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 1241 | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, |
| 1242 | {"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 1243 | {"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, |
| 1244 | {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, |
| 1245 | {"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1246 | {"nmsub.ps", "D,S,T", 0x7160001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, |
| 1247 | /* nop is at the start of the table. */ |
| 1248 | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1249 | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, |
| 1250 | {"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1251 | {"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 1252 | {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1253 | {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1254 | {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1255 | {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1256 | {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1257 | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ |
| 1258 | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1259 | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, |
| 1260 | {"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1261 | {"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 1262 | {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1263 | {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1264 | {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1265 | {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1266 | {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1267 | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 1268 | {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, |
| 1269 | {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, |
| 1270 | {"pause", "", 0x00000140, 0xffffffff, TRAP, 0, I33 }, |
| 1271 | {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, |
| 1272 | {"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1273 | {"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1274 | {"paddsw", "d,s,t", 0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1275 | {"paddub", "d,s,t", 0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1276 | {"padduh", "d,s,t", 0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1277 | {"padduw", "d,s,t", 0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1278 | {"padsbh", "d,s,t", 0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1279 | {"pand", "d,s,t", 0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1280 | {"pceqb", "d,s,t", 0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1281 | {"pceqh", "d,s,t", 0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1282 | {"pceqw", "d,s,t", 0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1283 | {"pcgtb", "d,s,t", 0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1284 | {"pcgth", "d,s,t", 0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1285 | {"pcgtw", "d,s,t", 0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1286 | {"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1287 | {"pcpyld", "d,s,t", 0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1288 | {"pcpyud", "d,s,t", 0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1289 | {"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1290 | {"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1291 | {"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1292 | {"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1293 | {"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1294 | {"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1295 | {"pexew", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1296 | {"pext5", "d,t", 0x70000788, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1297 | {"pextlb", "d,s,t", 0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1298 | {"pextlh", "d,s,t", 0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1299 | {"pextlw", "d,s,t", 0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1300 | {"pextub", "d,s,t", 0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1301 | {"pextuh", "d,s,t", 0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1302 | {"pextuw", "d,s,t", 0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1303 | {"phmadh", "d,s,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1304 | {"phmsbh", "d,s,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1305 | {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1306 | {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1307 | {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1308 | {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1309 | {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1310 | {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1311 | {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1312 | {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1313 | {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1314 | {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1315 | {"pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1316 | {"pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1317 | {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, |
| 1318 | {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, |
| 1319 | {"plzcw", "d,s", 0x70000004, 0xfc1f07ff, WR_d|RD_s, 0, MMI }, |
| 1320 | {"pmaddh", "d,s,t", 0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1321 | {"pmadduw", "d,s,t", 0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI }, |
| 1322 | {"pmaddw", "d,s,t", 0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI }, |
| 1323 | {"pmaxh", "d,s,t", 0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1324 | {"pmaxw", "d,s,t", 0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1325 | {"pmfhi", "d", 0x70000209, 0xffff07ff, WR_d|RD_HI, 0, MMI }, |
| 1326 | {"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_d|RD_HILO, 0, MMI }, |
| 1327 | {"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_d|RD_HILO, 0, MMI }, |
| 1328 | {"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_d|RD_HILO, 0, MMI }, |
| 1329 | {"pmfhl.slw", "d", 0x700000b0, 0xffff07ff, WR_d|RD_HILO, 0, MMI }, |
| 1330 | {"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_d|RD_HILO, 0, MMI }, |
| 1331 | {"pmflo", "d", 0x70000249, 0xffff07ff, WR_d|RD_LO, 0, MMI }, |
| 1332 | {"pminh", "d,s,t", 0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1333 | {"pminw", "d,s,t", 0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1334 | {"pmsubh", "d,s,t", 0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI }, |
| 1335 | {"pmsubw", "d,s,t", 0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|MOD_HILO, 0, MMI }, |
| 1336 | {"pmthi", "s", 0x70000229, 0xfc1fffff, RD_s|WR_HI, 0, MMI }, |
| 1337 | {"pmthl.lw", "s", 0x70000031, 0xfc1fffff, RD_s|MOD_HILO, 0, MMI }, |
| 1338 | {"pmtlo", "s", 0x70000269, 0xfc1fffff, RD_s|WR_LO, 0, MMI }, |
| 1339 | {"pmulth", "d,s,t", 0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1340 | {"pmultuw", "d,s,t", 0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1341 | {"pmultw", "d,s,t", 0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI }, |
| 1342 | {"pnor", "d,s,t", 0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1343 | {"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_d|RD_s, 0, IOCT }, |
| 1344 | {"por", "d,s,t", 0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1345 | {"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1346 | {"ppacb", "d,s,t", 0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1347 | {"ppach", "d,s,t", 0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1348 | {"ppacw", "d,s,t", 0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1349 | {"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1350 | {"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_d|RD_t, 0, MMI }, |
| 1351 | {"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1352 | {"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1353 | {"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1354 | {"psubsw", "d,s,t", 0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1355 | {"psubub", "d,s,t", 0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1356 | {"psubuh", "d,s,t", 0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1357 | {"psubuw", "d,s,t", 0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1358 | {"pxor", "d,s,t", 0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1359 | /* pref and prefx are at the start of the table. */ |
| 1360 | {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, |
| 1361 | {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, |
| 1362 | {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, |
| 1363 | {"qfsrv", "d,s,t", 0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 1364 | {"qmac.00", "s,t", 0x70000412, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1365 | {"qmac.01", "s,t", 0x70000452, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1366 | {"qmac.02", "s,t", 0x70000492, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1367 | {"qmac.03", "s,t", 0x700004d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1368 | {"qmacs.00", "s,t", 0x70000012, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1369 | {"qmacs.01", "s,t", 0x70000052, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1370 | {"qmacs.02", "s,t", 0x70000092, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1371 | {"qmacs.03", "s,t", 0x700000d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 }, |
| 1372 | {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, |
| 1373 | {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, |
| 1374 | {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, |
| 1375 | {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, |
| 1376 | {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, |
| 1377 | {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, |
| 1378 | {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, |
| 1379 | {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, |
| 1380 | {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, |
| 1381 | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, |
| 1382 | {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, |
| 1383 | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, |
| 1384 | {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, |
| 1385 | {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
| 1386 | {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
| 1387 | {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
| 1388 | {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
| 1389 | {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
| 1390 | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
| 1391 | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, |
| 1392 | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, |
| 1393 | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
| 1394 | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, |
| 1395 | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, |
| 1396 | {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, |
| 1397 | {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, |
| 1398 | /* rfe is moved below as it now conflicts with tlbgp */ |
| 1399 | {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
| 1400 | {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, |
| 1401 | {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
| 1402 | {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
| 1403 | {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, |
| 1404 | {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
| 1405 | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, |
| 1406 | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, |
| 1407 | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, |
| 1408 | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, |
| 1409 | {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, |
| 1410 | {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, |
| 1411 | {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, |
| 1412 | {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, |
| 1413 | {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, |
| 1414 | {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, |
| 1415 | {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, |
| 1416 | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, |
| 1417 | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, |
| 1418 | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, SF }, |
| 1419 | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
| 1420 | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, |
| 1421 | {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, |
| 1422 | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, |
| 1423 | {"rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, EE }, |
| 1424 | {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, |
| 1425 | {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
| 1426 | {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, |
| 1427 | {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, |
| 1428 | {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
| 1429 | {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, |
| 1430 | {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
| 1431 | {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, |
| 1432 | {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1433 | {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, |
| 1434 | {"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP }, |
| 1435 | {"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP }, |
| 1436 | {"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP }, |
| 1437 | {"saad", "t,o(b)", 0, (int) M_SAAD_OB, INSN_MACRO, 0, IOCTP }, |
| 1438 | {"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP }, |
| 1439 | {"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP }, |
| 1440 | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
| 1441 | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, |
| 1442 | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2, EE }, |
| 1443 | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, EE }, |
| 1444 | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3, EE }, |
| 1445 | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, EE }, |
| 1446 | /* The macro has to be first to handle o32 correctly. */ |
| 1447 | {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, |
| 1448 | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, |
| 1449 | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, |
| 1450 | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, |
| 1451 | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, |
| 1452 | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, |
| 1453 | {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, |
| 1454 | {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, |
| 1455 | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, SF }, |
| 1456 | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, SF }, |
| 1457 | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, SF }, |
| 1458 | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, SF }, |
| 1459 | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 1460 | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 1461 | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 1462 | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2|EE }, |
| 1463 | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, SF }, |
| 1464 | {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, |
| 1465 | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, |
| 1466 | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, |
| 1467 | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, |
| 1468 | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, |
| 1469 | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, |
| 1470 | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 }, |
| 1471 | {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, |
| 1472 | {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, |
| 1473 | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, |
| 1474 | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, |
| 1475 | {"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, |
| 1476 | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, |
| 1477 | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, |
| 1478 | {"seq", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 1479 | {"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, |
| 1480 | {"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, IOCT }, |
| 1481 | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, |
| 1482 | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, |
| 1483 | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, |
| 1484 | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, |
| 1485 | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, |
| 1486 | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, |
| 1487 | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, |
| 1488 | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, |
| 1489 | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
| 1490 | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, |
| 1491 | {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1492 | {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1493 | {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1494 | {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1495 | {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1496 | {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1497 | {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1498 | {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1499 | {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1500 | {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1501 | {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1502 | {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1503 | {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1504 | {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1505 | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, |
| 1506 | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, |
| 1507 | {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 1508 | {"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, |
| 1509 | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, |
| 1510 | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, |
| 1511 | {"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 1512 | {"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, |
| 1513 | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, |
| 1514 | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ |
| 1515 | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, |
| 1516 | {"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1517 | {"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 1518 | {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1519 | {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1520 | {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1521 | {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1522 | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1523 | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, |
| 1524 | {"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 1525 | {"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, |
| 1526 | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 1527 | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 1528 | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1529 | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, |
| 1530 | {"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 1531 | {"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, |
| 1532 | {"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, |
| 1533 | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, |
| 1534 | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, |
| 1535 | {"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, IOCT }, |
| 1536 | {"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, 0, MMI }, |
| 1537 | {"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI }, |
| 1538 | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2, SF }, |
| 1539 | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, |
| 1540 | {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, |
| 1541 | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, |
| 1542 | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ |
| 1543 | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, |
| 1544 | {"sra", "D,S,T", 0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1545 | {"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 1546 | {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1547 | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, |
| 1548 | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ |
| 1549 | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, |
| 1550 | {"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1551 | {"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 1552 | {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1553 | {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1554 | {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1555 | {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1556 | /* ssnop is at the start of the table. */ |
| 1557 | {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, |
| 1558 | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1559 | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, |
| 1560 | {"sub", "D,S,T", 0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 1561 | {"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, |
| 1562 | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, SF }, |
| 1563 | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, |
| 1564 | {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1565 | {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1566 | {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1567 | {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1568 | {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, |
| 1569 | {"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, |
| 1570 | {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1571 | {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1572 | {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1573 | {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1574 | {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1575 | {"suba.s", "V,T", 0x46000019, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE }, |
| 1576 | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1577 | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, |
| 1578 | {"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, |
| 1579 | {"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, |
| 1580 | {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, |
| 1581 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55}, |
| 1582 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
| 1583 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, |
| 1584 | {"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, |
| 1585 | {"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, |
| 1586 | {"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, |
| 1587 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 1588 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 1589 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, |
| 1590 | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, |
| 1591 | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 1592 | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 1593 | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ |
| 1594 | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 1595 | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1596 | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1597 | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1598 | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1599 | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
| 1600 | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, |
| 1601 | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ |
| 1602 | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ |
| 1603 | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, |
| 1604 | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, |
| 1605 | {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ |
| 1606 | {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ |
| 1607 | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 }, |
| 1608 | {"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT }, |
| 1609 | {"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT }, |
| 1610 | {"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT }, |
| 1611 | {"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT }, |
| 1612 | {"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33 }, |
| 1613 | {"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33 }, |
| 1614 | {"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33 }, |
| 1615 | {"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33 }, |
| 1616 | {"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33 }, |
| 1617 | {"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1 }, |
| 1618 | {"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32 }, |
| 1619 | {"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2 }, |
| 1620 | {"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2 }, |
| 1621 | {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, |
| 1622 | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, |
| 1623 | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, |
| 1624 | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
| 1625 | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
| 1626 | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
| 1627 | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ |
| 1628 | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, |
| 1629 | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
| 1630 | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
| 1631 | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
| 1632 | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ |
| 1633 | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, |
| 1634 | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
| 1635 | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
| 1636 | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
| 1637 | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ |
| 1638 | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, |
| 1639 | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, |
| 1640 | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, |
| 1641 | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, |
| 1642 | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, |
| 1643 | {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, IVIRT }, |
| 1644 | {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, IVIRT }, |
| 1645 | {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, IVIRT }, |
| 1646 | {"tlbginvf","", 0x4200000c, 0xffffffff, INSN_TLB, 0, IVIRT }, |
| 1647 | {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, IVIRT }, |
| 1648 | {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, IVIRT }, |
| 1649 | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
| 1650 | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
| 1651 | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
| 1652 | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ |
| 1653 | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, |
| 1654 | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
| 1655 | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
| 1656 | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
| 1657 | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ |
| 1658 | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, |
| 1659 | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, |
| 1660 | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, |
| 1661 | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, |
| 1662 | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ |
| 1663 | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, |
| 1664 | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, |
| 1665 | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, |
| 1666 | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, SF }, |
| 1667 | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2, SF }, |
| 1668 | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1, SF }, |
| 1669 | {"trunc.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, EE }, |
| 1670 | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, EE }, |
| 1671 | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, EE }, |
| 1672 | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, EE }, |
| 1673 | {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, |
| 1674 | {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, |
| 1675 | {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, |
| 1676 | {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, |
| 1677 | {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, |
| 1678 | {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, |
| 1679 | {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, |
| 1680 | {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, |
| 1681 | {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, |
| 1682 | {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, |
| 1683 | {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, |
| 1684 | {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, |
| 1685 | {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, |
| 1686 | {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, |
| 1687 | {"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, |
| 1688 | {"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, |
| 1689 | {"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, |
| 1690 | {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, |
| 1691 | {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, |
| 1692 | {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, |
| 1693 | {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, |
| 1694 | {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, |
| 1695 | {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, |
| 1696 | {"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32 }, |
| 1697 | {"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 }, |
| 1698 | {"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 }, |
| 1699 | {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, |
| 1700 | {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, |
| 1701 | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
| 1702 | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, |
| 1703 | {"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 1704 | {"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 1705 | {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, |
| 1706 | {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1707 | {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1708 | {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, |
| 1709 | {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
| 1710 | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, |
| 1711 | {"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, MT32 }, |
| 1712 | {"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, MT32 }, |
| 1713 | {"zcb", "(b)", 0x7000071f, 0xfc1fffff, SM|RD_b, 0, IOCT2 }, |
| 1714 | {"zcbt", "(b)", 0x7000075f, 0xfc1fffff, SM|RD_b, 0, IOCT2 }, |
| 1715 | |
| 1716 | /* User Defined Instruction. */ |
| 1717 | {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1718 | {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1719 | {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1720 | {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1721 | {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1722 | {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1723 | {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1724 | {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1725 | {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1726 | {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1727 | {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1728 | {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1729 | {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1730 | {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1731 | {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1732 | {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1733 | {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1734 | {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1735 | {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1736 | {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1737 | {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1738 | {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1739 | {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1740 | {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1741 | {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1742 | {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1743 | {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1744 | {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1745 | {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1746 | {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1747 | {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1748 | {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1749 | {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1750 | {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1751 | {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1752 | {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1753 | {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1754 | {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1755 | {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1756 | {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1757 | {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1758 | {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1759 | {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1760 | {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1761 | {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1762 | {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1763 | {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1764 | {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1765 | {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1766 | {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1767 | {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1768 | {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1769 | {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1770 | {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1771 | {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1772 | {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1773 | {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1774 | {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1775 | {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1776 | {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1777 | {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1778 | {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1779 | {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1780 | {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, |
| 1781 | |
| 1782 | /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format |
| 1783 | instructions so they are here for the latters to take precedence. */ |
| 1784 | {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1785 | {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 }, |
| 1786 | {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE }, |
| 1787 | {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 }, |
| 1788 | {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1789 | {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 }, |
| 1790 | {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE }, |
| 1791 | {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 }, |
| 1792 | {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1793 | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1794 | {"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, |
| 1795 | {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2|EE }, |
| 1796 | {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 }, |
| 1797 | {"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, |
| 1798 | {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3, IOCT|IOCTP|IOCT2|EE }, |
| 1799 | {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64, IOCT|IOCTP|IOCT2 }, |
| 1800 | {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1801 | {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32, IOCT|IOCTP|IOCT2 }, |
| 1802 | {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 }, |
| 1803 | {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 }, |
| 1804 | {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 }, |
| 1805 | {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1806 | {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 }, |
| 1807 | {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 }, |
| 1808 | {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 }, |
| 1809 | {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 }, |
| 1810 | |
| 1811 | /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X |
| 1812 | instructions, so they are here for the latters to take precedence. */ |
| 1813 | {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1814 | {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE }, |
| 1815 | {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1816 | {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE }, |
| 1817 | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1818 | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1819 | {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3, IOCT|IOCTP|IOCT2|EE }, |
| 1820 | {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3, IOCT|IOCTP|IOCT2|EE }, |
| 1821 | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1822 | {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32, IOCT|IOCTP|IOCT2|EE }, |
| 1823 | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE }, |
| 1824 | {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32, IOCT|IOCTP|IOCT2|EE }, |
| 1825 | |
| 1826 | /* Conflicts with the 4650's "mul" instruction. Nobody's using the |
| 1827 | 4010 any more, so move this insn out of the way. If the object |
| 1828 | format gave us more info, we could do this right. */ |
| 1829 | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, |
| 1830 | /* MIPS DSP ASE */ |
| 1831 | {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1832 | {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1833 | {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1834 | {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1835 | {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1836 | {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1837 | {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1838 | {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1839 | {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1840 | {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1841 | {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1842 | {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1843 | {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1844 | {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1845 | {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1846 | {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1847 | {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1848 | {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1849 | {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, |
| 1850 | {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, |
| 1851 | {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
| 1852 | {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1853 | {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1854 | {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1855 | {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1856 | {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1857 | {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1858 | {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1859 | {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1860 | {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
| 1861 | {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1862 | {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1863 | {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
| 1864 | {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1865 | {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1866 | {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1867 | {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
| 1868 | {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1869 | {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
| 1870 | {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, |
| 1871 | {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, |
| 1872 | {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, |
| 1873 | {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, |
| 1874 | {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1875 | {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1876 | {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1877 | {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1878 | {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1879 | {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1880 | {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1881 | {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1882 | {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1883 | {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1884 | {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1885 | {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1886 | {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1887 | {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1888 | {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, |
| 1889 | {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, |
| 1890 | {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, |
| 1891 | {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1892 | {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1893 | {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1894 | {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1895 | {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, |
| 1896 | {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1897 | {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1898 | {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1899 | {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1900 | {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1901 | {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1902 | {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1903 | {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1904 | {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1905 | {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1906 | {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1907 | {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1908 | {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1909 | {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1910 | {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1911 | {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1912 | {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, |
| 1913 | {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, |
| 1914 | {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, |
| 1915 | {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, |
| 1916 | {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
| 1917 | {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
| 1918 | {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
| 1919 | {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
| 1920 | {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
| 1921 | {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
| 1922 | {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
| 1923 | {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
| 1924 | {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, |
| 1925 | {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, |
| 1926 | {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, |
| 1927 | /* lbux, ldx, lhx and lwx are the basic instruction section. */ |
| 1928 | {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1929 | {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1930 | {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1931 | {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1932 | {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1933 | {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1934 | {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1935 | {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1936 | {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1937 | {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1938 | {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1939 | {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1940 | {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1941 | {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1942 | {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1943 | {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, |
| 1944 | {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
| 1945 | {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
| 1946 | {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
| 1947 | {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
| 1948 | {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
| 1949 | {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
| 1950 | {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
| 1951 | {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
| 1952 | {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, |
| 1953 | {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, |
| 1954 | {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1955 | {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, |
| 1956 | {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, |
| 1957 | {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1958 | {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1959 | {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1960 | {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1961 | {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1962 | {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1963 | {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1964 | {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1965 | {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1966 | {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1967 | {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1968 | {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1969 | {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1970 | {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1971 | {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1972 | {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1973 | {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1974 | {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1975 | {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1976 | {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1977 | {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1978 | {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1979 | {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1980 | {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1981 | {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1982 | {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1983 | {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 1984 | {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1985 | {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1986 | {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1987 | {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 1988 | {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1989 | {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1990 | {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1991 | {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1992 | {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1993 | {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1994 | {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1995 | {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 1996 | {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 1997 | {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, |
| 1998 | {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, |
| 1999 | {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, |
| 2000 | {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, |
| 2001 | {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, |
| 2002 | {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, |
| 2003 | {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, |
| 2004 | {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, |
| 2005 | {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, |
| 2006 | {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 2007 | {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 2008 | {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 2009 | {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, |
| 2010 | {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, |
| 2011 | {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, |
| 2012 | {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, |
| 2013 | {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, |
| 2014 | {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
| 2015 | {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
| 2016 | {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, |
| 2017 | {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
| 2018 | {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
| 2019 | {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
| 2020 | {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
| 2021 | {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, |
| 2022 | {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2023 | {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2024 | {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2025 | {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2026 | {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2027 | {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2028 | {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2029 | {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2030 | {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2031 | {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
| 2032 | {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
| 2033 | {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
| 2034 | {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, |
| 2035 | {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, |
| 2036 | {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, |
| 2037 | {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, |
| 2038 | {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2039 | {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2040 | {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2041 | {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2042 | {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2043 | {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2044 | {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2045 | {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, |
| 2046 | {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, |
| 2047 | {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2048 | {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2049 | {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2050 | {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2051 | {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2052 | {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2053 | {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2054 | {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2055 | {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2056 | {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2057 | {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2058 | {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, |
| 2059 | {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, |
| 2060 | {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, |
| 2061 | {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, |
| 2062 | /* MIPS DSP ASE Rev2 */ |
| 2063 | {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, |
| 2064 | {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2065 | {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2066 | {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2067 | {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2068 | {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
| 2069 | {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, |
| 2070 | {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, |
| 2071 | {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2072 | {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2073 | {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2074 | {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2075 | {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2076 | {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
| 2077 | {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
| 2078 | {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
| 2079 | {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
| 2080 | {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, |
| 2081 | {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2082 | {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2083 | {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
| 2084 | {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
| 2085 | {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, |
| 2086 | {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, |
| 2087 | {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, |
| 2088 | {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2089 | {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2090 | {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, |
| 2091 | {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2092 | {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2093 | {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2094 | {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2095 | {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2096 | {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2097 | {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2098 | {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2099 | {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2100 | {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2101 | {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2102 | {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2103 | {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, |
| 2104 | {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2105 | {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2106 | {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2107 | {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2108 | {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2109 | {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, |
| 2110 | /* Move bc0* after mftr and mttr to avoid opcode collision. */ |
| 2111 | {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2112 | {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 }, |
| 2113 | {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2114 | {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 }, |
| 2115 | /* ST Microelectronics Loongson-2E and -2F. */ |
| 2116 | {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2117 | {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2118 | {"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2119 | {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2120 | {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2121 | {"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2122 | {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2123 | {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2124 | {"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2125 | {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2126 | {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2127 | {"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2128 | {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2129 | {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2130 | {"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2131 | {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2132 | {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2133 | {"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2134 | {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2135 | {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2136 | {"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2137 | {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2138 | {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2139 | {"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2140 | {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2141 | {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2142 | {"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2143 | {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2144 | {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2145 | {"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2146 | {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2147 | {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2148 | {"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2149 | {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, |
| 2150 | {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, |
| 2151 | {"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, |
| 2152 | {"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2153 | {"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2154 | {"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2155 | {"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2156 | {"packushb", "D,S,T", 0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2157 | {"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2158 | {"paddb", "D,S,T", 0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2159 | {"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2160 | {"paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2161 | {"paddh", "D,S,T", 0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2162 | {"paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2163 | {"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2164 | {"paddw", "D,S,T", 0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2165 | {"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2166 | {"paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2167 | {"paddd", "D,S,T", 0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2168 | {"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2169 | {"paddsb", "D,S,T", 0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2170 | {"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2171 | {"paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2172 | {"paddsh", "D,S,T", 0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2173 | {"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2174 | {"paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2175 | {"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2176 | {"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2177 | {"paddush", "D,S,T", 0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2178 | {"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2179 | {"pandn", "D,S,T", 0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2180 | {"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2181 | {"pavgb", "D,S,T", 0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2182 | {"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2183 | {"pavgh", "D,S,T", 0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2184 | {"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2185 | {"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2186 | {"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2187 | {"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2188 | {"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2189 | {"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2190 | {"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2191 | {"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2192 | {"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2193 | {"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2194 | {"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2195 | {"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2196 | {"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2197 | {"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2198 | {"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2199 | {"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2200 | {"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2201 | {"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2202 | {"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2203 | {"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2204 | {"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2205 | {"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2206 | {"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2207 | {"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2208 | {"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2209 | {"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2210 | {"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2211 | {"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2212 | {"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2213 | {"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2214 | {"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2215 | {"pminub", "D,S,T", 0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2216 | {"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2217 | {"pmovmskb", "D,S", 0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E }, |
| 2218 | {"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2219 | {"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2220 | {"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2221 | {"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2222 | {"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2223 | {"pmullh", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2224 | {"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2225 | {"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2226 | {"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2227 | {"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2228 | {"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2229 | {"biadd", "D,S", 0x46800005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E }, |
| 2230 | {"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2231 | {"pshufh", "D,S,T", 0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2232 | {"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2233 | {"psllh", "D,S,T", 0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2234 | {"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2235 | {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_d|RD_t, 0, MMI }, |
| 2236 | {"psllw", "D,S,T", 0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2237 | {"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2238 | {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_d|RD_t, 0, MMI }, |
| 2239 | {"psrah", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2240 | {"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2241 | {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_d|RD_t, 0, MMI }, |
| 2242 | {"psraw", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2243 | {"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2244 | {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_d|RD_t, 0, MMI }, |
| 2245 | {"psrlh", "D,S,T", 0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2246 | {"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2247 | {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_d|RD_t, 0, MMI }, |
| 2248 | {"psrlw", "D,S,T", 0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2249 | {"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2250 | {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_d|RD_t, 0, MMI }, |
| 2251 | {"psubb", "D,S,T", 0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2252 | {"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2253 | {"psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2254 | {"psubh", "D,S,T", 0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2255 | {"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2256 | {"psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2257 | {"psubw", "D,S,T", 0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2258 | {"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2259 | {"psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2260 | {"psubd", "D,S,T", 0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2261 | {"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2262 | {"psubsb", "D,S,T", 0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2263 | {"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2264 | {"psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2265 | {"psubsh", "D,S,T", 0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2266 | {"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2267 | {"psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI }, |
| 2268 | {"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2269 | {"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2270 | {"psubush", "D,S,T", 0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2271 | {"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2272 | {"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2273 | {"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2274 | {"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2275 | {"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2276 | {"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2277 | {"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2278 | {"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2279 | {"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2280 | {"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2281 | {"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2282 | {"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, |
| 2283 | {"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, |
| 2284 | {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, |
| 2285 | {"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, |
| 2286 | /* No hazard protection on coprocessor instructions--they shouldn't |
| 2287 | change the state of the processor and if they do it's up to the |
| 2288 | user to put in nops as necessary. These are at the end so that the |
| 2289 | disassembler recognizes more specific versions first. */ |
| 2290 | {"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2291 | {"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 }, |
| 2292 | {"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2293 | {"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2294 | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2295 | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 }, |
| 2296 | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2297 | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 }, |
| 2298 | /* RFE conflicts with the new Virt spec instruction tlbgp. */ |
| 2299 | {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, |
| 2300 | }; |
| 2301 | |
| 2302 | #define MIPS_NUM_OPCODES \ |
| 2303 | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) |
| 2304 | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; |
| 2305 | |
| 2306 | /* const removed from the following to allow for dynamic extensions to the |
| 2307 | * built-in instruction set. */ |
| 2308 | struct mips_opcode *mips_opcodes = |
| 2309 | (struct mips_opcode *) mips_builtin_opcodes; |
| 2310 | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; |
| 2311 | #undef MIPS_NUM_OPCODES |