[deliverable/binutils-gdb.git] / opcodes / mn10300-opc.c

/* Assemble Matsushita MN10300 instructions.
   Copyright (C) 1996 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "ansidecl.h"
#include "opcode/mn10300.h"

\f
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED	0
  {0, 0, 0}, 

#define DN0      (UNUSED+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DN1      (DN0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DN2      (DN1+1)
  {2, 4, MN10300_OPERAND_DREG},

#define DM0      (DN2+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DM1      (DM0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DM2      (DM1+1)
  {2, 4, MN10300_OPERAND_DREG},

#define AN0      (DM2+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AN1      (AN0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AN2      (AN1+1)
  {2, 4, MN10300_OPERAND_AREG},

#define AM0      (AN2+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AM1      (AM0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AM2      (AM1+1)
  {2, 4, MN10300_OPERAND_AREG},

#define IMM8    (AM2+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define IMM16    (IMM8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

/* 32bit immediate, high 16 bits in the main instruction
   word, 16bits in the extension word.  */
#define IMM32    (IMM16+1)
  {32, 0, MN10300_OPERAND_SPLIT},

/* 32bit immediate, high 16 bits in the main instruction
   word, 16bits in the extension word, low 16bits are left
   shifted 8 places.  */
#define IMM32_LOWSHIFT8    (IMM32+1)
  {32, 8, MN10300_OPERAND_SPLIT},

#define SP    (IMM32_LOWSHIFT8+1)
  {8, 0, MN10300_OPERAND_SP},

#define PSW    (SP+1)
  {0, 0, MN10300_OPERAND_PSW},

#define MDR    (PSW+1)
  {0, 0, MN10300_OPERAND_MDR},

#define DI (MDR+1)
  {2, 2, MN10300_OPERAND_DREG},

#define SD8    (DI+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD16    (SD8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD8N    (SD16+1)
  {8, 0, MN10300_OPERAND_SIGNED},

#define SD8N_SHIFT8    (SD8N+1)
  {8, 8, MN10300_OPERAND_SIGNED},

#define SIMM8    (SD8N_SHIFT8+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SIMM16    (SIMM8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define PAREN	(SIMM16+1)
  {0, 0, MN10300_OPERAND_PAREN}, 

#define DN01     (PAREN+1)
  {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},

#define AN01     (DN01+1)
  {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},

#define D16_SHIFT (AN01+1)
  {16, 8, MN10300_OPERAND_PROMOTE},

#define IMM8E    (D16_SHIFT+1)
  {8, 0, MN10300_OPERAND_EXTENDED},

#define IMM8_SHIFT8 (IMM8E + 1)
  {8, 8, 0},

} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x8000,		0xf000,		FMT_S1, {SIMM8, DN01}},
{ "mov",	0x80,		0xf0,		FMT_S0, {DM1, DN0}},
{ "mov",	0xf1e0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "mov",	0xf1d0,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "mov",	0x9000,		0xf000,		FMT_S1, {IMM8, AN01}},
{ "mov",	0x90,		0xf0,		FMT_S0, {AM1, AN0}},
{ "mov",	0x3c,		0xfc,		FMT_S0, {SP, AN0}},
{ "mov",	0xf2f0,		0xfff3,		FMT_D0, {AM1, SP}},
{ "mov",	0xf2e4,		0xfffc,		FMT_D0, {PSW, DN0}},
{ "mov",	0xf2f3,		0xfff3,		FMT_D0, {DM1, PSW}},
{ "mov",	0xf2e0,		0xfffc,		FMT_D0, {MDR, DN0}},
{ "mov",	0xf2f2,		0xfff3,		FMT_D0, {DM1, MDR}},
{ "mov",	0x70,		0xf0,		FMT_S0, {MEM(AM0), DN1}},
{ "mov",	0xf80000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "mov",	0xfa000000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), DN0}},
{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "mov",	0xf300,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
{ "mov",	0xf000,		0xfff0,		FMT_D0, {MEM(AM0), AN1}},
{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(SD8,AM0), AN1}},
{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), AN1}},
{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), AN1}},
{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), AN0}},
{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), AN0}},
{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), AN0}},
{ "mov",	0xf380,		0xffc0,		FMT_D0, {MEM2(DI, AM0), AN2}},
{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(IMM16), AN0}},
{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(IMM32), AN0}},
{ "mov",	0xf8f000,	0xfffc00,	FMT_D1, {MEM2(SD8N, AM0), SP}},
{ "mov",	0x60,		0xf0,		FMT_S0, {DM1, MEM(AN0)}},
{ "mov",	0xf81000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa100000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "mov",	0x4200,		0xf300,		FMT_S1, {DM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "mov",	0xf340,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},
{ "mov",	0xf010,		0xfff0,		FMT_D0, {AM1, MEM(AN0)}},
{ "mov",	0xf83000,	0xfff000,	FMT_D1, {AM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa300000,	0xfff00000,	FMT_D2, {AM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM1, MEM2(IMM32,AN0)}},
{ "mov",	0x4300,		0xf300,		FMT_S1, {AM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM1, MEM2(IMM16, SP)}},
{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM1, MEM2(IMM32, SP)}},
{ "mov",	0xf3c0,		0xffc0,		FMT_D0, {AM2, MEM2(DI, AN0)}},
{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM1, MEM(IMM16)}},
{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM1, MEM(IMM32)}},
{ "mov",	0xf8f400,	0xfffc00,	FMT_D1, {SP, MEM2(SD8N, AN0)}},
{ "mov",	0x2c0000,	0xfc0000,	FMT_S2, {SIMM16, DN0}},
{ "mov",	0xfccc0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mov",	0x240000,	0xfc0000,	FMT_S2, {IMM16, AN0}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "movbu",	0xf040,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movbu",	0xf84000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movbu",	0xfa400000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "movbu",	0xf400,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
{ "movbu",	0xf050,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movbu",	0xf85000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movbu",	0xfa500000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "movbu",	0xf440,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},

{ "movhu",	0xf060,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movhu",	0xf86000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movhu",	0xfa600000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "movhu",	0xf480,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "movhu",	0x380000,	0xfc0000,	FMT_S2, {MEM(IMM16), DN0}},
{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(IMM32), DN0}},
{ "movhu",	0xf070,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movhu",	0xf87000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movhu",	0xfa700000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "movhu",	0xf4c0,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16)}},
{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32)}},

{ "ext",	0xf2d0,		0xfffc,		FMT_D0, {DN0}},
{ "extb",	0x10, 		0xfc,		FMT_S0, {DN0}},
{ "extbu",	0x14,		0xfc,		FMT_S0, {DN0}},
{ "exth",	0x18,		0xfc,		FMT_S0, {DN0}},
{ "exthu",	0x1c,		0xfc,		FMT_S0, {DN0}},

{ "movm",	0xce00,		0xff00,		FMT_S1, {MEM(SP), IMM8}},
{ "movm",	0xcf00,		0xff00,		FMT_S1, {IMM8, MEM(SP)}},

{ "clr",	0x00,		0xf3,		FMT_S0, {DN1}},

{ "add",	0xe0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "add",	0xf160,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "add",	0xf150,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "add",	0xf170,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "add",	0x2800,		0xfc00,		FMT_S1, {SIMM8, DN0}},
{ "add",	0xfac00000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "add",	0xfcc00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "add",	0x2000,		0xfc00,		FMT_S1, {SIMM8, AN0}},
{ "add",	0xfad00000,	0xfffc0000,	FMT_D2, {SIMM16, AN0}},
{ "add",	0xfcd00000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "add",	0xf8fe00,	0xffff00,	FMT_D1, {SIMM8, SP}},
{ "add",	0xfafe0000,	0xfffc0000,	FMT_D2, {SIMM16, SP}},
{ "add",	0xfcfe0000,	0xfff0000,	FMT_D4, {IMM32, SP}},
{ "addc",	0xf140,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "sub",	0xf100,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sub",	0xf120,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "sub",	0xf110,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "sub",	0xf130,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "sub",	0xfcc40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sub",	0xfcd40000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "subc",	0xf180,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "mul",	0xf240,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulu",	0xf250,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "div",	0xf260,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "divu",	0xf270,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "inc",	0x40,		0xf3,		FMT_S0, {DN1}},
{ "inc",	0x41,		0xf3,		FMT_S0, {AN1}},
{ "inc4",	0x50,		0xfc,		FMT_S0, {AN0}},

{ "cmp",	0xa000,		0xf000,		FMT_S1, {SIMM8, DN01}},
{ "cmp",	0xa0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "cmp",	0xf1a0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "cmp",	0xf190,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "cmp",	0xb000,		0xf000,		FMT_S1, {IMM8, AN01}},
{ "cmp",	0xb0,		0xf0,		FMT_S0, {AM1, AN0}},
{ "cmp",	0xfac80000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "cmp",	0xfcc80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "cmp",	0xfad80000,	0xfffc0000,	FMT_D2, {IMM16, AN0}},
{ "cmp",	0xfcd80000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "and",	0xf200,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "and",	0xf8e000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "and",	0xfae00000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "and",	0xfce00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "and",	0xfafc0000,	0xfffc0000,	FMT_D2, {IMM16, PSW}},
{ "or",		0xf210,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "or",		0xf8e400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "or",		0xfae40000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "or",		0xfce40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "or",		0xfafd0000,	0xfffc0000,	FMT_D2, {IMM16, PSW}},
{ "xor",	0xf220,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "xor",	0xfae80000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "xor",	0xfce80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "not",	0xf230,		0xfffc,		FMT_D0, {DN0}},

{ "btst",	0xf8ec00,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "btst",	0xfaec0000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "btst",	0xfcec0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "btst",	0xfaf80000,	0xfffc0000,	FMT_D2,
					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bset",	0xf080,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "bset",	0xfaf00000,	0xfffc0000,	FMT_D2,
					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bclr",	0xf090,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "bclr",	0xfaf40000,	0xfffc0000,	FMT_D2, {IMM8,
						MEM2(SD8N_SHIFT8,AN0)}},

{ "asr",	0xf2b0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asr",	0xf8c800,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "lsr",	0xf2a0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "lsr",	0xf8c400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl",	0xf290,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asl",	0xf8c000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl2",	0x54,		0xfc,		FMT_S0, {DN0}},
{ "ror",	0xf284,		0xfffc,		FMT_D0, {DN0}},
{ "rol",	0xf280,		0xfffc,		FMT_D0, {DN0}},

{ "beq",	0xc800,		0xff00,		FMT_S1, {SD8N}},
{ "bne",	0xc900,		0xff00,		FMT_S1, {SD8N}},
{ "bgt",	0xc100,		0xff00,		FMT_S1, {SD8N}},
{ "bge",	0xc200,		0xff00,		FMT_S1, {SD8N}},
{ "ble",	0xc300,		0xff00,		FMT_S1, {SD8N}},
{ "blt",	0xc000,		0xff00,		FMT_S1, {SD8N}},
{ "bhi",	0xc500,		0xff00,		FMT_S1, {SD8N}},
{ "bcc",	0xc600,		0xff00,		FMT_S1, {SD8N}},
{ "bls",	0xc700,		0xff00,		FMT_S1, {SD8N}},
{ "bcs",	0xc400,		0xff00,		FMT_S1, {SD8N}},
{ "bvc",	0xf8e800,	0xffff00,	FMT_D1, {SD8N}},
{ "bvs",	0xf8e900,	0xffff00,	FMT_D1, {SD8N}},
{ "bnc",	0xf8ea00,	0xffff00,	FMT_D1, {SD8N}},
{ "bns",	0xf8eb00,	0xffff00,	FMT_D1, {SD8N}},
{ "bra",	0xca00,		0xff00,		FMT_S1, {SD8N}},

{ "leq",	0xd8,		0xff,		FMT_S0, {UNUSED}},
{ "lne",	0xd9,		0xff,		FMT_S0, {UNUSED}},
{ "lgt",	0xd1,		0xff,		FMT_S0, {UNUSED}},
{ "lge",	0xd2,		0xff,		FMT_S0, {UNUSED}},
{ "lle",	0xd3,		0xff,		FMT_S0, {UNUSED}},
{ "llt",	0xd0,		0xff,		FMT_S0, {UNUSED}},
{ "lhi",	0xd5,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "lls",	0xd7,		0xff,		FMT_S0, {UNUSED}},
{ "lcs",	0xd4,		0xff,		FMT_S0, {UNUSED}},
{ "lra",	0xda,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "setlb",	0xdb,		0xff,	 	FMT_S0, {UNUSED}},

{ "jmp",	0xf0f4,		0xfffc,		FMT_D0, {AN0}},
{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {IMM16}},
{ "jmp",	0xdc0000,	0xff0000,	FMT_S4, {IMM32}},
{ "call",	0xcd000000,	0xff000000,	FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
{ "call",	0xdd000000,	0xff000000,	FMT_S6, {IMM32,IMM8,IMM8}},
{ "calls",	0xf0f0,		0xfffc,		FMT_D0, {AN0}},
{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {IMM16}},
{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {IMM32}},

{ "ret",	0xdf0000,	0xff00000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
{ "retf",	0xde0000,	0xff00000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
{ "rets",	0xf0fc,		0xffff,		FMT_D0, {UNUSED}},
{ "rti",	0xf0fd,		0xffff,		FMT_D0, {UNUSED}},
{ "trap",	0xf0fe,		0xffff,		FMT_D0, {UNUSED}},
{ "rtm",	0xf0ff,		0xffff,		FMT_D0, {UNUSED}},
{ "nop",	0xcb,		0xff,		FMT_S0, {UNUSED}},
/* { "udf", 0, 0, {0}},  */

{ "putx",	0xf500,		0xfff0,		FMT_D0, {DM0}},
{ "getx",	0xf6f0,		0xfff0,		FMT_D0, {DN0}},
{ "mulq",	0xf600,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulq",	0xf90000,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulq",	0xfb000000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulq",	0xfd000000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mulqu",	0xf610,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulqu",	0xf90400,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulqu",	0xfb040000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulqu",	0xfd040000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sat16",	0xf640,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sat24",	0xf650,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "bsch",	0xf670,		0xfff0,		FMT_D0, {DM1, DN0}},
{ 0, 0, 0, 0, {0}},

} ;

const int mn10300_num_opcodes =
  sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);

\f
Commit	Line	Data
	1	/* Assemble Matsushita MN10300 instructions.
	2	Copyright (C) 1996 Free Software Foundation, Inc.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	#include "ansidecl.h"
	19	#include "opcode/mn10300.h"
	20
	21	\f
	22	const struct mn10300_operand mn10300_operands[] = {
	23	#define UNUSED 0
	24	{0, 0, 0},
	25
	26	#define DN0 (UNUSED+1)
	27	{2, 0, MN10300_OPERAND_DREG},
	28
	29	#define DN1 (DN0+1)
	30	{2, 2, MN10300_OPERAND_DREG},
	31
	32	#define DN2 (DN1+1)
	33	{2, 4, MN10300_OPERAND_DREG},
	34
	35	#define DM0 (DN2+1)
	36	{2, 0, MN10300_OPERAND_DREG},
	37
	38	#define DM1 (DM0+1)
	39	{2, 2, MN10300_OPERAND_DREG},
	40
	41	#define DM2 (DM1+1)
	42	{2, 4, MN10300_OPERAND_DREG},
	43
	44	#define AN0 (DM2+1)
	45	{2, 0, MN10300_OPERAND_AREG},
	46
	47	#define AN1 (AN0+1)
	48	{2, 2, MN10300_OPERAND_AREG},
	49
	50	#define AN2 (AN1+1)
	51	{2, 4, MN10300_OPERAND_AREG},
	52
	53	#define AM0 (AN2+1)
	54	{2, 0, MN10300_OPERAND_AREG},
	55
	56	#define AM1 (AM0+1)
	57	{2, 2, MN10300_OPERAND_AREG},
	58
	59	#define AM2 (AM1+1)
	60	{2, 4, MN10300_OPERAND_AREG},
	61
	62	#define IMM8 (AM2+1)
	63	{8, 0, MN10300_OPERAND_PROMOTE},
	64
	65	#define IMM16 (IMM8+1)
	66	{16, 0, MN10300_OPERAND_PROMOTE},
	67
	68	/* 32bit immediate, high 16 bits in the main instruction
	69	word, 16bits in the extension word. */
	70	#define IMM32 (IMM16+1)
	71	{32, 0, MN10300_OPERAND_SPLIT},
	72
	73	/* 32bit immediate, high 16 bits in the main instruction
	74	word, 16bits in the extension word, low 16bits are left
	75	shifted 8 places. */
	76	#define IMM32_LOWSHIFT8 (IMM32+1)
	77	{32, 8, MN10300_OPERAND_SPLIT},
	78
	79	#define SP (IMM32_LOWSHIFT8+1)
	80	{8, 0, MN10300_OPERAND_SP},
	81
	82	#define PSW (SP+1)
	83	{0, 0, MN10300_OPERAND_PSW},
	84
	85	#define MDR (PSW+1)
	86	{0, 0, MN10300_OPERAND_MDR},
	87
	88	#define DI (MDR+1)
	89	{2, 2, MN10300_OPERAND_DREG},
	90
	91	#define SD8 (DI+1)
	92	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	93
	94	#define SD16 (SD8+1)
	95	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	96
	97	#define SD8N (SD16+1)
	98	{8, 0, MN10300_OPERAND_SIGNED},
	99
	100	#define SD8N_SHIFT8 (SD8N+1)
	101	{8, 8, MN10300_OPERAND_SIGNED},
	102
	103	#define SIMM8 (SD8N_SHIFT8+1)
	104	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	105
	106	#define SIMM16 (SIMM8+1)
	107	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	108
	109	#define PAREN (SIMM16+1)
	110	{0, 0, MN10300_OPERAND_PAREN},
	111
	112	#define DN01 (PAREN+1)
	113	{2, 0, MN10300_OPERAND_DREG \| MN10300_OPERAND_REPEATED},
	114
	115	#define AN01 (DN01+1)
	116	{2, 0, MN10300_OPERAND_AREG \| MN10300_OPERAND_REPEATED},
	117
	118	#define D16_SHIFT (AN01+1)
	119	{16, 8, MN10300_OPERAND_PROMOTE},
	120
	121	#define IMM8E (D16_SHIFT+1)
	122	{8, 0, MN10300_OPERAND_EXTENDED},
	123
	124	#define IMM8_SHIFT8 (IMM8E + 1)
	125	{8, 8, 0},
	126
	127	} ;
	128
	129	#define MEM(ADDR) PAREN, ADDR, PAREN
	130	#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
	131	\f
	132	/* The opcode table.
	133
	134	The format of the opcode table is:
	135
	136	NAME OPCODE MASK { OPERANDS }
	137
	138	NAME is the name of the instruction.
	139	OPCODE is the instruction opcode.
	140	MASK is the opcode mask; this is used to tell the disassembler
	141	which bits in the actual opcode must match OPCODE.
	142	OPERANDS is the list of operands.
	143
	144	The disassembler reads the table in order and prints the first
	145	instruction which matches, so this table is sorted to put more
	146	specific instructions before more general instructions. It is also
	147	sorted by major opcode. */
	148
	149	const struct mn10300_opcode mn10300_opcodes[] = {
	150	{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}},
	151	{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
	152	{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
	153	{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
	154	{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}},
	155	{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
	156	{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
	157	{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
	158	{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
	159	{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
	160	{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
	161	{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
	162	{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
	163	{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	164	{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	165	{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	166	{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}},
	167	{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	168	{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
	169	{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
	170	{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16), DN0}},
	171	{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32), DN0}},
	172	{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
	173	{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}},
	174	{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}},
	175	{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}},
	176	{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}},
	177	{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}},
	178	{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}},
	179	{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
	180	{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16), AN0}},
	181	{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32), AN0}},
	182	{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
	183	{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
	184	{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	185	{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	186	{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	187	{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}},
	188	{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	189	{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
	190	{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
	191	{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16)}},
	192	{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32)}},
	193	{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
	194	{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
	195	{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
	196	{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}},
	197	{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}},
	198	{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}},
	199	{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM1, MEM2(IMM32, SP)}},
	200	{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
	201	{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16)}},
	202	{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32)}},
	203	{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
	204	{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
	205	{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	206	{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
	207	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	208
	209	{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	210	{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	211	{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	212	{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	213	{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
	214	{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	215	{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
	216	{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
	217	{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16), DN0}},
	218	{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32), DN0}},
	219	{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	220	{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	221	{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	222	{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	223	{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
	224	{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	225	{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
	226	{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
	227	{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16)}},
	228	{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32)}},
	229
	230	{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	231	{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	232	{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	233	{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	234	{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
	235	{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	236	{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
	237	{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
	238	{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16), DN0}},
	239	{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32), DN0}},
	240	{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	241	{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	242	{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	243	{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	244	{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
	245	{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	246	{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
	247	{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
	248	{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16)}},
	249	{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32)}},
	250
	251	{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
	252	{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
	253	{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
	254	{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
	255	{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
	256
	257	{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), IMM8}},
	258	{ "movm", 0xcf00, 0xff00, FMT_S1, {IMM8, MEM(SP)}},
	259
	260	{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
	261
	262	{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
	263	{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
	264	{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
	265	{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
	266	{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
	267	{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	268	{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	269	{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
	270	{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
	271	{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	272	{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
	273	{ "add", 0xfafe0000, 0xfffc0000, FMT_D2, {SIMM16, SP}},
	274	{ "add", 0xfcfe0000, 0xfff0000, FMT_D4, {IMM32, SP}},
	275	{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
	276
	277	{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
	278	{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
	279	{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
	280	{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
	281	{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	282	{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	283	{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
	284
	285	{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
	286	{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
	287
	288	{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
	289	{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
	290
	291	{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
	292	{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
	293	{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
	294
	295	{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}},
	296	{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
	297	{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
	298	{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
	299	{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}},
	300	{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
	301	{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	302	{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	303	{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
	304	{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	305
	306	{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
	307	{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	308	{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	309	{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	310	{ "and", 0xfafc0000, 0xfffc0000, FMT_D2, {IMM16, PSW}},
	311	{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
	312	{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
	313	{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	314	{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	315	{ "or", 0xfafd0000, 0xfffc0000, FMT_D2, {IMM16, PSW}},
	316	{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
	317	{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	318	{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	319	{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
	320
	321	{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
	322	{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	323	{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	324	{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
	325	MEM(IMM32_LOWSHIFT8)}},
	326	{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
	327	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
	328	{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	329	{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
	330	MEM(IMM32_LOWSHIFT8)}},
	331	{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
	332	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
	333	{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	334	{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
	335	MEM(IMM32_LOWSHIFT8)}},
	336	{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
	337	MEM2(SD8N_SHIFT8,AN0)}},
	338
	339	{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
	340	{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
	341	{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
	342	{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
	343	{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
	344	{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	345	{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
	346	{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
	347	{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
	348
	349	{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N}},
	350	{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N}},
	351	{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N}},
	352	{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N}},
	353	{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N}},
	354	{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N}},
	355	{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N}},
	356	{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N}},
	357	{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N}},
	358	{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N}},
	359	{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N}},
	360	{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N}},
	361	{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N}},
	362	{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N}},
	363	{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N}},
	364
	365	{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
	366	{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
	367	{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
	368	{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
	369	{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
	370	{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
	371	{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
	372	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	373	{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
	374	{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
	375	{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
	376	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	377	{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
	378
	379	{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {AN0}},
	380	{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16}},
	381	{ "jmp", 0xdc0000, 0xff0000, FMT_S4, {IMM32}},
	382	{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
	383	{ "call", 0xdd000000, 0xff000000, FMT_S6, {IMM32,IMM8,IMM8}},
	384	{ "calls", 0xf0f0, 0xfffc, FMT_D0, {AN0}},
	385	{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16}},
	386	{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32}},
	387
	388	{ "ret", 0xdf0000, 0xff00000, FMT_S2, {IMM8_SHIFT8, IMM8}},
	389	{ "retf", 0xde0000, 0xff00000, FMT_S2, {IMM8_SHIFT8, IMM8}},
	390	{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
	391	{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
	392	{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
	393	{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
	394	{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
	395	/* { "udf", 0, 0, {0}}, */
	396
	397	{ "putx", 0xf500, 0xfff0, FMT_D0, {DM0}},
	398	{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN0}},
	399	{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
	400	{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	401	{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	402	{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	403	{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
	404	{ "mulqu", 0xf90400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	405	{ "mulqu", 0xfb040000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	406	{ "mulqu", 0xfd040000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	407	{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
	408	{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
	409	{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
	410	{ 0, 0, 0, 0, {0}},
	411
	412	} ;
	413
	414	const int mn10300_num_opcodes =
	415	sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
	416
	417	\f