[deliverable/binutils-gdb.git] / opcodes / mn10300-opc.c

/* Assemble Matsushita MN10300 instructions.
   Copyright (C) 1996 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "ansidecl.h"
#include "opcode/mn10300.h"

\f
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED	0
  {0, 0, 0}, 

#define DN0      (UNUSED+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DN1      (DN0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DN2      (DN1+1)
  {2, 4, MN10300_OPERAND_DREG},

#define DM0      (DN2+1)
  {2, 0, MN10300_OPERAND_DREG},

#define DM1      (DM0+1)
  {2, 2, MN10300_OPERAND_DREG},

#define DM2      (DM1+1)
  {2, 4, MN10300_OPERAND_DREG},

#define AN0      (DM2+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AN1      (AN0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AN2      (AN1+1)
  {2, 4, MN10300_OPERAND_AREG},

#define AM0      (AN2+1)
  {2, 0, MN10300_OPERAND_AREG},

#define AM1      (AM0+1)
  {2, 2, MN10300_OPERAND_AREG},

#define AM2      (AM1+1)
  {2, 4, MN10300_OPERAND_AREG},

#define IMM8    (AM2+1)
  {8, 0, MN10300_OPERAND_PROMOTE},

#define IMM16    (IMM8+1)
  {16, 0, MN10300_OPERAND_PROMOTE},

#define IMM16_PCREL    (IMM16+1)
  {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},

#define IMM16_MEM    (IMM16_PCREL+1)
  {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},

/* 32bit immediate, high 16 bits in the main instruction
   word, 16bits in the extension word. 

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32    (IMM16_MEM+1)
  {16, 0, MN10300_OPERAND_SPLIT},

#define IMM32_PCREL    (IMM32+1)
  {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},

#define IMM32_MEM    (IMM32_PCREL+1)
  {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},

/* 32bit immediate, high 16 bits in the main instruction
   word, 16bits in the extension word, low 16bits are left
   shifted 8 places. 

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_LOWSHIFT8    (IMM32_MEM+1)
  {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},

/* 32bit immediate, high 24 bits in the main instruction
   word, 8 in the extension word.

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
  {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},

/* 32bit immediate, high 24 bits in the main instruction
   word, 8 in the extension word, low 8 bits are left
   shifted 16 places. 

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
  {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},

#define SP    (IMM32_HIGH24_LOWSHIFT16+1)
  {8, 0, MN10300_OPERAND_SP},

#define PSW    (SP+1)
  {0, 0, MN10300_OPERAND_PSW},

#define MDR    (PSW+1)
  {0, 0, MN10300_OPERAND_MDR},

#define DI (MDR+1)
  {2, 2, MN10300_OPERAND_DREG},

#define SD8    (DI+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD16    (SD8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SD8N    (SD16+1)
  {8, 0, MN10300_OPERAND_SIGNED},

#define SD8N_PCREL    (SD8N+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL},

#define SD8N_SHIFT8    (SD8N_PCREL+1)
  {8, 8, MN10300_OPERAND_SIGNED},

#define SIMM8    (SD8N_SHIFT8+1)
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define SIMM16    (SIMM8+1)
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

#define PAREN	(SIMM16+1)
  {0, 0, MN10300_OPERAND_PAREN}, 

#define DN01     (PAREN+1)
  {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},

#define AN01     (DN01+1)
  {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},

#define D16_SHIFT (AN01+1)
  {16, 8, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},

#define IMM8E    (D16_SHIFT+1)
  {8, 0, MN10300_OPERAND_EXTENDED},

#define IMM8E_SHIFT8    (IMM8E+1)
  {8, 8, MN10300_OPERAND_EXTENDED},

#define IMM8_SHIFT8 (IMM8E_SHIFT8 + 1)
  {8, 8, 0},

#define REGS    (IMM8_SHIFT8+1)
  {8, 0, MN10300_OPERAND_REG_LIST},

} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x8000,		0xf000,		FMT_S1, {SIMM8, DN01}},
{ "mov",	0x80,		0xf0,		FMT_S0, {DM1, DN0}},
{ "mov",	0xf1e0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "mov",	0xf1d0,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "mov",	0x9000,		0xf000,		FMT_S1, {IMM8, AN01}},
{ "mov",	0x90,		0xf0,		FMT_S0, {AM1, AN0}},
{ "mov",	0x3c,		0xfc,		FMT_S0, {SP, AN0}},
{ "mov",	0xf2f0,		0xfff3,		FMT_D0, {AM1, SP}},
{ "mov",	0xf2e4,		0xfffc,		FMT_D0, {PSW, DN0}},
{ "mov",	0xf2f3,		0xfff3,		FMT_D0, {DM1, PSW}},
{ "mov",	0xf2e0,		0xfffc,		FMT_D0, {MDR, DN0}},
{ "mov",	0xf2f2,		0xfff3,		FMT_D0, {DM1, MDR}},
{ "mov",	0x70,		0xf0,		FMT_S0, {MEM(AM0), DN1}},
{ "mov",	0xf80000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "mov",	0xfa000000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "mov",	0xfc000000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "mov",	0x5800,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), DN0}},
{ "mov",	0xfab40000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "mov",	0xfcb40000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "mov",	0xf300,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "mov",	0x300000,	0xfc0000,	FMT_S2, {MEM(IMM16_MEM), DN0}},
{ "mov",	0xfca40000,	0xfffc0000,	FMT_D4, {MEM(IMM32_MEM), DN0}},
{ "mov",	0xf000,		0xfff0,		FMT_D0, {MEM(AM0), AN1}},
{ "mov",	0xf82000,	0xfff000,	FMT_D1, {MEM2(SD8,AM0), AN1}},
{ "mov",	0xfa200000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), AN1}},
{ "mov",	0xfc200000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), AN1}},
{ "mov",	0x5c00,		0xfc00,		FMT_S1, {MEM2(IMM8, SP), AN0}},
{ "mov",	0xfab00000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), AN0}},
{ "mov",	0xfcb00000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), AN0}},
{ "mov",	0xf380,		0xffc0,		FMT_D0, {MEM2(DI, AM0), AN2}},
{ "mov",	0xfaa00000,	0xfffc0000,	FMT_D2, {MEM(IMM16_MEM), AN0}},
{ "mov",	0xfca00000,	0xfffc0000,	FMT_D4, {MEM(IMM32_MEM), AN0}},
{ "mov",	0xf8f000,	0xfffc00,	FMT_D1, {MEM2(SD8N, AM0), SP}},
{ "mov",	0x60,		0xf0,		FMT_S0, {DM1, MEM(AN0)}},
{ "mov",	0xf81000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa100000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc100000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "mov",	0x4200,		0xf300,		FMT_S1, {DM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa910000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "mov",	0xfc910000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "mov",	0xf340,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "mov",	0x010000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16_MEM)}},
{ "mov",	0xfc810000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32_MEM)}},
{ "mov",	0xf010,		0xfff0,		FMT_D0, {AM1, MEM(AN0)}},
{ "mov",	0xf83000,	0xfff000,	FMT_D1, {AM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa300000,	0xfff00000,	FMT_D2, {AM1, MEM2(SD16, AN0)}},
{ "mov",	0xfc300000,	0xfff00000,	FMT_D4, {AM1, MEM2(IMM32,AN0)}},
{ "mov",	0x4300,		0xf300,		FMT_S1, {AM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa900000,	0xfff30000,	FMT_D2, {AM1, MEM2(IMM16, SP)}},
{ "mov",	0xfc900000,	0xfc930000,	FMT_D4, {AM1, MEM2(IMM32, SP)}},
{ "mov",	0xf3c0,		0xffc0,		FMT_D0, {AM2, MEM2(DI, AN0)}},
{ "mov",	0xfa800000,	0xfff30000,	FMT_D2, {AM1, MEM(IMM16_MEM)}},
{ "mov",	0xfc800000,	0xfff30000,	FMT_D4, {AM1, MEM(IMM32_MEM)}},
{ "mov",	0xf8f400,	0xfffc00,	FMT_D1, {SP, MEM2(SD8N, AN0)}},
{ "mov",	0x2c0000,	0xfc0000,	FMT_S2, {SIMM16, DN0}},
{ "mov",	0xfccc0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mov",	0x240000,	0xfc0000,	FMT_S2, {IMM16, AN0}},
{ "mov",	0xfcdc0000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "movbu",	0xf040,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movbu",	0xf84000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movbu",	0xfa400000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movbu",	0xfc400000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "movbu",	0xf8b800,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
{ "movbu",	0xfab80000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "movbu",	0xfcb80000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "movbu",	0xf400,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "movbu",	0x340000,	0xfc0000,	FMT_S2, {MEM(IMM16_MEM), DN0}},
{ "movbu",	0xfca80000,	0xfffc0000,	FMT_D4, {MEM(IMM32_MEM), DN0}},
{ "movbu",	0xf050,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movbu",	0xf85000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movbu",	0xfa500000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movbu",	0xfc500000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "movbu",	0xf89200,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
{ "movbu",	0xfa920000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "movbu",	0xfc920000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "movbu",	0xf440,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "movbu",	0x020000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16_MEM)}},
{ "movbu",	0xfc820000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32_MEM)}},

{ "movhu",	0xf060,		0xfff0,		FMT_D0, {MEM(AM0), DN1}},
{ "movhu",	0xf86000,	0xfff000,	FMT_D1, {MEM2(SD8, AM0), DN1}},
{ "movhu",	0xfa600000,	0xfff00000,	FMT_D2, {MEM2(SD16, AM0), DN1}},
{ "movhu",	0xfc600000,	0xfff00000,	FMT_D4, {MEM2(IMM32,AM0), DN1}},
{ "movhu",	0xf8bc00,	0xfffc00,	FMT_D1, {MEM2(IMM8, SP), DN0}},
{ "movhu",	0xfabc0000,	0xfffc0000,	FMT_D2, {MEM2(IMM16, SP), DN0}},
{ "movhu",	0xfcbc0000,	0xfffc0000,	FMT_D4, {MEM2(IMM32, SP), DN0}},
{ "movhu",	0xf480,		0xffc0,		FMT_D0, {MEM2(DI, AM0), DN2}},
{ "movhu",	0x380000,	0xfc0000,	FMT_S2, {MEM(IMM16_MEM), DN0}},
{ "movhu",	0xfcac0000,	0xfffc0000,	FMT_D4, {MEM(IMM32_MEM), DN0}},
{ "movhu",	0xf070,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "movhu",	0xf87000,	0xfff000,	FMT_D1, {DM1, MEM2(SD8, AN0)}},
{ "movhu",	0xfa700000,	0xfff00000,	FMT_D2, {DM1, MEM2(SD16, AN0)}},
{ "movhu",	0xfc700000,	0xfff00000,	FMT_D4, {DM1, MEM2(IMM32,AN0)}},
{ "movhu",	0xf89300,	0xfff300,	FMT_D1, {DM1, MEM2(IMM8, SP)}},
{ "movhu",	0xfa930000,	0xfff30000,	FMT_D2, {DM1, MEM2(IMM16, SP)}},
{ "movhu",	0xfc930000,	0xfff30000,	FMT_D4, {DM1, MEM2(IMM32, SP)}},
{ "movhu",	0xf4c0,		0xffc0,		FMT_D0, {DM2, MEM2(DI, AN0)}},
{ "movhu",	0x030000,	0xf30000,	FMT_S2, {DM1, MEM(IMM16_MEM)}},
{ "movhu",	0xfc830000,	0xfff30000,	FMT_D4, {DM1, MEM(IMM32_MEM)}},

{ "ext",	0xf2d0,		0xfffc,		FMT_D0, {DN0}},
{ "extb",	0x10, 		0xfc,		FMT_S0, {DN0}},
{ "extbu",	0x14,		0xfc,		FMT_S0, {DN0}},
{ "exth",	0x18,		0xfc,		FMT_S0, {DN0}},
{ "exthu",	0x1c,		0xfc,		FMT_S0, {DN0}},

{ "movm",	0xce00,		0xff00,		FMT_S1, {MEM(SP), REGS}},
{ "movm",	0xcf00,		0xff00,		FMT_S1, {REGS, MEM(SP)}},

{ "clr",	0x00,		0xf3,		FMT_S0, {DN1}},

{ "add",	0xe0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "add",	0xf160,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "add",	0xf150,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "add",	0xf170,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "add",	0x2800,		0xfc00,		FMT_S1, {SIMM8, DN0}},
{ "add",	0xfac00000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "add",	0xfcc00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "add",	0x2000,		0xfc00,		FMT_S1, {SIMM8, AN0}},
{ "add",	0xfad00000,	0xfffc0000,	FMT_D2, {SIMM16, AN0}},
{ "add",	0xfcd00000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "add",	0xf8fe00,	0xffff00,	FMT_D1, {SIMM8, SP}},
{ "add",	0xfafe0000,	0xffff0000,	FMT_D2, {SIMM16, SP}},
{ "add",	0xfcfe0000,	0xffff0000,	FMT_D4, {IMM32, SP}},
{ "addc",	0xf140,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "sub",	0xf100,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sub",	0xf120,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "sub",	0xf110,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "sub",	0xf130,		0xfff0,		FMT_D0, {AM1, AN0}},
{ "sub",	0xfcc40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sub",	0xfcd40000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},
{ "subc",	0xf180,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "mul",	0xf240,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulu",	0xf250,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "div",	0xf260,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "divu",	0xf270,		0xfff0,		FMT_D0, {DM1, DN0}},

{ "inc",	0x40,		0xf3,		FMT_S0, {DN1}},
{ "inc",	0x41,		0xf3,		FMT_S0, {AN1}},
{ "inc4",	0x50,		0xfc,		FMT_S0, {AN0}},

{ "cmp",	0xa000,		0xf000,		FMT_S1, {SIMM8, DN01}},
{ "cmp",	0xa0,		0xf0,		FMT_S0, {DM1, DN0}},
{ "cmp",	0xf1a0,		0xfff0,		FMT_D0, {DM1, AN0}},
{ "cmp",	0xf190,		0xfff0,		FMT_D0, {AM1, DN0}},
{ "cmp",	0xb000,		0xf000,		FMT_S1, {IMM8, AN01}},
{ "cmp",	0xb0,		0xf0,		FMT_S0, {AM1, AN0}},
{ "cmp",	0xfac80000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "cmp",	0xfcc80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "cmp",	0xfad80000,	0xfffc0000,	FMT_D2, {IMM16, AN0}},
{ "cmp",	0xfcd80000,	0xfffc0000,	FMT_D4, {IMM32, AN0}},

{ "and",	0xf200,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "and",	0xf8e000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "and",	0xfae00000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "and",	0xfce00000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "and",	0xfafc0000,	0xffff0000,	FMT_D2, {IMM16, PSW}},
{ "or",		0xf210,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "or",		0xf8e400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "or",		0xfae40000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "or",		0xfce40000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "or",		0xfafd0000,	0xffff0000,	FMT_D2, {IMM16, PSW}},
{ "xor",	0xf220,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "xor",	0xfae80000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "xor",	0xfce80000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "not",	0xf230,		0xfffc,		FMT_D0, {DN0}},

{ "btst",	0xf8ec00,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "btst",	0xfaec0000,	0xfffc0000,	FMT_D2, {IMM16, DN0}},
{ "btst",	0xfcec0000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "btst",	0xfe020000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "btst",	0xfaf80000,	0xfffc0000,	FMT_D2,
					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bset",	0xf080,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bset",	0xfe000000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "bset",	0xfaf00000,	0xfffc0000,	FMT_D2,
					{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bclr",	0xf090,		0xfff0,		FMT_D0, {DM1, MEM(AN0)}},
{ "bclr",	0xfe010000,	0xffff0000,	FMT_D5, {IMM8E,
							 MEM(IMM32_LOWSHIFT8)}},
{ "bclr",	0xfaf40000,	0xfffc0000,	FMT_D2, {IMM8,
						MEM2(SD8N_SHIFT8,AN0)}},

{ "asr",	0xf2b0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asr",	0xf8c800,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "lsr",	0xf2a0,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "lsr",	0xf8c400,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl",	0xf290,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "asl",	0xf8c000,	0xfffc00,	FMT_D1, {IMM8, DN0}},
{ "asl2",	0x54,		0xfc,		FMT_S0, {DN0}},
{ "ror",	0xf284,		0xfffc,		FMT_D0, {DN0}},
{ "rol",	0xf280,		0xfffc,		FMT_D0, {DN0}},

{ "beq",	0xc800,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bne",	0xc900,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bgt",	0xc100,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bge",	0xc200,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "ble",	0xc300,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "blt",	0xc000,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bhi",	0xc500,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bcc",	0xc600,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bls",	0xc700,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bcs",	0xc400,		0xff00,		FMT_S1, {SD8N_PCREL}},
{ "bvc",	0xf8e800,	0xffff00,	FMT_D1, {SD8N_PCREL}},
{ "bvs",	0xf8e900,	0xffff00,	FMT_D1, {SD8N_PCREL}},
{ "bnc",	0xf8ea00,	0xffff00,	FMT_D1, {SD8N_PCREL}},
{ "bns",	0xf8eb00,	0xffff00,	FMT_D1, {SD8N_PCREL}},
{ "bra",	0xca00,		0xff00,		FMT_S1, {SD8N_PCREL}},

{ "leq",	0xd8,		0xff,		FMT_S0, {UNUSED}},
{ "lne",	0xd9,		0xff,		FMT_S0, {UNUSED}},
{ "lgt",	0xd1,		0xff,		FMT_S0, {UNUSED}},
{ "lge",	0xd2,		0xff,		FMT_S0, {UNUSED}},
{ "lle",	0xd3,		0xff,		FMT_S0, {UNUSED}},
{ "llt",	0xd0,		0xff,		FMT_S0, {UNUSED}},
{ "lhi",	0xd5,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "lls",	0xd7,		0xff,		FMT_S0, {UNUSED}},
{ "lcs",	0xd4,		0xff,		FMT_S0, {UNUSED}},
{ "lra",	0xda,		0xff,		FMT_S0, {UNUSED}},
{ "lcc",	0xd6,		0xff,		FMT_S0, {UNUSED}},
{ "setlb",	0xdb,		0xff,	 	FMT_S0, {UNUSED}},

{ "jmp",	0xf0f4,		0xfffc,		FMT_D0, {PAREN,AN0,PAREN}},
{ "jmp",	0xcc0000,	0xff0000,	FMT_S2, {IMM16_PCREL}},
{ "jmp",	0xdc000000,	0xff000000,	FMT_S4, {IMM32_HIGH24}},
{ "call",	0xcd000000,	0xff000000,	FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
{ "call",	0xdd000000,	0xff000000,	FMT_S6,
					{IMM32_HIGH24_LOWSHIFT16,IMM8E_SHIFT8,IMM8E}},
{ "calls",	0xf0f0,		0xfffc,		FMT_D0, {PAREN,AN0,PAREN}},
{ "calls",	0xfaff0000,	0xffff0000,	FMT_D2, {IMM16_PCREL}},
{ "calls",	0xfcff0000,	0xffff0000,	FMT_D4, {IMM32_PCREL}},

{ "ret",	0xdf0000,	0xff0000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
{ "retf",	0xde0000,	0xff0000,	FMT_S2, {IMM8_SHIFT8, IMM8}},
{ "rets",	0xf0fc,		0xffff,		FMT_D0, {UNUSED}},
{ "rti",	0xf0fd,		0xffff,		FMT_D0, {UNUSED}},
{ "trap",	0xf0fe,		0xffff,		FMT_D0, {UNUSED}},
{ "rtm",	0xf0ff,		0xffff,		FMT_D0, {UNUSED}},
{ "nop",	0xcb,		0xff,		FMT_S0, {UNUSED}},
/* { "udf", 0, 0, {0}},  */

{ "putx",	0xf500,		0xfff0,		FMT_D0, {DN01}},
{ "getx",	0xf6f0,		0xfff0,		FMT_D0, {DN01}},
{ "mulq",	0xf600,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulq",	0xf90000,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulq",	0xfb000000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulq",	0xfd000000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "mulqu",	0xf610,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "mulqu",	0xf91400,	0xfffc00,	FMT_D1, {SIMM8, DN0}},
{ "mulqu",	0xfb140000,	0xfffc0000,	FMT_D2, {SIMM16, DN0}},
{ "mulqu",	0xfd140000,	0xfffc0000,	FMT_D4, {IMM32, DN0}},
{ "sat16",	0xf640,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "sat24",	0xf650,		0xfff0,		FMT_D0, {DM1, DN0}},
{ "bsch",	0xf670,		0xfff0,		FMT_D0, {DM1, DN0}},
{ 0, 0, 0, 0, {0}},

} ;

const int mn10300_num_opcodes =
  sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);

\f
Commit	Line	Data
	1	/* Assemble Matsushita MN10300 instructions.
	2	Copyright (C) 1996 Free Software Foundation, Inc.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	#include "ansidecl.h"
	19	#include "opcode/mn10300.h"
	20
	21	\f
	22	const struct mn10300_operand mn10300_operands[] = {
	23	#define UNUSED 0
	24	{0, 0, 0},
	25
	26	#define DN0 (UNUSED+1)
	27	{2, 0, MN10300_OPERAND_DREG},
	28
	29	#define DN1 (DN0+1)
	30	{2, 2, MN10300_OPERAND_DREG},
	31
	32	#define DN2 (DN1+1)
	33	{2, 4, MN10300_OPERAND_DREG},
	34
	35	#define DM0 (DN2+1)
	36	{2, 0, MN10300_OPERAND_DREG},
	37
	38	#define DM1 (DM0+1)
	39	{2, 2, MN10300_OPERAND_DREG},
	40
	41	#define DM2 (DM1+1)
	42	{2, 4, MN10300_OPERAND_DREG},
	43
	44	#define AN0 (DM2+1)
	45	{2, 0, MN10300_OPERAND_AREG},
	46
	47	#define AN1 (AN0+1)
	48	{2, 2, MN10300_OPERAND_AREG},
	49
	50	#define AN2 (AN1+1)
	51	{2, 4, MN10300_OPERAND_AREG},
	52
	53	#define AM0 (AN2+1)
	54	{2, 0, MN10300_OPERAND_AREG},
	55
	56	#define AM1 (AM0+1)
	57	{2, 2, MN10300_OPERAND_AREG},
	58
	59	#define AM2 (AM1+1)
	60	{2, 4, MN10300_OPERAND_AREG},
	61
	62	#define IMM8 (AM2+1)
	63	{8, 0, MN10300_OPERAND_PROMOTE},
	64
	65	#define IMM16 (IMM8+1)
	66	{16, 0, MN10300_OPERAND_PROMOTE},
	67
	68	#define IMM16_PCREL (IMM16+1)
	69	{16, 0, MN10300_OPERAND_PROMOTE \| MN10300_OPERAND_PCREL},
	70
	71	#define IMM16_MEM (IMM16_PCREL+1)
	72	{16, 0, MN10300_OPERAND_PROMOTE \| MN10300_OPERAND_MEMADDR},
	73
	74	/* 32bit immediate, high 16 bits in the main instruction
	75	word, 16bits in the extension word.
	76
	77	The "bits" field indicates how many bits are in the
	78	main instruction word for MN10300_OPERAND_SPLIT! */
	79	#define IMM32 (IMM16_MEM+1)
	80	{16, 0, MN10300_OPERAND_SPLIT},
	81
	82	#define IMM32_PCREL (IMM32+1)
	83	{16, 0, MN10300_OPERAND_SPLIT \| MN10300_OPERAND_PCREL},
	84
	85	#define IMM32_MEM (IMM32_PCREL+1)
	86	{16, 0, MN10300_OPERAND_SPLIT \| MN10300_OPERAND_MEMADDR},
	87
	88	/* 32bit immediate, high 16 bits in the main instruction
	89	word, 16bits in the extension word, low 16bits are left
	90	shifted 8 places.
	91
	92	The "bits" field indicates how many bits are in the
	93	main instruction word for MN10300_OPERAND_SPLIT! */
	94	#define IMM32_LOWSHIFT8 (IMM32_MEM+1)
	95	{16, 8, MN10300_OPERAND_SPLIT \| MN10300_OPERAND_MEMADDR},
	96
	97	/* 32bit immediate, high 24 bits in the main instruction
	98	word, 8 in the extension word.
	99
	100	The "bits" field indicates how many bits are in the
	101	main instruction word for MN10300_OPERAND_SPLIT! */
	102	#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
	103	{24, 0, MN10300_OPERAND_SPLIT \| MN10300_OPERAND_PCREL},
	104
	105	/* 32bit immediate, high 24 bits in the main instruction
	106	word, 8 in the extension word, low 8 bits are left
	107	shifted 16 places.
	108
	109	The "bits" field indicates how many bits are in the
	110	main instruction word for MN10300_OPERAND_SPLIT! */
	111	#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
	112	{24, 16, MN10300_OPERAND_SPLIT \| MN10300_OPERAND_PCREL},
	113
	114	#define SP (IMM32_HIGH24_LOWSHIFT16+1)
	115	{8, 0, MN10300_OPERAND_SP},
	116
	117	#define PSW (SP+1)
	118	{0, 0, MN10300_OPERAND_PSW},
	119
	120	#define MDR (PSW+1)
	121	{0, 0, MN10300_OPERAND_MDR},
	122
	123	#define DI (MDR+1)
	124	{2, 2, MN10300_OPERAND_DREG},
	125
	126	#define SD8 (DI+1)
	127	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	128
	129	#define SD16 (SD8+1)
	130	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	131
	132	#define SD8N (SD16+1)
	133	{8, 0, MN10300_OPERAND_SIGNED},
	134
	135	#define SD8N_PCREL (SD8N+1)
	136	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PCREL},
	137
	138	#define SD8N_SHIFT8 (SD8N_PCREL+1)
	139	{8, 8, MN10300_OPERAND_SIGNED},
	140
	141	#define SIMM8 (SD8N_SHIFT8+1)
	142	{8, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	143
	144	#define SIMM16 (SIMM8+1)
	145	{16, 0, MN10300_OPERAND_SIGNED \| MN10300_OPERAND_PROMOTE},
	146
	147	#define PAREN (SIMM16+1)
	148	{0, 0, MN10300_OPERAND_PAREN},
	149
	150	#define DN01 (PAREN+1)
	151	{2, 0, MN10300_OPERAND_DREG \| MN10300_OPERAND_REPEATED},
	152
	153	#define AN01 (DN01+1)
	154	{2, 0, MN10300_OPERAND_AREG \| MN10300_OPERAND_REPEATED},
	155
	156	#define D16_SHIFT (AN01+1)
	157	{16, 8, MN10300_OPERAND_PROMOTE \| MN10300_OPERAND_PCREL},
	158
	159	#define IMM8E (D16_SHIFT+1)
	160	{8, 0, MN10300_OPERAND_EXTENDED},
	161
	162	#define IMM8E_SHIFT8 (IMM8E+1)
	163	{8, 8, MN10300_OPERAND_EXTENDED},
	164
	165	#define IMM8_SHIFT8 (IMM8E_SHIFT8 + 1)
	166	{8, 8, 0},
	167
	168	#define REGS (IMM8_SHIFT8+1)
	169	{8, 0, MN10300_OPERAND_REG_LIST},
	170
	171	} ;
	172
	173	#define MEM(ADDR) PAREN, ADDR, PAREN
	174	#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
	175	\f
	176	/* The opcode table.
	177
	178	The format of the opcode table is:
	179
	180	NAME OPCODE MASK { OPERANDS }
	181
	182	NAME is the name of the instruction.
	183	OPCODE is the instruction opcode.
	184	MASK is the opcode mask; this is used to tell the disassembler
	185	which bits in the actual opcode must match OPCODE.
	186	OPERANDS is the list of operands.
	187
	188	The disassembler reads the table in order and prints the first
	189	instruction which matches, so this table is sorted to put more
	190	specific instructions before more general instructions. It is also
	191	sorted by major opcode. */
	192
	193	const struct mn10300_opcode mn10300_opcodes[] = {
	194	{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}},
	195	{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
	196	{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
	197	{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
	198	{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}},
	199	{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
	200	{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
	201	{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
	202	{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
	203	{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
	204	{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
	205	{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
	206	{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
	207	{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	208	{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	209	{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	210	{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}},
	211	{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	212	{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
	213	{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
	214	{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
	215	{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
	216	{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
	217	{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}},
	218	{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}},
	219	{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}},
	220	{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}},
	221	{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}},
	222	{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}},
	223	{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
	224	{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16_MEM), AN0}},
	225	{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), AN0}},
	226	{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
	227	{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
	228	{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	229	{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	230	{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	231	{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}},
	232	{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	233	{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
	234	{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
	235	{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
	236	{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
	237	{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
	238	{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
	239	{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
	240	{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}},
	241	{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}},
	242	{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}},
	243	{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM1, MEM2(IMM32, SP)}},
	244	{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
	245	{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16_MEM)}},
	246	{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32_MEM)}},
	247	{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
	248	{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
	249	{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	250	{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
	251	{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	252
	253	{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	254	{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	255	{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	256	{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	257	{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
	258	{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	259	{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
	260	{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
	261	{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
	262	{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
	263	{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	264	{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	265	{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	266	{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	267	{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
	268	{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	269	{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
	270	{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
	271	{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
	272	{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
	273
	274	{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
	275	{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
	276	{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
	277	{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
	278	{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
	279	{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
	280	{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
	281	{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
	282	{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
	283	{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
	284	{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	285	{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
	286	{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
	287	{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
	288	{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
	289	{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
	290	{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
	291	{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
	292	{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
	293	{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
	294
	295	{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
	296	{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
	297	{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
	298	{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
	299	{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
	300
	301	{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), REGS}},
	302	{ "movm", 0xcf00, 0xff00, FMT_S1, {REGS, MEM(SP)}},
	303
	304	{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
	305
	306	{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
	307	{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
	308	{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
	309	{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
	310	{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
	311	{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	312	{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	313	{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
	314	{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
	315	{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	316	{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
	317	{ "add", 0xfafe0000, 0xffff0000, FMT_D2, {SIMM16, SP}},
	318	{ "add", 0xfcfe0000, 0xffff0000, FMT_D4, {IMM32, SP}},
	319	{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
	320
	321	{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
	322	{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
	323	{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
	324	{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
	325	{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	326	{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	327	{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
	328
	329	{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
	330	{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
	331
	332	{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
	333	{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
	334
	335	{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
	336	{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
	337	{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
	338
	339	{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}},
	340	{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
	341	{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
	342	{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
	343	{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}},
	344	{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
	345	{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	346	{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	347	{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
	348	{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
	349
	350	{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
	351	{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	352	{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	353	{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	354	{ "and", 0xfafc0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
	355	{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
	356	{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
	357	{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	358	{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	359	{ "or", 0xfafd0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
	360	{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
	361	{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	362	{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	363	{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
	364
	365	{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
	366	{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
	367	{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	368	{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
	369	MEM(IMM32_LOWSHIFT8)}},
	370	{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
	371	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
	372	{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	373	{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
	374	MEM(IMM32_LOWSHIFT8)}},
	375	{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
	376	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
	377	{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
	378	{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
	379	MEM(IMM32_LOWSHIFT8)}},
	380	{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
	381	MEM2(SD8N_SHIFT8,AN0)}},
	382
	383	{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
	384	{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
	385	{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
	386	{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
	387	{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
	388	{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
	389	{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
	390	{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
	391	{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
	392
	393	{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N_PCREL}},
	394	{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N_PCREL}},
	395	{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N_PCREL}},
	396	{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N_PCREL}},
	397	{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N_PCREL}},
	398	{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N_PCREL}},
	399	{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N_PCREL}},
	400	{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N_PCREL}},
	401	{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N_PCREL}},
	402	{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N_PCREL}},
	403	{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N_PCREL}},
	404	{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N_PCREL}},
	405	{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N_PCREL}},
	406	{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N_PCREL}},
	407	{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N_PCREL}},
	408
	409	{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
	410	{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
	411	{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
	412	{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
	413	{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
	414	{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
	415	{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
	416	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	417	{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
	418	{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
	419	{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
	420	{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
	421	{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
	422
	423	{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
	424	{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16_PCREL}},
	425	{ "jmp", 0xdc000000, 0xff000000, FMT_S4, {IMM32_HIGH24}},
	426	{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
	427	{ "call", 0xdd000000, 0xff000000, FMT_S6,
	428	{IMM32_HIGH24_LOWSHIFT16,IMM8E_SHIFT8,IMM8E}},
	429	{ "calls", 0xf0f0, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
	430	{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16_PCREL}},
	431	{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32_PCREL}},
	432
	433	{ "ret", 0xdf0000, 0xff0000, FMT_S2, {IMM8_SHIFT8, IMM8}},
	434	{ "retf", 0xde0000, 0xff0000, FMT_S2, {IMM8_SHIFT8, IMM8}},
	435	{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
	436	{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
	437	{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
	438	{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
	439	{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
	440	/* { "udf", 0, 0, {0}}, */
	441
	442	{ "putx", 0xf500, 0xfff0, FMT_D0, {DN01}},
	443	{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN01}},
	444	{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
	445	{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	446	{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	447	{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	448	{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
	449	{ "mulqu", 0xf91400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
	450	{ "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
	451	{ "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
	452	{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
	453	{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
	454	{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
	455	{ 0, 0, 0, 0, {0}},
	456
	457	} ;
	458
	459	const int mn10300_num_opcodes =
	460	sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
	461
	462	\f