| 1 | /* CPU data header for mt. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2009 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #ifndef MT_CPU_H |
| 26 | #define MT_CPU_H |
| 27 | |
| 28 | #define CGEN_ARCH mt |
| 29 | |
| 30 | /* Given symbol S, return mt_cgen_<S>. */ |
| 31 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 32 | #define CGEN_SYM(s) mt##_cgen_##s |
| 33 | #else |
| 34 | #define CGEN_SYM(s) mt/**/_cgen_/**/s |
| 35 | #endif |
| 36 | |
| 37 | |
| 38 | /* Selected cpu families. */ |
| 39 | #define HAVE_CPU_MS1BF |
| 40 | #define HAVE_CPU_MS1_003BF |
| 41 | #define HAVE_CPU_MS2BF |
| 42 | |
| 43 | #define CGEN_INSN_LSB0_P 1 |
| 44 | |
| 45 | /* Minimum size of any insn (in bytes). */ |
| 46 | #define CGEN_MIN_INSN_SIZE 4 |
| 47 | |
| 48 | /* Maximum size of any insn (in bytes). */ |
| 49 | #define CGEN_MAX_INSN_SIZE 4 |
| 50 | |
| 51 | #define CGEN_INT_INSN_P 1 |
| 52 | |
| 53 | /* Maximum number of syntax elements in an instruction. */ |
| 54 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40 |
| 55 | |
| 56 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. |
| 57 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands |
| 58 | we can't hash on everything up to the space. */ |
| 59 | #define CGEN_MNEMONIC_OPERANDS |
| 60 | |
| 61 | /* Maximum number of fields in an instruction. */ |
| 62 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14 |
| 63 | |
| 64 | /* Enums. */ |
| 65 | |
| 66 | /* Enum declaration for msys enums. */ |
| 67 | typedef enum insn_msys { |
| 68 | MSYS_NO, MSYS_YES |
| 69 | } INSN_MSYS; |
| 70 | |
| 71 | /* Enum declaration for opc enums. */ |
| 72 | typedef enum insn_opc { |
| 73 | OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3 |
| 74 | , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10 |
| 75 | , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14 |
| 76 | , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24 |
| 77 | , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28 |
| 78 | , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32 |
| 79 | , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50 |
| 80 | , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53 |
| 81 | } INSN_OPC; |
| 82 | |
| 83 | /* Enum declaration for msopc enums. */ |
| 84 | typedef enum insn_msopc { |
| 85 | MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB |
| 86 | , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI |
| 87 | , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI |
| 88 | , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB |
| 89 | , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB |
| 90 | , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR |
| 91 | , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR |
| 92 | , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS |
| 93 | } INSN_MSOPC; |
| 94 | |
| 95 | /* Enum declaration for imm enums. */ |
| 96 | typedef enum insn_imm { |
| 97 | IMM_NO, IMM_YES |
| 98 | } INSN_IMM; |
| 99 | |
| 100 | /* Enum declaration for . */ |
| 101 | typedef enum msys_syms { |
| 102 | H_NIL_DUP = 1, H_NIL_XX = 0 |
| 103 | } MSYS_SYMS; |
| 104 | |
| 105 | /* Attributes. */ |
| 106 | |
| 107 | /* Enum declaration for machine type selection. */ |
| 108 | typedef enum mach_attr { |
| 109 | MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2 |
| 110 | , MACH_MAX |
| 111 | } MACH_ATTR; |
| 112 | |
| 113 | /* Enum declaration for instruction set selection. */ |
| 114 | typedef enum isa_attr { |
| 115 | ISA_MT, ISA_MAX |
| 116 | } ISA_ATTR; |
| 117 | |
| 118 | /* Number of architecture variants. */ |
| 119 | #define MAX_ISAS 1 |
| 120 | #define MAX_MACHS ((int) MACH_MAX) |
| 121 | |
| 122 | /* Ifield support. */ |
| 123 | |
| 124 | /* Ifield attribute indices. */ |
| 125 | |
| 126 | /* Enum declaration for cgen_ifld attrs. */ |
| 127 | typedef enum cgen_ifld_attr { |
| 128 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED |
| 129 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 |
| 130 | , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS |
| 131 | } CGEN_IFLD_ATTR; |
| 132 | |
| 133 | /* Number of non-boolean elements in cgen_ifld_attr. */ |
| 134 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) |
| 135 | |
| 136 | /* cgen_ifld attribute accessor macros. */ |
| 137 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) |
| 138 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) |
| 139 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) |
| 140 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) |
| 141 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) |
| 142 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) |
| 143 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) |
| 144 | |
| 145 | /* Enum declaration for mt ifield types. */ |
| 146 | typedef enum ifield_type { |
| 147 | MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC |
| 148 | , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2 |
| 149 | , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S |
| 150 | , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12 |
| 151 | , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC |
| 152 | , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA |
| 153 | , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE |
| 154 | , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23 |
| 155 | , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR |
| 156 | , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19 |
| 157 | , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR |
| 158 | , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15 |
| 159 | , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX |
| 160 | , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11 |
| 161 | , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB |
| 162 | , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM |
| 163 | , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP |
| 164 | , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL |
| 165 | , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2 |
| 166 | , MT_F_BRC2, MT_F_BALL2, MT_F_MAX |
| 167 | } IFIELD_TYPE; |
| 168 | |
| 169 | #define MAX_IFLD ((int) MT_F_MAX) |
| 170 | |
| 171 | /* Hardware attribute indices. */ |
| 172 | |
| 173 | /* Enum declaration for cgen_hw attrs. */ |
| 174 | typedef enum cgen_hw_attr { |
| 175 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE |
| 176 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS |
| 177 | } CGEN_HW_ATTR; |
| 178 | |
| 179 | /* Number of non-boolean elements in cgen_hw_attr. */ |
| 180 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) |
| 181 | |
| 182 | /* cgen_hw attribute accessor macros. */ |
| 183 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) |
| 184 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) |
| 185 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) |
| 186 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) |
| 187 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) |
| 188 | |
| 189 | /* Enum declaration for mt hardware types. */ |
| 190 | typedef enum cgen_hw_type { |
| 191 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR |
| 192 | , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX |
| 193 | } CGEN_HW_TYPE; |
| 194 | |
| 195 | #define MAX_HW ((int) HW_MAX) |
| 196 | |
| 197 | /* Operand attribute indices. */ |
| 198 | |
| 199 | /* Enum declaration for cgen_operand attrs. */ |
| 200 | typedef enum cgen_operand_attr { |
| 201 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT |
| 202 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY |
| 203 | , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS |
| 204 | } CGEN_OPERAND_ATTR; |
| 205 | |
| 206 | /* Number of non-boolean elements in cgen_operand_attr. */ |
| 207 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) |
| 208 | |
| 209 | /* cgen_operand attribute accessor macros. */ |
| 210 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
| 211 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) |
| 212 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) |
| 213 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) |
| 214 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) |
| 215 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) |
| 216 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) |
| 217 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) |
| 218 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) |
| 219 | |
| 220 | /* Enum declaration for mt operand types. */ |
| 221 | typedef enum cgen_operand_type { |
| 222 | MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR |
| 223 | , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O |
| 224 | , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC |
| 225 | , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2 |
| 226 | , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL |
| 227 | , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE |
| 228 | , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE |
| 229 | , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA |
| 230 | , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM |
| 231 | , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR |
| 232 | , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB |
| 233 | , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR |
| 234 | , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL |
| 235 | , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX |
| 236 | } CGEN_OPERAND_TYPE; |
| 237 | |
| 238 | /* Number of operands types. */ |
| 239 | #define MAX_OPERANDS 55 |
| 240 | |
| 241 | /* Maximum number of operands referenced by any insn. */ |
| 242 | #define MAX_OPERAND_INSTANCES 8 |
| 243 | |
| 244 | /* Insn attribute indices. */ |
| 245 | |
| 246 | /* Enum declaration for cgen_insn attrs. */ |
| 247 | typedef enum cgen_insn_attr { |
| 248 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI |
| 249 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED |
| 250 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS |
| 251 | , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD |
| 252 | , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2 |
| 253 | , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH |
| 254 | , CGEN_INSN_END_NBOOLS |
| 255 | } CGEN_INSN_ATTR; |
| 256 | |
| 257 | /* Number of non-boolean elements in cgen_insn_attr. */ |
| 258 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) |
| 259 | |
| 260 | /* cgen_insn attribute accessor macros. */ |
| 261 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 262 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) |
| 263 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) |
| 264 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) |
| 265 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) |
| 266 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) |
| 267 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) |
| 268 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) |
| 269 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) |
| 270 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) |
| 271 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) |
| 272 | #define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0) |
| 273 | #define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0) |
| 274 | #define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0) |
| 275 | #define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0) |
| 276 | #define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0) |
| 277 | #define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_JAL_HAZARD)) != 0) |
| 278 | #define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0) |
| 279 | #define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0) |
| 280 | #define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0) |
| 281 | #define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR2)) != 0) |
| 282 | #define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0) |
| 283 | |
| 284 | /* cgen.h uses things we just defined. */ |
| 285 | #include "opcode/cgen.h" |
| 286 | |
| 287 | extern const struct cgen_ifld mt_cgen_ifld_table[]; |
| 288 | |
| 289 | /* Attributes. */ |
| 290 | extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[]; |
| 291 | extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[]; |
| 292 | extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[]; |
| 293 | extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[]; |
| 294 | |
| 295 | /* Hardware decls. */ |
| 296 | |
| 297 | extern CGEN_KEYWORD mt_cgen_opval_h_spr; |
| 298 | |
| 299 | extern const CGEN_HW_ENTRY mt_cgen_hw_table[]; |
| 300 | |
| 301 | |
| 302 | |
| 303 | #endif /* MT_CPU_H */ |