| 1 | /* NDS32-specific support for 32-bit ELF. |
| 2 | Copyright (C) 2012-2017 Free Software Foundation, Inc. |
| 3 | Contributed by Andes Technology Corporation. |
| 4 | |
| 5 | This file is part of BFD, the Binary File Descriptor library. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | 02110-1301, USA. */ |
| 21 | |
| 22 | |
| 23 | #ifndef NDS32_ASM_H |
| 24 | #define NDS32_ASM_H |
| 25 | |
| 26 | #ifdef __cplusplus |
| 27 | extern "C" { |
| 28 | #endif |
| 29 | |
| 30 | /* Constant values for assembler. */ |
| 31 | enum |
| 32 | { |
| 33 | /* Error code for assembling an instruction. */ |
| 34 | NASM_OK = 0, |
| 35 | NASM_ERR_UNKNOWN_OP, |
| 36 | NASM_ERR_SYNTAX, |
| 37 | NASM_ERR_OPERAND, |
| 38 | NASM_ERR_OUT_OF_RANGE, |
| 39 | NASM_ERR_REG_REDUCED, |
| 40 | NASM_ERR_JUNK_EOL, |
| 41 | |
| 42 | /* Results of parse_operand. */ |
| 43 | NASM_R_CONST, |
| 44 | NASM_R_SYMBOL, |
| 45 | NASM_R_ILLEGAL, |
| 46 | |
| 47 | /* Flags for open description. */ |
| 48 | NASM_OPEN_ARCH_V1 = 0x0, |
| 49 | NASM_OPEN_ARCH_V2 = 0x1, |
| 50 | NASM_OPEN_ARCH_V3 = 0x2, |
| 51 | NASM_OPEN_ARCH_V3M = 0x3, |
| 52 | NASM_OPEN_ARCH_MASK = 0xf, |
| 53 | NASM_OPEN_REDUCED_REG = 0x10, |
| 54 | |
| 55 | /* Common attributes. */ |
| 56 | NASM_ATTR_ISA_V1 = 0x01, |
| 57 | NASM_ATTR_ISA_V2 = 0x02, |
| 58 | NASM_ATTR_ISA_V3 = 0x04, |
| 59 | NASM_ATTR_ISA_V3M = 0x08, |
| 60 | NASM_ATTR_ISA_ALL = 0x0f, |
| 61 | |
| 62 | /* Attributes for instructions. */ |
| 63 | NASM_ATTR_MAC = 0x0000100, |
| 64 | NASM_ATTR_DIV = 0x0000200, |
| 65 | NASM_ATTR_FPU = 0x0000400, |
| 66 | NASM_ATTR_FPU_SP_EXT = 0x0000800, |
| 67 | NASM_ATTR_FPU_DP_EXT = 0x0001000, |
| 68 | NASM_ATTR_STR_EXT = 0x0002000, |
| 69 | NASM_ATTR_PERF_EXT = 0x0004000, |
| 70 | NASM_ATTR_PERF2_EXT = 0x0008000, |
| 71 | NASM_ATTR_AUDIO_ISAEXT = 0x0010000, |
| 72 | NASM_ATTR_IFC_EXT = 0x0020000, |
| 73 | NASM_ATTR_EX9_EXT = 0x0040000, |
| 74 | NASM_ATTR_FPU_FMA = 0x0080000, |
| 75 | NASM_ATTR_DXREG = 0x0100000, |
| 76 | NASM_ATTR_BRANCH = 0x0200000, |
| 77 | NASM_ATTR_SATURATION_EXT = 0x0400000, |
| 78 | NASM_ATTR_PCREL = 0x0800000, |
| 79 | NASM_ATTR_GPREL = 0x1000000, |
| 80 | |
| 81 | /* Attributes for relocations. */ |
| 82 | NASM_ATTR_HI20 = 0x10000000, |
| 83 | NASM_ATTR_LO12 = 0x20000000, |
| 84 | NASM_ATTR_LO20 = 0x40000000, |
| 85 | |
| 86 | /* Attributes for registers. */ |
| 87 | NASM_ATTR_RDREG = 0x000100 |
| 88 | }; |
| 89 | |
| 90 | enum |
| 91 | { |
| 92 | /* This is a field (operand) of just a separator char. */ |
| 93 | SYN_FIELD = 0x100, |
| 94 | |
| 95 | /* This operand is used for input or output. (define or use) */ |
| 96 | SYN_INPUT = 0x1000, |
| 97 | SYN_OUTPUT = 0x2000, |
| 98 | SYN_LOPT = 0x4000, |
| 99 | SYN_ROPT = 0x8000, |
| 100 | |
| 101 | /* Hardware resources. */ |
| 102 | HW_GPR = 0, |
| 103 | HW_USR, |
| 104 | HW_DXR, |
| 105 | HW_SR, |
| 106 | HW_FSR, |
| 107 | HW_FDR, |
| 108 | HW_CP, /* Co-processor ID. */ |
| 109 | HW_CPR, /* Co-processor registers. */ |
| 110 | HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */ |
| 111 | HW_ABM, /* [ab]m? flag for LSMWZB. */ |
| 112 | HW_DTITON, |
| 113 | HW_DTITOFF, |
| 114 | HW_DPREF_ST, |
| 115 | HW_CCTL_ST0, |
| 116 | HW_CCTL_ST1, |
| 117 | HW_CCTL_ST2, |
| 118 | HW_CCTL_ST3, |
| 119 | HW_CCTL_ST4, |
| 120 | HW_CCTL_ST5, |
| 121 | HW_CCTL_LV, |
| 122 | HW_TLBOP_ST, |
| 123 | HW_STANDBY_ST, |
| 124 | HW_MSYNC_ST, |
| 125 | HW_AEXT_IM_I, |
| 126 | HW_AEXT_IM_M, |
| 127 | HW_AEXT_ACC, |
| 128 | HW_AEXT_ARIDX, |
| 129 | HW_AEXT_ARIDX2, |
| 130 | HW_AEXT_ARIDXI, |
| 131 | _HW_LAST, |
| 132 | /* TODO: Maybe we should add a new type to distinguish address and |
| 133 | const int. Only the former allows symbols and relocations. */ |
| 134 | HW_INT, |
| 135 | HW_UINT |
| 136 | }; |
| 137 | |
| 138 | /* for audio-extension. */ |
| 139 | enum |
| 140 | { |
| 141 | N32_AEXT_AMADD = 0, |
| 142 | N32_AEXT_AMSUB, |
| 143 | N32_AEXT_AMULT, |
| 144 | N32_AEXT_AMFAR, |
| 145 | N32_AEXT_AMADDS, |
| 146 | N32_AEXT_AMSUBS, |
| 147 | N32_AEXT_AMULTS, |
| 148 | N32_AEXT_AMNEGS, |
| 149 | N32_AEXT_AADDL, |
| 150 | N32_AEXT_AMTARI, |
| 151 | N32_AEXT_AMAWBS = 0x0c, |
| 152 | N32_AEXT_AMAWTS, |
| 153 | N32_AEXT_AMWBS, |
| 154 | N32_AEXT_AMWTS, |
| 155 | N32_AEXT_AMABBS, |
| 156 | N32_AEXT_AMABTS, |
| 157 | N32_AEXT_AMATBS, |
| 158 | N32_AEXT_AMATTS, |
| 159 | N32_AEXT_AMBBS, |
| 160 | N32_AEXT_AMBTS, |
| 161 | N32_AEXT_AMTBS, |
| 162 | N32_AEXT_AMTTS |
| 163 | }; |
| 164 | |
| 165 | /* Macro for instruction attribute. */ |
| 166 | #define ATTR(attr) NASM_ATTR_ ## attr |
| 167 | #define ATTR_NONE 0 |
| 168 | #define ATTR_PCREL (ATTR (PCREL) | ATTR (BRANCH)) |
| 169 | |
| 170 | #define ATTR_ALL (ATTR (ISA_ALL)) |
| 171 | #define ATTR_V2UP (ATTR_ALL & ~(ATTR (ISA_V1))) |
| 172 | #define ATTR_V3MUP (ATTR (ISA_V3) | ATTR (ISA_V3M)) |
| 173 | #define ATTR_V3 (ATTR (ISA_V3)) |
| 174 | #define ATTR_V3MEX_V1 (ATTR_ALL & ~(ATTR (ISA_V3M))) |
| 175 | #define ATTR_V3MEX_V2 (ATTR_V2UP & ~(ATTR (ISA_V3M))) |
| 176 | |
| 177 | /* Lexical element in parsed syntax. */ |
| 178 | typedef int lex_t; |
| 179 | |
| 180 | /* Common header for hash entries. */ |
| 181 | struct nds32_hash_entry |
| 182 | { |
| 183 | const char *name; |
| 184 | }; |
| 185 | |
| 186 | typedef struct nds32_keyword |
| 187 | { |
| 188 | const char *name; |
| 189 | int value; |
| 190 | uint64_t attr; |
| 191 | } keyword_t; |
| 192 | |
| 193 | typedef struct nds32_opcode |
| 194 | { |
| 195 | /* Opcode for the instruction. */ |
| 196 | const char *opcode; |
| 197 | /* Human readable string of this instruction. */ |
| 198 | const char *instruction; |
| 199 | /* Base value of this instruction. */ |
| 200 | uint32_t value; |
| 201 | /* The byte-size of the instruction. */ |
| 202 | int isize; |
| 203 | /* Attributes of this instruction. */ |
| 204 | uint64_t attr; |
| 205 | /* Implicit define/use. */ |
| 206 | uint64_t defuse; |
| 207 | /* Parsed string for assembling. */ |
| 208 | lex_t *syntax; |
| 209 | /* Number of variant. */ |
| 210 | int variant; |
| 211 | /* Next form of the same mnemonic. */ |
| 212 | struct nds32_opcode *next; |
| 213 | |
| 214 | /* TODO: Extra constrains and verification. |
| 215 | For example, `mov55 $sp, $sp' is not allowed in v3. */ |
| 216 | } opcode_t; |
| 217 | |
| 218 | typedef struct nds32_asm_insn |
| 219 | { |
| 220 | /* Assembled instruction bytes. */ |
| 221 | uint32_t insn; |
| 222 | /* The opcode structure for this instruction. */ |
| 223 | struct nds32_opcode *opcode; |
| 224 | /* The field need special fix-up, used for relocation. */ |
| 225 | const struct nds32_field *field; |
| 226 | /* Attributes for relocation. */ |
| 227 | uint64_t attr; |
| 228 | /* Application-dependent data, e.g., expression. */ |
| 229 | void *info; |
| 230 | /* Input/output registers. */ |
| 231 | uint64_t defuse; |
| 232 | } nds32_asm_insn_t; |
| 233 | |
| 234 | typedef struct nds32_asm_desc |
| 235 | { |
| 236 | /* The callback provided by assembler user for parse an operand, |
| 237 | e.g., parse integer. */ |
| 238 | int (*parse_operand) (struct nds32_asm_desc *, |
| 239 | struct nds32_asm_insn *, |
| 240 | char **, int64_t *); |
| 241 | |
| 242 | /* Result of assembling. */ |
| 243 | int result; |
| 244 | |
| 245 | /* The mach for this assembling. */ |
| 246 | int mach; |
| 247 | |
| 248 | int flags; |
| 249 | } nds32_asm_desc_t; |
| 250 | |
| 251 | /* The field information for an operand. */ |
| 252 | typedef struct nds32_field |
| 253 | { |
| 254 | /* Name of the field. */ |
| 255 | const char *name; |
| 256 | |
| 257 | int bitpos; |
| 258 | int bitsize; |
| 259 | int shift; |
| 260 | int hw_res; |
| 261 | |
| 262 | int (*parse) (struct nds32_asm_desc *, |
| 263 | struct nds32_asm_insn *, |
| 264 | char **, int64_t *); |
| 265 | } field_t; |
| 266 | |
| 267 | extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *); |
| 268 | extern void nds32_asm_init (nds32_asm_desc_t *, int); |
| 269 | |
| 270 | #define OP6(op6) (N32_OP6_ ## op6 << 25) |
| 271 | |
| 272 | #define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub) |
| 273 | #define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub) |
| 274 | #define JREG_RET (1 << 5) |
| 275 | #define JREG_IFC (1 << 6) |
| 276 | #define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16)) |
| 277 | #define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub) |
| 278 | #define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub) |
| 279 | #define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub) |
| 280 | #define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub) |
| 281 | #define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub) |
| 282 | #define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12)) |
| 283 | #define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6)) |
| 284 | #define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \ |
| 285 | | (N32_FPU_FS1_F2OP_ ## sub << 10)) |
| 286 | #define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6)) |
| 287 | #define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6)) |
| 288 | #define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \ |
| 289 | | (N32_FPU_FD1_F2OP_ ## sub << 10)) |
| 290 | #define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6)) |
| 291 | #define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6)) |
| 292 | #define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \ |
| 293 | | (N32_FPU_MFCP_XR_ ## sub << 10)) |
| 294 | #define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6)) |
| 295 | #define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \ |
| 296 | | (N32_FPU_MTCP_XR_ ## sub << 10)) |
| 297 | #define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub) |
| 298 | #define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7) |
| 299 | #define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20)) |
| 300 | |
| 301 | #ifdef __cplusplus |
| 302 | } |
| 303 | #endif |
| 304 | |
| 305 | #endif |