| 1 | /* Altera Nios II disassemble routines |
| 2 | Copyright (C) 2012-2019 Free Software Foundation, Inc. |
| 3 | Contributed by Nigel Gray (ngray@altera.com). |
| 4 | Contributed by Mentor Graphics, Inc. |
| 5 | |
| 6 | This file is part of the GNU opcodes library. |
| 7 | |
| 8 | This library is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3, or (at your option) |
| 11 | any later version. |
| 12 | |
| 13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 16 | License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this file; see the file COPYING. If not, write to the |
| 20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 21 | MA 02110-1301, USA. */ |
| 22 | |
| 23 | #include "sysdep.h" |
| 24 | #include "disassemble.h" |
| 25 | #include "opintl.h" |
| 26 | #include "opcode/nios2.h" |
| 27 | #include "libiberty.h" |
| 28 | #include <string.h> |
| 29 | #include <assert.h> |
| 30 | |
| 31 | /* No symbol table is available when this code runs out in an embedded |
| 32 | system as when it is used for disassembler support in a monitor. */ |
| 33 | #if !defined(EMBEDDED_ENV) |
| 34 | #define SYMTAB_AVAILABLE 1 |
| 35 | #include "elf-bfd.h" |
| 36 | #include "elf/nios2.h" |
| 37 | #endif |
| 38 | |
| 39 | /* Default length of Nios II instruction in bytes. */ |
| 40 | #define INSNLEN 4 |
| 41 | |
| 42 | /* Data structures used by the opcode hash table. */ |
| 43 | typedef struct _nios2_opcode_hash |
| 44 | { |
| 45 | const struct nios2_opcode *opcode; |
| 46 | struct _nios2_opcode_hash *next; |
| 47 | } nios2_opcode_hash; |
| 48 | |
| 49 | /* Hash table size. */ |
| 50 | #define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1) |
| 51 | |
| 52 | /* Extract the opcode from an instruction word. */ |
| 53 | static unsigned int |
| 54 | nios2_r1_extract_opcode (unsigned int x) |
| 55 | { |
| 56 | return GET_IW_R1_OP (x); |
| 57 | } |
| 58 | |
| 59 | static unsigned int |
| 60 | nios2_r2_extract_opcode (unsigned int x) |
| 61 | { |
| 62 | return GET_IW_R2_OP (x); |
| 63 | } |
| 64 | |
| 65 | /* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops |
| 66 | are stored in a different table than regular instructions. */ |
| 67 | |
| 68 | typedef struct _nios2_disassembler_state |
| 69 | { |
| 70 | const struct nios2_opcode *opcodes; |
| 71 | const int *num_opcodes; |
| 72 | unsigned int (*extract_opcode) (unsigned int); |
| 73 | nios2_opcode_hash *hash[OPCODE_HASH_SIZE]; |
| 74 | nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE]; |
| 75 | const struct nios2_opcode *nop; |
| 76 | bfd_boolean init; |
| 77 | } nios2_disassembler_state; |
| 78 | |
| 79 | static nios2_disassembler_state |
| 80 | nios2_r1_disassembler_state = { |
| 81 | nios2_r1_opcodes, |
| 82 | &nios2_num_r1_opcodes, |
| 83 | nios2_r1_extract_opcode, |
| 84 | {}, |
| 85 | {}, |
| 86 | NULL, |
| 87 | 0 |
| 88 | }; |
| 89 | |
| 90 | static nios2_disassembler_state |
| 91 | nios2_r2_disassembler_state = { |
| 92 | nios2_r2_opcodes, |
| 93 | &nios2_num_r2_opcodes, |
| 94 | nios2_r2_extract_opcode, |
| 95 | {}, |
| 96 | {}, |
| 97 | NULL, |
| 98 | 0 |
| 99 | }; |
| 100 | |
| 101 | /* Function to initialize the opcode hash table. */ |
| 102 | static void |
| 103 | nios2_init_opcode_hash (nios2_disassembler_state *state) |
| 104 | { |
| 105 | unsigned int i; |
| 106 | register const struct nios2_opcode *op; |
| 107 | |
| 108 | for (i = 0; i < OPCODE_HASH_SIZE; i++) |
| 109 | for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++) |
| 110 | { |
| 111 | nios2_opcode_hash *new_hash; |
| 112 | nios2_opcode_hash **bucket = NULL; |
| 113 | |
| 114 | if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO) |
| 115 | { |
| 116 | if (i == state->extract_opcode (op->match) |
| 117 | && (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI) |
| 118 | & 0x7fffffff)) |
| 119 | { |
| 120 | bucket = &(state->ps_hash[i]); |
| 121 | if (strcmp (op->name, "nop") == 0) |
| 122 | state->nop = op; |
| 123 | } |
| 124 | } |
| 125 | else if (i == state->extract_opcode (op->match)) |
| 126 | bucket = &(state->hash[i]); |
| 127 | |
| 128 | if (bucket) |
| 129 | { |
| 130 | new_hash = |
| 131 | (nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash)); |
| 132 | if (new_hash == NULL) |
| 133 | { |
| 134 | /* xgettext:c-format */ |
| 135 | opcodes_error_handler (_("out of memory")); |
| 136 | exit (1); |
| 137 | } |
| 138 | new_hash->opcode = op; |
| 139 | new_hash->next = NULL; |
| 140 | while (*bucket) |
| 141 | bucket = &((*bucket)->next); |
| 142 | *bucket = new_hash; |
| 143 | } |
| 144 | } |
| 145 | state->init = 1; |
| 146 | |
| 147 | #ifdef DEBUG_HASHTABLE |
| 148 | for (i = 0; i < OPCODE_HASH_SIZE; ++i) |
| 149 | { |
| 150 | nios2_opcode_hash *tmp_hash = state->hash[i]; |
| 151 | printf ("index: 0x%02X ops: ", i); |
| 152 | while (tmp_hash != NULL) |
| 153 | { |
| 154 | printf ("%s ", tmp_hash->opcode->name); |
| 155 | tmp_hash = tmp_hash->next; |
| 156 | } |
| 157 | printf ("\n"); |
| 158 | } |
| 159 | |
| 160 | for (i = 0; i < OPCODE_HASH_SIZE; ++i) |
| 161 | { |
| 162 | nios2_opcode_hash *tmp_hash = state->ps_hash[i]; |
| 163 | printf ("index: 0x%02X ops: ", i); |
| 164 | while (tmp_hash != NULL) |
| 165 | { |
| 166 | printf ("%s ", tmp_hash->opcode->name); |
| 167 | tmp_hash = tmp_hash->next; |
| 168 | } |
| 169 | printf ("\n"); |
| 170 | } |
| 171 | #endif /* DEBUG_HASHTABLE */ |
| 172 | } |
| 173 | |
| 174 | /* Return a pointer to an nios2_opcode struct for a given instruction |
| 175 | word OPCODE for bfd machine MACH, or NULL if there is an error. */ |
| 176 | const struct nios2_opcode * |
| 177 | nios2_find_opcode_hash (unsigned long opcode, unsigned long mach) |
| 178 | { |
| 179 | nios2_opcode_hash *entry; |
| 180 | nios2_disassembler_state *state; |
| 181 | |
| 182 | /* Select the right instruction set, hash tables, and opcode accessor |
| 183 | for the mach variant. */ |
| 184 | if (mach == bfd_mach_nios2r2) |
| 185 | state = &nios2_r2_disassembler_state; |
| 186 | else |
| 187 | state = &nios2_r1_disassembler_state; |
| 188 | |
| 189 | /* Build a hash table to shorten the search time. */ |
| 190 | if (!state->init) |
| 191 | nios2_init_opcode_hash (state); |
| 192 | |
| 193 | /* Check for NOP first. Both NOP and MOV are macros that expand into |
| 194 | an ADD instruction, and we always want to give priority to NOP. */ |
| 195 | if (state->nop->match == (opcode & state->nop->mask)) |
| 196 | return state->nop; |
| 197 | |
| 198 | /* First look in the pseudo-op hashtable. */ |
| 199 | for (entry = state->ps_hash[state->extract_opcode (opcode)]; |
| 200 | entry; entry = entry->next) |
| 201 | if (entry->opcode->match == (opcode & entry->opcode->mask)) |
| 202 | return entry->opcode; |
| 203 | |
| 204 | /* Otherwise look in the main hashtable. */ |
| 205 | for (entry = state->hash[state->extract_opcode (opcode)]; |
| 206 | entry; entry = entry->next) |
| 207 | if (entry->opcode->match == (opcode & entry->opcode->mask)) |
| 208 | return entry->opcode; |
| 209 | |
| 210 | return NULL; |
| 211 | } |
| 212 | |
| 213 | /* There are 32 regular registers, 32 coprocessor registers, |
| 214 | and 32 control registers. */ |
| 215 | #define NUMREGNAMES 32 |
| 216 | |
| 217 | /* Return a pointer to the base of the coprocessor register name array. */ |
| 218 | static struct nios2_reg * |
| 219 | nios2_coprocessor_regs (void) |
| 220 | { |
| 221 | static struct nios2_reg *cached = NULL; |
| 222 | |
| 223 | if (!cached) |
| 224 | { |
| 225 | int i; |
| 226 | for (i = NUMREGNAMES; i < nios2_num_regs; i++) |
| 227 | if (!strcmp (nios2_regs[i].name, "c0")) |
| 228 | { |
| 229 | cached = nios2_regs + i; |
| 230 | break; |
| 231 | } |
| 232 | assert (cached); |
| 233 | } |
| 234 | return cached; |
| 235 | } |
| 236 | |
| 237 | /* Return a pointer to the base of the control register name array. */ |
| 238 | static struct nios2_reg * |
| 239 | nios2_control_regs (void) |
| 240 | { |
| 241 | static struct nios2_reg *cached = NULL; |
| 242 | |
| 243 | if (!cached) |
| 244 | { |
| 245 | int i; |
| 246 | for (i = NUMREGNAMES; i < nios2_num_regs; i++) |
| 247 | if (!strcmp (nios2_regs[i].name, "status")) |
| 248 | { |
| 249 | cached = nios2_regs + i; |
| 250 | break; |
| 251 | } |
| 252 | assert (cached); |
| 253 | } |
| 254 | return cached; |
| 255 | } |
| 256 | |
| 257 | /* Helper routine to report internal errors. */ |
| 258 | static void |
| 259 | bad_opcode (const struct nios2_opcode *op) |
| 260 | { |
| 261 | opcodes_error_handler |
| 262 | /* xgettext:c-format */ |
| 263 | (_("internal error: broken opcode descriptor for `%s %s'"), |
| 264 | op->name, op->args); |
| 265 | abort (); |
| 266 | } |
| 267 | |
| 268 | /* The function nios2_print_insn_arg uses the character pointed |
| 269 | to by ARGPTR to determine how it print the next token or separator |
| 270 | character in the arguments to an instruction. */ |
| 271 | static int |
| 272 | nios2_print_insn_arg (const char *argptr, |
| 273 | unsigned long opcode, bfd_vma address, |
| 274 | disassemble_info *info, |
| 275 | const struct nios2_opcode *op) |
| 276 | { |
| 277 | unsigned long i = 0; |
| 278 | long s = 0; |
| 279 | bfd_signed_vma o = 0; |
| 280 | struct nios2_reg *reg_base; |
| 281 | |
| 282 | switch (*argptr) |
| 283 | { |
| 284 | case ',': |
| 285 | case '(': |
| 286 | case ')': |
| 287 | (*info->fprintf_func) (info->stream, "%c", *argptr); |
| 288 | break; |
| 289 | |
| 290 | case 'c': |
| 291 | /* Control register index. */ |
| 292 | switch (op->format) |
| 293 | { |
| 294 | case iw_r_type: |
| 295 | i = GET_IW_R_IMM5 (opcode); |
| 296 | break; |
| 297 | case iw_F3X6L5_type: |
| 298 | i = GET_IW_F3X6L5_IMM5 (opcode); |
| 299 | break; |
| 300 | default: |
| 301 | bad_opcode (op); |
| 302 | } |
| 303 | reg_base = nios2_control_regs (); |
| 304 | (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); |
| 305 | break; |
| 306 | |
| 307 | case 'd': |
| 308 | reg_base = nios2_regs; |
| 309 | switch (op->format) |
| 310 | { |
| 311 | case iw_r_type: |
| 312 | i = GET_IW_R_C (opcode); |
| 313 | break; |
| 314 | case iw_custom_type: |
| 315 | i = GET_IW_CUSTOM_C (opcode); |
| 316 | if (GET_IW_CUSTOM_READC (opcode) == 0) |
| 317 | reg_base = nios2_coprocessor_regs (); |
| 318 | break; |
| 319 | case iw_F3X6L5_type: |
| 320 | case iw_F3X6_type: |
| 321 | i = GET_IW_F3X6L5_C (opcode); |
| 322 | break; |
| 323 | case iw_F3X8_type: |
| 324 | i = GET_IW_F3X8_C (opcode); |
| 325 | if (GET_IW_F3X8_READC (opcode) == 0) |
| 326 | reg_base = nios2_coprocessor_regs (); |
| 327 | break; |
| 328 | case iw_F2_type: |
| 329 | i = GET_IW_F2_B (opcode); |
| 330 | break; |
| 331 | default: |
| 332 | bad_opcode (op); |
| 333 | } |
| 334 | if (i < NUMREGNAMES) |
| 335 | (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); |
| 336 | else |
| 337 | (*info->fprintf_func) (info->stream, "unknown"); |
| 338 | break; |
| 339 | |
| 340 | case 's': |
| 341 | reg_base = nios2_regs; |
| 342 | switch (op->format) |
| 343 | { |
| 344 | case iw_r_type: |
| 345 | i = GET_IW_R_A (opcode); |
| 346 | break; |
| 347 | case iw_i_type: |
| 348 | i = GET_IW_I_A (opcode); |
| 349 | break; |
| 350 | case iw_custom_type: |
| 351 | i = GET_IW_CUSTOM_A (opcode); |
| 352 | if (GET_IW_CUSTOM_READA (opcode) == 0) |
| 353 | reg_base = nios2_coprocessor_regs (); |
| 354 | break; |
| 355 | case iw_F2I16_type: |
| 356 | i = GET_IW_F2I16_A (opcode); |
| 357 | break; |
| 358 | case iw_F2X4I12_type: |
| 359 | i = GET_IW_F2X4I12_A (opcode); |
| 360 | break; |
| 361 | case iw_F1X4I12_type: |
| 362 | i = GET_IW_F1X4I12_A (opcode); |
| 363 | break; |
| 364 | case iw_F1X4L17_type: |
| 365 | i = GET_IW_F1X4L17_A (opcode); |
| 366 | break; |
| 367 | case iw_F3X6L5_type: |
| 368 | case iw_F3X6_type: |
| 369 | i = GET_IW_F3X6L5_A (opcode); |
| 370 | break; |
| 371 | case iw_F2X6L10_type: |
| 372 | i = GET_IW_F2X6L10_A (opcode); |
| 373 | break; |
| 374 | case iw_F3X8_type: |
| 375 | i = GET_IW_F3X8_A (opcode); |
| 376 | if (GET_IW_F3X8_READA (opcode) == 0) |
| 377 | reg_base = nios2_coprocessor_regs (); |
| 378 | break; |
| 379 | case iw_F1X1_type: |
| 380 | i = GET_IW_F1X1_A (opcode); |
| 381 | break; |
| 382 | case iw_F1I5_type: |
| 383 | i = 27; /* Implicit stack pointer reference. */ |
| 384 | break; |
| 385 | case iw_F2_type: |
| 386 | i = GET_IW_F2_A (opcode); |
| 387 | break; |
| 388 | default: |
| 389 | bad_opcode (op); |
| 390 | } |
| 391 | if (i < NUMREGNAMES) |
| 392 | (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); |
| 393 | else |
| 394 | (*info->fprintf_func) (info->stream, "unknown"); |
| 395 | break; |
| 396 | |
| 397 | case 't': |
| 398 | reg_base = nios2_regs; |
| 399 | switch (op->format) |
| 400 | { |
| 401 | case iw_r_type: |
| 402 | i = GET_IW_R_B (opcode); |
| 403 | break; |
| 404 | case iw_i_type: |
| 405 | i = GET_IW_I_B (opcode); |
| 406 | break; |
| 407 | case iw_custom_type: |
| 408 | i = GET_IW_CUSTOM_B (opcode); |
| 409 | if (GET_IW_CUSTOM_READB (opcode) == 0) |
| 410 | reg_base = nios2_coprocessor_regs (); |
| 411 | break; |
| 412 | case iw_F2I16_type: |
| 413 | i = GET_IW_F2I16_B (opcode); |
| 414 | break; |
| 415 | case iw_F2X4I12_type: |
| 416 | i = GET_IW_F2X4I12_B (opcode); |
| 417 | break; |
| 418 | case iw_F3X6L5_type: |
| 419 | case iw_F3X6_type: |
| 420 | i = GET_IW_F3X6L5_B (opcode); |
| 421 | break; |
| 422 | case iw_F2X6L10_type: |
| 423 | i = GET_IW_F2X6L10_B (opcode); |
| 424 | break; |
| 425 | case iw_F3X8_type: |
| 426 | i = GET_IW_F3X8_B (opcode); |
| 427 | if (GET_IW_F3X8_READB (opcode) == 0) |
| 428 | reg_base = nios2_coprocessor_regs (); |
| 429 | break; |
| 430 | case iw_F1I5_type: |
| 431 | i = GET_IW_F1I5_B (opcode); |
| 432 | break; |
| 433 | case iw_F2_type: |
| 434 | i = GET_IW_F2_B (opcode); |
| 435 | break; |
| 436 | case iw_T1X1I6_type: |
| 437 | i = 0; |
| 438 | break; |
| 439 | default: |
| 440 | bad_opcode (op); |
| 441 | } |
| 442 | if (i < NUMREGNAMES) |
| 443 | (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); |
| 444 | else |
| 445 | (*info->fprintf_func) (info->stream, "unknown"); |
| 446 | break; |
| 447 | |
| 448 | case 'D': |
| 449 | switch (op->format) |
| 450 | { |
| 451 | case iw_T1I7_type: |
| 452 | i = GET_IW_T1I7_A3 (opcode); |
| 453 | break; |
| 454 | case iw_T2X1L3_type: |
| 455 | i = GET_IW_T2X1L3_B3 (opcode); |
| 456 | break; |
| 457 | case iw_T2X1I3_type: |
| 458 | i = GET_IW_T2X1I3_B3 (opcode); |
| 459 | break; |
| 460 | case iw_T3X1_type: |
| 461 | i = GET_IW_T3X1_C3 (opcode); |
| 462 | break; |
| 463 | case iw_T2X3_type: |
| 464 | if (op->num_args == 3) |
| 465 | i = GET_IW_T2X3_A3 (opcode); |
| 466 | else |
| 467 | i = GET_IW_T2X3_B3 (opcode); |
| 468 | break; |
| 469 | default: |
| 470 | bad_opcode (op); |
| 471 | } |
| 472 | i = nios2_r2_reg3_mappings[i]; |
| 473 | (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name); |
| 474 | break; |
| 475 | |
| 476 | case 'M': |
| 477 | /* 6-bit unsigned immediate with no shift. */ |
| 478 | switch (op->format) |
| 479 | { |
| 480 | case iw_T1X1I6_type: |
| 481 | i = GET_IW_T1X1I6_IMM6 (opcode); |
| 482 | break; |
| 483 | default: |
| 484 | bad_opcode (op); |
| 485 | } |
| 486 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 487 | break; |
| 488 | |
| 489 | case 'N': |
| 490 | /* 6-bit unsigned immediate with 2-bit shift. */ |
| 491 | switch (op->format) |
| 492 | { |
| 493 | case iw_T1X1I6_type: |
| 494 | i = GET_IW_T1X1I6_IMM6 (opcode) << 2; |
| 495 | break; |
| 496 | default: |
| 497 | bad_opcode (op); |
| 498 | } |
| 499 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 500 | break; |
| 501 | |
| 502 | case 'S': |
| 503 | switch (op->format) |
| 504 | { |
| 505 | case iw_T1I7_type: |
| 506 | i = GET_IW_T1I7_A3 (opcode); |
| 507 | break; |
| 508 | case iw_T2I4_type: |
| 509 | i = GET_IW_T2I4_A3 (opcode); |
| 510 | break; |
| 511 | case iw_T2X1L3_type: |
| 512 | i = GET_IW_T2X1L3_A3 (opcode); |
| 513 | break; |
| 514 | case iw_T2X1I3_type: |
| 515 | i = GET_IW_T2X1I3_A3 (opcode); |
| 516 | break; |
| 517 | case iw_T3X1_type: |
| 518 | i = GET_IW_T3X1_A3 (opcode); |
| 519 | break; |
| 520 | case iw_T2X3_type: |
| 521 | i = GET_IW_T2X3_A3 (opcode); |
| 522 | break; |
| 523 | case iw_T1X1I6_type: |
| 524 | i = GET_IW_T1X1I6_A3 (opcode); |
| 525 | break; |
| 526 | default: |
| 527 | bad_opcode (op); |
| 528 | } |
| 529 | i = nios2_r2_reg3_mappings[i]; |
| 530 | (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name); |
| 531 | break; |
| 532 | |
| 533 | case 'T': |
| 534 | switch (op->format) |
| 535 | { |
| 536 | case iw_T2I4_type: |
| 537 | i = GET_IW_T2I4_B3 (opcode); |
| 538 | break; |
| 539 | case iw_T3X1_type: |
| 540 | i = GET_IW_T3X1_B3 (opcode); |
| 541 | break; |
| 542 | case iw_T2X3_type: |
| 543 | i = GET_IW_T2X3_B3 (opcode); |
| 544 | break; |
| 545 | default: |
| 546 | bad_opcode (op); |
| 547 | } |
| 548 | i = nios2_r2_reg3_mappings[i]; |
| 549 | (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name); |
| 550 | break; |
| 551 | |
| 552 | case 'i': |
| 553 | /* 16-bit signed immediate. */ |
| 554 | switch (op->format) |
| 555 | { |
| 556 | case iw_i_type: |
| 557 | s = (int32_t) (GET_IW_I_IMM16 (opcode) << 16) >> 16; |
| 558 | break; |
| 559 | case iw_F2I16_type: |
| 560 | s = (int32_t) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16; |
| 561 | break; |
| 562 | default: |
| 563 | bad_opcode (op); |
| 564 | } |
| 565 | (*info->fprintf_func) (info->stream, "%ld", s); |
| 566 | break; |
| 567 | |
| 568 | case 'I': |
| 569 | /* 12-bit signed immediate. */ |
| 570 | switch (op->format) |
| 571 | { |
| 572 | case iw_F2X4I12_type: |
| 573 | s = (int32_t) (GET_IW_F2X4I12_IMM12 (opcode) << 20) >> 20; |
| 574 | break; |
| 575 | case iw_F1X4I12_type: |
| 576 | s = (int32_t) (GET_IW_F1X4I12_IMM12 (opcode) << 20) >> 20; |
| 577 | break; |
| 578 | default: |
| 579 | bad_opcode (op); |
| 580 | } |
| 581 | (*info->fprintf_func) (info->stream, "%ld", s); |
| 582 | break; |
| 583 | |
| 584 | case 'u': |
| 585 | /* 16-bit unsigned immediate. */ |
| 586 | switch (op->format) |
| 587 | { |
| 588 | case iw_i_type: |
| 589 | i = GET_IW_I_IMM16 (opcode); |
| 590 | break; |
| 591 | case iw_F2I16_type: |
| 592 | i = GET_IW_F2I16_IMM16 (opcode); |
| 593 | break; |
| 594 | default: |
| 595 | bad_opcode (op); |
| 596 | } |
| 597 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 598 | break; |
| 599 | |
| 600 | case 'U': |
| 601 | /* 7-bit unsigned immediate with 2-bit shift. */ |
| 602 | switch (op->format) |
| 603 | { |
| 604 | case iw_T1I7_type: |
| 605 | i = GET_IW_T1I7_IMM7 (opcode) << 2; |
| 606 | break; |
| 607 | case iw_X1I7_type: |
| 608 | i = GET_IW_X1I7_IMM7 (opcode) << 2; |
| 609 | break; |
| 610 | default: |
| 611 | bad_opcode (op); |
| 612 | } |
| 613 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 614 | break; |
| 615 | |
| 616 | case 'V': |
| 617 | /* 5-bit unsigned immediate with 2-bit shift. */ |
| 618 | switch (op->format) |
| 619 | { |
| 620 | case iw_F1I5_type: |
| 621 | i = GET_IW_F1I5_IMM5 (opcode) << 2; |
| 622 | break; |
| 623 | default: |
| 624 | bad_opcode (op); |
| 625 | } |
| 626 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 627 | break; |
| 628 | |
| 629 | case 'W': |
| 630 | /* 4-bit unsigned immediate with 2-bit shift. */ |
| 631 | switch (op->format) |
| 632 | { |
| 633 | case iw_T2I4_type: |
| 634 | i = GET_IW_T2I4_IMM4 (opcode) << 2; |
| 635 | break; |
| 636 | case iw_L5I4X1_type: |
| 637 | i = GET_IW_L5I4X1_IMM4 (opcode) << 2; |
| 638 | break; |
| 639 | default: |
| 640 | bad_opcode (op); |
| 641 | } |
| 642 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 643 | break; |
| 644 | |
| 645 | case 'X': |
| 646 | /* 4-bit unsigned immediate with 1-bit shift. */ |
| 647 | switch (op->format) |
| 648 | { |
| 649 | case iw_T2I4_type: |
| 650 | i = GET_IW_T2I4_IMM4 (opcode) << 1; |
| 651 | break; |
| 652 | default: |
| 653 | bad_opcode (op); |
| 654 | } |
| 655 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 656 | break; |
| 657 | |
| 658 | case 'Y': |
| 659 | /* 4-bit unsigned immediate without shift. */ |
| 660 | switch (op->format) |
| 661 | { |
| 662 | case iw_T2I4_type: |
| 663 | i = GET_IW_T2I4_IMM4 (opcode); |
| 664 | break; |
| 665 | default: |
| 666 | bad_opcode (op); |
| 667 | } |
| 668 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 669 | break; |
| 670 | |
| 671 | case 'o': |
| 672 | /* 16-bit signed immediate address offset. */ |
| 673 | switch (op->format) |
| 674 | { |
| 675 | case iw_i_type: |
| 676 | o = (int32_t) (GET_IW_I_IMM16 (opcode) << 16) >> 16; |
| 677 | break; |
| 678 | case iw_F2I16_type: |
| 679 | o = (int32_t) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16; |
| 680 | break; |
| 681 | default: |
| 682 | bad_opcode (op); |
| 683 | } |
| 684 | address = address + 4 + o; |
| 685 | (*info->print_address_func) (address, info); |
| 686 | break; |
| 687 | |
| 688 | case 'O': |
| 689 | /* 10-bit signed address offset with 1-bit shift. */ |
| 690 | switch (op->format) |
| 691 | { |
| 692 | case iw_I10_type: |
| 693 | o = (int32_t) (GET_IW_I10_IMM10 (opcode) << 22) >> 21; |
| 694 | break; |
| 695 | default: |
| 696 | bad_opcode (op); |
| 697 | } |
| 698 | address = address + 2 + o; |
| 699 | (*info->print_address_func) (address, info); |
| 700 | break; |
| 701 | |
| 702 | case 'P': |
| 703 | /* 7-bit signed address offset with 1-bit shift. */ |
| 704 | switch (op->format) |
| 705 | { |
| 706 | case iw_T1I7_type: |
| 707 | o = (int32_t) (GET_IW_T1I7_IMM7 (opcode) << 25) >> 24; |
| 708 | break; |
| 709 | default: |
| 710 | bad_opcode (op); |
| 711 | } |
| 712 | address = address + 2 + o; |
| 713 | (*info->print_address_func) (address, info); |
| 714 | break; |
| 715 | |
| 716 | case 'j': |
| 717 | /* 5-bit unsigned immediate. */ |
| 718 | switch (op->format) |
| 719 | { |
| 720 | case iw_r_type: |
| 721 | i = GET_IW_R_IMM5 (opcode); |
| 722 | break; |
| 723 | case iw_F3X6L5_type: |
| 724 | i = GET_IW_F3X6L5_IMM5 (opcode); |
| 725 | break; |
| 726 | case iw_F2X6L10_type: |
| 727 | i = GET_IW_F2X6L10_MSB (opcode); |
| 728 | break; |
| 729 | case iw_X2L5_type: |
| 730 | i = GET_IW_X2L5_IMM5 (opcode); |
| 731 | break; |
| 732 | default: |
| 733 | bad_opcode (op); |
| 734 | } |
| 735 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 736 | break; |
| 737 | |
| 738 | case 'k': |
| 739 | /* Second 5-bit unsigned immediate field. */ |
| 740 | switch (op->format) |
| 741 | { |
| 742 | case iw_F2X6L10_type: |
| 743 | i = GET_IW_F2X6L10_LSB (opcode); |
| 744 | break; |
| 745 | default: |
| 746 | bad_opcode (op); |
| 747 | } |
| 748 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 749 | break; |
| 750 | |
| 751 | case 'l': |
| 752 | /* 8-bit unsigned immediate. */ |
| 753 | switch (op->format) |
| 754 | { |
| 755 | case iw_custom_type: |
| 756 | i = GET_IW_CUSTOM_N (opcode); |
| 757 | break; |
| 758 | case iw_F3X8_type: |
| 759 | i = GET_IW_F3X8_N (opcode); |
| 760 | break; |
| 761 | default: |
| 762 | bad_opcode (op); |
| 763 | } |
| 764 | (*info->fprintf_func) (info->stream, "%lu", i); |
| 765 | break; |
| 766 | |
| 767 | case 'm': |
| 768 | /* 26-bit unsigned immediate. */ |
| 769 | switch (op->format) |
| 770 | { |
| 771 | case iw_j_type: |
| 772 | i = GET_IW_J_IMM26 (opcode); |
| 773 | break; |
| 774 | case iw_L26_type: |
| 775 | i = GET_IW_L26_IMM26 (opcode); |
| 776 | break; |
| 777 | default: |
| 778 | bad_opcode (op); |
| 779 | } |
| 780 | /* This translates to an address because it's only used in call |
| 781 | instructions. */ |
| 782 | address = (address & 0xf0000000) | (i << 2); |
| 783 | (*info->print_address_func) (address, info); |
| 784 | break; |
| 785 | |
| 786 | case 'e': |
| 787 | /* Encoded enumeration for addi.n/subi.n. */ |
| 788 | switch (op->format) |
| 789 | { |
| 790 | case iw_T2X1I3_type: |
| 791 | i = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)]; |
| 792 | break; |
| 793 | default: |
| 794 | bad_opcode (op); |
| 795 | } |
| 796 | (*info->fprintf_func) (info->stream, "%lu", i); |
| 797 | break; |
| 798 | |
| 799 | case 'f': |
| 800 | /* Encoded enumeration for slli.n/srli.n. */ |
| 801 | switch (op->format) |
| 802 | { |
| 803 | case iw_T2X1L3_type: |
| 804 | i = nios2_r2_shi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)]; |
| 805 | break; |
| 806 | default: |
| 807 | bad_opcode (op); |
| 808 | } |
| 809 | (*info->fprintf_func) (info->stream, "%lu", i); |
| 810 | break; |
| 811 | |
| 812 | case 'g': |
| 813 | /* Encoded enumeration for andi.n. */ |
| 814 | switch (op->format) |
| 815 | { |
| 816 | case iw_T2I4_type: |
| 817 | i = nios2_r2_andi_n_mappings[GET_IW_T2I4_IMM4 (opcode)]; |
| 818 | break; |
| 819 | default: |
| 820 | bad_opcode (op); |
| 821 | } |
| 822 | (*info->fprintf_func) (info->stream, "%lu", i); |
| 823 | break; |
| 824 | |
| 825 | case 'h': |
| 826 | /* Encoded enumeration for movi.n. */ |
| 827 | switch (op->format) |
| 828 | { |
| 829 | case iw_T1I7_type: |
| 830 | i = GET_IW_T1I7_IMM7 (opcode); |
| 831 | if (i == 125) |
| 832 | i = 0xff; |
| 833 | else if (i == 126) |
| 834 | i = -2; |
| 835 | else if (i == 127) |
| 836 | i = -1; |
| 837 | break; |
| 838 | default: |
| 839 | bad_opcode (op); |
| 840 | } |
| 841 | (*info->fprintf_func) (info->stream, "%ld", i); |
| 842 | break; |
| 843 | |
| 844 | case 'R': |
| 845 | { |
| 846 | unsigned long reglist = 0; |
| 847 | int dir = 1; |
| 848 | int k, t; |
| 849 | |
| 850 | switch (op->format) |
| 851 | { |
| 852 | case iw_F1X4L17_type: |
| 853 | /* Encoding for ldwm/stwm. */ |
| 854 | i = GET_IW_F1X4L17_REGMASK (opcode); |
| 855 | if (GET_IW_F1X4L17_RS (opcode)) |
| 856 | { |
| 857 | reglist = ((i << 14) & 0x00ffc000); |
| 858 | if (i & (1 << 10)) |
| 859 | reglist |= (1 << 28); |
| 860 | if (i & (1 << 11)) |
| 861 | reglist |= (1 << 31); |
| 862 | } |
| 863 | else |
| 864 | reglist = i << 2; |
| 865 | dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1; |
| 866 | break; |
| 867 | |
| 868 | case iw_L5I4X1_type: |
| 869 | /* Encoding for push.n/pop.n. */ |
| 870 | reglist |= (1 << 31); |
| 871 | if (GET_IW_L5I4X1_FP (opcode)) |
| 872 | reglist |= (1 << 28); |
| 873 | if (GET_IW_L5I4X1_CS (opcode)) |
| 874 | { |
| 875 | int val = GET_IW_L5I4X1_REGRANGE (opcode); |
| 876 | reglist |= nios2_r2_reg_range_mappings[val]; |
| 877 | } |
| 878 | dir = (op->match == MATCH_R2_POP_N ? 1 : -1); |
| 879 | break; |
| 880 | |
| 881 | default: |
| 882 | bad_opcode (op); |
| 883 | } |
| 884 | |
| 885 | t = 0; |
| 886 | (*info->fprintf_func) (info->stream, "{"); |
| 887 | for (k = (dir == 1 ? 0 : 31); |
| 888 | (dir == 1 && k < 32) || (dir == -1 && k >= 0); |
| 889 | k += dir) |
| 890 | if (reglist & (1 << k)) |
| 891 | { |
| 892 | if (t) |
| 893 | (*info->fprintf_func) (info->stream, ","); |
| 894 | else |
| 895 | t++; |
| 896 | (*info->fprintf_func) (info->stream, "%s", nios2_regs[k].name); |
| 897 | } |
| 898 | (*info->fprintf_func) (info->stream, "}"); |
| 899 | break; |
| 900 | } |
| 901 | |
| 902 | case 'B': |
| 903 | /* Base register and options for ldwm/stwm. */ |
| 904 | switch (op->format) |
| 905 | { |
| 906 | case iw_F1X4L17_type: |
| 907 | if (GET_IW_F1X4L17_ID (opcode) == 0) |
| 908 | (*info->fprintf_func) (info->stream, "--"); |
| 909 | |
| 910 | i = GET_IW_F1X4I12_A (opcode); |
| 911 | (*info->fprintf_func) (info->stream, "(%s)", |
| 912 | nios2_builtin_regs[i].name); |
| 913 | |
| 914 | if (GET_IW_F1X4L17_ID (opcode)) |
| 915 | (*info->fprintf_func) (info->stream, "++"); |
| 916 | if (GET_IW_F1X4L17_WB (opcode)) |
| 917 | (*info->fprintf_func) (info->stream, ",writeback"); |
| 918 | if (GET_IW_F1X4L17_PC (opcode)) |
| 919 | (*info->fprintf_func) (info->stream, ",ret"); |
| 920 | break; |
| 921 | default: |
| 922 | bad_opcode (op); |
| 923 | } |
| 924 | break; |
| 925 | |
| 926 | default: |
| 927 | (*info->fprintf_func) (info->stream, "unknown"); |
| 928 | break; |
| 929 | } |
| 930 | return 0; |
| 931 | } |
| 932 | |
| 933 | /* nios2_disassemble does all the work of disassembling a Nios II |
| 934 | instruction opcode. */ |
| 935 | static int |
| 936 | nios2_disassemble (bfd_vma address, unsigned long opcode, |
| 937 | disassemble_info *info) |
| 938 | { |
| 939 | const struct nios2_opcode *op; |
| 940 | |
| 941 | info->bytes_per_line = INSNLEN; |
| 942 | info->bytes_per_chunk = INSNLEN; |
| 943 | info->display_endian = info->endian; |
| 944 | info->insn_info_valid = 1; |
| 945 | info->branch_delay_insns = 0; |
| 946 | info->data_size = 0; |
| 947 | info->insn_type = dis_nonbranch; |
| 948 | info->target = 0; |
| 949 | info->target2 = 0; |
| 950 | |
| 951 | /* Find the major opcode and use this to disassemble |
| 952 | the instruction and its arguments. */ |
| 953 | op = nios2_find_opcode_hash (opcode, info->mach); |
| 954 | |
| 955 | if (op != NULL) |
| 956 | { |
| 957 | const char *argstr = op->args; |
| 958 | (*info->fprintf_func) (info->stream, "%s", op->name); |
| 959 | if (argstr != NULL && *argstr != '\0') |
| 960 | { |
| 961 | (*info->fprintf_func) (info->stream, "\t"); |
| 962 | while (*argstr != '\0') |
| 963 | { |
| 964 | nios2_print_insn_arg (argstr, opcode, address, info, op); |
| 965 | ++argstr; |
| 966 | } |
| 967 | } |
| 968 | /* Tell the caller how far to advance the program counter. */ |
| 969 | info->bytes_per_chunk = op->size; |
| 970 | return op->size; |
| 971 | } |
| 972 | else |
| 973 | { |
| 974 | /* Handle undefined instructions. */ |
| 975 | info->insn_type = dis_noninsn; |
| 976 | (*info->fprintf_func) (info->stream, "0x%lx", opcode); |
| 977 | return INSNLEN; |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | |
| 982 | /* print_insn_nios2 is the main disassemble function for Nios II. |
| 983 | The function diassembler(abfd) (source in disassemble.c) returns a |
| 984 | pointer to this either print_insn_big_nios2 or |
| 985 | print_insn_little_nios2, which in turn call this function when the |
| 986 | bfd machine type is Nios II. print_insn_nios2 reads the |
| 987 | instruction word at the address given, and prints the disassembled |
| 988 | instruction on the stream info->stream using info->fprintf_func. */ |
| 989 | |
| 990 | static int |
| 991 | print_insn_nios2 (bfd_vma address, disassemble_info *info, |
| 992 | enum bfd_endian endianness) |
| 993 | { |
| 994 | bfd_byte buffer[INSNLEN]; |
| 995 | int status; |
| 996 | |
| 997 | status = (*info->read_memory_func) (address, buffer, INSNLEN, info); |
| 998 | if (status == 0) |
| 999 | { |
| 1000 | unsigned long insn; |
| 1001 | if (endianness == BFD_ENDIAN_BIG) |
| 1002 | insn = (unsigned long) bfd_getb32 (buffer); |
| 1003 | else |
| 1004 | insn = (unsigned long) bfd_getl32 (buffer); |
| 1005 | return nios2_disassemble (address, insn, info); |
| 1006 | } |
| 1007 | |
| 1008 | /* We might have a 16-bit R2 instruction at the end of memory. Try that. */ |
| 1009 | if (info->mach == bfd_mach_nios2r2) |
| 1010 | { |
| 1011 | status = (*info->read_memory_func) (address, buffer, 2, info); |
| 1012 | if (status == 0) |
| 1013 | { |
| 1014 | unsigned long insn; |
| 1015 | if (endianness == BFD_ENDIAN_BIG) |
| 1016 | insn = (unsigned long) bfd_getb16 (buffer); |
| 1017 | else |
| 1018 | insn = (unsigned long) bfd_getl16 (buffer); |
| 1019 | return nios2_disassemble (address, insn, info); |
| 1020 | } |
| 1021 | } |
| 1022 | |
| 1023 | /* If we got here, we couldn't read anything. */ |
| 1024 | (*info->memory_error_func) (status, address, info); |
| 1025 | return -1; |
| 1026 | } |
| 1027 | |
| 1028 | /* These two functions are the main entry points, accessed from |
| 1029 | disassemble.c. */ |
| 1030 | int |
| 1031 | print_insn_big_nios2 (bfd_vma address, disassemble_info *info) |
| 1032 | { |
| 1033 | return print_insn_nios2 (address, info, BFD_ENDIAN_BIG); |
| 1034 | } |
| 1035 | |
| 1036 | int |
| 1037 | print_insn_little_nios2 (bfd_vma address, disassemble_info *info) |
| 1038 | { |
| 1039 | return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE); |
| 1040 | } |