| 1 | /* Altera Nios II opcode list. |
| 2 | Copyright (C) 2012-2020 Free Software Foundation, Inc. |
| 3 | Contributed by Nigel Gray (ngray@altera.com). |
| 4 | Contributed by Mentor Graphics, Inc. |
| 5 | |
| 6 | This file is part of the GNU opcodes library. |
| 7 | |
| 8 | This library is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3, or (at your option) |
| 11 | any later version. |
| 12 | |
| 13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 16 | License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this file; see the file COPYING. If not, write to the |
| 20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 21 | MA 02110-1301, USA. */ |
| 22 | |
| 23 | #include "sysdep.h" |
| 24 | #include <stdio.h> |
| 25 | #include "opcode/nios2.h" |
| 26 | |
| 27 | /* Register string table */ |
| 28 | |
| 29 | const struct nios2_reg nios2_builtin_regs[] = { |
| 30 | /* Standard register names. */ |
| 31 | {"zero", 0, REG_NORMAL}, |
| 32 | {"at", 1, REG_NORMAL}, /* assembler temporary */ |
| 33 | {"r2", 2, REG_NORMAL | REG_3BIT | REG_LDWM}, |
| 34 | {"r3", 3, REG_NORMAL | REG_3BIT | REG_LDWM}, |
| 35 | {"r4", 4, REG_NORMAL | REG_3BIT | REG_LDWM}, |
| 36 | {"r5", 5, REG_NORMAL | REG_3BIT | REG_LDWM}, |
| 37 | {"r6", 6, REG_NORMAL | REG_3BIT | REG_LDWM}, |
| 38 | {"r7", 7, REG_NORMAL | REG_3BIT | REG_LDWM}, |
| 39 | {"r8", 8, REG_NORMAL | REG_LDWM}, |
| 40 | {"r9", 9, REG_NORMAL | REG_LDWM}, |
| 41 | {"r10", 10, REG_NORMAL | REG_LDWM}, |
| 42 | {"r11", 11, REG_NORMAL | REG_LDWM}, |
| 43 | {"r12", 12, REG_NORMAL | REG_LDWM}, |
| 44 | {"r13", 13, REG_NORMAL | REG_LDWM}, |
| 45 | {"r14", 14, REG_NORMAL | REG_LDWM}, |
| 46 | {"r15", 15, REG_NORMAL | REG_LDWM}, |
| 47 | {"r16", 16, REG_NORMAL | REG_3BIT | REG_LDWM | REG_POP}, |
| 48 | {"r17", 17, REG_NORMAL | REG_3BIT | REG_LDWM | REG_POP}, |
| 49 | {"r18", 18, REG_NORMAL | REG_LDWM | REG_POP}, |
| 50 | {"r19", 19, REG_NORMAL | REG_LDWM | REG_POP}, |
| 51 | {"r20", 20, REG_NORMAL | REG_LDWM | REG_POP}, |
| 52 | {"r21", 21, REG_NORMAL | REG_LDWM | REG_POP}, |
| 53 | {"r22", 22, REG_NORMAL | REG_LDWM | REG_POP}, |
| 54 | {"r23", 23, REG_NORMAL | REG_LDWM | REG_POP}, |
| 55 | {"et", 24, REG_NORMAL}, |
| 56 | {"bt", 25, REG_NORMAL}, |
| 57 | {"gp", 26, REG_NORMAL}, /* global pointer */ |
| 58 | {"sp", 27, REG_NORMAL}, /* stack pointer */ |
| 59 | {"fp", 28, REG_NORMAL | REG_LDWM | REG_POP}, /* frame pointer */ |
| 60 | {"ea", 29, REG_NORMAL}, /* exception return address */ |
| 61 | {"sstatus", 30, REG_NORMAL}, /* saved processor status */ |
| 62 | {"ra", 31, REG_NORMAL | REG_LDWM | REG_POP}, /* return address */ |
| 63 | |
| 64 | /* Alternative names for special registers. */ |
| 65 | {"r0", 0, REG_NORMAL}, |
| 66 | {"r1", 1, REG_NORMAL}, |
| 67 | {"r24", 24, REG_NORMAL}, |
| 68 | {"r25", 25, REG_NORMAL}, |
| 69 | {"r26", 26, REG_NORMAL}, |
| 70 | {"r27", 27, REG_NORMAL}, |
| 71 | {"r28", 28, REG_NORMAL | REG_LDWM | REG_POP}, |
| 72 | {"r29", 29, REG_NORMAL}, |
| 73 | {"r30", 30, REG_NORMAL}, |
| 74 | {"ba", 30, REG_NORMAL}, /* breakpoint return address */ |
| 75 | {"r31", 31, REG_NORMAL | REG_LDWM | REG_POP}, |
| 76 | |
| 77 | /* Control register names. */ |
| 78 | {"status", 0, REG_CONTROL}, |
| 79 | {"estatus", 1, REG_CONTROL}, |
| 80 | {"bstatus", 2, REG_CONTROL}, |
| 81 | {"ienable", 3, REG_CONTROL}, |
| 82 | {"ipending", 4, REG_CONTROL}, |
| 83 | {"cpuid", 5, REG_CONTROL}, |
| 84 | {"ctl6", 6, REG_CONTROL}, |
| 85 | {"exception", 7, REG_CONTROL}, |
| 86 | {"pteaddr", 8, REG_CONTROL}, |
| 87 | {"tlbacc", 9, REG_CONTROL}, |
| 88 | {"tlbmisc", 10, REG_CONTROL}, |
| 89 | {"eccinj", 11, REG_CONTROL}, |
| 90 | {"badaddr", 12, REG_CONTROL}, |
| 91 | {"config", 13, REG_CONTROL}, |
| 92 | {"mpubase", 14, REG_CONTROL}, |
| 93 | {"mpuacc", 15, REG_CONTROL}, |
| 94 | {"ctl16", 16, REG_CONTROL}, |
| 95 | {"ctl17", 17, REG_CONTROL}, |
| 96 | {"ctl18", 18, REG_CONTROL}, |
| 97 | {"ctl19", 19, REG_CONTROL}, |
| 98 | {"ctl20", 20, REG_CONTROL}, |
| 99 | {"ctl21", 21, REG_CONTROL}, |
| 100 | {"ctl22", 22, REG_CONTROL}, |
| 101 | {"ctl23", 23, REG_CONTROL}, |
| 102 | {"ctl24", 24, REG_CONTROL}, |
| 103 | {"ctl25", 25, REG_CONTROL}, |
| 104 | {"ctl26", 26, REG_CONTROL}, |
| 105 | {"ctl27", 27, REG_CONTROL}, |
| 106 | {"ctl28", 28, REG_CONTROL}, |
| 107 | {"ctl29", 29, REG_CONTROL}, |
| 108 | {"ctl30", 30, REG_CONTROL}, |
| 109 | {"ctl31", 31, REG_CONTROL}, |
| 110 | |
| 111 | /* Alternative names for special control registers. */ |
| 112 | {"ctl0", 0, REG_CONTROL}, |
| 113 | {"ctl1", 1, REG_CONTROL}, |
| 114 | {"ctl2", 2, REG_CONTROL}, |
| 115 | {"ctl3", 3, REG_CONTROL}, |
| 116 | {"ctl4", 4, REG_CONTROL}, |
| 117 | {"ctl5", 5, REG_CONTROL}, |
| 118 | {"ctl7", 7, REG_CONTROL}, |
| 119 | {"ctl8", 8, REG_CONTROL}, |
| 120 | {"ctl9", 9, REG_CONTROL}, |
| 121 | {"ctl10", 10, REG_CONTROL}, |
| 122 | {"ctl11", 11, REG_CONTROL}, |
| 123 | {"ctl12", 12, REG_CONTROL}, |
| 124 | {"ctl13", 13, REG_CONTROL}, |
| 125 | {"ctl14", 14, REG_CONTROL}, |
| 126 | {"ctl15", 15, REG_CONTROL}, |
| 127 | |
| 128 | /* Coprocessor register names. */ |
| 129 | {"c0", 0, REG_COPROCESSOR}, |
| 130 | {"c1", 1, REG_COPROCESSOR}, |
| 131 | {"c2", 2, REG_COPROCESSOR}, |
| 132 | {"c3", 3, REG_COPROCESSOR}, |
| 133 | {"c4", 4, REG_COPROCESSOR}, |
| 134 | {"c5", 5, REG_COPROCESSOR}, |
| 135 | {"c6", 6, REG_COPROCESSOR}, |
| 136 | {"c7", 7, REG_COPROCESSOR}, |
| 137 | {"c8", 8, REG_COPROCESSOR}, |
| 138 | {"c9", 9, REG_COPROCESSOR}, |
| 139 | {"c10", 10, REG_COPROCESSOR}, |
| 140 | {"c11", 11, REG_COPROCESSOR}, |
| 141 | {"c12", 12, REG_COPROCESSOR}, |
| 142 | {"c13", 13, REG_COPROCESSOR}, |
| 143 | {"c14", 14, REG_COPROCESSOR}, |
| 144 | {"c15", 15, REG_COPROCESSOR}, |
| 145 | {"c16", 16, REG_COPROCESSOR}, |
| 146 | {"c17", 17, REG_COPROCESSOR}, |
| 147 | {"c18", 18, REG_COPROCESSOR}, |
| 148 | {"c19", 19, REG_COPROCESSOR}, |
| 149 | {"c20", 20, REG_COPROCESSOR}, |
| 150 | {"c21", 21, REG_COPROCESSOR}, |
| 151 | {"c22", 22, REG_COPROCESSOR}, |
| 152 | {"c23", 23, REG_COPROCESSOR}, |
| 153 | {"c24", 24, REG_COPROCESSOR}, |
| 154 | {"c25", 25, REG_COPROCESSOR}, |
| 155 | {"c26", 26, REG_COPROCESSOR}, |
| 156 | {"c27", 27, REG_COPROCESSOR}, |
| 157 | {"c28", 28, REG_COPROCESSOR}, |
| 158 | {"c29", 29, REG_COPROCESSOR}, |
| 159 | {"c30", 30, REG_COPROCESSOR}, |
| 160 | {"c31", 31, REG_COPROCESSOR}, |
| 161 | }; |
| 162 | |
| 163 | #define NIOS2_NUM_REGS \ |
| 164 | ((sizeof nios2_builtin_regs) / (sizeof (nios2_builtin_regs[0]))) |
| 165 | const int nios2_num_builtin_regs = NIOS2_NUM_REGS; |
| 166 | |
| 167 | /* This is not const in order to allow for dynamic extensions to the |
| 168 | built-in instruction set. */ |
| 169 | struct nios2_reg *nios2_regs = (struct nios2_reg *) nios2_builtin_regs; |
| 170 | int nios2_num_regs = NIOS2_NUM_REGS; |
| 171 | #undef NIOS2_NUM_REGS |
| 172 | |
| 173 | /* This is the opcode table used by the Nios II GNU as, disassembler |
| 174 | and GDB. */ |
| 175 | const struct nios2_opcode nios2_r1_opcodes[] = |
| 176 | { |
| 177 | /* { name, args, args_test, num_args, size, format, |
| 178 | match, mask, pinfo, overflow } */ |
| 179 | {"add", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 180 | MATCH_R1_ADD, MASK_R1_ADD, 0, no_overflow}, |
| 181 | {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 182 | MATCH_R1_ADDI, MASK_R1_ADDI, 0, signed_immed16_overflow}, |
| 183 | {"and", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 184 | MATCH_R1_AND, MASK_R1_AND, 0, no_overflow}, |
| 185 | {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 186 | MATCH_R1_ANDHI, MASK_R1_ANDHI, 0, unsigned_immed16_overflow}, |
| 187 | {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 188 | MATCH_R1_ANDI, MASK_R1_ANDI, 0, unsigned_immed16_overflow}, |
| 189 | {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 190 | MATCH_R1_BEQ, MASK_R1_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 191 | {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 192 | MATCH_R1_BGE, MASK_R1_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 193 | {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 194 | MATCH_R1_BGEU, MASK_R1_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 195 | {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 196 | MATCH_R1_BGT, MASK_R1_BGT, |
| 197 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 198 | {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 199 | MATCH_R1_BGTU, MASK_R1_BGTU, |
| 200 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 201 | {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 202 | MATCH_R1_BLE, MASK_R1_BLE, |
| 203 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 204 | {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 205 | MATCH_R1_BLEU, MASK_R1_BLEU, |
| 206 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 207 | {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 208 | MATCH_R1_BLT, MASK_R1_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 209 | {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 210 | MATCH_R1_BLTU, MASK_R1_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 211 | {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_i_type, |
| 212 | MATCH_R1_BNE, MASK_R1_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 213 | {"br", "o", "o,E", 1, 4, iw_i_type, |
| 214 | MATCH_R1_BR, MASK_R1_BR, NIOS2_INSN_UBRANCH, branch_target_overflow}, |
| 215 | {"break", "j", "j,E", 1, 4, iw_r_type, |
| 216 | MATCH_R1_BREAK, MASK_R1_BREAK, NIOS2_INSN_OPTARG, no_overflow}, |
| 217 | {"bret", "", "E", 0, 4, iw_r_type, |
| 218 | MATCH_R1_BRET, MASK_R1_BRET, 0, no_overflow}, |
| 219 | {"call", "m", "m,E", 1, 4, iw_j_type, |
| 220 | MATCH_R1_CALL, MASK_R1_CALL, NIOS2_INSN_CALL, call_target_overflow}, |
| 221 | {"callr", "s", "s,E", 1, 4, iw_r_type, |
| 222 | MATCH_R1_CALLR, MASK_R1_CALLR, 0, no_overflow}, |
| 223 | {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 224 | MATCH_R1_CMPEQ, MASK_R1_CMPEQ, 0, no_overflow}, |
| 225 | {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 226 | MATCH_R1_CMPEQI, MASK_R1_CMPEQI, 0, signed_immed16_overflow}, |
| 227 | {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 228 | MATCH_R1_CMPGE, MASK_R1_CMPGE, 0, no_overflow}, |
| 229 | {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 230 | MATCH_R1_CMPGEI, MASK_R1_CMPGEI, 0, signed_immed16_overflow}, |
| 231 | {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 232 | MATCH_R1_CMPGEU, MASK_R1_CMPGEU, 0, no_overflow}, |
| 233 | {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 234 | MATCH_R1_CMPGEUI, MASK_R1_CMPGEUI, 0, unsigned_immed16_overflow}, |
| 235 | {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 236 | MATCH_R1_CMPGT, MASK_R1_CMPGT, NIOS2_INSN_MACRO, no_overflow}, |
| 237 | {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 238 | MATCH_R1_CMPGTI, MASK_R1_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow}, |
| 239 | {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 240 | MATCH_R1_CMPGTU, MASK_R1_CMPGTU, NIOS2_INSN_MACRO, no_overflow}, |
| 241 | {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 242 | MATCH_R1_CMPGTUI, MASK_R1_CMPGTUI, |
| 243 | NIOS2_INSN_MACRO, unsigned_immed16_overflow}, |
| 244 | {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 245 | MATCH_R1_CMPLE, MASK_R1_CMPLE, NIOS2_INSN_MACRO, no_overflow}, |
| 246 | {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 247 | MATCH_R1_CMPLEI, MASK_R1_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow}, |
| 248 | {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 249 | MATCH_R1_CMPLEU, MASK_R1_CMPLEU, NIOS2_INSN_MACRO, no_overflow}, |
| 250 | {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 251 | MATCH_R1_CMPLEUI, MASK_R1_CMPLEUI, |
| 252 | NIOS2_INSN_MACRO, unsigned_immed16_overflow}, |
| 253 | {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 254 | MATCH_R1_CMPLT, MASK_R1_CMPLT, 0, no_overflow}, |
| 255 | {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 256 | MATCH_R1_CMPLTI, MASK_R1_CMPLTI, 0, signed_immed16_overflow}, |
| 257 | {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 258 | MATCH_R1_CMPLTU, MASK_R1_CMPLTU, 0, no_overflow}, |
| 259 | {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 260 | MATCH_R1_CMPLTUI, MASK_R1_CMPLTUI, 0, unsigned_immed16_overflow}, |
| 261 | {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 262 | MATCH_R1_CMPNE, MASK_R1_CMPNE, 0, no_overflow}, |
| 263 | {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 264 | MATCH_R1_CMPNEI, MASK_R1_CMPNEI, 0, signed_immed16_overflow}, |
| 265 | {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_custom_type, |
| 266 | MATCH_R1_CUSTOM, MASK_R1_CUSTOM, 0, custom_opcode_overflow}, |
| 267 | {"div", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 268 | MATCH_R1_DIV, MASK_R1_DIV, 0, no_overflow}, |
| 269 | {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 270 | MATCH_R1_DIVU, MASK_R1_DIVU, 0, no_overflow}, |
| 271 | {"eret", "", "E", 0, 4, iw_r_type, |
| 272 | MATCH_R1_ERET, MASK_R1_ERET, 0, no_overflow}, |
| 273 | {"flushd", "i(s)", "i(s),E", 2, 4, iw_i_type, |
| 274 | MATCH_R1_FLUSHD, MASK_R1_FLUSHD, 0, address_offset_overflow}, |
| 275 | {"flushda", "i(s)", "i(s),E", 2, 4, iw_i_type, |
| 276 | MATCH_R1_FLUSHDA, MASK_R1_FLUSHDA, 0, address_offset_overflow}, |
| 277 | {"flushi", "s", "s,E", 1, 4, iw_r_type, |
| 278 | MATCH_R1_FLUSHI, MASK_R1_FLUSHI, 0, no_overflow}, |
| 279 | {"flushp", "", "E", 0, 4, iw_r_type, |
| 280 | MATCH_R1_FLUSHP, MASK_R1_FLUSHP, 0, no_overflow}, |
| 281 | {"initd", "i(s)", "i(s),E", 2, 4, iw_i_type, |
| 282 | MATCH_R1_INITD, MASK_R1_INITD, 0, address_offset_overflow}, |
| 283 | {"initda", "i(s)", "i(s),E", 2, 4, iw_i_type, |
| 284 | MATCH_R1_INITDA, MASK_R1_INITDA, 0, address_offset_overflow}, |
| 285 | {"initi", "s", "s,E", 1, 4, iw_r_type, |
| 286 | MATCH_R1_INITI, MASK_R1_INITI, 0, no_overflow}, |
| 287 | {"jmp", "s", "s,E", 1, 4, iw_r_type, |
| 288 | MATCH_R1_JMP, MASK_R1_JMP, 0, no_overflow}, |
| 289 | {"jmpi", "m", "m,E", 1, 4, iw_j_type, |
| 290 | MATCH_R1_JMPI, MASK_R1_JMPI, 0, call_target_overflow}, |
| 291 | {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 292 | MATCH_R1_LDB, MASK_R1_LDB, 0, address_offset_overflow}, |
| 293 | {"ldbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 294 | MATCH_R1_LDBIO, MASK_R1_LDBIO, 0, address_offset_overflow}, |
| 295 | {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 296 | MATCH_R1_LDBU, MASK_R1_LDBU, 0, address_offset_overflow}, |
| 297 | {"ldbuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 298 | MATCH_R1_LDBUIO, MASK_R1_LDBUIO, 0, address_offset_overflow}, |
| 299 | {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 300 | MATCH_R1_LDH, MASK_R1_LDH, 0, address_offset_overflow}, |
| 301 | {"ldhio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 302 | MATCH_R1_LDHIO, MASK_R1_LDHIO, 0, address_offset_overflow}, |
| 303 | {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 304 | MATCH_R1_LDHU, MASK_R1_LDHU, 0, address_offset_overflow}, |
| 305 | {"ldhuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 306 | MATCH_R1_LDHUIO, MASK_R1_LDHUIO, 0, address_offset_overflow}, |
| 307 | {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 308 | MATCH_R1_LDW, MASK_R1_LDW, 0, address_offset_overflow}, |
| 309 | {"ldwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 310 | MATCH_R1_LDWIO, MASK_R1_LDWIO, 0, address_offset_overflow}, |
| 311 | {"mov", "d,s", "d,s,E", 2, 4, iw_r_type, |
| 312 | MATCH_R1_MOV, MASK_R1_MOV, NIOS2_INSN_MACRO_MOV, no_overflow}, |
| 313 | {"movhi", "t,u", "t,u,E", 2, 4, iw_i_type, |
| 314 | MATCH_R1_MOVHI, MASK_R1_MOVHI, |
| 315 | NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, |
| 316 | {"movi", "t,i", "t,i,E", 2, 4, iw_i_type, |
| 317 | MATCH_R1_MOVI, MASK_R1_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow}, |
| 318 | {"movia", "t,o", "t,o,E", 2, 4, iw_i_type, |
| 319 | MATCH_R1_ORHI, MASK_R1_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow}, |
| 320 | {"movui", "t,u", "t,u,E", 2, 4, iw_i_type, |
| 321 | MATCH_R1_MOVUI, MASK_R1_MOVUI, |
| 322 | NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, |
| 323 | {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 324 | MATCH_R1_MUL, MASK_R1_MUL, 0, no_overflow}, |
| 325 | {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 326 | MATCH_R1_MULI, MASK_R1_MULI, 0, signed_immed16_overflow}, |
| 327 | {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 328 | MATCH_R1_MULXSS, MASK_R1_MULXSS, 0, no_overflow}, |
| 329 | {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 330 | MATCH_R1_MULXSU, MASK_R1_MULXSU, 0, no_overflow}, |
| 331 | {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 332 | MATCH_R1_MULXUU, MASK_R1_MULXUU, 0, no_overflow}, |
| 333 | {"nextpc", "d", "d,E", 1, 4, iw_r_type, |
| 334 | MATCH_R1_NEXTPC, MASK_R1_NEXTPC, 0, no_overflow}, |
| 335 | {"nop", "", "E", 0, 4, iw_r_type, |
| 336 | MATCH_R1_NOP, MASK_R1_NOP, NIOS2_INSN_MACRO_MOV, no_overflow}, |
| 337 | {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 338 | MATCH_R1_NOR, MASK_R1_NOR, 0, no_overflow}, |
| 339 | {"or", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 340 | MATCH_R1_OR, MASK_R1_OR, 0, no_overflow}, |
| 341 | {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 342 | MATCH_R1_ORHI, MASK_R1_ORHI, 0, unsigned_immed16_overflow}, |
| 343 | {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 344 | MATCH_R1_ORI, MASK_R1_ORI, 0, unsigned_immed16_overflow}, |
| 345 | {"rdctl", "d,c", "d,c,E", 2, 4, iw_r_type, |
| 346 | MATCH_R1_RDCTL, MASK_R1_RDCTL, 0, no_overflow}, |
| 347 | {"rdprs", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 348 | MATCH_R1_RDPRS, MASK_R1_RDPRS, 0, signed_immed16_overflow}, |
| 349 | {"ret", "", "E", 0, 4, iw_r_type, |
| 350 | MATCH_R1_RET, MASK_R1_RET, 0, no_overflow}, |
| 351 | {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 352 | MATCH_R1_ROL, MASK_R1_ROL, 0, no_overflow}, |
| 353 | {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type, |
| 354 | MATCH_R1_ROLI, MASK_R1_ROLI, 0, unsigned_immed5_overflow}, |
| 355 | {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 356 | MATCH_R1_ROR, MASK_R1_ROR, 0, no_overflow}, |
| 357 | {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 358 | MATCH_R1_SLL, MASK_R1_SLL, 0, no_overflow}, |
| 359 | {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type, |
| 360 | MATCH_R1_SLLI, MASK_R1_SLLI, 0, unsigned_immed5_overflow}, |
| 361 | {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 362 | MATCH_R1_SRA, MASK_R1_SRA, 0, no_overflow}, |
| 363 | {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_r_type, |
| 364 | MATCH_R1_SRAI, MASK_R1_SRAI, 0, unsigned_immed5_overflow}, |
| 365 | {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 366 | MATCH_R1_SRL, MASK_R1_SRL, 0, no_overflow}, |
| 367 | {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type, |
| 368 | MATCH_R1_SRLI, MASK_R1_SRLI, 0, unsigned_immed5_overflow}, |
| 369 | {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 370 | MATCH_R1_STB, MASK_R1_STB, 0, address_offset_overflow}, |
| 371 | {"stbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 372 | MATCH_R1_STBIO, MASK_R1_STBIO, 0, address_offset_overflow}, |
| 373 | {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 374 | MATCH_R1_STH, MASK_R1_STH, 0, address_offset_overflow}, |
| 375 | {"sthio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 376 | MATCH_R1_STHIO, MASK_R1_STHIO, 0, address_offset_overflow}, |
| 377 | {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 378 | MATCH_R1_STW, MASK_R1_STW, 0, address_offset_overflow}, |
| 379 | {"stwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type, |
| 380 | MATCH_R1_STWIO, MASK_R1_STWIO, 0, address_offset_overflow}, |
| 381 | {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 382 | MATCH_R1_SUB, MASK_R1_SUB, 0, no_overflow}, |
| 383 | {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type, |
| 384 | MATCH_R1_SUBI, MASK_R1_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow}, |
| 385 | {"sync", "", "E", 0, 4, iw_r_type, |
| 386 | MATCH_R1_SYNC, MASK_R1_SYNC, 0, no_overflow}, |
| 387 | {"trap", "j", "j,E", 1, 4, iw_r_type, |
| 388 | MATCH_R1_TRAP, MASK_R1_TRAP, NIOS2_INSN_OPTARG, no_overflow}, |
| 389 | {"wrctl", "c,s", "c,s,E", 2, 4, iw_r_type, |
| 390 | MATCH_R1_WRCTL, MASK_R1_WRCTL, 0, no_overflow}, |
| 391 | {"wrprs", "d,s", "d,s,E", 2, 4, iw_r_type, |
| 392 | MATCH_R1_WRPRS, MASK_R1_WRPRS, 0, no_overflow}, |
| 393 | {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type, |
| 394 | MATCH_R1_XOR, MASK_R1_XOR, 0, no_overflow}, |
| 395 | {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 396 | MATCH_R1_XORHI, MASK_R1_XORHI, 0, unsigned_immed16_overflow}, |
| 397 | {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type, |
| 398 | MATCH_R1_XORI, MASK_R1_XORI, 0, unsigned_immed16_overflow} |
| 399 | }; |
| 400 | |
| 401 | #define NIOS2_NUM_R1_OPCODES \ |
| 402 | ((sizeof nios2_r1_opcodes) / (sizeof (nios2_r1_opcodes[0]))) |
| 403 | const int nios2_num_r1_opcodes = NIOS2_NUM_R1_OPCODES; |
| 404 | |
| 405 | |
| 406 | const struct nios2_opcode nios2_r2_opcodes[] = |
| 407 | { |
| 408 | /* { name, args, args_test, num_args, size, format, |
| 409 | match, mask, pinfo, overflow } */ |
| 410 | {"add", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 411 | MATCH_R2_ADD, MASK_R2_ADD, 0, no_overflow}, |
| 412 | {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 413 | MATCH_R2_ADDI, MASK_R2_ADDI, 0, signed_immed16_overflow}, |
| 414 | {"add.n", "D,S,T", "D,S,T,E", 3, 2, iw_T3X1_type, |
| 415 | MATCH_R2_ADD_N, MASK_R2_ADD_N, 0, no_overflow}, |
| 416 | {"addi.n", "D,S,e", "D,S,e,E", 3, 2, iw_T2X1I3_type, |
| 417 | MATCH_R2_ADDI_N, MASK_R2_ADDI_N, 0, enumeration_overflow}, |
| 418 | {"and", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 419 | MATCH_R2_AND, MASK_R2_AND, 0, no_overflow}, |
| 420 | {"andchi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 421 | MATCH_R2_ANDCHI, MASK_R2_ANDCHI, 0, unsigned_immed16_overflow}, |
| 422 | {"andci", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 423 | MATCH_R2_ANDCI, MASK_R2_ANDCI, 0, unsigned_immed16_overflow}, |
| 424 | {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 425 | MATCH_R2_ANDHI, MASK_R2_ANDHI, 0, unsigned_immed16_overflow}, |
| 426 | {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 427 | MATCH_R2_ANDI, MASK_R2_ANDI, 0, unsigned_immed16_overflow}, |
| 428 | {"andi.n", "T,S,g", "T,S,g,E", 3, 2, iw_T2I4_type, |
| 429 | MATCH_R2_ANDI_N, MASK_R2_ANDI_N, 0, enumeration_overflow}, |
| 430 | {"and.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, |
| 431 | MATCH_R2_AND_N, MASK_R2_AND_N, 0, no_overflow}, |
| 432 | {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 433 | MATCH_R2_BEQ, MASK_R2_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 434 | {"beqz.n", "S,P", "S,P,E", 2, 2, iw_T1I7_type, |
| 435 | MATCH_R2_BEQZ_N, MASK_R2_BEQZ_N, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 436 | {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 437 | MATCH_R2_BGE, MASK_R2_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 438 | {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 439 | MATCH_R2_BGEU, MASK_R2_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 440 | {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 441 | MATCH_R2_BGT, MASK_R2_BGT, |
| 442 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 443 | {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 444 | MATCH_R2_BGTU, MASK_R2_BGTU, |
| 445 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 446 | {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 447 | MATCH_R2_BLE, MASK_R2_BLE, |
| 448 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 449 | {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 450 | MATCH_R2_BLEU, MASK_R2_BLEU, |
| 451 | NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 452 | {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 453 | MATCH_R2_BLT, MASK_R2_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 454 | {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 455 | MATCH_R2_BLTU, MASK_R2_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 456 | {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, |
| 457 | MATCH_R2_BNE, MASK_R2_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 458 | {"bnez.n", "S,P", "S,P,E", 2, 2, iw_T1I7_type, |
| 459 | MATCH_R2_BNEZ_N, MASK_R2_BNEZ_N, NIOS2_INSN_CBRANCH, branch_target_overflow}, |
| 460 | {"br", "o", "o,E", 1, 4, iw_F2I16_type, |
| 461 | MATCH_R2_BR, MASK_R2_BR, NIOS2_INSN_UBRANCH, branch_target_overflow}, |
| 462 | {"break", "j", "j,E", 1, 4, iw_F3X6L5_type, |
| 463 | MATCH_R2_BREAK, MASK_R2_BREAK, NIOS2_INSN_OPTARG, no_overflow}, |
| 464 | {"break.n", "j", "j,E", 1, 2, iw_X2L5_type, |
| 465 | MATCH_R2_BREAK_N, MASK_R2_BREAK_N, NIOS2_INSN_OPTARG, no_overflow}, |
| 466 | {"bret", "", "E", 0, 4, iw_F3X6_type, |
| 467 | MATCH_R2_BRET, MASK_R2_BRET, 0, no_overflow}, |
| 468 | {"br.n", "O", "O,E", 1, 2, iw_I10_type, |
| 469 | MATCH_R2_BR_N, MASK_R2_BR_N, NIOS2_INSN_UBRANCH, branch_target_overflow}, |
| 470 | {"call", "m", "m,E", 1, 4, iw_L26_type, |
| 471 | MATCH_R2_CALL, MASK_R2_CALL, NIOS2_INSN_CALL, call_target_overflow}, |
| 472 | {"callr", "s", "s,E", 1, 4, iw_F3X6_type, |
| 473 | MATCH_R2_CALLR, MASK_R2_CALLR, 0, no_overflow}, |
| 474 | {"callr.n", "s", "s,E", 1, 2, iw_F1X1_type, |
| 475 | MATCH_R2_CALLR_N, MASK_R2_CALLR_N, 0, no_overflow}, |
| 476 | {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 477 | MATCH_R2_CMPEQ, MASK_R2_CMPEQ, 0, no_overflow}, |
| 478 | {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 479 | MATCH_R2_CMPEQI, MASK_R2_CMPEQI, 0, signed_immed16_overflow}, |
| 480 | {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 481 | MATCH_R2_CMPGE, MASK_R2_CMPGE, 0, no_overflow}, |
| 482 | {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 483 | MATCH_R2_CMPGEI, MASK_R2_CMPGEI, 0, signed_immed16_overflow}, |
| 484 | {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 485 | MATCH_R2_CMPGEU, MASK_R2_CMPGEU, 0, no_overflow}, |
| 486 | {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 487 | MATCH_R2_CMPGEUI, MASK_R2_CMPGEUI, 0, unsigned_immed16_overflow}, |
| 488 | {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 489 | MATCH_R2_CMPGT, MASK_R2_CMPGT, NIOS2_INSN_MACRO, no_overflow}, |
| 490 | {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 491 | MATCH_R2_CMPGTI, MASK_R2_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow}, |
| 492 | {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 493 | MATCH_R2_CMPGTU, MASK_R2_CMPGTU, NIOS2_INSN_MACRO, no_overflow}, |
| 494 | {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 495 | MATCH_R2_CMPGTUI, MASK_R2_CMPGTUI, |
| 496 | NIOS2_INSN_MACRO, unsigned_immed16_overflow}, |
| 497 | {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 498 | MATCH_R2_CMPLE, MASK_R2_CMPLE, NIOS2_INSN_MACRO, no_overflow}, |
| 499 | {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 500 | MATCH_R2_CMPLEI, MASK_R2_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow}, |
| 501 | {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 502 | MATCH_R2_CMPLEU, MASK_R2_CMPLEU, NIOS2_INSN_MACRO, no_overflow}, |
| 503 | {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 504 | MATCH_R2_CMPLEUI, MASK_R2_CMPLEUI, |
| 505 | NIOS2_INSN_MACRO, unsigned_immed16_overflow}, |
| 506 | {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 507 | MATCH_R2_CMPLT, MASK_R2_CMPLT, 0, no_overflow}, |
| 508 | {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 509 | MATCH_R2_CMPLTI, MASK_R2_CMPLTI, 0, signed_immed16_overflow}, |
| 510 | {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 511 | MATCH_R2_CMPLTU, MASK_R2_CMPLTU, 0, no_overflow}, |
| 512 | {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 513 | MATCH_R2_CMPLTUI, MASK_R2_CMPLTUI, 0, unsigned_immed16_overflow}, |
| 514 | {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 515 | MATCH_R2_CMPNE, MASK_R2_CMPNE, 0, no_overflow}, |
| 516 | {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 517 | MATCH_R2_CMPNEI, MASK_R2_CMPNEI, 0, signed_immed16_overflow}, |
| 518 | {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_F3X8_type, |
| 519 | MATCH_R2_CUSTOM, MASK_R2_CUSTOM, 0, custom_opcode_overflow}, |
| 520 | {"div", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 521 | MATCH_R2_DIV, MASK_R2_DIV, 0, no_overflow}, |
| 522 | {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 523 | MATCH_R2_DIVU, MASK_R2_DIVU, 0, no_overflow}, |
| 524 | {"eni", "j", "j,E", 1, 4, iw_F3X6L5_type, |
| 525 | MATCH_R2_ENI, MASK_R2_ENI, NIOS2_INSN_OPTARG, no_overflow}, |
| 526 | {"eret", "", "E", 0, 4, iw_F3X6_type, |
| 527 | MATCH_R2_ERET, MASK_R2_ERET, 0, no_overflow}, |
| 528 | {"extract", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type, |
| 529 | MATCH_R2_EXTRACT, MASK_R2_EXTRACT, 0, no_overflow}, |
| 530 | {"flushd", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, |
| 531 | MATCH_R2_FLUSHD, MASK_R2_FLUSHD, 0, address_offset_overflow}, |
| 532 | {"flushda", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, |
| 533 | MATCH_R2_FLUSHDA, MASK_R2_FLUSHDA, 0, address_offset_overflow}, |
| 534 | {"flushi", "s", "s,E", 1, 4, iw_F3X6_type, |
| 535 | MATCH_R2_FLUSHI, MASK_R2_FLUSHI, 0, no_overflow}, |
| 536 | {"flushp", "", "E", 0, 4, iw_F3X6_type, |
| 537 | MATCH_R2_FLUSHP, MASK_R2_FLUSHP, 0, no_overflow}, |
| 538 | {"initd", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, |
| 539 | MATCH_R2_INITD, MASK_R2_INITD, 0, address_offset_overflow}, |
| 540 | {"initda", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, |
| 541 | MATCH_R2_INITDA, MASK_R2_INITDA, 0, address_offset_overflow}, |
| 542 | {"initi", "s", "s,E", 1, 4, iw_F3X6_type, |
| 543 | MATCH_R2_INITI, MASK_R2_INITI, 0, no_overflow}, |
| 544 | {"insert", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type, |
| 545 | MATCH_R2_INSERT, MASK_R2_INSERT, 0, no_overflow}, |
| 546 | {"jmp", "s", "s,E", 1, 4, iw_F3X6_type, |
| 547 | MATCH_R2_JMP, MASK_R2_JMP, 0, no_overflow}, |
| 548 | {"jmpi", "m", "m,E", 1, 4, iw_L26_type, |
| 549 | MATCH_R2_JMPI, MASK_R2_JMPI, 0, call_target_overflow}, |
| 550 | {"jmpr.n", "s", "s,E", 1, 2, iw_F1X1_type, |
| 551 | MATCH_R2_JMPR_N, MASK_R2_JMPR_N, 0, no_overflow}, |
| 552 | {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 553 | MATCH_R2_LDB, MASK_R2_LDB, 0, address_offset_overflow}, |
| 554 | {"ldbio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 555 | MATCH_R2_LDBIO, MASK_R2_LDBIO, 0, signed_immed12_overflow}, |
| 556 | {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 557 | MATCH_R2_LDBU, MASK_R2_LDBU, 0, address_offset_overflow}, |
| 558 | {"ldbuio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 559 | MATCH_R2_LDBUIO, MASK_R2_LDBUIO, 0, signed_immed12_overflow}, |
| 560 | {"ldbu.n", "T,Y(S)", "T,Y(S),E", 3, 2, iw_T2I4_type, |
| 561 | MATCH_R2_LDBU_N, MASK_R2_LDBU_N, 0, address_offset_overflow}, |
| 562 | {"ldex", "d,(s)", "d,(s),E", 2, 4, iw_F3X6_type, |
| 563 | MATCH_R2_LDEX, MASK_R2_LDEX, 0, no_overflow}, |
| 564 | {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 565 | MATCH_R2_LDH, MASK_R2_LDH, 0, address_offset_overflow}, |
| 566 | {"ldhio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 567 | MATCH_R2_LDHIO, MASK_R2_LDHIO, 0, signed_immed12_overflow}, |
| 568 | {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 569 | MATCH_R2_LDHU, MASK_R2_LDHU, 0, address_offset_overflow}, |
| 570 | {"ldhuio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 571 | MATCH_R2_LDHUIO, MASK_R2_LDHUIO, 0, signed_immed12_overflow}, |
| 572 | {"ldhu.n", "T,X(S)", "T,X(S),E", 3, 2, iw_T2I4_type, |
| 573 | MATCH_R2_LDHU_N, MASK_R2_LDHU_N, 0, address_offset_overflow}, |
| 574 | {"ldsex", "d,(s)", "d,(s),E", 2, 4, iw_F3X6_type, |
| 575 | MATCH_R2_LDSEX, MASK_R2_LDSEX, 0, no_overflow}, |
| 576 | {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 577 | MATCH_R2_LDW, MASK_R2_LDW, 0, address_offset_overflow}, |
| 578 | {"ldwio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 579 | MATCH_R2_LDWIO, MASK_R2_LDWIO, 0, signed_immed12_overflow}, |
| 580 | {"ldwm", "R,B", "R,B,E", 2, 4, iw_F1X4L17_type, |
| 581 | MATCH_R2_LDWM, MASK_R2_LDWM, 0, no_overflow}, |
| 582 | {"ldw.n", "T,W(S)", "T,W(S),E", 3, 2, iw_T2I4_type, |
| 583 | MATCH_R2_LDW_N, MASK_R2_LDW_N, 0, address_offset_overflow}, |
| 584 | {"ldwsp.n", "t,V(s)", "t,V(s),E", 3, 2, iw_F1I5_type, |
| 585 | MATCH_R2_LDWSP_N, MASK_R2_LDWSP_N, 0, address_offset_overflow}, |
| 586 | {"merge", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type, |
| 587 | MATCH_R2_MERGE, MASK_R2_MERGE, 0, no_overflow}, |
| 588 | {"mov", "d,s", "d,s,E", 2, 4, iw_F3X6_type, |
| 589 | MATCH_R2_MOV, MASK_R2_MOV, NIOS2_INSN_MACRO_MOV, no_overflow}, |
| 590 | {"mov.n", "d,s", "d,s,E", 2, 2, iw_F2_type, |
| 591 | MATCH_R2_MOV_N, MASK_R2_MOV_N, 0, no_overflow}, |
| 592 | {"movi.n", "D,h", "D,h,E", 2, 2, iw_T1I7_type, |
| 593 | MATCH_R2_MOVI_N, MASK_R2_MOVI_N, 0, enumeration_overflow}, |
| 594 | {"movhi", "t,u", "t,u,E", 2, 4, iw_F2I16_type, |
| 595 | MATCH_R2_MOVHI, MASK_R2_MOVHI, |
| 596 | NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, |
| 597 | {"movi", "t,i", "t,i,E", 2, 4, iw_F2I16_type, |
| 598 | MATCH_R2_MOVI, MASK_R2_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow}, |
| 599 | {"movia", "t,o", "t,o,E", 2, 4, iw_F2I16_type, |
| 600 | MATCH_R2_ORHI, MASK_R2_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow}, |
| 601 | {"movui", "t,u", "t,u,E", 2, 4, iw_F2I16_type, |
| 602 | MATCH_R2_MOVUI, MASK_R2_MOVUI, |
| 603 | NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, |
| 604 | {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 605 | MATCH_R2_MUL, MASK_R2_MUL, 0, no_overflow}, |
| 606 | {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 607 | MATCH_R2_MULI, MASK_R2_MULI, 0, signed_immed16_overflow}, |
| 608 | {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 609 | MATCH_R2_MULXSS, MASK_R2_MULXSS, 0, no_overflow}, |
| 610 | {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 611 | MATCH_R2_MULXSU, MASK_R2_MULXSU, 0, no_overflow}, |
| 612 | {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 613 | MATCH_R2_MULXUU, MASK_R2_MULXUU, 0, no_overflow}, |
| 614 | /* The encoding of the neg.n operands is backwards, not |
| 615 | the interpretation -- the first operand is still the |
| 616 | destination and the second the source. */ |
| 617 | {"neg.n", "S,D", "S,D,E", 2, 2, iw_T2X3_type, |
| 618 | MATCH_R2_NEG_N, MASK_R2_NEG_N, 0, no_overflow}, |
| 619 | {"nextpc", "d", "d,E", 1, 4, iw_F3X6_type, |
| 620 | MATCH_R2_NEXTPC, MASK_R2_NEXTPC, 0, no_overflow}, |
| 621 | {"nop", "", "E", 0, 4, iw_F3X6_type, |
| 622 | MATCH_R2_NOP, MASK_R2_NOP, NIOS2_INSN_MACRO_MOV, no_overflow}, |
| 623 | {"nop.n", "", "E", 0, 2, iw_F2_type, |
| 624 | MATCH_R2_NOP_N, MASK_R2_NOP_N, NIOS2_INSN_MACRO_MOV, no_overflow}, |
| 625 | {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 626 | MATCH_R2_NOR, MASK_R2_NOR, 0, no_overflow}, |
| 627 | {"not.n", "D,S", "D,S,E", 2, 2, iw_T2X3_type, |
| 628 | MATCH_R2_NOT_N, MASK_R2_NOT_N, 0, no_overflow}, |
| 629 | {"or", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 630 | MATCH_R2_OR, MASK_R2_OR, 0, no_overflow}, |
| 631 | {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 632 | MATCH_R2_ORHI, MASK_R2_ORHI, 0, unsigned_immed16_overflow}, |
| 633 | {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 634 | MATCH_R2_ORI, MASK_R2_ORI, 0, unsigned_immed16_overflow}, |
| 635 | {"or.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, |
| 636 | MATCH_R2_OR_N, MASK_R2_OR_N, 0, no_overflow}, |
| 637 | {"pop.n", "R,W", "R,W,E", 2, 2, iw_L5I4X1_type, |
| 638 | MATCH_R2_POP_N, MASK_R2_POP_N, NIOS2_INSN_OPTARG, no_overflow}, |
| 639 | {"push.n", "R,W", "R,W,E", 2, 2, iw_L5I4X1_type, |
| 640 | MATCH_R2_PUSH_N, MASK_R2_PUSH_N, NIOS2_INSN_OPTARG, no_overflow}, |
| 641 | {"rdctl", "d,c", "d,c,E", 2, 4, iw_F3X6L5_type, |
| 642 | MATCH_R2_RDCTL, MASK_R2_RDCTL, 0, no_overflow}, |
| 643 | {"rdprs", "t,s,I", "t,s,I,E", 3, 4, iw_F2X4I12_type, |
| 644 | MATCH_R2_RDPRS, MASK_R2_RDPRS, 0, signed_immed12_overflow}, |
| 645 | {"ret", "", "E", 0, 4, iw_F3X6_type, |
| 646 | MATCH_R2_RET, MASK_R2_RET, 0, no_overflow}, |
| 647 | {"ret.n", "", "E", 0, 2, iw_X2L5_type, |
| 648 | MATCH_R2_RET_N, MASK_R2_RET_N, 0, no_overflow}, |
| 649 | {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 650 | MATCH_R2_ROL, MASK_R2_ROL, 0, no_overflow}, |
| 651 | {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, |
| 652 | MATCH_R2_ROLI, MASK_R2_ROLI, 0, unsigned_immed5_overflow}, |
| 653 | {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 654 | MATCH_R2_ROR, MASK_R2_ROR, 0, no_overflow}, |
| 655 | {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 656 | MATCH_R2_SLL, MASK_R2_SLL, 0, no_overflow}, |
| 657 | {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, |
| 658 | MATCH_R2_SLLI, MASK_R2_SLLI, 0, unsigned_immed5_overflow}, |
| 659 | {"sll.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, |
| 660 | MATCH_R2_SLL_N, MASK_R2_SLL_N, 0, no_overflow}, |
| 661 | {"slli.n", "D,S,f", "D,S,f,E", 3, 2, iw_T2X1L3_type, |
| 662 | MATCH_R2_SLLI_N, MASK_R2_SLLI_N, 0, enumeration_overflow}, |
| 663 | {"spaddi.n", "D,U", "D,U,E", 2, 2, iw_T1I7_type, |
| 664 | MATCH_R2_SPADDI_N, MASK_R2_SPADDI_N, 0, address_offset_overflow}, |
| 665 | {"spdeci.n", "U", "U,E", 1, 2, iw_X1I7_type, |
| 666 | MATCH_R2_SPDECI_N, MASK_R2_SPDECI_N, 0, address_offset_overflow}, |
| 667 | {"spinci.n", "U", "U,E", 1, 2, iw_X1I7_type, |
| 668 | MATCH_R2_SPINCI_N, MASK_R2_SPINCI_N, 0, address_offset_overflow}, |
| 669 | {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 670 | MATCH_R2_SRA, MASK_R2_SRA, 0, no_overflow}, |
| 671 | {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, |
| 672 | MATCH_R2_SRAI, MASK_R2_SRAI, 0, unsigned_immed5_overflow}, |
| 673 | {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 674 | MATCH_R2_SRL, MASK_R2_SRL, 0, no_overflow}, |
| 675 | {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, |
| 676 | MATCH_R2_SRLI, MASK_R2_SRLI, 0, unsigned_immed5_overflow}, |
| 677 | {"srl.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, |
| 678 | MATCH_R2_SRL_N, MASK_R2_SRL_N, 0, no_overflow}, |
| 679 | {"srli.n", "D,S,f", "D,S,f,E", 3, 2, iw_T2X1L3_type, |
| 680 | MATCH_R2_SRLI_N, MASK_R2_SRLI_N, 0, enumeration_overflow}, |
| 681 | {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 682 | MATCH_R2_STB, MASK_R2_STB, 0, address_offset_overflow}, |
| 683 | {"stbio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 684 | MATCH_R2_STBIO, MASK_R2_STBIO, 0, signed_immed12_overflow}, |
| 685 | {"stb.n", "T,Y(S)", "T,Y(S),E", 3, 2, iw_T2I4_type, |
| 686 | MATCH_R2_STB_N, MASK_R2_STB_N, 0, address_offset_overflow}, |
| 687 | {"stbz.n", "t,M(S)", "t,M(S),E", 3, 2, iw_T1X1I6_type, |
| 688 | MATCH_R2_STBZ_N, MASK_R2_STBZ_N, 0, address_offset_overflow}, |
| 689 | {"stex", "d,t,(s)", "d,t,(s),E", 3, 4, iw_F3X6_type, |
| 690 | MATCH_R2_STEX, MASK_R2_STEX, 0, no_overflow}, |
| 691 | {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 692 | MATCH_R2_STH, MASK_R2_STH, 0, address_offset_overflow}, |
| 693 | {"sthio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 694 | MATCH_R2_STHIO, MASK_R2_STHIO, 0, signed_immed12_overflow}, |
| 695 | {"sth.n", "T,X(S)", "T,X(S),E", 3, 2, iw_T2I4_type, |
| 696 | MATCH_R2_STH_N, MASK_R2_STH_N, 0, address_offset_overflow}, |
| 697 | {"stsex", "d,t,(s)", "d,t,(s),E", 3, 4, iw_F3X6_type, |
| 698 | MATCH_R2_STSEX, MASK_R2_STSEX, 0, no_overflow}, |
| 699 | {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, |
| 700 | MATCH_R2_STW, MASK_R2_STW, 0, address_offset_overflow}, |
| 701 | {"stwio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, |
| 702 | MATCH_R2_STWIO, MASK_R2_STWIO, 0, signed_immed12_overflow}, |
| 703 | {"stwm", "R,B", "R,B,E", 2, 4, iw_F1X4L17_type, |
| 704 | MATCH_R2_STWM, MASK_R2_STWM, 0, no_overflow}, |
| 705 | {"stwsp.n", "t,V(s)", "t,V(s),E", 3, 2, iw_F1I5_type, |
| 706 | MATCH_R2_STWSP_N, MASK_R2_STWSP_N, 0, address_offset_overflow}, |
| 707 | {"stw.n", "T,W(S)", "T,W(S),E", 3, 2, iw_T2I4_type, |
| 708 | MATCH_R2_STW_N, MASK_R2_STW_N, 0, address_offset_overflow}, |
| 709 | {"stwz.n", "t,N(S)", "t,N(S),E", 3, 2, iw_T1X1I6_type, |
| 710 | MATCH_R2_STWZ_N, MASK_R2_STWZ_N, 0, address_offset_overflow}, |
| 711 | {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 712 | MATCH_R2_SUB, MASK_R2_SUB, 0, no_overflow}, |
| 713 | {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, |
| 714 | MATCH_R2_SUBI, MASK_R2_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow}, |
| 715 | {"sub.n", "D,S,T", "D,S,T,E", 3, 2, iw_T3X1_type, |
| 716 | MATCH_R2_SUB_N, MASK_R2_SUB_N, 0, no_overflow}, |
| 717 | {"subi.n", "D,S,e", "D,S,e,E", 3, 2, iw_T2X1I3_type, |
| 718 | MATCH_R2_SUBI_N, MASK_R2_SUBI_N, 0, enumeration_overflow}, |
| 719 | {"sync", "", "E", 0, 4, iw_F3X6_type, |
| 720 | MATCH_R2_SYNC, MASK_R2_SYNC, 0, no_overflow}, |
| 721 | {"trap", "j", "j,E", 1, 4, iw_F3X6L5_type, |
| 722 | MATCH_R2_TRAP, MASK_R2_TRAP, NIOS2_INSN_OPTARG, no_overflow}, |
| 723 | {"trap.n", "j", "j,E", 1, 2, iw_X2L5_type, |
| 724 | MATCH_R2_TRAP_N, MASK_R2_TRAP_N, NIOS2_INSN_OPTARG, no_overflow}, |
| 725 | {"wrctl", "c,s", "c,s,E", 2, 4, iw_F3X6L5_type, |
| 726 | MATCH_R2_WRCTL, MASK_R2_WRCTL, 0, no_overflow}, |
| 727 | {"wrpie", "d,s", "d,s,E", 2, 4, iw_F3X6L5_type, |
| 728 | MATCH_R2_WRPIE, MASK_R2_WRPIE, 0, no_overflow}, |
| 729 | {"wrprs", "d,s", "d,s,E", 2, 4, iw_F3X6_type, |
| 730 | MATCH_R2_WRPRS, MASK_R2_WRPRS, 0, no_overflow}, |
| 731 | {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, |
| 732 | MATCH_R2_XOR, MASK_R2_XOR, 0, no_overflow}, |
| 733 | {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 734 | MATCH_R2_XORHI, MASK_R2_XORHI, 0, unsigned_immed16_overflow}, |
| 735 | {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, |
| 736 | MATCH_R2_XORI, MASK_R2_XORI, 0, unsigned_immed16_overflow}, |
| 737 | {"xor.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, |
| 738 | MATCH_R2_XOR_N, MASK_R2_XOR_N, 0, no_overflow}, |
| 739 | }; |
| 740 | |
| 741 | #define NIOS2_NUM_R2_OPCODES \ |
| 742 | ((sizeof nios2_r2_opcodes) / (sizeof (nios2_r2_opcodes[0]))) |
| 743 | const int nios2_num_r2_opcodes = NIOS2_NUM_R2_OPCODES; |
| 744 | |
| 745 | /* Default to using the R1 instruction tables. */ |
| 746 | struct nios2_opcode *nios2_opcodes = (struct nios2_opcode *) nios2_r1_opcodes; |
| 747 | int nios2_num_opcodes = NIOS2_NUM_R1_OPCODES; |
| 748 | #undef NIOS2_NUM_R1_OPCODES |
| 749 | #undef NIOS2_NUM_R2_OPCODES |
| 750 | |
| 751 | /* Decodings for R2 asi.n (addi.n/subi.n) immediate values. */ |
| 752 | unsigned int nios2_r2_asi_n_mappings[] = |
| 753 | {1, 2, 4, 8, 16, 32, 64, 128}; |
| 754 | const int nios2_num_r2_asi_n_mappings = 8; |
| 755 | |
| 756 | /* Decodings for R2 shi.n (slli.n/srli.n) immediate values. */ |
| 757 | unsigned int nios2_r2_shi_n_mappings[] = |
| 758 | {1, 2, 3, 8, 12, 16, 24, 31}; |
| 759 | const int nios2_num_r2_shi_n_mappings = 8; |
| 760 | |
| 761 | /* Decodings for R2 andi.n immediate values. */ |
| 762 | unsigned int nios2_r2_andi_n_mappings[] = |
| 763 | {1, 2, 3, 4, 8, 0xf, 0x10, 0x1f, |
| 764 | 0x20, 0x3f, 0x7f, 0x80, 0xff, 0x7ff, 0xff00, 0xffff}; |
| 765 | const int nios2_num_r2_andi_n_mappings = 16; |
| 766 | |
| 767 | /* Decodings for R2 3-bit register fields. */ |
| 768 | int nios2_r2_reg3_mappings[] = |
| 769 | {16, 17, 2, 3, 4, 5, 6, 7}; |
| 770 | const int nios2_num_r2_reg3_mappings = 8; |
| 771 | |
| 772 | /* Decodings for R2 push.n/pop.n REG_RANGE value list. */ |
| 773 | unsigned long nios2_r2_reg_range_mappings[] = { |
| 774 | 0x00010000, |
| 775 | 0x00030000, |
| 776 | 0x00070000, |
| 777 | 0x000f0000, |
| 778 | 0x001f0000, |
| 779 | 0x003f0000, |
| 780 | 0x007f0000, |
| 781 | 0x00ff0000 |
| 782 | }; |
| 783 | const int nios2_num_r2_reg_range_mappings = 8; |