| 1 | /* Instruction building/extraction support for openrisc. -*- C -*- |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. |
| 4 | - the resultant file is machine generated, cgen-ibld.in isn't |
| 5 | |
| 6 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007 |
| 7 | Free Software Foundation, Inc. |
| 8 | |
| 9 | This file is part of libopcodes. |
| 10 | |
| 11 | This library is free software; you can redistribute it and/or modify |
| 12 | it under the terms of the GNU General Public License as published by |
| 13 | the Free Software Foundation; either version 3, or (at your option) |
| 14 | any later version. |
| 15 | |
| 16 | It is distributed in the hope that it will be useful, but WITHOUT |
| 17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 19 | License for more details. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License |
| 22 | along with this program; if not, write to the Free Software Foundation, Inc., |
| 23 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
| 24 | |
| 25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. |
| 26 | Keep that in mind. */ |
| 27 | |
| 28 | #include "sysdep.h" |
| 29 | #include <stdio.h> |
| 30 | #include "ansidecl.h" |
| 31 | #include "dis-asm.h" |
| 32 | #include "bfd.h" |
| 33 | #include "symcat.h" |
| 34 | #include "openrisc-desc.h" |
| 35 | #include "openrisc-opc.h" |
| 36 | #include "opintl.h" |
| 37 | #include "safe-ctype.h" |
| 38 | |
| 39 | #undef min |
| 40 | #define min(a,b) ((a) < (b) ? (a) : (b)) |
| 41 | #undef max |
| 42 | #define max(a,b) ((a) > (b) ? (a) : (b)) |
| 43 | |
| 44 | /* Used by the ifield rtx function. */ |
| 45 | #define FLD(f) (fields->f) |
| 46 | |
| 47 | static const char * insert_normal |
| 48 | (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, |
| 49 | unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); |
| 50 | static const char * insert_insn_normal |
| 51 | (CGEN_CPU_DESC, const CGEN_INSN *, |
| 52 | CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); |
| 53 | static int extract_normal |
| 54 | (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, |
| 55 | unsigned int, unsigned int, unsigned int, unsigned int, |
| 56 | unsigned int, unsigned int, bfd_vma, long *); |
| 57 | static int extract_insn_normal |
| 58 | (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, |
| 59 | CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); |
| 60 | #if CGEN_INT_INSN_P |
| 61 | static void put_insn_int_value |
| 62 | (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); |
| 63 | #endif |
| 64 | #if ! CGEN_INT_INSN_P |
| 65 | static CGEN_INLINE void insert_1 |
| 66 | (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); |
| 67 | static CGEN_INLINE int fill_cache |
| 68 | (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); |
| 69 | static CGEN_INLINE long extract_1 |
| 70 | (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); |
| 71 | #endif |
| 72 | \f |
| 73 | /* Operand insertion. */ |
| 74 | |
| 75 | #if ! CGEN_INT_INSN_P |
| 76 | |
| 77 | /* Subroutine of insert_normal. */ |
| 78 | |
| 79 | static CGEN_INLINE void |
| 80 | insert_1 (CGEN_CPU_DESC cd, |
| 81 | unsigned long value, |
| 82 | int start, |
| 83 | int length, |
| 84 | int word_length, |
| 85 | unsigned char *bufp) |
| 86 | { |
| 87 | unsigned long x,mask; |
| 88 | int shift; |
| 89 | |
| 90 | x = cgen_get_insn_value (cd, bufp, word_length); |
| 91 | |
| 92 | /* Written this way to avoid undefined behaviour. */ |
| 93 | mask = (((1L << (length - 1)) - 1) << 1) | 1; |
| 94 | if (CGEN_INSN_LSB0_P) |
| 95 | shift = (start + 1) - length; |
| 96 | else |
| 97 | shift = (word_length - (start + length)); |
| 98 | x = (x & ~(mask << shift)) | ((value & mask) << shift); |
| 99 | |
| 100 | cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); |
| 101 | } |
| 102 | |
| 103 | #endif /* ! CGEN_INT_INSN_P */ |
| 104 | |
| 105 | /* Default insertion routine. |
| 106 | |
| 107 | ATTRS is a mask of the boolean attributes. |
| 108 | WORD_OFFSET is the offset in bits from the start of the insn of the value. |
| 109 | WORD_LENGTH is the length of the word in bits in which the value resides. |
| 110 | START is the starting bit number in the word, architecture origin. |
| 111 | LENGTH is the length of VALUE in bits. |
| 112 | TOTAL_LENGTH is the total length of the insn in bits. |
| 113 | |
| 114 | The result is an error message or NULL if success. */ |
| 115 | |
| 116 | /* ??? This duplicates functionality with bfd's howto table and |
| 117 | bfd_install_relocation. */ |
| 118 | /* ??? This doesn't handle bfd_vma's. Create another function when |
| 119 | necessary. */ |
| 120 | |
| 121 | static const char * |
| 122 | insert_normal (CGEN_CPU_DESC cd, |
| 123 | long value, |
| 124 | unsigned int attrs, |
| 125 | unsigned int word_offset, |
| 126 | unsigned int start, |
| 127 | unsigned int length, |
| 128 | unsigned int word_length, |
| 129 | unsigned int total_length, |
| 130 | CGEN_INSN_BYTES_PTR buffer) |
| 131 | { |
| 132 | static char errbuf[100]; |
| 133 | /* Written this way to avoid undefined behaviour. */ |
| 134 | unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; |
| 135 | |
| 136 | /* If LENGTH is zero, this operand doesn't contribute to the value. */ |
| 137 | if (length == 0) |
| 138 | return NULL; |
| 139 | |
| 140 | if (word_length > 32) |
| 141 | abort (); |
| 142 | |
| 143 | /* For architectures with insns smaller than the base-insn-bitsize, |
| 144 | word_length may be too big. */ |
| 145 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) |
| 146 | { |
| 147 | if (word_offset == 0 |
| 148 | && word_length > total_length) |
| 149 | word_length = total_length; |
| 150 | } |
| 151 | |
| 152 | /* Ensure VALUE will fit. */ |
| 153 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) |
| 154 | { |
| 155 | long minval = - (1L << (length - 1)); |
| 156 | unsigned long maxval = mask; |
| 157 | |
| 158 | if ((value > 0 && (unsigned long) value > maxval) |
| 159 | || value < minval) |
| 160 | { |
| 161 | /* xgettext:c-format */ |
| 162 | sprintf (errbuf, |
| 163 | _("operand out of range (%ld not between %ld and %lu)"), |
| 164 | value, minval, maxval); |
| 165 | return errbuf; |
| 166 | } |
| 167 | } |
| 168 | else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) |
| 169 | { |
| 170 | unsigned long maxval = mask; |
| 171 | unsigned long val = (unsigned long) value; |
| 172 | |
| 173 | /* For hosts with a word size > 32 check to see if value has been sign |
| 174 | extended beyond 32 bits. If so then ignore these higher sign bits |
| 175 | as the user is attempting to store a 32-bit signed value into an |
| 176 | unsigned 32-bit field which is allowed. */ |
| 177 | if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) |
| 178 | val &= 0xFFFFFFFF; |
| 179 | |
| 180 | if (val > maxval) |
| 181 | { |
| 182 | /* xgettext:c-format */ |
| 183 | sprintf (errbuf, |
| 184 | _("operand out of range (0x%lx not between 0 and 0x%lx)"), |
| 185 | val, maxval); |
| 186 | return errbuf; |
| 187 | } |
| 188 | } |
| 189 | else |
| 190 | { |
| 191 | if (! cgen_signed_overflow_ok_p (cd)) |
| 192 | { |
| 193 | long minval = - (1L << (length - 1)); |
| 194 | long maxval = (1L << (length - 1)) - 1; |
| 195 | |
| 196 | if (value < minval || value > maxval) |
| 197 | { |
| 198 | sprintf |
| 199 | /* xgettext:c-format */ |
| 200 | (errbuf, _("operand out of range (%ld not between %ld and %ld)"), |
| 201 | value, minval, maxval); |
| 202 | return errbuf; |
| 203 | } |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | #if CGEN_INT_INSN_P |
| 208 | |
| 209 | { |
| 210 | int shift; |
| 211 | |
| 212 | if (CGEN_INSN_LSB0_P) |
| 213 | shift = (word_offset + start + 1) - length; |
| 214 | else |
| 215 | shift = total_length - (word_offset + start + length); |
| 216 | *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); |
| 217 | } |
| 218 | |
| 219 | #else /* ! CGEN_INT_INSN_P */ |
| 220 | |
| 221 | { |
| 222 | unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; |
| 223 | |
| 224 | insert_1 (cd, value, start, length, word_length, bufp); |
| 225 | } |
| 226 | |
| 227 | #endif /* ! CGEN_INT_INSN_P */ |
| 228 | |
| 229 | return NULL; |
| 230 | } |
| 231 | |
| 232 | /* Default insn builder (insert handler). |
| 233 | The instruction is recorded in CGEN_INT_INSN_P byte order (meaning |
| 234 | that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is |
| 235 | recorded in host byte order, otherwise BUFFER is an array of bytes |
| 236 | and the value is recorded in target byte order). |
| 237 | The result is an error message or NULL if success. */ |
| 238 | |
| 239 | static const char * |
| 240 | insert_insn_normal (CGEN_CPU_DESC cd, |
| 241 | const CGEN_INSN * insn, |
| 242 | CGEN_FIELDS * fields, |
| 243 | CGEN_INSN_BYTES_PTR buffer, |
| 244 | bfd_vma pc) |
| 245 | { |
| 246 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); |
| 247 | unsigned long value; |
| 248 | const CGEN_SYNTAX_CHAR_TYPE * syn; |
| 249 | |
| 250 | CGEN_INIT_INSERT (cd); |
| 251 | value = CGEN_INSN_BASE_VALUE (insn); |
| 252 | |
| 253 | /* If we're recording insns as numbers (rather than a string of bytes), |
| 254 | target byte order handling is deferred until later. */ |
| 255 | |
| 256 | #if CGEN_INT_INSN_P |
| 257 | |
| 258 | put_insn_int_value (cd, buffer, cd->base_insn_bitsize, |
| 259 | CGEN_FIELDS_BITSIZE (fields), value); |
| 260 | |
| 261 | #else |
| 262 | |
| 263 | cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, |
| 264 | (unsigned) CGEN_FIELDS_BITSIZE (fields)), |
| 265 | value); |
| 266 | |
| 267 | #endif /* ! CGEN_INT_INSN_P */ |
| 268 | |
| 269 | /* ??? It would be better to scan the format's fields. |
| 270 | Still need to be able to insert a value based on the operand though; |
| 271 | e.g. storing a branch displacement that got resolved later. |
| 272 | Needs more thought first. */ |
| 273 | |
| 274 | for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) |
| 275 | { |
| 276 | const char *errmsg; |
| 277 | |
| 278 | if (CGEN_SYNTAX_CHAR_P (* syn)) |
| 279 | continue; |
| 280 | |
| 281 | errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), |
| 282 | fields, buffer, pc); |
| 283 | if (errmsg) |
| 284 | return errmsg; |
| 285 | } |
| 286 | |
| 287 | return NULL; |
| 288 | } |
| 289 | |
| 290 | #if CGEN_INT_INSN_P |
| 291 | /* Cover function to store an insn value into an integral insn. Must go here |
| 292 | because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ |
| 293 | |
| 294 | static void |
| 295 | put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
| 296 | CGEN_INSN_BYTES_PTR buf, |
| 297 | int length, |
| 298 | int insn_length, |
| 299 | CGEN_INSN_INT value) |
| 300 | { |
| 301 | /* For architectures with insns smaller than the base-insn-bitsize, |
| 302 | length may be too big. */ |
| 303 | if (length > insn_length) |
| 304 | *buf = value; |
| 305 | else |
| 306 | { |
| 307 | int shift = insn_length - length; |
| 308 | /* Written this way to avoid undefined behaviour. */ |
| 309 | CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; |
| 310 | |
| 311 | *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); |
| 312 | } |
| 313 | } |
| 314 | #endif |
| 315 | \f |
| 316 | /* Operand extraction. */ |
| 317 | |
| 318 | #if ! CGEN_INT_INSN_P |
| 319 | |
| 320 | /* Subroutine of extract_normal. |
| 321 | Ensure sufficient bytes are cached in EX_INFO. |
| 322 | OFFSET is the offset in bytes from the start of the insn of the value. |
| 323 | BYTES is the length of the needed value. |
| 324 | Returns 1 for success, 0 for failure. */ |
| 325 | |
| 326 | static CGEN_INLINE int |
| 327 | fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
| 328 | CGEN_EXTRACT_INFO *ex_info, |
| 329 | int offset, |
| 330 | int bytes, |
| 331 | bfd_vma pc) |
| 332 | { |
| 333 | /* It's doubtful that the middle part has already been fetched so |
| 334 | we don't optimize that case. kiss. */ |
| 335 | unsigned int mask; |
| 336 | disassemble_info *info = (disassemble_info *) ex_info->dis_info; |
| 337 | |
| 338 | /* First do a quick check. */ |
| 339 | mask = (1 << bytes) - 1; |
| 340 | if (((ex_info->valid >> offset) & mask) == mask) |
| 341 | return 1; |
| 342 | |
| 343 | /* Search for the first byte we need to read. */ |
| 344 | for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) |
| 345 | if (! (mask & ex_info->valid)) |
| 346 | break; |
| 347 | |
| 348 | if (bytes) |
| 349 | { |
| 350 | int status; |
| 351 | |
| 352 | pc += offset; |
| 353 | status = (*info->read_memory_func) |
| 354 | (pc, ex_info->insn_bytes + offset, bytes, info); |
| 355 | |
| 356 | if (status != 0) |
| 357 | { |
| 358 | (*info->memory_error_func) (status, pc, info); |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | ex_info->valid |= ((1 << bytes) - 1) << offset; |
| 363 | } |
| 364 | |
| 365 | return 1; |
| 366 | } |
| 367 | |
| 368 | /* Subroutine of extract_normal. */ |
| 369 | |
| 370 | static CGEN_INLINE long |
| 371 | extract_1 (CGEN_CPU_DESC cd, |
| 372 | CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, |
| 373 | int start, |
| 374 | int length, |
| 375 | int word_length, |
| 376 | unsigned char *bufp, |
| 377 | bfd_vma pc ATTRIBUTE_UNUSED) |
| 378 | { |
| 379 | unsigned long x; |
| 380 | int shift; |
| 381 | |
| 382 | x = cgen_get_insn_value (cd, bufp, word_length); |
| 383 | |
| 384 | if (CGEN_INSN_LSB0_P) |
| 385 | shift = (start + 1) - length; |
| 386 | else |
| 387 | shift = (word_length - (start + length)); |
| 388 | return x >> shift; |
| 389 | } |
| 390 | |
| 391 | #endif /* ! CGEN_INT_INSN_P */ |
| 392 | |
| 393 | /* Default extraction routine. |
| 394 | |
| 395 | INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, |
| 396 | or sometimes less for cases like the m32r where the base insn size is 32 |
| 397 | but some insns are 16 bits. |
| 398 | ATTRS is a mask of the boolean attributes. We only need `SIGNED', |
| 399 | but for generality we take a bitmask of all of them. |
| 400 | WORD_OFFSET is the offset in bits from the start of the insn of the value. |
| 401 | WORD_LENGTH is the length of the word in bits in which the value resides. |
| 402 | START is the starting bit number in the word, architecture origin. |
| 403 | LENGTH is the length of VALUE in bits. |
| 404 | TOTAL_LENGTH is the total length of the insn in bits. |
| 405 | |
| 406 | Returns 1 for success, 0 for failure. */ |
| 407 | |
| 408 | /* ??? The return code isn't properly used. wip. */ |
| 409 | |
| 410 | /* ??? This doesn't handle bfd_vma's. Create another function when |
| 411 | necessary. */ |
| 412 | |
| 413 | static int |
| 414 | extract_normal (CGEN_CPU_DESC cd, |
| 415 | #if ! CGEN_INT_INSN_P |
| 416 | CGEN_EXTRACT_INFO *ex_info, |
| 417 | #else |
| 418 | CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, |
| 419 | #endif |
| 420 | CGEN_INSN_INT insn_value, |
| 421 | unsigned int attrs, |
| 422 | unsigned int word_offset, |
| 423 | unsigned int start, |
| 424 | unsigned int length, |
| 425 | unsigned int word_length, |
| 426 | unsigned int total_length, |
| 427 | #if ! CGEN_INT_INSN_P |
| 428 | bfd_vma pc, |
| 429 | #else |
| 430 | bfd_vma pc ATTRIBUTE_UNUSED, |
| 431 | #endif |
| 432 | long *valuep) |
| 433 | { |
| 434 | long value, mask; |
| 435 | |
| 436 | /* If LENGTH is zero, this operand doesn't contribute to the value |
| 437 | so give it a standard value of zero. */ |
| 438 | if (length == 0) |
| 439 | { |
| 440 | *valuep = 0; |
| 441 | return 1; |
| 442 | } |
| 443 | |
| 444 | if (word_length > 32) |
| 445 | abort (); |
| 446 | |
| 447 | /* For architectures with insns smaller than the insn-base-bitsize, |
| 448 | word_length may be too big. */ |
| 449 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) |
| 450 | { |
| 451 | if (word_offset + word_length > total_length) |
| 452 | word_length = total_length - word_offset; |
| 453 | } |
| 454 | |
| 455 | /* Does the value reside in INSN_VALUE, and at the right alignment? */ |
| 456 | |
| 457 | if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) |
| 458 | { |
| 459 | if (CGEN_INSN_LSB0_P) |
| 460 | value = insn_value >> ((word_offset + start + 1) - length); |
| 461 | else |
| 462 | value = insn_value >> (total_length - ( word_offset + start + length)); |
| 463 | } |
| 464 | |
| 465 | #if ! CGEN_INT_INSN_P |
| 466 | |
| 467 | else |
| 468 | { |
| 469 | unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; |
| 470 | |
| 471 | if (word_length > 32) |
| 472 | abort (); |
| 473 | |
| 474 | if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) |
| 475 | return 0; |
| 476 | |
| 477 | value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); |
| 478 | } |
| 479 | |
| 480 | #endif /* ! CGEN_INT_INSN_P */ |
| 481 | |
| 482 | /* Written this way to avoid undefined behaviour. */ |
| 483 | mask = (((1L << (length - 1)) - 1) << 1) | 1; |
| 484 | |
| 485 | value &= mask; |
| 486 | /* sign extend? */ |
| 487 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) |
| 488 | && (value & (1L << (length - 1)))) |
| 489 | value |= ~mask; |
| 490 | |
| 491 | *valuep = value; |
| 492 | |
| 493 | return 1; |
| 494 | } |
| 495 | |
| 496 | /* Default insn extractor. |
| 497 | |
| 498 | INSN_VALUE is the first base_insn_bitsize bits, translated to host order. |
| 499 | The extracted fields are stored in FIELDS. |
| 500 | EX_INFO is used to handle reading variable length insns. |
| 501 | Return the length of the insn in bits, or 0 if no match, |
| 502 | or -1 if an error occurs fetching data (memory_error_func will have |
| 503 | been called). */ |
| 504 | |
| 505 | static int |
| 506 | extract_insn_normal (CGEN_CPU_DESC cd, |
| 507 | const CGEN_INSN *insn, |
| 508 | CGEN_EXTRACT_INFO *ex_info, |
| 509 | CGEN_INSN_INT insn_value, |
| 510 | CGEN_FIELDS *fields, |
| 511 | bfd_vma pc) |
| 512 | { |
| 513 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); |
| 514 | const CGEN_SYNTAX_CHAR_TYPE *syn; |
| 515 | |
| 516 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); |
| 517 | |
| 518 | CGEN_INIT_EXTRACT (cd); |
| 519 | |
| 520 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) |
| 521 | { |
| 522 | int length; |
| 523 | |
| 524 | if (CGEN_SYNTAX_CHAR_P (*syn)) |
| 525 | continue; |
| 526 | |
| 527 | length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), |
| 528 | ex_info, insn_value, fields, pc); |
| 529 | if (length <= 0) |
| 530 | return length; |
| 531 | } |
| 532 | |
| 533 | /* We recognized and successfully extracted this insn. */ |
| 534 | return CGEN_INSN_BITSIZE (insn); |
| 535 | } |
| 536 | \f |
| 537 | /* Machine generated code added here. */ |
| 538 | |
| 539 | const char * openrisc_cgen_insert_operand |
| 540 | (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); |
| 541 | |
| 542 | /* Main entry point for operand insertion. |
| 543 | |
| 544 | This function is basically just a big switch statement. Earlier versions |
| 545 | used tables to look up the function to use, but |
| 546 | - if the table contains both assembler and disassembler functions then |
| 547 | the disassembler contains much of the assembler and vice-versa, |
| 548 | - there's a lot of inlining possibilities as things grow, |
| 549 | - using a switch statement avoids the function call overhead. |
| 550 | |
| 551 | This function could be moved into `parse_insn_normal', but keeping it |
| 552 | separate makes clear the interface between `parse_insn_normal' and each of |
| 553 | the handlers. It's also needed by GAS to insert operands that couldn't be |
| 554 | resolved during parsing. */ |
| 555 | |
| 556 | const char * |
| 557 | openrisc_cgen_insert_operand (CGEN_CPU_DESC cd, |
| 558 | int opindex, |
| 559 | CGEN_FIELDS * fields, |
| 560 | CGEN_INSN_BYTES_PTR buffer, |
| 561 | bfd_vma pc ATTRIBUTE_UNUSED) |
| 562 | { |
| 563 | const char * errmsg = NULL; |
| 564 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); |
| 565 | |
| 566 | switch (opindex) |
| 567 | { |
| 568 | case OPENRISC_OPERAND_ABS_26 : |
| 569 | { |
| 570 | long value = fields->f_abs26; |
| 571 | value = ((unsigned int) (pc) >> (2)); |
| 572 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, buffer); |
| 573 | } |
| 574 | break; |
| 575 | case OPENRISC_OPERAND_DISP_26 : |
| 576 | { |
| 577 | long value = fields->f_disp26; |
| 578 | value = ((int) (((value) - (pc))) >> (2)); |
| 579 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); |
| 580 | } |
| 581 | break; |
| 582 | case OPENRISC_OPERAND_HI16 : |
| 583 | errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); |
| 584 | break; |
| 585 | case OPENRISC_OPERAND_LO16 : |
| 586 | errmsg = insert_normal (cd, fields->f_lo16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); |
| 587 | break; |
| 588 | case OPENRISC_OPERAND_OP_F_23 : |
| 589 | errmsg = insert_normal (cd, fields->f_op4, 0, 0, 23, 3, 32, total_length, buffer); |
| 590 | break; |
| 591 | case OPENRISC_OPERAND_OP_F_3 : |
| 592 | errmsg = insert_normal (cd, fields->f_op5, 0, 0, 25, 5, 32, total_length, buffer); |
| 593 | break; |
| 594 | case OPENRISC_OPERAND_RA : |
| 595 | errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); |
| 596 | break; |
| 597 | case OPENRISC_OPERAND_RB : |
| 598 | errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); |
| 599 | break; |
| 600 | case OPENRISC_OPERAND_RD : |
| 601 | errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); |
| 602 | break; |
| 603 | case OPENRISC_OPERAND_SIMM_16 : |
| 604 | errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); |
| 605 | break; |
| 606 | case OPENRISC_OPERAND_UI16NC : |
| 607 | { |
| 608 | { |
| 609 | FLD (f_i16_2) = ((((unsigned int) (FLD (f_i16nc)) >> (11))) & (31)); |
| 610 | FLD (f_i16_1) = ((FLD (f_i16nc)) & (2047)); |
| 611 | } |
| 612 | errmsg = insert_normal (cd, fields->f_i16_1, 0, 0, 10, 11, 32, total_length, buffer); |
| 613 | if (errmsg) |
| 614 | break; |
| 615 | errmsg = insert_normal (cd, fields->f_i16_2, 0, 0, 25, 5, 32, total_length, buffer); |
| 616 | if (errmsg) |
| 617 | break; |
| 618 | } |
| 619 | break; |
| 620 | case OPENRISC_OPERAND_UIMM_16 : |
| 621 | errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); |
| 622 | break; |
| 623 | case OPENRISC_OPERAND_UIMM_5 : |
| 624 | errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 4, 5, 32, total_length, buffer); |
| 625 | break; |
| 626 | |
| 627 | default : |
| 628 | /* xgettext:c-format */ |
| 629 | fprintf (stderr, _("Unrecognized field %d while building insn.\n"), |
| 630 | opindex); |
| 631 | abort (); |
| 632 | } |
| 633 | |
| 634 | return errmsg; |
| 635 | } |
| 636 | |
| 637 | int openrisc_cgen_extract_operand |
| 638 | (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); |
| 639 | |
| 640 | /* Main entry point for operand extraction. |
| 641 | The result is <= 0 for error, >0 for success. |
| 642 | ??? Actual values aren't well defined right now. |
| 643 | |
| 644 | This function is basically just a big switch statement. Earlier versions |
| 645 | used tables to look up the function to use, but |
| 646 | - if the table contains both assembler and disassembler functions then |
| 647 | the disassembler contains much of the assembler and vice-versa, |
| 648 | - there's a lot of inlining possibilities as things grow, |
| 649 | - using a switch statement avoids the function call overhead. |
| 650 | |
| 651 | This function could be moved into `print_insn_normal', but keeping it |
| 652 | separate makes clear the interface between `print_insn_normal' and each of |
| 653 | the handlers. */ |
| 654 | |
| 655 | int |
| 656 | openrisc_cgen_extract_operand (CGEN_CPU_DESC cd, |
| 657 | int opindex, |
| 658 | CGEN_EXTRACT_INFO *ex_info, |
| 659 | CGEN_INSN_INT insn_value, |
| 660 | CGEN_FIELDS * fields, |
| 661 | bfd_vma pc) |
| 662 | { |
| 663 | /* Assume success (for those operands that are nops). */ |
| 664 | int length = 1; |
| 665 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); |
| 666 | |
| 667 | switch (opindex) |
| 668 | { |
| 669 | case OPENRISC_OPERAND_ABS_26 : |
| 670 | { |
| 671 | long value; |
| 672 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, pc, & value); |
| 673 | value = ((value) << (2)); |
| 674 | fields->f_abs26 = value; |
| 675 | } |
| 676 | break; |
| 677 | case OPENRISC_OPERAND_DISP_26 : |
| 678 | { |
| 679 | long value; |
| 680 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); |
| 681 | value = ((((value) << (2))) + (pc)); |
| 682 | fields->f_disp26 = value; |
| 683 | } |
| 684 | break; |
| 685 | case OPENRISC_OPERAND_HI16 : |
| 686 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); |
| 687 | break; |
| 688 | case OPENRISC_OPERAND_LO16 : |
| 689 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_lo16); |
| 690 | break; |
| 691 | case OPENRISC_OPERAND_OP_F_23 : |
| 692 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_op4); |
| 693 | break; |
| 694 | case OPENRISC_OPERAND_OP_F_3 : |
| 695 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_op5); |
| 696 | break; |
| 697 | case OPENRISC_OPERAND_RA : |
| 698 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); |
| 699 | break; |
| 700 | case OPENRISC_OPERAND_RB : |
| 701 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); |
| 702 | break; |
| 703 | case OPENRISC_OPERAND_RD : |
| 704 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); |
| 705 | break; |
| 706 | case OPENRISC_OPERAND_SIMM_16 : |
| 707 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); |
| 708 | break; |
| 709 | case OPENRISC_OPERAND_UI16NC : |
| 710 | { |
| 711 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_i16_1); |
| 712 | if (length <= 0) break; |
| 713 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); |
| 714 | if (length <= 0) break; |
| 715 | { |
| 716 | FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); |
| 717 | } |
| 718 | } |
| 719 | break; |
| 720 | case OPENRISC_OPERAND_UIMM_16 : |
| 721 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); |
| 722 | break; |
| 723 | case OPENRISC_OPERAND_UIMM_5 : |
| 724 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_uimm5); |
| 725 | break; |
| 726 | |
| 727 | default : |
| 728 | /* xgettext:c-format */ |
| 729 | fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), |
| 730 | opindex); |
| 731 | abort (); |
| 732 | } |
| 733 | |
| 734 | return length; |
| 735 | } |
| 736 | |
| 737 | cgen_insert_fn * const openrisc_cgen_insert_handlers[] = |
| 738 | { |
| 739 | insert_insn_normal, |
| 740 | }; |
| 741 | |
| 742 | cgen_extract_fn * const openrisc_cgen_extract_handlers[] = |
| 743 | { |
| 744 | extract_insn_normal, |
| 745 | }; |
| 746 | |
| 747 | int openrisc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); |
| 748 | bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); |
| 749 | |
| 750 | /* Getting values from cgen_fields is handled by a collection of functions. |
| 751 | They are distinguished by the type of the VALUE argument they return. |
| 752 | TODO: floating point, inlining support, remove cases where result type |
| 753 | not appropriate. */ |
| 754 | |
| 755 | int |
| 756 | openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
| 757 | int opindex, |
| 758 | const CGEN_FIELDS * fields) |
| 759 | { |
| 760 | int value; |
| 761 | |
| 762 | switch (opindex) |
| 763 | { |
| 764 | case OPENRISC_OPERAND_ABS_26 : |
| 765 | value = fields->f_abs26; |
| 766 | break; |
| 767 | case OPENRISC_OPERAND_DISP_26 : |
| 768 | value = fields->f_disp26; |
| 769 | break; |
| 770 | case OPENRISC_OPERAND_HI16 : |
| 771 | value = fields->f_simm16; |
| 772 | break; |
| 773 | case OPENRISC_OPERAND_LO16 : |
| 774 | value = fields->f_lo16; |
| 775 | break; |
| 776 | case OPENRISC_OPERAND_OP_F_23 : |
| 777 | value = fields->f_op4; |
| 778 | break; |
| 779 | case OPENRISC_OPERAND_OP_F_3 : |
| 780 | value = fields->f_op5; |
| 781 | break; |
| 782 | case OPENRISC_OPERAND_RA : |
| 783 | value = fields->f_r2; |
| 784 | break; |
| 785 | case OPENRISC_OPERAND_RB : |
| 786 | value = fields->f_r3; |
| 787 | break; |
| 788 | case OPENRISC_OPERAND_RD : |
| 789 | value = fields->f_r1; |
| 790 | break; |
| 791 | case OPENRISC_OPERAND_SIMM_16 : |
| 792 | value = fields->f_simm16; |
| 793 | break; |
| 794 | case OPENRISC_OPERAND_UI16NC : |
| 795 | value = fields->f_i16nc; |
| 796 | break; |
| 797 | case OPENRISC_OPERAND_UIMM_16 : |
| 798 | value = fields->f_uimm16; |
| 799 | break; |
| 800 | case OPENRISC_OPERAND_UIMM_5 : |
| 801 | value = fields->f_uimm5; |
| 802 | break; |
| 803 | |
| 804 | default : |
| 805 | /* xgettext:c-format */ |
| 806 | fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), |
| 807 | opindex); |
| 808 | abort (); |
| 809 | } |
| 810 | |
| 811 | return value; |
| 812 | } |
| 813 | |
| 814 | bfd_vma |
| 815 | openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
| 816 | int opindex, |
| 817 | const CGEN_FIELDS * fields) |
| 818 | { |
| 819 | bfd_vma value; |
| 820 | |
| 821 | switch (opindex) |
| 822 | { |
| 823 | case OPENRISC_OPERAND_ABS_26 : |
| 824 | value = fields->f_abs26; |
| 825 | break; |
| 826 | case OPENRISC_OPERAND_DISP_26 : |
| 827 | value = fields->f_disp26; |
| 828 | break; |
| 829 | case OPENRISC_OPERAND_HI16 : |
| 830 | value = fields->f_simm16; |
| 831 | break; |
| 832 | case OPENRISC_OPERAND_LO16 : |
| 833 | value = fields->f_lo16; |
| 834 | break; |
| 835 | case OPENRISC_OPERAND_OP_F_23 : |
| 836 | value = fields->f_op4; |
| 837 | break; |
| 838 | case OPENRISC_OPERAND_OP_F_3 : |
| 839 | value = fields->f_op5; |
| 840 | break; |
| 841 | case OPENRISC_OPERAND_RA : |
| 842 | value = fields->f_r2; |
| 843 | break; |
| 844 | case OPENRISC_OPERAND_RB : |
| 845 | value = fields->f_r3; |
| 846 | break; |
| 847 | case OPENRISC_OPERAND_RD : |
| 848 | value = fields->f_r1; |
| 849 | break; |
| 850 | case OPENRISC_OPERAND_SIMM_16 : |
| 851 | value = fields->f_simm16; |
| 852 | break; |
| 853 | case OPENRISC_OPERAND_UI16NC : |
| 854 | value = fields->f_i16nc; |
| 855 | break; |
| 856 | case OPENRISC_OPERAND_UIMM_16 : |
| 857 | value = fields->f_uimm16; |
| 858 | break; |
| 859 | case OPENRISC_OPERAND_UIMM_5 : |
| 860 | value = fields->f_uimm5; |
| 861 | break; |
| 862 | |
| 863 | default : |
| 864 | /* xgettext:c-format */ |
| 865 | fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), |
| 866 | opindex); |
| 867 | abort (); |
| 868 | } |
| 869 | |
| 870 | return value; |
| 871 | } |
| 872 | |
| 873 | void openrisc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); |
| 874 | void openrisc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); |
| 875 | |
| 876 | /* Stuffing values in cgen_fields is handled by a collection of functions. |
| 877 | They are distinguished by the type of the VALUE argument they accept. |
| 878 | TODO: floating point, inlining support, remove cases where argument type |
| 879 | not appropriate. */ |
| 880 | |
| 881 | void |
| 882 | openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
| 883 | int opindex, |
| 884 | CGEN_FIELDS * fields, |
| 885 | int value) |
| 886 | { |
| 887 | switch (opindex) |
| 888 | { |
| 889 | case OPENRISC_OPERAND_ABS_26 : |
| 890 | fields->f_abs26 = value; |
| 891 | break; |
| 892 | case OPENRISC_OPERAND_DISP_26 : |
| 893 | fields->f_disp26 = value; |
| 894 | break; |
| 895 | case OPENRISC_OPERAND_HI16 : |
| 896 | fields->f_simm16 = value; |
| 897 | break; |
| 898 | case OPENRISC_OPERAND_LO16 : |
| 899 | fields->f_lo16 = value; |
| 900 | break; |
| 901 | case OPENRISC_OPERAND_OP_F_23 : |
| 902 | fields->f_op4 = value; |
| 903 | break; |
| 904 | case OPENRISC_OPERAND_OP_F_3 : |
| 905 | fields->f_op5 = value; |
| 906 | break; |
| 907 | case OPENRISC_OPERAND_RA : |
| 908 | fields->f_r2 = value; |
| 909 | break; |
| 910 | case OPENRISC_OPERAND_RB : |
| 911 | fields->f_r3 = value; |
| 912 | break; |
| 913 | case OPENRISC_OPERAND_RD : |
| 914 | fields->f_r1 = value; |
| 915 | break; |
| 916 | case OPENRISC_OPERAND_SIMM_16 : |
| 917 | fields->f_simm16 = value; |
| 918 | break; |
| 919 | case OPENRISC_OPERAND_UI16NC : |
| 920 | fields->f_i16nc = value; |
| 921 | break; |
| 922 | case OPENRISC_OPERAND_UIMM_16 : |
| 923 | fields->f_uimm16 = value; |
| 924 | break; |
| 925 | case OPENRISC_OPERAND_UIMM_5 : |
| 926 | fields->f_uimm5 = value; |
| 927 | break; |
| 928 | |
| 929 | default : |
| 930 | /* xgettext:c-format */ |
| 931 | fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), |
| 932 | opindex); |
| 933 | abort (); |
| 934 | } |
| 935 | } |
| 936 | |
| 937 | void |
| 938 | openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
| 939 | int opindex, |
| 940 | CGEN_FIELDS * fields, |
| 941 | bfd_vma value) |
| 942 | { |
| 943 | switch (opindex) |
| 944 | { |
| 945 | case OPENRISC_OPERAND_ABS_26 : |
| 946 | fields->f_abs26 = value; |
| 947 | break; |
| 948 | case OPENRISC_OPERAND_DISP_26 : |
| 949 | fields->f_disp26 = value; |
| 950 | break; |
| 951 | case OPENRISC_OPERAND_HI16 : |
| 952 | fields->f_simm16 = value; |
| 953 | break; |
| 954 | case OPENRISC_OPERAND_LO16 : |
| 955 | fields->f_lo16 = value; |
| 956 | break; |
| 957 | case OPENRISC_OPERAND_OP_F_23 : |
| 958 | fields->f_op4 = value; |
| 959 | break; |
| 960 | case OPENRISC_OPERAND_OP_F_3 : |
| 961 | fields->f_op5 = value; |
| 962 | break; |
| 963 | case OPENRISC_OPERAND_RA : |
| 964 | fields->f_r2 = value; |
| 965 | break; |
| 966 | case OPENRISC_OPERAND_RB : |
| 967 | fields->f_r3 = value; |
| 968 | break; |
| 969 | case OPENRISC_OPERAND_RD : |
| 970 | fields->f_r1 = value; |
| 971 | break; |
| 972 | case OPENRISC_OPERAND_SIMM_16 : |
| 973 | fields->f_simm16 = value; |
| 974 | break; |
| 975 | case OPENRISC_OPERAND_UI16NC : |
| 976 | fields->f_i16nc = value; |
| 977 | break; |
| 978 | case OPENRISC_OPERAND_UIMM_16 : |
| 979 | fields->f_uimm16 = value; |
| 980 | break; |
| 981 | case OPENRISC_OPERAND_UIMM_5 : |
| 982 | fields->f_uimm5 = value; |
| 983 | break; |
| 984 | |
| 985 | default : |
| 986 | /* xgettext:c-format */ |
| 987 | fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), |
| 988 | opindex); |
| 989 | abort (); |
| 990 | } |
| 991 | } |
| 992 | |
| 993 | /* Function to call before using the instruction builder tables. */ |
| 994 | |
| 995 | void |
| 996 | openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd) |
| 997 | { |
| 998 | cd->insert_handlers = & openrisc_cgen_insert_handlers[0]; |
| 999 | cd->extract_handlers = & openrisc_cgen_extract_handlers[0]; |
| 1000 | |
| 1001 | cd->insert_operand = openrisc_cgen_insert_operand; |
| 1002 | cd->extract_operand = openrisc_cgen_extract_operand; |
| 1003 | |
| 1004 | cd->get_int_operand = openrisc_cgen_get_int_operand; |
| 1005 | cd->set_int_operand = openrisc_cgen_set_int_operand; |
| 1006 | cd->get_vma_operand = openrisc_cgen_get_vma_operand; |
| 1007 | cd->set_vma_operand = openrisc_cgen_set_vma_operand; |
| 1008 | } |