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1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22#include "sysdep.h"
23#include <stdio.h>
24#include "disassemble.h"
25#include "elf-bfd.h"
26#include "elf/ppc.h"
27#include "opintl.h"
28#include "opcode/ppc.h"
29#include "libiberty.h"
30
31/* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
35 chip. */
36static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
37 ppc_cpu_t);
38
39struct dis_private
40{
41 /* Stash the result of parsing disassembler_options here. */
42 ppc_cpu_t dialect;
43} private;
44
45#define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
47
48struct ppc_mopt {
49 /* Option string, without -m or -M prefix. */
50 const char *opt;
51 /* CPU option flags. */
52 ppc_cpu_t cpu;
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
61 prior -m option. */
62 ppc_cpu_t sticky;
63};
64
65struct ppc_mopt ppc_opts[] = {
66 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
67 0 },
68 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
69 0 },
70 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
71 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
72 0 },
73 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
74 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
75 0 },
76 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
77 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
78 0 },
79 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
80 0 },
81 { "603", PPC_OPCODE_PPC,
82 0 },
83 { "604", PPC_OPCODE_PPC,
84 0 },
85 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
86 0 },
87 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
88 0 },
89 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
90 0 },
91 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
92 0 },
93 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
94 0 },
95 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
96 , 0 },
97 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
98 0 },
99 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
100 0 },
101 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
102 0 },
103 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
104 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
105 | PPC_OPCODE_A2),
106 0 },
107 { "altivec", PPC_OPCODE_PPC,
108 PPC_OPCODE_ALTIVEC },
109 { "any", PPC_OPCODE_PPC,
110 PPC_OPCODE_ANY },
111 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
112 0 },
113 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
114 0 },
115 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
116 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
117 0 },
118 { "com", PPC_OPCODE_COMMON,
119 0 },
120 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
121 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
122 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
123 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
124 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
125 0 },
126 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
127 0 },
128 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
129 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
130 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
131 | PPC_OPCODE_E500),
132 0 },
133 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
134 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
135 | PPC_OPCODE_E500MC),
136 0 },
137 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
140 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
141 0 },
142 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
143 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
144 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
145 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
146 0 },
147 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
148 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
149 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
150 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
151 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
152 0 },
153 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
154 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
155 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
156 | PPC_OPCODE_E500),
157 0 },
158 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
159 0 },
160 { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
161 0 },
162 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
163 0 },
164 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
165 | PPC_OPCODE_POWER5),
166 0 },
167 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
168 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
169 0 },
170 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
171 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
172 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
173 0 },
174 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
175 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
177 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
178 0 },
179 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
180 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
181 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
182 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
183 0 },
184 { "ppc", PPC_OPCODE_PPC,
185 0 },
186 { "ppc32", PPC_OPCODE_PPC,
187 0 },
188 { "32", PPC_OPCODE_PPC,
189 0 },
190 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
191 0 },
192 { "64", PPC_OPCODE_PPC | PPC_OPCODE_64,
193 0 },
194 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
195 0 },
196 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
197 0 },
198 { "pwr", PPC_OPCODE_POWER,
199 0 },
200 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
201 0 },
202 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
203 0 },
204 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
205 | PPC_OPCODE_POWER5),
206 0 },
207 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
208 | PPC_OPCODE_POWER5),
209 0 },
210 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
211 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
212 0 },
213 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
214 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
215 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
216 0 },
217 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
218 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
219 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
220 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
221 0 },
222 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
223 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
224 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
225 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
226 0 },
227 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
228 0 },
229 { "raw", PPC_OPCODE_PPC,
230 PPC_OPCODE_RAW },
231 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
232 PPC_OPCODE_SPE },
233 { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
234 PPC_OPCODE_SPE2 },
235 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
236 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
237 0 },
238 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
239 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
240 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
241 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
242 PPC_OPCODE_VLE },
243 { "vsx", PPC_OPCODE_PPC,
244 PPC_OPCODE_VSX },
245};
246
247/* Switch between Booke and VLE dialects for interlinked dumps. */
248static ppc_cpu_t
249get_powerpc_dialect (struct disassemble_info *info)
250{
251 ppc_cpu_t dialect = 0;
252
253 dialect = POWERPC_DIALECT (info);
254
255 /* Disassemble according to the section headers flags for VLE-mode. */
256 if (dialect & PPC_OPCODE_VLE
257 && info->section != NULL && info->section->owner != NULL
258 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
259 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
260 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
261 return dialect;
262 else
263 return dialect & ~ PPC_OPCODE_VLE;
264}
265
266/* Handle -m and -M options that set cpu type, and .machine arg. */
267
268ppc_cpu_t
269ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
270{
271 unsigned int i;
272
273 for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
274 if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
275 {
276 if (ppc_opts[i].sticky)
277 {
278 *sticky |= ppc_opts[i].sticky;
279 if ((ppc_cpu & ~*sticky) != 0)
280 break;
281 }
282 ppc_cpu = ppc_opts[i].cpu;
283 break;
284 }
285 if (i >= ARRAY_SIZE (ppc_opts))
286 return 0;
287
288 ppc_cpu |= *sticky;
289 return ppc_cpu;
290}
291
292/* Determine which set of machines to disassemble for. */
293
294static void
295powerpc_init_dialect (struct disassemble_info *info)
296{
297 ppc_cpu_t dialect = 0;
298 ppc_cpu_t sticky = 0;
299 struct dis_private *priv = calloc (sizeof (*priv), 1);
300
301 if (priv == NULL)
302 priv = &private;
303
304 switch (info->mach)
305 {
306 case bfd_mach_ppc_403:
307 case bfd_mach_ppc_403gc:
308 dialect = ppc_parse_cpu (dialect, &sticky, "403");
309 break;
310 case bfd_mach_ppc_405:
311 dialect = ppc_parse_cpu (dialect, &sticky, "405");
312 break;
313 case bfd_mach_ppc_601:
314 dialect = ppc_parse_cpu (dialect, &sticky, "601");
315 break;
316 case bfd_mach_ppc_a35:
317 case bfd_mach_ppc_rs64ii:
318 case bfd_mach_ppc_rs64iii:
319 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
320 break;
321 case bfd_mach_ppc_e500:
322 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
323 break;
324 case bfd_mach_ppc_e500mc:
325 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
326 break;
327 case bfd_mach_ppc_e500mc64:
328 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
329 break;
330 case bfd_mach_ppc_e5500:
331 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
332 break;
333 case bfd_mach_ppc_e6500:
334 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
335 break;
336 case bfd_mach_ppc_titan:
337 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
338 break;
339 case bfd_mach_ppc_vle:
340 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
341 break;
342 default:
343 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
344 break;
345 }
346
347 const char *opt;
348 FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
349 {
350 ppc_cpu_t new_cpu = 0;
351
352 if (disassembler_options_cmp (opt, "32") == 0)
353 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
354 else if (disassembler_options_cmp (opt, "64") == 0)
355 dialect |= PPC_OPCODE_64;
356 else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
357 dialect = new_cpu;
358 else
359 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), opt);
360 }
361
362 info->private_data = priv;
363 POWERPC_DIALECT(info) = dialect;
364}
365
366#define PPC_OPCD_SEGS 64
367static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
368#define VLE_OPCD_SEGS 32
369static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
370#define SPE2_OPCD_SEGS 13
371static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1];
372
373/* Calculate opcode table indices to speed up disassembly,
374 and init dialect. */
375
376void
377disassemble_init_powerpc (struct disassemble_info *info)
378{
379 int i;
380 unsigned short last;
381
382 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
383 {
384 i = powerpc_num_opcodes;
385 while (--i >= 0)
386 {
387 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
388 powerpc_opcd_indices[op] = i;
389 }
390
391 last = powerpc_num_opcodes;
392 for (i = PPC_OPCD_SEGS; i > 0; --i)
393 {
394 if (powerpc_opcd_indices[i] == 0)
395 powerpc_opcd_indices[i] = last;
396 last = powerpc_opcd_indices[i];
397 }
398
399 i = vle_num_opcodes;
400 while (--i >= 0)
401 {
402 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
403 unsigned seg = VLE_OP_TO_SEG (op);
404 vle_opcd_indices[seg] = i;
405 }
406
407 last = vle_num_opcodes;
408 for (i = VLE_OPCD_SEGS; i > 0; --i)
409 {
410 if (vle_opcd_indices[i] == 0)
411 vle_opcd_indices[i] = last;
412 last = vle_opcd_indices[i];
413 }
414 }
415
416 /* SPE2 opcodes */
417 i = spe2_num_opcodes;
418 while (--i >= 0)
419 {
420 unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
421 unsigned seg = SPE2_XOP_TO_SEG (xop);
422 spe2_opcd_indices[seg] = i;
423 }
424
425 last = spe2_num_opcodes;
426 for (i = SPE2_OPCD_SEGS; i > 1; --i)
427 {
428 if (spe2_opcd_indices[i] == 0)
429 spe2_opcd_indices[i] = last;
430 last = spe2_opcd_indices[i];
431 }
432
433 if (info->arch == bfd_arch_powerpc)
434 powerpc_init_dialect (info);
435}
436
437/* Print a big endian PowerPC instruction. */
438
439int
440print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
441{
442 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
443}
444
445/* Print a little endian PowerPC instruction. */
446
447int
448print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
449{
450 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
451}
452
453/* Print a POWER (RS/6000) instruction. */
454
455int
456print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
457{
458 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
459}
460
461/* Extract the operand value from the PowerPC or POWER instruction. */
462
463static int64_t
464operand_value_powerpc (const struct powerpc_operand *operand,
465 uint64_t insn, ppc_cpu_t dialect)
466{
467 int64_t value;
468 int invalid;
469 /* Extract the value from the instruction. */
470 if (operand->extract)
471 value = (*operand->extract) (insn, dialect, &invalid);
472 else
473 {
474 if (operand->shift >= 0)
475 value = (insn >> operand->shift) & operand->bitm;
476 else
477 value = (insn << -operand->shift) & operand->bitm;
478 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
479 {
480 /* BITM is always some number of zeros followed by some
481 number of ones, followed by some number of zeros. */
482 uint64_t top = operand->bitm;
483 /* top & -top gives the rightmost 1 bit, so this
484 fills in any trailing zeros. */
485 top |= (top & -top) - 1;
486 top &= ~(top >> 1);
487 value = (value ^ top) - top;
488 }
489 }
490
491 return value;
492}
493
494/* Determine whether the optional operand(s) should be printed. */
495
496static int
497skip_optional_operands (const unsigned char *opindex,
498 uint64_t insn, ppc_cpu_t dialect)
499{
500 const struct powerpc_operand *operand;
501
502 for (; *opindex != 0; opindex++)
503 {
504 operand = &powerpc_operands[*opindex];
505 if ((operand->flags & PPC_OPERAND_NEXT) != 0
506 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
507 && operand_value_powerpc (operand, insn, dialect) !=
508 ppc_optional_operand_value (operand)))
509 return 0;
510 }
511
512 return 1;
513}
514
515/* Find a match for INSN in the opcode table, given machine DIALECT. */
516
517static const struct powerpc_opcode *
518lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
519{
520 const struct powerpc_opcode *opcode, *opcode_end, *last;
521 unsigned long op;
522
523 /* Get the major opcode of the instruction. */
524 op = PPC_OP (insn);
525
526 /* Find the first match in the opcode table for this major opcode. */
527 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
528 last = NULL;
529 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
530 opcode < opcode_end;
531 ++opcode)
532 {
533 const unsigned char *opindex;
534 const struct powerpc_operand *operand;
535 int invalid;
536
537 if ((insn & opcode->mask) != opcode->opcode
538 || ((dialect & PPC_OPCODE_ANY) == 0
539 && ((opcode->flags & dialect) == 0
540 || (opcode->deprecated & dialect) != 0)))
541 continue;
542
543 /* Check validity of operands. */
544 invalid = 0;
545 for (opindex = opcode->operands; *opindex != 0; opindex++)
546 {
547 operand = powerpc_operands + *opindex;
548 if (operand->extract)
549 (*operand->extract) (insn, dialect, &invalid);
550 }
551 if (invalid)
552 continue;
553
554 if ((dialect & PPC_OPCODE_RAW) == 0)
555 return opcode;
556
557 /* The raw machine insn is one that is not a specialization. */
558 if (last == NULL
559 || (last->mask & ~opcode->mask) != 0)
560 last = opcode;
561 }
562
563 return last;
564}
565
566/* Find a match for INSN in the VLE opcode table. */
567
568static const struct powerpc_opcode *
569lookup_vle (uint64_t insn)
570{
571 const struct powerpc_opcode *opcode;
572 const struct powerpc_opcode *opcode_end;
573 unsigned op, seg;
574
575 op = PPC_OP (insn);
576 if (op >= 0x20 && op <= 0x37)
577 {
578 /* This insn has a 4-bit opcode. */
579 op &= 0x3c;
580 }
581 seg = VLE_OP_TO_SEG (op);
582
583 /* Find the first match in the opcode table for this major opcode. */
584 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
585 for (opcode = vle_opcodes + vle_opcd_indices[seg];
586 opcode < opcode_end;
587 ++opcode)
588 {
589 uint64_t table_opcd = opcode->opcode;
590 uint64_t table_mask = opcode->mask;
591 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
592 uint64_t insn2;
593 const unsigned char *opindex;
594 const struct powerpc_operand *operand;
595 int invalid;
596
597 insn2 = insn;
598 if (table_op_is_short)
599 insn2 >>= 16;
600 if ((insn2 & table_mask) != table_opcd)
601 continue;
602
603 /* Check validity of operands. */
604 invalid = 0;
605 for (opindex = opcode->operands; *opindex != 0; ++opindex)
606 {
607 operand = powerpc_operands + *opindex;
608 if (operand->extract)
609 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
610 }
611 if (invalid)
612 continue;
613
614 return opcode;
615 }
616
617 return NULL;
618}
619
620/* Find a match for INSN in the SPE2 opcode table. */
621
622static const struct powerpc_opcode *
623lookup_spe2 (uint64_t insn)
624{
625 const struct powerpc_opcode *opcode, *opcode_end;
626 unsigned op, xop, seg;
627
628 op = PPC_OP (insn);
629 if (op != 0x4)
630 {
631 /* This is not SPE2 insn.
632 * All SPE2 instructions have OP=4 and differs by XOP */
633 return NULL;
634 }
635 xop = SPE2_XOP (insn);
636 seg = SPE2_XOP_TO_SEG (xop);
637
638 /* Find the first match in the opcode table for this major opcode. */
639 opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
640 for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
641 opcode < opcode_end;
642 ++opcode)
643 {
644 uint64_t table_opcd = opcode->opcode;
645 uint64_t table_mask = opcode->mask;
646 uint64_t insn2;
647 const unsigned char *opindex;
648 const struct powerpc_operand *operand;
649 int invalid;
650
651 insn2 = insn;
652 if ((insn2 & table_mask) != table_opcd)
653 continue;
654
655 /* Check validity of operands. */
656 invalid = 0;
657 for (opindex = opcode->operands; *opindex != 0; ++opindex)
658 {
659 operand = powerpc_operands + *opindex;
660 if (operand->extract)
661 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
662 }
663 if (invalid)
664 continue;
665
666 return opcode;
667 }
668
669 return NULL;
670}
671
672/* Print a PowerPC or POWER instruction. */
673
674static int
675print_insn_powerpc (bfd_vma memaddr,
676 struct disassemble_info *info,
677 int bigendian,
678 ppc_cpu_t dialect)
679{
680 bfd_byte buffer[4];
681 int status;
682 uint64_t insn;
683 const struct powerpc_opcode *opcode;
684 bfd_boolean insn_is_short;
685
686 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
687 if (status != 0)
688 {
689 /* The final instruction may be a 2-byte VLE insn. */
690 if ((dialect & PPC_OPCODE_VLE) != 0)
691 {
692 /* Clear buffer so unused bytes will not have garbage in them. */
693 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
694 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
695 if (status != 0)
696 {
697 (*info->memory_error_func) (status, memaddr, info);
698 return -1;
699 }
700 }
701 else
702 {
703 (*info->memory_error_func) (status, memaddr, info);
704 return -1;
705 }
706 }
707
708 if (bigendian)
709 insn = bfd_getb32 (buffer);
710 else
711 insn = bfd_getl32 (buffer);
712
713 /* Get the major opcode of the insn. */
714 opcode = NULL;
715 insn_is_short = FALSE;
716 if ((dialect & PPC_OPCODE_VLE) != 0)
717 {
718 opcode = lookup_vle (insn);
719 if (opcode != NULL)
720 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
721 }
722 if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
723 opcode = lookup_spe2 (insn);
724 if (opcode == NULL)
725 opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
726 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
727 opcode = lookup_powerpc (insn, dialect);
728
729 if (opcode != NULL)
730 {
731 const unsigned char *opindex;
732 const struct powerpc_operand *operand;
733 int need_comma;
734 int need_paren;
735 int skip_optional;
736
737 if (opcode->operands[0] != 0)
738 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
739 else
740 (*info->fprintf_func) (info->stream, "%s", opcode->name);
741
742 if (insn_is_short)
743 /* The operands will be fetched out of the 16-bit instruction. */
744 insn >>= 16;
745
746 /* Now extract and print the operands. */
747 need_comma = 0;
748 need_paren = 0;
749 skip_optional = -1;
750 for (opindex = opcode->operands; *opindex != 0; opindex++)
751 {
752 int64_t value;
753
754 operand = powerpc_operands + *opindex;
755
756 /* Operands that are marked FAKE are simply ignored. We
757 already made sure that the extract function considered
758 the instruction to be valid. */
759 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
760 continue;
761
762 /* If all of the optional operands have the value zero,
763 then don't print any of them. */
764 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
765 {
766 if (skip_optional < 0)
767 skip_optional = skip_optional_operands (opindex, insn,
768 dialect);
769 if (skip_optional)
770 continue;
771 }
772
773 value = operand_value_powerpc (operand, insn, dialect);
774
775 if (need_comma)
776 {
777 (*info->fprintf_func) (info->stream, ",");
778 need_comma = 0;
779 }
780
781 /* Print the operand as directed by the flags. */
782 if ((operand->flags & PPC_OPERAND_GPR) != 0
783 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
784 (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
785 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
786 (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
787 else if ((operand->flags & PPC_OPERAND_VR) != 0)
788 (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
789 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
790 (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
791 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
792 (*info->print_address_func) (memaddr + value, info);
793 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
794 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
795 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
796 (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
797 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
798 (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
799 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
800 (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
801 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
802 && (((dialect & PPC_OPCODE_PPC) != 0)
803 || ((dialect & PPC_OPCODE_VLE) != 0)))
804 (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
805 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
806 && (((dialect & PPC_OPCODE_PPC) != 0)
807 || ((dialect & PPC_OPCODE_VLE) != 0)))
808 {
809 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
810 int cr;
811 int cc;
812
813 cr = value >> 2;
814 if (cr != 0)
815 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
816 cc = value & 3;
817 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
818 }
819 else
820 (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
821
822 if (need_paren)
823 {
824 (*info->fprintf_func) (info->stream, ")");
825 need_paren = 0;
826 }
827
828 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
829 need_comma = 1;
830 else
831 {
832 (*info->fprintf_func) (info->stream, "(");
833 need_paren = 1;
834 }
835 }
836
837 /* We have found and printed an instruction.
838 If it was a short VLE instruction we have more to do. */
839 if (insn_is_short)
840 {
841 memaddr += 2;
842 return 2;
843 }
844 else
845 /* Otherwise, return. */
846 return 4;
847 }
848
849 /* We could not find a match. */
850 (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
851
852 return 4;
853}
854
855const disasm_options_t *
856disassembler_options_powerpc (void)
857{
858 static disasm_options_t *opts = NULL;
859
860 if (opts == NULL)
861 {
862 size_t i, num_options = ARRAY_SIZE (ppc_opts);
863 opts = XNEW (disasm_options_t);
864 opts->name = XNEWVEC (const char *, num_options + 1);
865 for (i = 0; i < num_options; i++)
866 opts->name[i] = ppc_opts[i].opt;
867 /* The array we return must be NULL terminated. */
868 opts->name[i] = NULL;
869 opts->description = NULL;
870 }
871
872 return opts;
873}
874
875void
876print_ppc_disassembler_options (FILE *stream)
877{
878 unsigned int i, col;
879
880 fprintf (stream, _("\n\
881The following PPC specific disassembler options are supported for use with\n\
882the -M switch:\n"));
883
884 for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
885 {
886 col += fprintf (stream, " %s,", ppc_opts[i].opt);
887 if (col > 66)
888 {
889 fprintf (stream, "\n");
890 col = 0;
891 }
892 }
893 fprintf (stream, "\n");
894}
GDB Binutils - Deliverables
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