| 1 | /* -*- c -*- */ |
| 2 | #include <stdio.h> |
| 3 | #include <stdlib.h> |
| 4 | #include <string.h> |
| 5 | |
| 6 | #include "config.h" |
| 7 | #include "ansidecl.h" |
| 8 | #include "opcode/rx.h" |
| 9 | |
| 10 | #define RX_OPCODE_BIG_ENDIAN 0 |
| 11 | |
| 12 | typedef struct |
| 13 | { |
| 14 | RX_Opcode_Decoded * rx; |
| 15 | int (* getbyte)(void *); |
| 16 | void * ptr; |
| 17 | unsigned char * op; |
| 18 | } LocalData; |
| 19 | |
| 20 | static int trace = 0; |
| 21 | |
| 22 | #define BSIZE 0 |
| 23 | #define WSIZE 1 |
| 24 | #define LSIZE 2 |
| 25 | |
| 26 | /* These are for when the upper bits are "don't care" or "undefined". */ |
| 27 | static int bwl[] = |
| 28 | { |
| 29 | RX_Byte, |
| 30 | RX_Word, |
| 31 | RX_Long |
| 32 | }; |
| 33 | |
| 34 | static int sbwl[] = |
| 35 | { |
| 36 | RX_SByte, |
| 37 | RX_SWord, |
| 38 | RX_Long |
| 39 | }; |
| 40 | |
| 41 | static int ubwl[] = |
| 42 | { |
| 43 | RX_UByte, |
| 44 | RX_UWord, |
| 45 | RX_Long |
| 46 | }; |
| 47 | |
| 48 | static int memex[] = |
| 49 | { |
| 50 | RX_SByte, |
| 51 | RX_SWord, |
| 52 | RX_Long, |
| 53 | RX_UWord |
| 54 | }; |
| 55 | |
| 56 | #define ID(x) rx->id = RXO_##x |
| 57 | #define OP(n,t,r,a) (rx->op[n].type = t, \ |
| 58 | rx->op[n].reg = r, \ |
| 59 | rx->op[n].addend = a ) |
| 60 | #define OPs(n,t,r,a,s) (OP (n,t,r,a), \ |
| 61 | rx->op[n].size = s ) |
| 62 | |
| 63 | /* This is for the BWL and BW bitfields. */ |
| 64 | static int SCALE[] = { 1, 2, 4 }; |
| 65 | /* This is for the prefix size enum. */ |
| 66 | static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 }; |
| 67 | |
| 68 | static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0, |
| 69 | 16, 17, 0, 0, 0, 0, 0, 0 }; |
| 70 | |
| 71 | static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 }; |
| 72 | |
| 73 | /* |
| 74 | *C a constant (immediate) c |
| 75 | *R A register |
| 76 | *I Register indirect, no offset |
| 77 | *Is Register indirect, with offset |
| 78 | *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code |
| 79 | *P standard displacement: type (r,[r]), reg, assumes UByte |
| 80 | *Pm memex displacement: type (r,[r]), reg, memex code |
| 81 | *cc condition code. */ |
| 82 | |
| 83 | #define DC(c) OP (0, RX_Operand_Immediate, 0, c) |
| 84 | #define DR(r) OP (0, RX_Operand_Register, r, 0) |
| 85 | #define DI(r,a) OP (0, RX_Operand_Indirect, r, a) |
| 86 | #define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s]) |
| 87 | #define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld); |
| 88 | #define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0) |
| 89 | |
| 90 | #define SC(i) OP (1, RX_Operand_Immediate, 0, i) |
| 91 | #define SR(r) OP (1, RX_Operand_Register, r, 0) |
| 92 | #define SRR(r) OP (1, RX_Operand_TwoReg, r, 0) |
| 93 | #define SI(r,a) OP (1, RX_Operand_Indirect, r, a) |
| 94 | #define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s]) |
| 95 | #define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld); |
| 96 | #define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1); |
| 97 | #define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m]; |
| 98 | #define Scc(cc) OP (1, RX_Operand_Condition, cc, 0) |
| 99 | |
| 100 | #define S2C(i) OP (2, RX_Operand_Immediate, 0, i) |
| 101 | #define S2R(r) OP (2, RX_Operand_Register, r, 0) |
| 102 | #define S2I(r,a) OP (2, RX_Operand_Indirect, r, a) |
| 103 | #define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s]) |
| 104 | #define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld); |
| 105 | #define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2); |
| 106 | #define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m]; |
| 107 | #define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0) |
| 108 | |
| 109 | #define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz] |
| 110 | #define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz] |
| 111 | #define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz] |
| 112 | #define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long; |
| 113 | |
| 114 | #define F(f) store_flags(rx, f) |
| 115 | |
| 116 | #define AU ATTRIBUTE_UNUSED |
| 117 | #define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr)) |
| 118 | |
| 119 | #define SYNTAX(x) rx->syntax = x |
| 120 | |
| 121 | #define UNSUPPORTED() \ |
| 122 | rx->syntax = "*unknown*" |
| 123 | |
| 124 | #define IMM(sf) immediate (sf, 0, ld) |
| 125 | #define IMMex(sf) immediate (sf, 1, ld) |
| 126 | |
| 127 | static int |
| 128 | immediate (int sfield, int ex, LocalData * ld) |
| 129 | { |
| 130 | unsigned long i = 0, j; |
| 131 | |
| 132 | switch (sfield) |
| 133 | { |
| 134 | #define B ((unsigned long) GETBYTE()) |
| 135 | case 0: |
| 136 | #if RX_OPCODE_BIG_ENDIAN |
| 137 | i = B; |
| 138 | if (ex && (i & 0x80)) |
| 139 | i -= 0x100; |
| 140 | i <<= 24; |
| 141 | i |= B << 16; |
| 142 | i |= B << 8; |
| 143 | i |= B; |
| 144 | #else |
| 145 | i = B; |
| 146 | i |= B << 8; |
| 147 | i |= B << 16; |
| 148 | j = B; |
| 149 | if (ex && (j & 0x80)) |
| 150 | j -= 0x100; |
| 151 | i |= j << 24; |
| 152 | #endif |
| 153 | break; |
| 154 | case 3: |
| 155 | #if RX_OPCODE_BIG_ENDIAN |
| 156 | i = B << 16; |
| 157 | i |= B << 8; |
| 158 | i |= B; |
| 159 | #else |
| 160 | i = B; |
| 161 | i |= B << 8; |
| 162 | i |= B << 16; |
| 163 | #endif |
| 164 | if (ex && (i & 0x800000)) |
| 165 | i -= 0x1000000; |
| 166 | break; |
| 167 | case 2: |
| 168 | #if RX_OPCODE_BIG_ENDIAN |
| 169 | i |= B << 8; |
| 170 | i |= B; |
| 171 | #else |
| 172 | i |= B; |
| 173 | i |= B << 8; |
| 174 | #endif |
| 175 | if (ex && (i & 0x8000)) |
| 176 | i -= 0x10000; |
| 177 | break; |
| 178 | case 1: |
| 179 | i |= B; |
| 180 | if (ex && (i & 0x80)) |
| 181 | i -= 0x100; |
| 182 | break; |
| 183 | default: |
| 184 | abort(); |
| 185 | } |
| 186 | return i; |
| 187 | } |
| 188 | |
| 189 | static void |
| 190 | rx_disp (int n, int type, int reg, int size, LocalData * ld) |
| 191 | { |
| 192 | int disp; |
| 193 | |
| 194 | ld->rx->op[n].reg = reg; |
| 195 | switch (type) |
| 196 | { |
| 197 | case 3: |
| 198 | ld->rx->op[n].type = RX_Operand_Register; |
| 199 | break; |
| 200 | case 0: |
| 201 | ld->rx->op[n].type = RX_Operand_Indirect; |
| 202 | ld->rx->op[n].addend = 0; |
| 203 | break; |
| 204 | case 1: |
| 205 | ld->rx->op[n].type = RX_Operand_Indirect; |
| 206 | disp = GETBYTE (); |
| 207 | ld->rx->op[n].addend = disp * PSCALE[size]; |
| 208 | break; |
| 209 | case 2: |
| 210 | ld->rx->op[n].type = RX_Operand_Indirect; |
| 211 | disp = GETBYTE (); |
| 212 | #if RX_OPCODE_BIG_ENDIAN |
| 213 | disp = disp * 256 + GETBYTE (); |
| 214 | #else |
| 215 | disp = disp + GETBYTE () * 256; |
| 216 | #endif |
| 217 | ld->rx->op[n].addend = disp * PSCALE[size]; |
| 218 | break; |
| 219 | default: |
| 220 | abort (); |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | #define xO 8 |
| 225 | #define xS 4 |
| 226 | #define xZ 2 |
| 227 | #define xC 1 |
| 228 | |
| 229 | #define F_____ |
| 230 | #define F___ZC rx->flags_0 = rx->flags_s = xZ|xC; |
| 231 | #define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ; |
| 232 | #define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC; |
| 233 | #define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC; |
| 234 | #define F_O___ rx->flags_0 = rx->flags_s = xO; |
| 235 | #define F_OS__ rx->flags_0 = rx->flags_s = xO|xS; |
| 236 | #define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ; |
| 237 | #define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC; |
| 238 | |
| 239 | int |
| 240 | rx_decode_opcode (unsigned long pc AU, |
| 241 | RX_Opcode_Decoded * rx, |
| 242 | int (* getbyte)(void *), |
| 243 | void * ptr) |
| 244 | { |
| 245 | LocalData lds, * ld = &lds; |
| 246 | unsigned char op[20] = {0}; |
| 247 | |
| 248 | lds.rx = rx; |
| 249 | lds.getbyte = getbyte; |
| 250 | lds.ptr = ptr; |
| 251 | lds.op = op; |
| 252 | |
| 253 | memset (rx, 0, sizeof (*rx)); |
| 254 | BWL(LSIZE); |
| 255 | |
| 256 | /** VARY sz 00 01 10 */ |
| 257 | |
| 258 | /*----------------------------------------------------------------------*/ |
| 259 | /* MOV */ |
| 260 | |
| 261 | /** 0111 0101 0100 rdst mov%s #%1, %0 */ |
| 262 | ID(mov); DR(rdst); SC(IMM (1)); F_____; |
| 263 | |
| 264 | /** 1111 10sd rdst im sz mov%s #%1, %0 */ |
| 265 | ID(mov); sBWL (sz); DD(sd, rdst, sz); SC(IMMex(im)); F_____; |
| 266 | |
| 267 | /** 0110 0110 immm rdst mov%s #%1, %0 */ |
| 268 | ID(mov); DR(rdst); SC(immm); F_____; |
| 269 | |
| 270 | /** 0011 11sz d dst sppp mov%s #%1, %0 */ |
| 271 | ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____; |
| 272 | |
| 273 | /** 11sz sd ss rsrc rdst mov%s %1, %0 */ |
| 274 | if (ss == 3 && sz == 2 && rsrc == 0 && rdst == 0) |
| 275 | { |
| 276 | ID(nop2); |
| 277 | } |
| 278 | else |
| 279 | { |
| 280 | ID(mov); sBWL(sz); F_____; |
| 281 | if ((ss == 3) && (sd != 3)) |
| 282 | { |
| 283 | SD(ss, rdst, sz); DD(sd, rsrc, sz); |
| 284 | } |
| 285 | else |
| 286 | { |
| 287 | SD(ss, rsrc, sz); DD(sd, rdst, sz); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | /** 10sz 1dsp a src b dst mov%s %1, %0 */ |
| 292 | ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____; |
| 293 | |
| 294 | /** 10sz 0dsp a dst b src mov%s %1, %0 */ |
| 295 | ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____; |
| 296 | |
| 297 | /** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */ |
| 298 | ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; |
| 299 | |
| 300 | /** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */ |
| 301 | ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; |
| 302 | |
| 303 | /** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */ |
| 304 | ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; |
| 305 | |
| 306 | /** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */ |
| 307 | ID(mov); sBWL (sz); SR(rsrc); F_____; |
| 308 | OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0); |
| 309 | |
| 310 | /** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */ |
| 311 | ID(mov); sBWL (sz); DR(rdst); F_____; |
| 312 | OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); |
| 313 | |
| 314 | /** 1011 w dsp a src b dst movu%s %1, %0 */ |
| 315 | ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____; |
| 316 | |
| 317 | /** 0101 1 s ss rsrc rdst movu%s %1, %0 */ |
| 318 | ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____; |
| 319 | |
| 320 | /** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */ |
| 321 | ID(mov); uBWL (sz); DR(rdst); F_____; |
| 322 | OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); |
| 323 | |
| 324 | /*----------------------------------------------------------------------*/ |
| 325 | /* PUSH/POP */ |
| 326 | |
| 327 | /** 0110 1111 dsta dstb popm %1-%2 */ |
| 328 | ID(popm); SR(dsta); S2R(dstb); F_____; |
| 329 | |
| 330 | /** 0110 1110 dsta dstb pushm %1-%2 */ |
| 331 | ID(pushm); SR(dsta); S2R(dstb); F_____; |
| 332 | |
| 333 | /** 0111 1110 1011 rdst pop %0 */ |
| 334 | ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____; |
| 335 | |
| 336 | /** 0111 1110 10sz rsrc push%s %1 */ |
| 337 | ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____; |
| 338 | |
| 339 | /** 1111 01ss rsrc 10sz push%s %1 */ |
| 340 | ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____; |
| 341 | |
| 342 | /*----------------------------------------------------------------------*/ |
| 343 | /* XCHG */ |
| 344 | |
| 345 | /** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */ |
| 346 | ID(xchg); DR(rdst); SP(ss, rsrc); |
| 347 | |
| 348 | /** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */ |
| 349 | ID(xchg); DR(rdst); SPm(ss, rsrc, mx); |
| 350 | |
| 351 | /*----------------------------------------------------------------------*/ |
| 352 | /* STZ/STNZ */ |
| 353 | |
| 354 | /** 1111 1101 0111 im00 1110rdst stz #%1, %0 */ |
| 355 | ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z); |
| 356 | |
| 357 | /** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */ |
| 358 | ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz); |
| 359 | |
| 360 | /*----------------------------------------------------------------------*/ |
| 361 | /* RTSD */ |
| 362 | |
| 363 | /** 0110 0111 rtsd #%1 */ |
| 364 | ID(rtsd); SC(IMM(1) * 4); |
| 365 | |
| 366 | /** 0011 1111 rega regb rtsd #%1, %2-%0 */ |
| 367 | ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); |
| 368 | |
| 369 | /*----------------------------------------------------------------------*/ |
| 370 | /* AND */ |
| 371 | |
| 372 | /** 0110 0100 immm rdst and #%1, %0 */ |
| 373 | ID(and); SC(immm); DR(rdst); F__SZ_; |
| 374 | |
| 375 | /** 0111 01im 0010 rdst and #%1, %0 */ |
| 376 | ID(and); SC(IMMex(im)); DR(rdst); F__SZ_; |
| 377 | |
| 378 | /** 0101 00ss rsrc rdst and %1%S1, %0 */ |
| 379 | ID(and); SP(ss, rsrc); DR(rdst); F__SZ_; |
| 380 | |
| 381 | /** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */ |
| 382 | ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; |
| 383 | |
| 384 | /** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */ |
| 385 | ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_; |
| 386 | |
| 387 | /*----------------------------------------------------------------------*/ |
| 388 | /* OR */ |
| 389 | |
| 390 | /** 0110 0101 immm rdst or #%1, %0 */ |
| 391 | ID(or); SC(immm); DR(rdst); F__SZ_; |
| 392 | |
| 393 | /** 0111 01im 0011 rdst or #%1, %0 */ |
| 394 | ID(or); SC(IMMex(im)); DR(rdst); F__SZ_; |
| 395 | |
| 396 | /** 0101 01ss rsrc rdst or %1%S1, %0 */ |
| 397 | ID(or); SP(ss, rsrc); DR(rdst); F__SZ_; |
| 398 | |
| 399 | /** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */ |
| 400 | ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; |
| 401 | |
| 402 | /** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */ |
| 403 | ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_; |
| 404 | |
| 405 | /*----------------------------------------------------------------------*/ |
| 406 | /* XOR */ |
| 407 | |
| 408 | /** 1111 1101 0111 im00 1101rdst xor #%1, %0 */ |
| 409 | ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_; |
| 410 | |
| 411 | /** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */ |
| 412 | ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_; |
| 413 | |
| 414 | /** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */ |
| 415 | ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; |
| 416 | |
| 417 | /*----------------------------------------------------------------------*/ |
| 418 | /* NOT */ |
| 419 | |
| 420 | /** 0111 1110 0000 rdst not %0 */ |
| 421 | ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_; |
| 422 | |
| 423 | /** 1111 1100 0011 1011 rsrc rdst not %1, %0 */ |
| 424 | ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_; |
| 425 | |
| 426 | /*----------------------------------------------------------------------*/ |
| 427 | /* TST */ |
| 428 | |
| 429 | /** 1111 1101 0111 im00 1100rdst tst #%1, %2 */ |
| 430 | ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_; |
| 431 | |
| 432 | /** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */ |
| 433 | ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_; |
| 434 | |
| 435 | /** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */ |
| 436 | ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_; |
| 437 | |
| 438 | /*----------------------------------------------------------------------*/ |
| 439 | /* NEG */ |
| 440 | |
| 441 | /** 0111 1110 0001 rdst neg %0 */ |
| 442 | ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC; |
| 443 | |
| 444 | /** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */ |
| 445 | ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC; |
| 446 | |
| 447 | /*----------------------------------------------------------------------*/ |
| 448 | /* ADC */ |
| 449 | |
| 450 | /** 1111 1101 0111 im00 0010rdst adc #%1, %0 */ |
| 451 | ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC; |
| 452 | |
| 453 | /** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */ |
| 454 | ID(adc); SR(rsrc); DR(rdst); F_OSZC; |
| 455 | |
| 456 | /** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */ |
| 457 | ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC; |
| 458 | |
| 459 | /*----------------------------------------------------------------------*/ |
| 460 | /* ADD */ |
| 461 | |
| 462 | /** 0110 0010 immm rdst add #%1, %0 */ |
| 463 | ID(add); SC(immm); DR(rdst); F_OSZC; |
| 464 | |
| 465 | /** 0100 10ss rsrc rdst add %1%S1, %0 */ |
| 466 | ID(add); SP(ss, rsrc); DR(rdst); F_OSZC; |
| 467 | |
| 468 | /** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */ |
| 469 | ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC; |
| 470 | |
| 471 | /** 0111 00im rsrc rdst add #%1, %2, %0 */ |
| 472 | ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC; |
| 473 | |
| 474 | /** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */ |
| 475 | ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC; |
| 476 | |
| 477 | /*----------------------------------------------------------------------*/ |
| 478 | /* CMP */ |
| 479 | |
| 480 | /** 0110 0001 immm rdst cmp #%2, %1 */ |
| 481 | ID(sub); S2C(immm); SR(rdst); F_OSZC; |
| 482 | |
| 483 | /** 0111 01im 0000 rsrc cmp #%2, %1%S1 */ |
| 484 | ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC; |
| 485 | |
| 486 | /** 0111 0101 0101 rsrc cmp #%2, %1 */ |
| 487 | ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC; |
| 488 | |
| 489 | /** 0100 01ss rsrc rdst cmp %2%S2, %1 */ |
| 490 | ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC; |
| 491 | |
| 492 | /** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */ |
| 493 | ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC; |
| 494 | |
| 495 | /*----------------------------------------------------------------------*/ |
| 496 | /* SUB */ |
| 497 | |
| 498 | /** 0110 0000 immm rdst sub #%2, %0 */ |
| 499 | ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC; |
| 500 | |
| 501 | /** 0100 00ss rsrc rdst sub %2%S2, %1 */ |
| 502 | ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC; |
| 503 | |
| 504 | /** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */ |
| 505 | ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC; |
| 506 | |
| 507 | /** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */ |
| 508 | ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC; |
| 509 | |
| 510 | /*----------------------------------------------------------------------*/ |
| 511 | /* SBB */ |
| 512 | |
| 513 | /** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */ |
| 514 | ID(sbb); SR (rsrc); DR(rdst); F_OSZC; |
| 515 | |
| 516 | /* FIXME: only supports .L */ |
| 517 | /** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */ |
| 518 | ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC; |
| 519 | |
| 520 | /*----------------------------------------------------------------------*/ |
| 521 | /* ABS */ |
| 522 | |
| 523 | /** 0111 1110 0010 rdst abs %0 */ |
| 524 | ID(abs); DR(rdst); SR(rdst); F_OSZ_; |
| 525 | |
| 526 | /** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */ |
| 527 | ID(abs); DR(rdst); SR(rsrc); F_OSZ_; |
| 528 | |
| 529 | /*----------------------------------------------------------------------*/ |
| 530 | /* MAX */ |
| 531 | |
| 532 | /** 1111 1101 0111 im00 0100rdst max #%1, %0 */ |
| 533 | ID(max); DR(rdst); SC(IMMex(im)); |
| 534 | |
| 535 | /** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */ |
| 536 | if (ss == 3 && rsrc == 0 && rdst == 0) |
| 537 | { |
| 538 | ID(nop3); |
| 539 | } |
| 540 | else |
| 541 | { |
| 542 | ID(max); SP(ss, rsrc); DR(rdst); |
| 543 | } |
| 544 | |
| 545 | /** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */ |
| 546 | ID(max); SPm(ss, rsrc, mx); DR(rdst); |
| 547 | |
| 548 | /*----------------------------------------------------------------------*/ |
| 549 | /* MIN */ |
| 550 | |
| 551 | /** 1111 1101 0111 im00 0101rdst min #%1, %0 */ |
| 552 | ID(min); DR(rdst); SC(IMMex(im)); |
| 553 | |
| 554 | /** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */ |
| 555 | ID(min); SP(ss, rsrc); DR(rdst); |
| 556 | |
| 557 | /** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */ |
| 558 | ID(min); SPm(ss, rsrc, mx); DR(rdst); |
| 559 | |
| 560 | /*----------------------------------------------------------------------*/ |
| 561 | /* MUL */ |
| 562 | |
| 563 | /** 0110 0011 immm rdst mul #%1, %0 */ |
| 564 | ID(mul); DR(rdst); SC(immm); F_____; |
| 565 | |
| 566 | /** 0111 01im 0001rdst mul #%1, %0 */ |
| 567 | ID(mul); DR(rdst); SC(IMMex(im)); F_____; |
| 568 | |
| 569 | /** 0100 11ss rsrc rdst mul %1%S1, %0 */ |
| 570 | ID(mul); SP(ss, rsrc); DR(rdst); F_____; |
| 571 | |
| 572 | /** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */ |
| 573 | ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____; |
| 574 | |
| 575 | /** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */ |
| 576 | ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____; |
| 577 | |
| 578 | /*----------------------------------------------------------------------*/ |
| 579 | /* EMUL */ |
| 580 | |
| 581 | /** 1111 1101 0111 im00 0110rdst emul #%1, %0 */ |
| 582 | ID(emul); DR(rdst); SC(IMMex(im)); |
| 583 | |
| 584 | /** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */ |
| 585 | ID(emul); SP(ss, rsrc); DR(rdst); |
| 586 | |
| 587 | /** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */ |
| 588 | ID(emul); SPm(ss, rsrc, mx); DR(rdst); |
| 589 | |
| 590 | /*----------------------------------------------------------------------*/ |
| 591 | /* EMULU */ |
| 592 | |
| 593 | /** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */ |
| 594 | ID(emulu); DR(rdst); SC(IMMex(im)); |
| 595 | |
| 596 | /** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */ |
| 597 | ID(emulu); SP(ss, rsrc); DR(rdst); |
| 598 | |
| 599 | /** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */ |
| 600 | ID(emulu); SPm(ss, rsrc, mx); DR(rdst); |
| 601 | |
| 602 | /*----------------------------------------------------------------------*/ |
| 603 | /* DIV */ |
| 604 | |
| 605 | /** 1111 1101 0111 im00 1000rdst div #%1, %0 */ |
| 606 | ID(div); DR(rdst); SC(IMMex(im)); F_O___; |
| 607 | |
| 608 | /** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */ |
| 609 | ID(div); SP(ss, rsrc); DR(rdst); F_O___; |
| 610 | |
| 611 | /** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */ |
| 612 | ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___; |
| 613 | |
| 614 | /*----------------------------------------------------------------------*/ |
| 615 | /* DIVU */ |
| 616 | |
| 617 | /** 1111 1101 0111 im00 1001rdst divu #%1, %0 */ |
| 618 | ID(divu); DR(rdst); SC(IMMex(im)); F_O___; |
| 619 | |
| 620 | /** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */ |
| 621 | ID(divu); SP(ss, rsrc); DR(rdst); F_O___; |
| 622 | |
| 623 | /** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */ |
| 624 | ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___; |
| 625 | |
| 626 | /*----------------------------------------------------------------------*/ |
| 627 | /* SHIFT */ |
| 628 | |
| 629 | /** 0110 110i mmmm rdst shll #%2, %0 */ |
| 630 | ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC; |
| 631 | |
| 632 | /** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */ |
| 633 | ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC; |
| 634 | |
| 635 | /** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */ |
| 636 | ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC; |
| 637 | |
| 638 | |
| 639 | /** 0110 101i mmmm rdst shar #%2, %0 */ |
| 640 | ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC; |
| 641 | |
| 642 | /** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */ |
| 643 | ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC; |
| 644 | |
| 645 | /** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */ |
| 646 | ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC; |
| 647 | |
| 648 | |
| 649 | /** 0110 100i mmmm rdst shlr #%2, %0 */ |
| 650 | ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC; |
| 651 | |
| 652 | /** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */ |
| 653 | ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC; |
| 654 | |
| 655 | /** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */ |
| 656 | ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC; |
| 657 | |
| 658 | /*----------------------------------------------------------------------*/ |
| 659 | /* ROTATE */ |
| 660 | |
| 661 | /** 0111 1110 0101 rdst rolc %0 */ |
| 662 | ID(rolc); DR(rdst); F__SZC; |
| 663 | |
| 664 | /** 0111 1110 0100 rdst rorc %0 */ |
| 665 | ID(rorc); DR(rdst); F__SZC; |
| 666 | |
| 667 | /** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */ |
| 668 | ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC; |
| 669 | |
| 670 | /** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */ |
| 671 | ID(rotl); SR(rsrc); DR(rdst); F__SZC; |
| 672 | |
| 673 | /** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */ |
| 674 | ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC; |
| 675 | |
| 676 | /** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */ |
| 677 | ID(rotr); SR(rsrc); DR(rdst); F__SZC; |
| 678 | |
| 679 | /** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */ |
| 680 | ID(revw); SR(rsrc); DR(rdst); |
| 681 | |
| 682 | /** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */ |
| 683 | ID(revl); SR(rsrc); DR(rdst); |
| 684 | |
| 685 | /*----------------------------------------------------------------------*/ |
| 686 | /* BRANCH */ |
| 687 | |
| 688 | /** 0001 n dsp b%1.s %a0 */ |
| 689 | ID(branch); Scc(n); DC(pc + dsp3map[dsp]); |
| 690 | |
| 691 | /** 0010 cond b%1.b %a0 */ |
| 692 | ID(branch); Scc(cond); DC(pc + IMMex (1)); |
| 693 | |
| 694 | /** 0011 101c b%1.w %a0 */ |
| 695 | ID(branch); Scc(c); DC(pc + IMMex (2)); |
| 696 | |
| 697 | |
| 698 | /** 0000 1dsp bra.s %a0 */ |
| 699 | ID(branch); DC(pc + dsp3map[dsp]); |
| 700 | |
| 701 | /** 0010 1110 bra.b %a0 */ |
| 702 | ID(branch); DC(pc + IMMex(1)); |
| 703 | |
| 704 | /** 0011 1000 bra.w %a0 */ |
| 705 | ID(branch); DC(pc + IMMex(2)); |
| 706 | |
| 707 | /** 0000 0100 bra.a %a0 */ |
| 708 | ID(branch); DC(pc + IMMex(3)); |
| 709 | |
| 710 | /** 0111 1111 0100 rsrc bra.l %0 */ |
| 711 | ID(branchrel); DR(rsrc); |
| 712 | |
| 713 | |
| 714 | /** 0111 1111 0000 rsrc jmp %0 */ |
| 715 | ID(branch); DR(rsrc); |
| 716 | |
| 717 | /** 0111 1111 0001 rsrc jsr %0 */ |
| 718 | ID(jsr); DR(rsrc); |
| 719 | |
| 720 | /** 0011 1001 bsr.w %a0 */ |
| 721 | ID(jsr); DC(pc + IMMex(2)); |
| 722 | |
| 723 | /** 0000 0101 bsr.a %a0 */ |
| 724 | ID(jsr); DC(pc + IMMex(3)); |
| 725 | |
| 726 | /** 0111 1111 0101 rsrc bsr.l %0 */ |
| 727 | ID(jsrrel); DR(rsrc); |
| 728 | |
| 729 | /** 0000 0010 rts */ |
| 730 | ID(rts); |
| 731 | |
| 732 | /*----------------------------------------------------------------------*/ |
| 733 | /* NOP */ |
| 734 | |
| 735 | /** 0000 0011 nop */ |
| 736 | ID(nop); |
| 737 | |
| 738 | /*----------------------------------------------------------------------*/ |
| 739 | /* STRING FUNCTIONS */ |
| 740 | |
| 741 | /** 0111 1111 1000 0011 scmpu */ |
| 742 | ID(scmpu); F___ZC; |
| 743 | |
| 744 | /** 0111 1111 1000 0111 smovu */ |
| 745 | ID(smovu); |
| 746 | |
| 747 | /** 0111 1111 1000 1011 smovb */ |
| 748 | ID(smovb); |
| 749 | |
| 750 | /** 0111 1111 1000 00sz suntil%s */ |
| 751 | ID(suntil); BWL(sz); F___ZC; |
| 752 | |
| 753 | /** 0111 1111 1000 01sz swhile%s */ |
| 754 | ID(swhile); BWL(sz); F___ZC; |
| 755 | |
| 756 | /** 0111 1111 1000 1111 smovf */ |
| 757 | ID(smovf); |
| 758 | |
| 759 | /** 0111 1111 1000 10sz sstr%s */ |
| 760 | ID(sstr); BWL(sz); |
| 761 | |
| 762 | /*----------------------------------------------------------------------*/ |
| 763 | /* RMPA */ |
| 764 | |
| 765 | /** 0111 1111 1000 11sz rmpa%s */ |
| 766 | ID(rmpa); BWL(sz); F_OS__; |
| 767 | |
| 768 | /*----------------------------------------------------------------------*/ |
| 769 | /* HI/LO stuff */ |
| 770 | |
| 771 | /** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */ |
| 772 | ID(mulhi); SR(srca); S2R(srcb); F_____; |
| 773 | |
| 774 | /** 1111 1101 0000 0001 srca srcb mullo %1, %2 */ |
| 775 | ID(mullo); SR(srca); S2R(srcb); F_____; |
| 776 | |
| 777 | /** 1111 1101 0000 0100 srca srcb machi %1, %2 */ |
| 778 | ID(machi); SR(srca); S2R(srcb); F_____; |
| 779 | |
| 780 | /** 1111 1101 0000 0101 srca srcb maclo %1, %2 */ |
| 781 | ID(maclo); SR(srca); S2R(srcb); F_____; |
| 782 | |
| 783 | /** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */ |
| 784 | ID(mvtachi); SR(rsrc); F_____; |
| 785 | |
| 786 | /** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */ |
| 787 | ID(mvtaclo); SR(rsrc); F_____; |
| 788 | |
| 789 | /** 1111 1101 0001 1111 0000 rdst mvfachi %0 */ |
| 790 | ID(mvfachi); DR(rdst); F_____; |
| 791 | |
| 792 | /** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */ |
| 793 | ID(mvfacmi); DR(rdst); F_____; |
| 794 | |
| 795 | /** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */ |
| 796 | ID(mvfaclo); DR(rdst); F_____; |
| 797 | |
| 798 | /** 1111 1101 0001 1000 000i 0000 racw #%1 */ |
| 799 | ID(racw); SC(i+1); F_____; |
| 800 | |
| 801 | /*----------------------------------------------------------------------*/ |
| 802 | /* SAT */ |
| 803 | |
| 804 | /** 0111 1110 0011 rdst sat %0 */ |
| 805 | ID(sat); DR (rdst); |
| 806 | |
| 807 | /** 0111 1111 1001 0011 satr */ |
| 808 | ID(satr); |
| 809 | |
| 810 | /*----------------------------------------------------------------------*/ |
| 811 | /* FLOAT */ |
| 812 | |
| 813 | /** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */ |
| 814 | ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_; |
| 815 | |
| 816 | /** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */ |
| 817 | ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; |
| 818 | |
| 819 | /** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */ |
| 820 | ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_; |
| 821 | |
| 822 | /** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */ |
| 823 | ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_; |
| 824 | |
| 825 | /** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */ |
| 826 | ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_; |
| 827 | |
| 828 | /** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */ |
| 829 | ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; |
| 830 | |
| 831 | /** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */ |
| 832 | ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; |
| 833 | |
| 834 | /** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */ |
| 835 | ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_; |
| 836 | |
| 837 | /** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */ |
| 838 | ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; |
| 839 | |
| 840 | /** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */ |
| 841 | ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_; |
| 842 | |
| 843 | /** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */ |
| 844 | ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; |
| 845 | |
| 846 | /** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */ |
| 847 | ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; |
| 848 | |
| 849 | /** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */ |
| 850 | ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_; |
| 851 | |
| 852 | /** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */ |
| 853 | ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_; |
| 854 | |
| 855 | /*----------------------------------------------------------------------*/ |
| 856 | /* BIT OPS */ |
| 857 | |
| 858 | /** 1111 00sd rdst 0bit bset #%1, %0%S0 */ |
| 859 | ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____; |
| 860 | |
| 861 | /** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */ |
| 862 | ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; |
| 863 | |
| 864 | /** 0111 100b ittt rdst bset #%1, %0 */ |
| 865 | ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; |
| 866 | |
| 867 | |
| 868 | /** 1111 00sd rdst 1bit bclr #%1, %0%S0 */ |
| 869 | ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____; |
| 870 | |
| 871 | /** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */ |
| 872 | ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; |
| 873 | |
| 874 | /** 0111 101b ittt rdst bclr #%1, %0 */ |
| 875 | ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; |
| 876 | |
| 877 | |
| 878 | /** 1111 01sd rdst 0bit btst #%2, %1%S1 */ |
| 879 | ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC; |
| 880 | |
| 881 | /** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */ |
| 882 | ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC; |
| 883 | |
| 884 | /** 0111 110b ittt rdst btst #%2, %1 */ |
| 885 | ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC; |
| 886 | |
| 887 | |
| 888 | /** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */ |
| 889 | ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); |
| 890 | |
| 891 | /** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */ |
| 892 | ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); |
| 893 | |
| 894 | /** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */ |
| 895 | ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst); |
| 896 | |
| 897 | |
| 898 | /** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */ |
| 899 | ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE); |
| 900 | |
| 901 | /** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */ |
| 902 | ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst); |
| 903 | |
| 904 | /*----------------------------------------------------------------------*/ |
| 905 | /* CONTROL REGISTERS */ |
| 906 | |
| 907 | /** 0111 1111 1011 rdst clrpsw %0 */ |
| 908 | ID(clrpsw); DF(rdst); |
| 909 | |
| 910 | /** 0111 1111 1010 rdst setpsw %0 */ |
| 911 | ID(setpsw); DF(rdst); |
| 912 | |
| 913 | /** 0111 0101 0111 0000 0000 immm mvtipl #%1 */ |
| 914 | ID(mvtipl); SC(immm); |
| 915 | |
| 916 | /** 0111 1110 111 crdst popc %0 */ |
| 917 | ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16); |
| 918 | |
| 919 | /** 0111 1110 110 crsrc pushc %1 */ |
| 920 | ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16); |
| 921 | |
| 922 | /** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */ |
| 923 | ID(mov); SC(IMMex(im)); DR(crdst + 16); |
| 924 | |
| 925 | /** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */ |
| 926 | ID(mov); SR(rsrc); DR(c*16+rdst + 16); |
| 927 | |
| 928 | /** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */ |
| 929 | ID(mov); SR((s*16+rsrc) + 16); DR(rdst); |
| 930 | |
| 931 | /*----------------------------------------------------------------------*/ |
| 932 | /* INTERRUPTS */ |
| 933 | |
| 934 | /** 0111 1111 1001 0100 rtfi */ |
| 935 | ID(rtfi); |
| 936 | |
| 937 | /** 0111 1111 1001 0101 rte */ |
| 938 | ID(rte); |
| 939 | |
| 940 | /** 0000 0000 brk */ |
| 941 | ID(brk); |
| 942 | |
| 943 | /** 0000 0001 dbt */ |
| 944 | ID(dbt); |
| 945 | |
| 946 | /** 0111 0101 0110 0000 int #%1 */ |
| 947 | ID(int); SC(IMM(1)); |
| 948 | |
| 949 | /** 0111 1111 1001 0110 wait */ |
| 950 | ID(wait); |
| 951 | |
| 952 | /*----------------------------------------------------------------------*/ |
| 953 | /* SCcnd */ |
| 954 | |
| 955 | /** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */ |
| 956 | ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond); |
| 957 | |
| 958 | /** */ |
| 959 | |
| 960 | return rx->n_bytes; |
| 961 | } |