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* powerpc.cc (Powerpc_relobj): Add and use Address typedef.
[deliverable/binutils-gdb.git] / opcodes / rx-decode.opc
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1/* -*- c -*- */
2#include "sysdep.h"
3#include <stdio.h>
4#include <stdlib.h>
5#include <string.h>
6#include "ansidecl.h"
7#include "opcode/rx.h"
8
9#define RX_OPCODE_BIG_ENDIAN 0
10
11typedef struct
12{
13 RX_Opcode_Decoded * rx;
14 int (* getbyte)(void *);
15 void * ptr;
16 unsigned char * op;
17} LocalData;
18
19static int trace = 0;
20
21#define BSIZE 0
22#define WSIZE 1
23#define LSIZE 2
24
25/* These are for when the upper bits are "don't care" or "undefined". */
26static int bwl[] =
27{
28 RX_Byte,
29 RX_Word,
30 RX_Long
31};
32
33static int sbwl[] =
34{
35 RX_SByte,
36 RX_SWord,
37 RX_Long
38};
39
40static int ubwl[] =
41{
42 RX_UByte,
43 RX_UWord,
44 RX_Long
45};
46
47static int memex[] =
48{
49 RX_SByte,
50 RX_SWord,
51 RX_Long,
52 RX_UWord
53};
54
55#define ID(x) rx->id = RXO_##x
56#define OP(n,t,r,a) (rx->op[n].type = t, \
57 rx->op[n].reg = r, \
58 rx->op[n].addend = a )
59#define OPs(n,t,r,a,s) (OP (n,t,r,a), \
60 rx->op[n].size = s )
61
62/* This is for the BWL and BW bitfields. */
63static int SCALE[] = { 1, 2, 4 };
64/* This is for the prefix size enum. */
65static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 };
66
67static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0,
68 16, 17, 0, 0, 0, 0, 0, 0 };
69
70static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
71
72/*
73 *C a constant (immediate) c
74 *R A register
75 *I Register indirect, no offset
76 *Is Register indirect, with offset
77 *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code
78 *P standard displacement: type (r,[r]), reg, assumes UByte
79 *Pm memex displacement: type (r,[r]), reg, memex code
80 *cc condition code. */
81
82#define DC(c) OP (0, RX_Operand_Immediate, 0, c)
83#define DR(r) OP (0, RX_Operand_Register, r, 0)
84#define DI(r,a) OP (0, RX_Operand_Indirect, r, a)
85#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s])
86#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld);
87#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0)
88
89#define SC(i) OP (1, RX_Operand_Immediate, 0, i)
90#define SR(r) OP (1, RX_Operand_Register, r, 0)
91#define SRR(r) OP (1, RX_Operand_TwoReg, r, 0)
92#define SI(r,a) OP (1, RX_Operand_Indirect, r, a)
93#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s])
94#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld);
95#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1);
96#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m];
97#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0)
98
99#define S2C(i) OP (2, RX_Operand_Immediate, 0, i)
100#define S2R(r) OP (2, RX_Operand_Register, r, 0)
101#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a)
102#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s])
103#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld);
104#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2);
105#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m];
106#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0)
107
108#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
109#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
110#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz]
111#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
112
113#define F(f) store_flags(rx, f)
114
115#define AU ATTRIBUTE_UNUSED
116#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr))
117
118#define SYNTAX(x) rx->syntax = x
119
120#define UNSUPPORTED() \
121 rx->syntax = "*unknown*"
122
123#define IMM(sf) immediate (sf, 0, ld)
124#define IMMex(sf) immediate (sf, 1, ld)
125
126static int
127immediate (int sfield, int ex, LocalData * ld)
128{
129 unsigned long i = 0, j;
130
131 switch (sfield)
132 {
133#define B ((unsigned long) GETBYTE())
134 case 0:
135#if RX_OPCODE_BIG_ENDIAN
136 i = B;
137 if (ex && (i & 0x80))
138 i -= 0x100;
139 i <<= 24;
140 i |= B << 16;
141 i |= B << 8;
142 i |= B;
143#else
144 i = B;
145 i |= B << 8;
146 i |= B << 16;
147 j = B;
148 if (ex && (j & 0x80))
149 j -= 0x100;
150 i |= j << 24;
151#endif
152 break;
153 case 3:
154#if RX_OPCODE_BIG_ENDIAN
155 i = B << 16;
156 i |= B << 8;
157 i |= B;
158#else
159 i = B;
160 i |= B << 8;
161 i |= B << 16;
162#endif
163 if (ex && (i & 0x800000))
164 i -= 0x1000000;
165 break;
166 case 2:
167#if RX_OPCODE_BIG_ENDIAN
168 i |= B << 8;
169 i |= B;
170#else
171 i |= B;
172 i |= B << 8;
173#endif
174 if (ex && (i & 0x8000))
175 i -= 0x10000;
176 break;
177 case 1:
178 i |= B;
179 if (ex && (i & 0x80))
180 i -= 0x100;
181 break;
182 default:
183 abort();
184 }
185 return i;
186}
187
188static void
189rx_disp (int n, int type, int reg, int size, LocalData * ld)
190{
191 int disp;
192
193 ld->rx->op[n].reg = reg;
194 switch (type)
195 {
196 case 3:
197 ld->rx->op[n].type = RX_Operand_Register;
198 break;
199 case 0:
200 ld->rx->op[n].type = RX_Operand_Indirect;
201 ld->rx->op[n].addend = 0;
202 break;
203 case 1:
204 ld->rx->op[n].type = RX_Operand_Indirect;
205 disp = GETBYTE ();
206 ld->rx->op[n].addend = disp * PSCALE[size];
207 break;
208 case 2:
209 ld->rx->op[n].type = RX_Operand_Indirect;
210 disp = GETBYTE ();
211#if RX_OPCODE_BIG_ENDIAN
212 disp = disp * 256 + GETBYTE ();
213#else
214 disp = disp + GETBYTE () * 256;
215#endif
216 ld->rx->op[n].addend = disp * PSCALE[size];
217 break;
218 default:
219 abort ();
220 }
221}
222
223#define xO 8
224#define xS 4
225#define xZ 2
226#define xC 1
227
228#define F_____
229#define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
230#define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
231#define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
232#define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC;
233#define F_O___ rx->flags_0 = rx->flags_s = xO;
234#define F_OS__ rx->flags_0 = rx->flags_s = xO|xS;
235#define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ;
236#define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC;
237
238int
239rx_decode_opcode (unsigned long pc AU,
240 RX_Opcode_Decoded * rx,
241 int (* getbyte)(void *),
242 void * ptr)
243{
244 LocalData lds, * ld = &lds;
245 unsigned char op[20] = {0};
246
247 lds.rx = rx;
248 lds.getbyte = getbyte;
249 lds.ptr = ptr;
250 lds.op = op;
251
252 memset (rx, 0, sizeof (*rx));
253 BWL(LSIZE);
254
255/** VARY sz 00 01 10 */
256
257/*----------------------------------------------------------------------*/
258/* MOV */
259
260/** 0111 0101 0100 rdst mov%s #%1, %0 */
261 ID(mov); DR(rdst); SC(IMM (1)); F_____;
262
263/** 1111 10sd rdst im sz mov%s #%1, %0 */
264 ID(mov); DD(sd, rdst, sz);
265 if ((im == 1 && sz == 0)
266 || (im == 2 && sz == 1)
267 || (im == 0 && sz == 2))
268 {
269 BWL (sz);
270 SC(IMM(im));
271 }
272 else
273 {
274 sBWL (sz);
275 SC(IMMex(im));
276 }
277 F_____;
278
279/** 0110 0110 immm rdst mov%s #%1, %0 */
280 ID(mov); DR(rdst); SC(immm); F_____;
281
282/** 0011 11sz d dst sppp mov%s #%1, %0 */
283 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
284
285/** 11sz sd ss rsrc rdst mov%s %1, %0 */
286 if (ss == 3 && sz == 2 && rsrc == 0 && rdst == 0)
287 {
288 ID(nop2);
289 rx->syntax = "nop";
290 }
291 else
292 {
293 ID(mov); sBWL(sz); F_____;
294 if ((ss == 3) && (sd != 3))
295 {
296 SD(ss, rdst, sz); DD(sd, rsrc, sz);
297 }
298 else
299 {
300 SD(ss, rsrc, sz); DD(sd, rdst, sz);
301 }
302 }
303
304/** 10sz 1dsp a src b dst mov%s %1, %0 */
305 ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____;
306
307/** 10sz 0dsp a dst b src mov%s %1, %0 */
308 ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
309
310/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */
311 ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
312
313/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */
314 ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
315
316/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */
317 ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
318
319/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */
320 ID(mov); sBWL (sz); SR(rsrc); F_____;
321 OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0);
322
323/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */
324 ID(mov); sBWL (sz); DR(rdst); F_____;
325 OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
326
327/** 1011 w dsp a src b dst movu%s %1, %0 */
328 ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
329
330/** 0101 1 s ss rsrc rdst movu%s %1, %0 */
331 ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____;
332
333/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */
334 ID(mov); uBWL (sz); DR(rdst); F_____;
335 OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
336
337/*----------------------------------------------------------------------*/
338/* PUSH/POP */
339
340/** 0110 1111 dsta dstb popm %1-%2 */
341 ID(popm); SR(dsta); S2R(dstb); F_____;
342
343/** 0110 1110 dsta dstb pushm %1-%2 */
344 ID(pushm); SR(dsta); S2R(dstb); F_____;
345
346/** 0111 1110 1011 rdst pop %0 */
347 ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
348
349/** 0111 1110 10sz rsrc push%s %1 */
350 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
351
352/** 1111 01ss rsrc 10sz push%s %1 */
353 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____;
354
355/*----------------------------------------------------------------------*/
356/* XCHG */
357
358/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */
359 ID(xchg); DR(rdst); SP(ss, rsrc);
360
361/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */
362 ID(xchg); DR(rdst); SPm(ss, rsrc, mx);
363
364/*----------------------------------------------------------------------*/
365/* STZ/STNZ */
366
367/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */
368 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
369
370/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */
371 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
372
373/*----------------------------------------------------------------------*/
374/* RTSD */
375
376/** 0110 0111 rtsd #%1 */
377 ID(rtsd); SC(IMM(1) * 4);
378
379/** 0011 1111 rega regb rtsd #%1, %2-%0 */
380 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
381
382/*----------------------------------------------------------------------*/
383/* AND */
384
385/** 0110 0100 immm rdst and #%1, %0 */
386 ID(and); SC(immm); DR(rdst); F__SZ_;
387
388/** 0111 01im 0010 rdst and #%1, %0 */
389 ID(and); SC(IMMex(im)); DR(rdst); F__SZ_;
390
391/** 0101 00ss rsrc rdst and %1%S1, %0 */
392 ID(and); SP(ss, rsrc); DR(rdst); F__SZ_;
393
394/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */
395 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
396
397/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */
398 ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
399
400/*----------------------------------------------------------------------*/
401/* OR */
402
403/** 0110 0101 immm rdst or #%1, %0 */
404 ID(or); SC(immm); DR(rdst); F__SZ_;
405
406/** 0111 01im 0011 rdst or #%1, %0 */
407 ID(or); SC(IMMex(im)); DR(rdst); F__SZ_;
408
409/** 0101 01ss rsrc rdst or %1%S1, %0 */
410 ID(or); SP(ss, rsrc); DR(rdst); F__SZ_;
411
412/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */
413 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
414
415/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */
416 ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
417
418/*----------------------------------------------------------------------*/
419/* XOR */
420
421/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */
422 ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_;
423
424/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */
425 ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_;
426
427/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */
428 ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
429
430/*----------------------------------------------------------------------*/
431/* NOT */
432
433/** 0111 1110 0000 rdst not %0 */
434 ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
435
436/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */
437 ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_;
438
439/*----------------------------------------------------------------------*/
440/* TST */
441
442/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */
443 ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_;
444
445/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */
446 ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_;
447
448/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */
449 ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_;
450
451/*----------------------------------------------------------------------*/
452/* NEG */
453
454/** 0111 1110 0001 rdst neg %0 */
455 ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC;
456
457/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */
458 ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC;
459
460/*----------------------------------------------------------------------*/
461/* ADC */
462
463/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */
464 ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC;
465
466/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */
467 ID(adc); SR(rsrc); DR(rdst); F_OSZC;
468
469/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */
470 ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC;
471
472/*----------------------------------------------------------------------*/
473/* ADD */
474
475/** 0110 0010 immm rdst add #%1, %0 */
476 ID(add); SC(immm); DR(rdst); F_OSZC;
477
478/** 0100 10ss rsrc rdst add %1%S1, %0 */
479 ID(add); SP(ss, rsrc); DR(rdst); F_OSZC;
480
481/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */
482 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
483
484/** 0111 00im rsrc rdst add #%1, %2, %0 */
485 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC;
486
487/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */
488 ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
489
490/*----------------------------------------------------------------------*/
491/* CMP */
492
493/** 0110 0001 immm rdst cmp #%2, %1 */
494 ID(sub); S2C(immm); SR(rdst); F_OSZC;
495
496/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */
497 ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC;
498
499/** 0111 0101 0101 rsrc cmp #%2, %1 */
500 ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC;
501
502/** 0100 01ss rsrc rdst cmp %2%S2, %1 */
503 ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC;
504
505/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */
506 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC;
507
508/*----------------------------------------------------------------------*/
509/* SUB */
510
511/** 0110 0000 immm rdst sub #%2, %0 */
512 ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC;
513
514/** 0100 00ss rsrc rdst sub %2%S2, %1 */
515 ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC;
516
517/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */
518 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
519
520/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */
521 ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
522
523/*----------------------------------------------------------------------*/
524/* SBB */
525
526/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */
527 ID(sbb); SR (rsrc); DR(rdst); F_OSZC;
528
529 /* FIXME: only supports .L */
530/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */
531 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
532
533/*----------------------------------------------------------------------*/
534/* ABS */
535
536/** 0111 1110 0010 rdst abs %0 */
537 ID(abs); DR(rdst); SR(rdst); F_OSZ_;
538
539/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */
540 ID(abs); DR(rdst); SR(rsrc); F_OSZ_;
541
542/*----------------------------------------------------------------------*/
543/* MAX */
544
545/** 1111 1101 0111 im00 0100rdst max #%1, %0 */
546 ID(max); DR(rdst); SC(IMMex(im));
547
548/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */
549 if (ss == 3 && rsrc == 0 && rdst == 0)
550 {
551 ID(nop3);
552 rx->syntax = "nop";
553 }
554 else
555 {
556 ID(max); SP(ss, rsrc); DR(rdst);
557 }
558
559/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */
560 ID(max); SPm(ss, rsrc, mx); DR(rdst);
561
562/*----------------------------------------------------------------------*/
563/* MIN */
564
565/** 1111 1101 0111 im00 0101rdst min #%1, %0 */
566 ID(min); DR(rdst); SC(IMMex(im));
567
568/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */
569 ID(min); SP(ss, rsrc); DR(rdst);
570
571/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */
572 ID(min); SPm(ss, rsrc, mx); DR(rdst);
573
574/*----------------------------------------------------------------------*/
575/* MUL */
576
577/** 0110 0011 immm rdst mul #%1, %0 */
578 ID(mul); DR(rdst); SC(immm); F_____;
579
580/** 0111 01im 0001rdst mul #%1, %0 */
581 ID(mul); DR(rdst); SC(IMMex(im)); F_____;
582
583/** 0100 11ss rsrc rdst mul %1%S1, %0 */
584 ID(mul); SP(ss, rsrc); DR(rdst); F_____;
585
586/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */
587 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
588
589/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */
590 ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____;
591
592/*----------------------------------------------------------------------*/
593/* EMUL */
594
595/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */
596 ID(emul); DR(rdst); SC(IMMex(im));
597
598/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */
599 ID(emul); SP(ss, rsrc); DR(rdst);
600
601/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */
602 ID(emul); SPm(ss, rsrc, mx); DR(rdst);
603
604/*----------------------------------------------------------------------*/
605/* EMULU */
606
607/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */
608 ID(emulu); DR(rdst); SC(IMMex(im));
609
610/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */
611 ID(emulu); SP(ss, rsrc); DR(rdst);
612
613/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */
614 ID(emulu); SPm(ss, rsrc, mx); DR(rdst);
615
616/*----------------------------------------------------------------------*/
617/* DIV */
618
619/** 1111 1101 0111 im00 1000rdst div #%1, %0 */
620 ID(div); DR(rdst); SC(IMMex(im)); F_O___;
621
622/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */
623 ID(div); SP(ss, rsrc); DR(rdst); F_O___;
624
625/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */
626 ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___;
627
628/*----------------------------------------------------------------------*/
629/* DIVU */
630
631/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */
632 ID(divu); DR(rdst); SC(IMMex(im)); F_O___;
633
634/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */
635 ID(divu); SP(ss, rsrc); DR(rdst); F_O___;
636
637/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */
638 ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___;
639
640/*----------------------------------------------------------------------*/
641/* SHIFT */
642
643/** 0110 110i mmmm rdst shll #%2, %0 */
644 ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC;
645
646/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */
647 ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC;
648
649/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */
650 ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC;
651
652
653/** 0110 101i mmmm rdst shar #%2, %0 */
654 ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC;
655
656/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */
657 ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC;
658
659/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */
660 ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC;
661
662
663/** 0110 100i mmmm rdst shlr #%2, %0 */
664 ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC;
665
666/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */
667 ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC;
668
669/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */
670 ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC;
671
672/*----------------------------------------------------------------------*/
673/* ROTATE */
674
675/** 0111 1110 0101 rdst rolc %0 */
676 ID(rolc); DR(rdst); F__SZC;
677
678/** 0111 1110 0100 rdst rorc %0 */
679 ID(rorc); DR(rdst); F__SZC;
680
681/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */
682 ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC;
683
684/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */
685 ID(rotl); SR(rsrc); DR(rdst); F__SZC;
686
687/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */
688 ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC;
689
690/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */
691 ID(rotr); SR(rsrc); DR(rdst); F__SZC;
692
693/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */
694 ID(revw); SR(rsrc); DR(rdst);
695
696/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */
697 ID(revl); SR(rsrc); DR(rdst);
698
699/*----------------------------------------------------------------------*/
700/* BRANCH */
701
702/** 0001 n dsp b%1.s %a0 */
703 ID(branch); Scc(n); DC(pc + dsp3map[dsp]);
704
705/** 0010 cond b%1.b %a0 */
706 ID(branch); Scc(cond); DC(pc + IMMex (1));
707
708/** 0011 101c b%1.w %a0 */
709 ID(branch); Scc(c); DC(pc + IMMex (2));
710
711
712/** 0000 1dsp bra.s %a0 */
713 ID(branch); DC(pc + dsp3map[dsp]);
714
715/** 0010 1110 bra.b %a0 */
716 ID(branch); DC(pc + IMMex(1));
717
718/** 0011 1000 bra.w %a0 */
719 ID(branch); DC(pc + IMMex(2));
720
721/** 0000 0100 bra.a %a0 */
722 ID(branch); DC(pc + IMMex(3));
723
724/** 0111 1111 0100 rsrc bra.l %0 */
725 ID(branchrel); DR(rsrc);
726
727
728/** 0111 1111 0000 rsrc jmp %0 */
729 ID(branch); DR(rsrc);
730
731/** 0111 1111 0001 rsrc jsr %0 */
732 ID(jsr); DR(rsrc);
733
734/** 0011 1001 bsr.w %a0 */
735 ID(jsr); DC(pc + IMMex(2));
736
737/** 0000 0101 bsr.a %a0 */
738 ID(jsr); DC(pc + IMMex(3));
739
740/** 0111 1111 0101 rsrc bsr.l %0 */
741 ID(jsrrel); DR(rsrc);
742
743/** 0000 0010 rts */
744 ID(rts);
745
746/*----------------------------------------------------------------------*/
747/* NOP */
748
749/** 0000 0011 nop */
750 ID(nop);
751
752/*----------------------------------------------------------------------*/
753/* STRING FUNCTIONS */
754
755/** 0111 1111 1000 0011 scmpu */
756 ID(scmpu); F___ZC;
757
758/** 0111 1111 1000 0111 smovu */
759 ID(smovu);
760
761/** 0111 1111 1000 1011 smovb */
762 ID(smovb);
763
764/** 0111 1111 1000 00sz suntil%s */
765 ID(suntil); BWL(sz); F___ZC;
766
767/** 0111 1111 1000 01sz swhile%s */
768 ID(swhile); BWL(sz); F___ZC;
769
770/** 0111 1111 1000 1111 smovf */
771 ID(smovf);
772
773/** 0111 1111 1000 10sz sstr%s */
774 ID(sstr); BWL(sz);
775
776/*----------------------------------------------------------------------*/
777/* RMPA */
778
779/** 0111 1111 1000 11sz rmpa%s */
780 ID(rmpa); BWL(sz); F_OS__;
781
782/*----------------------------------------------------------------------*/
783/* HI/LO stuff */
784
785/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */
786 ID(mulhi); SR(srca); S2R(srcb); F_____;
787
788/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */
789 ID(mullo); SR(srca); S2R(srcb); F_____;
790
791/** 1111 1101 0000 0100 srca srcb machi %1, %2 */
792 ID(machi); SR(srca); S2R(srcb); F_____;
793
794/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */
795 ID(maclo); SR(srca); S2R(srcb); F_____;
796
797/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */
798 ID(mvtachi); SR(rsrc); F_____;
799
800/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */
801 ID(mvtaclo); SR(rsrc); F_____;
802
803/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */
804 ID(mvfachi); DR(rdst); F_____;
805
806/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */
807 ID(mvfacmi); DR(rdst); F_____;
808
809/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */
810 ID(mvfaclo); DR(rdst); F_____;
811
812/** 1111 1101 0001 1000 000i 0000 racw #%1 */
813 ID(racw); SC(i+1); F_____;
814
815/*----------------------------------------------------------------------*/
816/* SAT */
817
818/** 0111 1110 0011 rdst sat %0 */
819 ID(sat); DR (rdst);
820
821/** 0111 1111 1001 0011 satr */
822 ID(satr);
823
824/*----------------------------------------------------------------------*/
825/* FLOAT */
826
827/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */
828 ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_;
829
830/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */
831 ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
832
833/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */
834 ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_;
835
836/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */
837 ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_;
838
839/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */
840 ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_;
841
842/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */
843 ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
844
845/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */
846 ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
847
848/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */
849 ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_;
850
851/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */
852 ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
853
854/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */
855 ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_;
856
857/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */
858 ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
859
860/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */
861 ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
862
863/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */
864 ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_;
865
866/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */
867 ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
868
869/*----------------------------------------------------------------------*/
870/* BIT OPS */
871
872/** 1111 00sd rdst 0bit bset #%1, %0%S0 */
873 ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
874
875/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */
876 ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
877
878/** 0111 100b ittt rdst bset #%1, %0 */
879 ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
880
881
882/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */
883 ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
884
885/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */
886 ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
887
888/** 0111 101b ittt rdst bclr #%1, %0 */
889 ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
890
891
892/** 1111 01sd rdst 0bit btst #%2, %1%S1 */
893 ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC;
894
895/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */
896 ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC;
897
898/** 0111 110b ittt rdst btst #%2, %1 */
899 ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC;
900
901
902/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */
903 ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE);
904
905/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */
906 ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE);
907
908/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */
909 ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst);
910
911
912/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */
913 ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE);
914
915/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */
916 ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst);
917
918/*----------------------------------------------------------------------*/
919/* CONTROL REGISTERS */
920
921/** 0111 1111 1011 rdst clrpsw %0 */
922 ID(clrpsw); DF(rdst);
923
924/** 0111 1111 1010 rdst setpsw %0 */
925 ID(setpsw); DF(rdst);
926
927/** 0111 0101 0111 0000 0000 immm mvtipl #%1 */
928 ID(mvtipl); SC(immm);
929
930/** 0111 1110 111 crdst popc %0 */
931 ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16);
932
933/** 0111 1110 110 crsrc pushc %1 */
934 ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16);
935
936/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */
937 ID(mov); SC(IMMex(im)); DR(crdst + 16);
938
939/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */
940 ID(mov); SR(rsrc); DR(c*16+rdst + 16);
941
942/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */
943 ID(mov); SR((s*16+rsrc) + 16); DR(rdst);
944
945/*----------------------------------------------------------------------*/
946/* INTERRUPTS */
947
948/** 0111 1111 1001 0100 rtfi */
949 ID(rtfi);
950
951/** 0111 1111 1001 0101 rte */
952 ID(rte);
953
954/** 0000 0000 brk */
955 ID(brk);
956
957/** 0000 0001 dbt */
958 ID(dbt);
959
960/** 0111 0101 0110 0000 int #%1 */
961 ID(int); SC(IMM(1));
962
963/** 0111 1111 1001 0110 wait */
964 ID(wait);
965
966/*----------------------------------------------------------------------*/
967/* SCcnd */
968
969/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */
970 ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
971
972/** */
973
974 return rx->n_bytes;
975}
GDB Binutils - Deliverables
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