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stap-probe: Remove unnecessary cast
[deliverable/binutils-gdb.git] / opcodes / rx-decode.opc
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1/* -*- c -*- */
2/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4 Written by DJ Delorie.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23#include "sysdep.h"
24#include <stdio.h>
25#include <stdlib.h>
26#include <string.h>
27#include "ansidecl.h"
28#include "opcode/rx.h"
29
30#define RX_OPCODE_BIG_ENDIAN 0
31
32typedef struct
33{
34 RX_Opcode_Decoded * rx;
35 int (* getbyte)(void *);
36 void * ptr;
37 unsigned char * op;
38} LocalData;
39
40static int trace = 0;
41
42#define BSIZE 0
43#define WSIZE 1
44#define LSIZE 2
45
46/* These are for when the upper bits are "don't care" or "undefined". */
47static int bwl[] =
48{
49 RX_Byte,
50 RX_Word,
51 RX_Long,
52 0 /* Bogus instructions can have a size field set to 3. */
53};
54
55static int sbwl[] =
56{
57 RX_SByte,
58 RX_SWord,
59 RX_Long,
60 0 /* Bogus instructions can have a size field set to 3. */
61};
62
63static int ubwl[] =
64{
65 RX_UByte,
66 RX_UWord,
67 RX_Long,
68 0 /* Bogus instructions can have a size field set to 3. */
69};
70
71static int memex[] =
72{
73 RX_SByte,
74 RX_SWord,
75 RX_Long,
76 RX_UWord
77};
78
79#define ID(x) rx->id = RXO_##x
80#define OP(n,t,r,a) (rx->op[n].type = t, \
81 rx->op[n].reg = r, \
82 rx->op[n].addend = a )
83#define OPs(n,t,r,a,s) (OP (n,t,r,a), \
84 rx->op[n].size = s )
85
86/* This is for the BWL and BW bitfields. */
87static int SCALE[] = { 1, 2, 4, 0 };
88/* This is for the prefix size enum. */
89static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 };
90
91static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0,
92 16, 17, 0, 0, 0, 0, 0, 0 };
93
94static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
95
96/*
97 *C a constant (immediate) c
98 *R A register
99 *I Register indirect, no offset
100 *Is Register indirect, with offset
101 *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code
102 *P standard displacement: type (r,[r]), reg, assumes UByte
103 *Pm memex displacement: type (r,[r]), reg, memex code
104 *cc condition code. */
105
106#define DC(c) OP (0, RX_Operand_Immediate, 0, c)
107#define DR(r) OP (0, RX_Operand_Register, r, 0)
108#define DI(r,a) OP (0, RX_Operand_Indirect, r, a)
109#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s])
110#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld);
111#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0)
112
113#define SC(i) OP (1, RX_Operand_Immediate, 0, i)
114#define SR(r) OP (1, RX_Operand_Register, r, 0)
115#define SRR(r) OP (1, RX_Operand_TwoReg, r, 0)
116#define SI(r,a) OP (1, RX_Operand_Indirect, r, a)
117#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s])
118#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld);
119#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1);
120#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m];
121#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0)
122
123#define S2C(i) OP (2, RX_Operand_Immediate, 0, i)
124#define S2R(r) OP (2, RX_Operand_Register, r, 0)
125#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a)
126#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s])
127#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld);
128#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2);
129#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m];
130#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0)
131
132#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
133#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
134#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz]
135#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
136
137#define F(f) store_flags(rx, f)
138
139#define AU ATTRIBUTE_UNUSED
140#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr))
141
142#define SYNTAX(x) rx->syntax = x
143
144#define UNSUPPORTED() \
145 rx->syntax = "*unknown*"
146
147#define IMM(sf) immediate (sf, 0, ld)
148#define IMMex(sf) immediate (sf, 1, ld)
149
150static int
151immediate (int sfield, int ex, LocalData * ld)
152{
153 unsigned long i = 0, j;
154
155 switch (sfield)
156 {
157#define B ((unsigned long) GETBYTE())
158 case 0:
159#if RX_OPCODE_BIG_ENDIAN
160 i = B;
161 if (ex && (i & 0x80))
162 i -= 0x100;
163 i <<= 24;
164 i |= B << 16;
165 i |= B << 8;
166 i |= B;
167#else
168 i = B;
169 i |= B << 8;
170 i |= B << 16;
171 j = B;
172 if (ex && (j & 0x80))
173 j -= 0x100;
174 i |= j << 24;
175#endif
176 break;
177 case 3:
178#if RX_OPCODE_BIG_ENDIAN
179 i = B << 16;
180 i |= B << 8;
181 i |= B;
182#else
183 i = B;
184 i |= B << 8;
185 i |= B << 16;
186#endif
187 if (ex && (i & 0x800000))
188 i -= 0x1000000;
189 break;
190 case 2:
191#if RX_OPCODE_BIG_ENDIAN
192 i |= B << 8;
193 i |= B;
194#else
195 i |= B;
196 i |= B << 8;
197#endif
198 if (ex && (i & 0x8000))
199 i -= 0x10000;
200 break;
201 case 1:
202 i |= B;
203 if (ex && (i & 0x80))
204 i -= 0x100;
205 break;
206 default:
207 abort();
208 }
209 return i;
210}
211
212static void
213rx_disp (int n, int type, int reg, int size, LocalData * ld)
214{
215 int disp;
216
217 ld->rx->op[n].reg = reg;
218 switch (type)
219 {
220 case 3:
221 ld->rx->op[n].type = RX_Operand_Register;
222 break;
223 case 0:
224 ld->rx->op[n].type = RX_Operand_Indirect;
225 ld->rx->op[n].addend = 0;
226 break;
227 case 1:
228 ld->rx->op[n].type = RX_Operand_Indirect;
229 disp = GETBYTE ();
230 ld->rx->op[n].addend = disp * PSCALE[size];
231 break;
232 case 2:
233 ld->rx->op[n].type = RX_Operand_Indirect;
234 disp = GETBYTE ();
235#if RX_OPCODE_BIG_ENDIAN
236 disp = disp * 256 + GETBYTE ();
237#else
238 disp = disp + GETBYTE () * 256;
239#endif
240 ld->rx->op[n].addend = disp * PSCALE[size];
241 break;
242 default:
243 abort ();
244 }
245}
246
247#define xO 8
248#define xS 4
249#define xZ 2
250#define xC 1
251
252#define F_____
253#define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
254#define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
255#define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
256#define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC;
257#define F_O___ rx->flags_0 = rx->flags_s = xO;
258#define F_OS__ rx->flags_0 = rx->flags_s = xO|xS;
259#define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ;
260#define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC;
261
262int
263rx_decode_opcode (unsigned long pc AU,
264 RX_Opcode_Decoded * rx,
265 int (* getbyte)(void *),
266 void * ptr)
267{
268 LocalData lds, * ld = &lds;
269 unsigned char op[20] = {0};
270
271 lds.rx = rx;
272 lds.getbyte = getbyte;
273 lds.ptr = ptr;
274 lds.op = op;
275
276 memset (rx, 0, sizeof (*rx));
277 BWL(LSIZE);
278
279/** VARY sz 00 01 10 */
280
281/*----------------------------------------------------------------------*/
282/* MOV */
283
284/** 0111 0101 0100 rdst mov%s #%1, %0 */
285 ID(mov); DR(rdst); SC(IMM (1)); F_____;
286
287/** 1111 10sd rdst im sz mov%s #%1, %0 */
288 ID(mov); DD(sd, rdst, sz);
289 if ((im == 1 && sz == 0)
290 || (im == 2 && sz == 1)
291 || (im == 0 && sz == 2))
292 {
293 BWL (sz);
294 SC(IMM(im));
295 }
296 else
297 {
298 sBWL (sz);
299 SC(IMMex(im));
300 }
301 F_____;
302
303/** 0110 0110 immm rdst mov%s #%1, %0 */
304 ID(mov); DR(rdst); SC(immm); F_____;
305
306/** 0011 11sz d dst sppp mov%s #%1, %0 */
307 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
308
309/** 11sz sd ss rsrc rdst mov%s %1, %0 */
310 if (sd == 3 && ss == 3 && sz == 2 && rsrc == 0 && rdst == 0)
311 {
312 ID(nop2);
313 rx->syntax = "nop";
314 }
315 else
316 {
317 ID(mov); sBWL(sz); F_____;
318 if ((ss == 3) && (sd != 3))
319 {
320 SD(ss, rdst, sz); DD(sd, rsrc, sz);
321 }
322 else
323 {
324 SD(ss, rsrc, sz); DD(sd, rdst, sz);
325 }
326 }
327
328/** 10sz 1dsp a src b dst mov%s %1, %0 */
329 ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____;
330
331/** 10sz 0dsp a dst b src mov%s %1, %0 */
332 ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
333
334/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */
335 ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
336
337/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */
338 ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
339
340/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */
341 ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
342
343/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */
344 ID(mov); sBWL (sz); SR(rsrc); F_____;
345 OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0);
346
347/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */
348 ID(mov); sBWL (sz); DR(rdst); F_____;
349 OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
350
351/** 1011 w dsp a src b dst movu%s %1, %0 */
352 ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
353
354/** 0101 1 s ss rsrc rdst movu%s %1, %0 */
355 ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____;
356
357/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */
358 ID(mov); uBWL (sz); DR(rdst); F_____;
359 OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
360
361/*----------------------------------------------------------------------*/
362/* PUSH/POP */
363
364/** 0110 1111 dsta dstb popm %1-%2 */
365 ID(popm); SR(dsta); S2R(dstb); F_____;
366
367/** 0110 1110 dsta dstb pushm %1-%2 */
368 ID(pushm); SR(dsta); S2R(dstb); F_____;
369
370/** 0111 1110 1011 rdst pop %0 */
371 ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
372
373/** 0111 1110 10sz rsrc push%s %1 */
374 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
375
376/** 1111 01ss rsrc 10sz push%s %1 */
377 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____;
378
379/*----------------------------------------------------------------------*/
380/* XCHG */
381
382/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */
383 ID(xchg); DR(rdst); SP(ss, rsrc);
384
385/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */
386 ID(xchg); DR(rdst); SPm(ss, rsrc, mx);
387
388/*----------------------------------------------------------------------*/
389/* STZ/STNZ */
390
391/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */
392 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
393
394/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */
395 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
396
397/*----------------------------------------------------------------------*/
398/* RTSD */
399
400/** 0110 0111 rtsd #%1 */
401 ID(rtsd); SC(IMM(1) * 4);
402
403/** 0011 1111 rega regb rtsd #%1, %2-%0 */
404 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
405
406/*----------------------------------------------------------------------*/
407/* AND */
408
409/** 0110 0100 immm rdst and #%1, %0 */
410 ID(and); SC(immm); DR(rdst); F__SZ_;
411
412/** 0111 01im 0010 rdst and #%1, %0 */
413 ID(and); SC(IMMex(im)); DR(rdst); F__SZ_;
414
415/** 0101 00ss rsrc rdst and %1%S1, %0 */
416 ID(and); SP(ss, rsrc); DR(rdst); F__SZ_;
417
418/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */
419 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
420
421/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */
422 ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
423
424/*----------------------------------------------------------------------*/
425/* OR */
426
427/** 0110 0101 immm rdst or #%1, %0 */
428 ID(or); SC(immm); DR(rdst); F__SZ_;
429
430/** 0111 01im 0011 rdst or #%1, %0 */
431 ID(or); SC(IMMex(im)); DR(rdst); F__SZ_;
432
433/** 0101 01ss rsrc rdst or %1%S1, %0 */
434 ID(or); SP(ss, rsrc); DR(rdst); F__SZ_;
435
436/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */
437 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
438
439/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */
440 ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
441
442/*----------------------------------------------------------------------*/
443/* XOR */
444
445/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */
446 ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_;
447
448/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */
449 ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_;
450
451/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */
452 ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
453
454/*----------------------------------------------------------------------*/
455/* NOT */
456
457/** 0111 1110 0000 rdst not %0 */
458 ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
459
460/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */
461 ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_;
462
463/*----------------------------------------------------------------------*/
464/* TST */
465
466/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */
467 ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_;
468
469/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */
470 ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_;
471
472/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */
473 ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_;
474
475/*----------------------------------------------------------------------*/
476/* NEG */
477
478/** 0111 1110 0001 rdst neg %0 */
479 ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC;
480
481/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */
482 ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC;
483
484/*----------------------------------------------------------------------*/
485/* ADC */
486
487/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */
488 ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC;
489
490/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */
491 ID(adc); SR(rsrc); DR(rdst); F_OSZC;
492
493/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */
494 ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC;
495
496/*----------------------------------------------------------------------*/
497/* ADD */
498
499/** 0110 0010 immm rdst add #%1, %0 */
500 ID(add); SC(immm); DR(rdst); F_OSZC;
501
502/** 0100 10ss rsrc rdst add %1%S1, %0 */
503 ID(add); SP(ss, rsrc); DR(rdst); F_OSZC;
504
505/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */
506 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
507
508/** 0111 00im rsrc rdst add #%1, %2, %0 */
509 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC;
510
511/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */
512 ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
513
514/*----------------------------------------------------------------------*/
515/* CMP */
516
517/** 0110 0001 immm rdst cmp #%2, %1 */
518 ID(sub); S2C(immm); SR(rdst); F_OSZC;
519
520/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */
521 ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC;
522
523/** 0111 0101 0101 rsrc cmp #%2, %1 */
524 ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC;
525
526/** 0100 01ss rsrc rdst cmp %2%S2, %1 */
527 ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC;
528
529/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */
530 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC;
531
532/*----------------------------------------------------------------------*/
533/* SUB */
534
535/** 0110 0000 immm rdst sub #%2, %0 */
536 ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC;
537
538/** 0100 00ss rsrc rdst sub %2%S2, %1 */
539 ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC;
540
541/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */
542 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
543
544/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */
545 ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
546
547/*----------------------------------------------------------------------*/
548/* SBB */
549
550/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */
551 ID(sbb); SR (rsrc); DR(rdst); F_OSZC;
552
553 /* FIXME: only supports .L */
554/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */
555 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
556
557/*----------------------------------------------------------------------*/
558/* ABS */
559
560/** 0111 1110 0010 rdst abs %0 */
561 ID(abs); DR(rdst); SR(rdst); F_OSZ_;
562
563/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */
564 ID(abs); DR(rdst); SR(rsrc); F_OSZ_;
565
566/*----------------------------------------------------------------------*/
567/* MAX */
568
569/** 1111 1101 0111 im00 0100rdst max #%1, %0 */
570 ID(max); DR(rdst); SC(IMMex(im));
571
572/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */
573 if (ss == 3 && rsrc == 0 && rdst == 0)
574 {
575 ID(nop3);
576 rx->syntax = "nop";
577 }
578 else
579 {
580 ID(max); SP(ss, rsrc); DR(rdst);
581 }
582
583/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */
584 ID(max); SPm(ss, rsrc, mx); DR(rdst);
585
586/*----------------------------------------------------------------------*/
587/* MIN */
588
589/** 1111 1101 0111 im00 0101rdst min #%1, %0 */
590 ID(min); DR(rdst); SC(IMMex(im));
591
592/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */
593 ID(min); SP(ss, rsrc); DR(rdst);
594
595/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */
596 ID(min); SPm(ss, rsrc, mx); DR(rdst);
597
598/*----------------------------------------------------------------------*/
599/* MUL */
600
601/** 0110 0011 immm rdst mul #%1, %0 */
602 ID(mul); DR(rdst); SC(immm); F_____;
603
604/** 0111 01im 0001rdst mul #%1, %0 */
605 ID(mul); DR(rdst); SC(IMMex(im)); F_____;
606
607/** 0100 11ss rsrc rdst mul %1%S1, %0 */
608 ID(mul); SP(ss, rsrc); DR(rdst); F_____;
609
610/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */
611 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
612
613/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */
614 ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____;
615
616/*----------------------------------------------------------------------*/
617/* EMUL */
618
619/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */
620 ID(emul); DR(rdst); SC(IMMex(im));
621
622/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */
623 ID(emul); SP(ss, rsrc); DR(rdst);
624
625/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */
626 ID(emul); SPm(ss, rsrc, mx); DR(rdst);
627
628/*----------------------------------------------------------------------*/
629/* EMULU */
630
631/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */
632 ID(emulu); DR(rdst); SC(IMMex(im));
633
634/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */
635 ID(emulu); SP(ss, rsrc); DR(rdst);
636
637/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */
638 ID(emulu); SPm(ss, rsrc, mx); DR(rdst);
639
640/*----------------------------------------------------------------------*/
641/* DIV */
642
643/** 1111 1101 0111 im00 1000rdst div #%1, %0 */
644 ID(div); DR(rdst); SC(IMMex(im)); F_O___;
645
646/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */
647 ID(div); SP(ss, rsrc); DR(rdst); F_O___;
648
649/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */
650 ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___;
651
652/*----------------------------------------------------------------------*/
653/* DIVU */
654
655/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */
656 ID(divu); DR(rdst); SC(IMMex(im)); F_O___;
657
658/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */
659 ID(divu); SP(ss, rsrc); DR(rdst); F_O___;
660
661/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */
662 ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___;
663
664/*----------------------------------------------------------------------*/
665/* SHIFT */
666
667/** 0110 110i mmmm rdst shll #%2, %0 */
668 ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC;
669
670/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */
671 ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC;
672
673/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */
674 ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC;
675
676
677/** 0110 101i mmmm rdst shar #%2, %0 */
678 ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC;
679
680/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */
681 ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC;
682
683/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */
684 ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC;
685
686
687/** 0110 100i mmmm rdst shlr #%2, %0 */
688 ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC;
689
690/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */
691 ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC;
692
693/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */
694 ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC;
695
696/*----------------------------------------------------------------------*/
697/* ROTATE */
698
699/** 0111 1110 0101 rdst rolc %0 */
700 ID(rolc); DR(rdst); F__SZC;
701
702/** 0111 1110 0100 rdst rorc %0 */
703 ID(rorc); DR(rdst); F__SZC;
704
705/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */
706 ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC;
707
708/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */
709 ID(rotl); SR(rsrc); DR(rdst); F__SZC;
710
711/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */
712 ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC;
713
714/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */
715 ID(rotr); SR(rsrc); DR(rdst); F__SZC;
716
717/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */
718 ID(revw); SR(rsrc); DR(rdst);
719
720/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */
721 ID(revl); SR(rsrc); DR(rdst);
722
723/*----------------------------------------------------------------------*/
724/* BRANCH */
725
726/** 0001 n dsp b%1.s %a0 */
727 ID(branch); Scc(n); DC(pc + dsp3map[dsp]);
728
729/** 0010 cond b%1.b %a0 */
730 ID(branch); Scc(cond); DC(pc + IMMex (1));
731
732/** 0011 101c b%1.w %a0 */
733 ID(branch); Scc(c); DC(pc + IMMex (2));
734
735
736/** 0000 1dsp bra.s %a0 */
737 ID(branch); DC(pc + dsp3map[dsp]);
738
739/** 0010 1110 bra.b %a0 */
740 ID(branch); DC(pc + IMMex(1));
741
742/** 0011 1000 bra.w %a0 */
743 ID(branch); DC(pc + IMMex(2));
744
745/** 0000 0100 bra.a %a0 */
746 ID(branch); DC(pc + IMMex(3));
747
748/** 0111 1111 0100 rsrc bra.l %0 */
749 ID(branchrel); DR(rsrc);
750
751
752/** 0111 1111 0000 rsrc jmp %0 */
753 ID(branch); DR(rsrc);
754
755/** 0111 1111 0001 rsrc jsr %0 */
756 ID(jsr); DR(rsrc);
757
758/** 0011 1001 bsr.w %a0 */
759 ID(jsr); DC(pc + IMMex(2));
760
761/** 0000 0101 bsr.a %a0 */
762 ID(jsr); DC(pc + IMMex(3));
763
764/** 0111 1111 0101 rsrc bsr.l %0 */
765 ID(jsrrel); DR(rsrc);
766
767/** 0000 0010 rts */
768 ID(rts);
769
770/*----------------------------------------------------------------------*/
771/* NOP */
772
773/** 0000 0011 nop */
774 ID(nop);
775
776/*----------------------------------------------------------------------*/
777/* STRING FUNCTIONS */
778
779/** 0111 1111 1000 0011 scmpu */
780 ID(scmpu); F___ZC;
781
782/** 0111 1111 1000 0111 smovu */
783 ID(smovu);
784
785/** 0111 1111 1000 1011 smovb */
786 ID(smovb);
787
788/** 0111 1111 1000 00sz suntil%s */
789 ID(suntil); BWL(sz); F___ZC;
790
791/** 0111 1111 1000 01sz swhile%s */
792 ID(swhile); BWL(sz); F___ZC;
793
794/** 0111 1111 1000 1111 smovf */
795 ID(smovf);
796
797/** 0111 1111 1000 10sz sstr%s */
798 ID(sstr); BWL(sz);
799
800/*----------------------------------------------------------------------*/
801/* RMPA */
802
803/** 0111 1111 1000 11sz rmpa%s */
804 ID(rmpa); BWL(sz); F_OS__;
805
806/*----------------------------------------------------------------------*/
807/* HI/LO stuff */
808
809/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */
810 ID(mulhi); SR(srca); S2R(srcb); F_____;
811
812/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */
813 ID(mullo); SR(srca); S2R(srcb); F_____;
814
815/** 1111 1101 0000 0100 srca srcb machi %1, %2 */
816 ID(machi); SR(srca); S2R(srcb); F_____;
817
818/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */
819 ID(maclo); SR(srca); S2R(srcb); F_____;
820
821/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */
822 ID(mvtachi); SR(rsrc); F_____;
823
824/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */
825 ID(mvtaclo); SR(rsrc); F_____;
826
827/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */
828 ID(mvfachi); DR(rdst); F_____;
829
830/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */
831 ID(mvfacmi); DR(rdst); F_____;
832
833/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */
834 ID(mvfaclo); DR(rdst); F_____;
835
836/** 1111 1101 0001 1000 000i 0000 racw #%1 */
837 ID(racw); SC(i+1); F_____;
838
839/*----------------------------------------------------------------------*/
840/* SAT */
841
842/** 0111 1110 0011 rdst sat %0 */
843 ID(sat); DR (rdst);
844
845/** 0111 1111 1001 0011 satr */
846 ID(satr);
847
848/*----------------------------------------------------------------------*/
849/* FLOAT */
850
851/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */
852 ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_;
853
854/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */
855 ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
856
857/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */
858 ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_;
859
860/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */
861 ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_;
862
863/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */
864 ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_;
865
866/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */
867 ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
868
869/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */
870 ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
871
872/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */
873 ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_;
874
875/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */
876 ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
877
878/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */
879 ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_;
880
881/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */
882 ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
883
884/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */
885 ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
886
887/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */
888 ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_;
889
890/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */
891 ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
892
893/*----------------------------------------------------------------------*/
894/* BIT OPS */
895
896/** 1111 00sd rdst 0bit bset #%1, %0%S0 */
897 ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
898
899/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */
900 ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
901 if (sd == 3) /* bset reg,reg */
902 BWL(LSIZE);
903
904/** 0111 100b ittt rdst bset #%1, %0 */
905 ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
906
907
908/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */
909 ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
910
911/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */
912 ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
913 if (sd == 3) /* bset reg,reg */
914 BWL(LSIZE);
915
916/** 0111 101b ittt rdst bclr #%1, %0 */
917 ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
918
919
920/** 1111 01sd rdst 0bit btst #%2, %1%S1 */
921 ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC;
922
923/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */
924 ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC;
925 if (sd == 3) /* bset reg,reg */
926 BWL(LSIZE);
927
928/** 0111 110b ittt rdst btst #%2, %1 */
929 ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC;
930
931
932/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */
933 ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE);
934
935/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */
936 ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE);
937 if (sd == 3) /* bset reg,reg */
938 BWL(LSIZE);
939
940/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */
941 ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst);
942
943
944/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */
945 ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE);
946
947/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */
948 ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst);
949
950/*----------------------------------------------------------------------*/
951/* CONTROL REGISTERS */
952
953/** 0111 1111 1011 rdst clrpsw %0 */
954 ID(clrpsw); DF(rdst);
955
956/** 0111 1111 1010 rdst setpsw %0 */
957 ID(setpsw); DF(rdst);
958
959/** 0111 0101 0111 0000 0000 immm mvtipl #%1 */
960 ID(mvtipl); SC(immm);
961
962/** 0111 1110 111 crdst popc %0 */
963 ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16);
964
965/** 0111 1110 110 crsrc pushc %1 */
966 ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16);
967
968/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */
969 ID(mov); SC(IMMex(im)); DR(crdst + 16);
970
971/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */
972 ID(mov); SR(rsrc); DR(c*16+rdst + 16);
973
974/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */
975 ID(mov); SR((s*16+rsrc) + 16); DR(rdst);
976
977/*----------------------------------------------------------------------*/
978/* INTERRUPTS */
979
980/** 0111 1111 1001 0100 rtfi */
981 ID(rtfi);
982
983/** 0111 1111 1001 0101 rte */
984 ID(rte);
985
986/** 0000 0000 brk */
987 ID(brk);
988
989/** 0000 0001 dbt */
990 ID(dbt);
991
992/** 0111 0101 0110 0000 int #%1 */
993 ID(int); SC(IMM(1));
994
995/** 0111 1111 1001 0110 wait */
996 ID(wait);
997
998/*----------------------------------------------------------------------*/
999/* SCcnd */
1000
1001/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */
1002 ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
1003
1004/** */
1005
1006 return rx->n_bytes;
1007}
GDB Binutils - Deliverables
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