| 1 | /* Print SPARC instructions. |
| 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
| 3 | 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the Free Software |
| 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 18 | MA 02110-1301, USA. */ |
| 19 | |
| 20 | #include <stdio.h> |
| 21 | |
| 22 | #include "sysdep.h" |
| 23 | #include "opcode/sparc.h" |
| 24 | #include "dis-asm.h" |
| 25 | #include "libiberty.h" |
| 26 | #include "opintl.h" |
| 27 | |
| 28 | /* Bitmask of v9 architectures. */ |
| 29 | #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ |
| 30 | | (1 << SPARC_OPCODE_ARCH_V9A) \ |
| 31 | | (1 << SPARC_OPCODE_ARCH_V9B)) |
| 32 | /* 1 if INSN is for v9 only. */ |
| 33 | #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) |
| 34 | /* 1 if INSN is for v9. */ |
| 35 | #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) |
| 36 | |
| 37 | /* The sorted opcode table. */ |
| 38 | static const sparc_opcode **sorted_opcodes; |
| 39 | |
| 40 | /* For faster lookup, after insns are sorted they are hashed. */ |
| 41 | /* ??? I think there is room for even more improvement. */ |
| 42 | |
| 43 | #define HASH_SIZE 256 |
| 44 | /* It is important that we only look at insn code bits as that is how the |
| 45 | opcode table is hashed. OPCODE_BITS is a table of valid bits for each |
| 46 | of the main types (0,1,2,3). */ |
| 47 | static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; |
| 48 | #define HASH_INSN(INSN) \ |
| 49 | ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) |
| 50 | typedef struct sparc_opcode_hash |
| 51 | { |
| 52 | struct sparc_opcode_hash *next; |
| 53 | const sparc_opcode *opcode; |
| 54 | } sparc_opcode_hash; |
| 55 | |
| 56 | static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; |
| 57 | |
| 58 | /* Sign-extend a value which is N bits long. */ |
| 59 | #define SEX(value, bits) \ |
| 60 | ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ |
| 61 | >> ((8 * sizeof (int)) - bits) ) |
| 62 | |
| 63 | static char *reg_names[] = |
| 64 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 65 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
| 66 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 67 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
| 68 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 69 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 70 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 71 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 72 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
| 73 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
| 74 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
| 75 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
| 76 | /* psr, wim, tbr, fpsr, cpsr are v8 only. */ |
| 77 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
| 78 | }; |
| 79 | |
| 80 | #define freg_names (®_names[4 * 8]) |
| 81 | |
| 82 | /* These are ordered according to there register number in |
| 83 | rdpr and wrpr insns. */ |
| 84 | static char *v9_priv_reg_names[] = |
| 85 | { |
| 86 | "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", |
| 87 | "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", |
| 88 | "wstate", "fq", "gl" |
| 89 | /* "ver" - special cased */ |
| 90 | }; |
| 91 | |
| 92 | /* These are ordered according to there register number in |
| 93 | rdhpr and wrhpr insns. */ |
| 94 | static char *v9_hpriv_reg_names[] = |
| 95 | { |
| 96 | "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", |
| 97 | "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", |
| 98 | "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", |
| 99 | "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27", |
| 100 | "resv28", "resv29", "resv30", "hstick_cmpr" |
| 101 | }; |
| 102 | |
| 103 | /* These are ordered according to there register number in |
| 104 | rd and wr insns (-16). */ |
| 105 | static char *v9a_asr_reg_names[] = |
| 106 | { |
| 107 | "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", |
| 108 | "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" |
| 109 | }; |
| 110 | |
| 111 | /* Macros used to extract instruction fields. Not all fields have |
| 112 | macros defined here, only those which are actually used. */ |
| 113 | |
| 114 | #define X_RD(i) (((i) >> 25) & 0x1f) |
| 115 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
| 116 | #define X_LDST_I(i) (((i) >> 13) & 1) |
| 117 | #define X_ASI(i) (((i) >> 5) & 0xff) |
| 118 | #define X_RS2(i) (((i) >> 0) & 0x1f) |
| 119 | #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) |
| 120 | #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) |
| 121 | #define X_DISP22(i) (((i) >> 0) & 0x3fffff) |
| 122 | #define X_IMM22(i) X_DISP22 (i) |
| 123 | #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) |
| 124 | |
| 125 | /* These are for v9. */ |
| 126 | #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) |
| 127 | #define X_DISP19(i) (((i) >> 0) & 0x7ffff) |
| 128 | #define X_MEMBAR(i) ((i) & 0x7f) |
| 129 | |
| 130 | /* Here is the union which was used to extract instruction fields |
| 131 | before the shift and mask macros were written. |
| 132 | |
| 133 | union sparc_insn |
| 134 | { |
| 135 | unsigned long int code; |
| 136 | struct |
| 137 | { |
| 138 | unsigned int anop:2; |
| 139 | #define op ldst.anop |
| 140 | unsigned int anrd:5; |
| 141 | #define rd ldst.anrd |
| 142 | unsigned int op3:6; |
| 143 | unsigned int anrs1:5; |
| 144 | #define rs1 ldst.anrs1 |
| 145 | unsigned int i:1; |
| 146 | unsigned int anasi:8; |
| 147 | #define asi ldst.anasi |
| 148 | unsigned int anrs2:5; |
| 149 | #define rs2 ldst.anrs2 |
| 150 | #define shcnt rs2 |
| 151 | } ldst; |
| 152 | struct |
| 153 | { |
| 154 | unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; |
| 155 | unsigned int IMM13:13; |
| 156 | #define imm13 IMM13.IMM13 |
| 157 | } IMM13; |
| 158 | struct |
| 159 | { |
| 160 | unsigned int anop:2; |
| 161 | unsigned int a:1; |
| 162 | unsigned int cond:4; |
| 163 | unsigned int op2:3; |
| 164 | unsigned int DISP22:22; |
| 165 | #define disp22 branch.DISP22 |
| 166 | #define imm22 disp22 |
| 167 | } branch; |
| 168 | struct |
| 169 | { |
| 170 | unsigned int anop:2; |
| 171 | unsigned int a:1; |
| 172 | unsigned int z:1; |
| 173 | unsigned int rcond:3; |
| 174 | unsigned int op2:3; |
| 175 | unsigned int DISP16HI:2; |
| 176 | unsigned int p:1; |
| 177 | unsigned int _rs1:5; |
| 178 | unsigned int DISP16LO:14; |
| 179 | } branch16; |
| 180 | struct |
| 181 | { |
| 182 | unsigned int anop:2; |
| 183 | unsigned int adisp30:30; |
| 184 | #define disp30 call.adisp30 |
| 185 | } call; |
| 186 | }; */ |
| 187 | |
| 188 | /* Nonzero if INSN is the opcode for a delayed branch. */ |
| 189 | |
| 190 | static int |
| 191 | is_delayed_branch (unsigned long insn) |
| 192 | { |
| 193 | sparc_opcode_hash *op; |
| 194 | |
| 195 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
| 196 | { |
| 197 | const sparc_opcode *opcode = op->opcode; |
| 198 | |
| 199 | if ((opcode->match & insn) == opcode->match |
| 200 | && (opcode->lose & insn) == 0) |
| 201 | return opcode->flags & F_DELAYED; |
| 202 | } |
| 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | /* extern void qsort (); */ |
| 207 | |
| 208 | /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value |
| 209 | to compare_opcodes. */ |
| 210 | static unsigned int current_arch_mask; |
| 211 | |
| 212 | /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ |
| 213 | |
| 214 | static int |
| 215 | compute_arch_mask (unsigned long mach) |
| 216 | { |
| 217 | switch (mach) |
| 218 | { |
| 219 | case 0 : |
| 220 | case bfd_mach_sparc : |
| 221 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); |
| 222 | case bfd_mach_sparc_sparclet : |
| 223 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); |
| 224 | case bfd_mach_sparc_sparclite : |
| 225 | case bfd_mach_sparc_sparclite_le : |
| 226 | /* sparclites insns are recognized by default (because that's how |
| 227 | they've always been treated, for better or worse). Kludge this by |
| 228 | indicating generic v8 is also selected. */ |
| 229 | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) |
| 230 | | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); |
| 231 | case bfd_mach_sparc_v8plus : |
| 232 | case bfd_mach_sparc_v9 : |
| 233 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); |
| 234 | case bfd_mach_sparc_v8plusa : |
| 235 | case bfd_mach_sparc_v9a : |
| 236 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); |
| 237 | case bfd_mach_sparc_v8plusb : |
| 238 | case bfd_mach_sparc_v9b : |
| 239 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); |
| 240 | } |
| 241 | abort (); |
| 242 | } |
| 243 | |
| 244 | /* Compare opcodes A and B. */ |
| 245 | |
| 246 | static int |
| 247 | compare_opcodes (const void * a, const void * b) |
| 248 | { |
| 249 | sparc_opcode *op0 = * (sparc_opcode **) a; |
| 250 | sparc_opcode *op1 = * (sparc_opcode **) b; |
| 251 | unsigned long int match0 = op0->match, match1 = op1->match; |
| 252 | unsigned long int lose0 = op0->lose, lose1 = op1->lose; |
| 253 | register unsigned int i; |
| 254 | |
| 255 | /* If one (and only one) insn isn't supported by the current architecture, |
| 256 | prefer the one that is. If neither are supported, but they're both for |
| 257 | the same architecture, continue processing. Otherwise (both unsupported |
| 258 | and for different architectures), prefer lower numbered arch's (fudged |
| 259 | by comparing the bitmasks). */ |
| 260 | if (op0->architecture & current_arch_mask) |
| 261 | { |
| 262 | if (! (op1->architecture & current_arch_mask)) |
| 263 | return -1; |
| 264 | } |
| 265 | else |
| 266 | { |
| 267 | if (op1->architecture & current_arch_mask) |
| 268 | return 1; |
| 269 | else if (op0->architecture != op1->architecture) |
| 270 | return op0->architecture - op1->architecture; |
| 271 | } |
| 272 | |
| 273 | /* If a bit is set in both match and lose, there is something |
| 274 | wrong with the opcode table. */ |
| 275 | if (match0 & lose0) |
| 276 | { |
| 277 | fprintf |
| 278 | (stderr, |
| 279 | /* xgettext:c-format */ |
| 280 | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), |
| 281 | op0->name, match0, lose0); |
| 282 | op0->lose &= ~op0->match; |
| 283 | lose0 = op0->lose; |
| 284 | } |
| 285 | |
| 286 | if (match1 & lose1) |
| 287 | { |
| 288 | fprintf |
| 289 | (stderr, |
| 290 | /* xgettext:c-format */ |
| 291 | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), |
| 292 | op1->name, match1, lose1); |
| 293 | op1->lose &= ~op1->match; |
| 294 | lose1 = op1->lose; |
| 295 | } |
| 296 | |
| 297 | /* Because the bits that are variable in one opcode are constant in |
| 298 | another, it is important to order the opcodes in the right order. */ |
| 299 | for (i = 0; i < 32; ++i) |
| 300 | { |
| 301 | unsigned long int x = 1 << i; |
| 302 | int x0 = (match0 & x) != 0; |
| 303 | int x1 = (match1 & x) != 0; |
| 304 | |
| 305 | if (x0 != x1) |
| 306 | return x1 - x0; |
| 307 | } |
| 308 | |
| 309 | for (i = 0; i < 32; ++i) |
| 310 | { |
| 311 | unsigned long int x = 1 << i; |
| 312 | int x0 = (lose0 & x) != 0; |
| 313 | int x1 = (lose1 & x) != 0; |
| 314 | |
| 315 | if (x0 != x1) |
| 316 | return x1 - x0; |
| 317 | } |
| 318 | |
| 319 | /* They are functionally equal. So as long as the opcode table is |
| 320 | valid, we can put whichever one first we want, on aesthetic grounds. */ |
| 321 | |
| 322 | /* Our first aesthetic ground is that aliases defer to real insns. */ |
| 323 | { |
| 324 | int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); |
| 325 | |
| 326 | if (alias_diff != 0) |
| 327 | /* Put the one that isn't an alias first. */ |
| 328 | return alias_diff; |
| 329 | } |
| 330 | |
| 331 | /* Except for aliases, two "identical" instructions had |
| 332 | better have the same opcode. This is a sanity check on the table. */ |
| 333 | i = strcmp (op0->name, op1->name); |
| 334 | if (i) |
| 335 | { |
| 336 | if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ |
| 337 | return i; |
| 338 | else |
| 339 | fprintf (stderr, |
| 340 | /* xgettext:c-format */ |
| 341 | _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), |
| 342 | op0->name, op1->name); |
| 343 | } |
| 344 | |
| 345 | /* Fewer arguments are preferred. */ |
| 346 | { |
| 347 | int length_diff = strlen (op0->args) - strlen (op1->args); |
| 348 | |
| 349 | if (length_diff != 0) |
| 350 | /* Put the one with fewer arguments first. */ |
| 351 | return length_diff; |
| 352 | } |
| 353 | |
| 354 | /* Put 1+i before i+1. */ |
| 355 | { |
| 356 | char *p0 = (char *) strchr (op0->args, '+'); |
| 357 | char *p1 = (char *) strchr (op1->args, '+'); |
| 358 | |
| 359 | if (p0 && p1) |
| 360 | { |
| 361 | /* There is a plus in both operands. Note that a plus |
| 362 | sign cannot be the first character in args, |
| 363 | so the following [-1]'s are valid. */ |
| 364 | if (p0[-1] == 'i' && p1[1] == 'i') |
| 365 | /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ |
| 366 | return 1; |
| 367 | if (p0[1] == 'i' && p1[-1] == 'i') |
| 368 | /* op0 is 1+i and op1 is i+1, so op0 goes first. */ |
| 369 | return -1; |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | /* Put 1,i before i,1. */ |
| 374 | { |
| 375 | int i0 = strncmp (op0->args, "i,1", 3) == 0; |
| 376 | int i1 = strncmp (op1->args, "i,1", 3) == 0; |
| 377 | |
| 378 | if (i0 ^ i1) |
| 379 | return i0 - i1; |
| 380 | } |
| 381 | |
| 382 | /* They are, as far as we can tell, identical. |
| 383 | Since qsort may have rearranged the table partially, there is |
| 384 | no way to tell which one was first in the opcode table as |
| 385 | written, so just say there are equal. */ |
| 386 | /* ??? This is no longer true now that we sort a vector of pointers, |
| 387 | not the table itself. */ |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | /* Build a hash table from the opcode table. |
| 392 | OPCODE_TABLE is a sorted list of pointers into the opcode table. */ |
| 393 | |
| 394 | static void |
| 395 | build_hash_table (const sparc_opcode **opcode_table, |
| 396 | sparc_opcode_hash **hash_table, |
| 397 | int num_opcodes) |
| 398 | { |
| 399 | int i; |
| 400 | int hash_count[HASH_SIZE]; |
| 401 | static sparc_opcode_hash *hash_buf = NULL; |
| 402 | |
| 403 | /* Start at the end of the table and work backwards so that each |
| 404 | chain is sorted. */ |
| 405 | |
| 406 | memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); |
| 407 | memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); |
| 408 | if (hash_buf != NULL) |
| 409 | free (hash_buf); |
| 410 | hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes); |
| 411 | for (i = num_opcodes - 1; i >= 0; --i) |
| 412 | { |
| 413 | int hash = HASH_INSN (opcode_table[i]->match); |
| 414 | sparc_opcode_hash *h = &hash_buf[i]; |
| 415 | |
| 416 | h->next = hash_table[hash]; |
| 417 | h->opcode = opcode_table[i]; |
| 418 | hash_table[hash] = h; |
| 419 | ++hash_count[hash]; |
| 420 | } |
| 421 | |
| 422 | #if 0 /* for debugging */ |
| 423 | { |
| 424 | int min_count = num_opcodes, max_count = 0; |
| 425 | int total; |
| 426 | |
| 427 | for (i = 0; i < HASH_SIZE; ++i) |
| 428 | { |
| 429 | if (hash_count[i] < min_count) |
| 430 | min_count = hash_count[i]; |
| 431 | if (hash_count[i] > max_count) |
| 432 | max_count = hash_count[i]; |
| 433 | total += hash_count[i]; |
| 434 | } |
| 435 | |
| 436 | printf ("Opcode hash table stats: min %d, max %d, ave %f\n", |
| 437 | min_count, max_count, (double) total / HASH_SIZE); |
| 438 | } |
| 439 | #endif |
| 440 | } |
| 441 | |
| 442 | /* Print one instruction from MEMADDR on INFO->STREAM. |
| 443 | |
| 444 | We suffix the instruction with a comment that gives the absolute |
| 445 | address involved, as well as its symbolic form, if the instruction |
| 446 | is preceded by a findable `sethi' and it either adds an immediate |
| 447 | displacement to that register, or it is an `add' or `or' instruction |
| 448 | on that register. */ |
| 449 | |
| 450 | int |
| 451 | print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
| 452 | { |
| 453 | FILE *stream = info->stream; |
| 454 | bfd_byte buffer[4]; |
| 455 | unsigned long insn; |
| 456 | sparc_opcode_hash *op; |
| 457 | /* Nonzero of opcode table has been initialized. */ |
| 458 | static int opcodes_initialized = 0; |
| 459 | /* bfd mach number of last call. */ |
| 460 | static unsigned long current_mach = 0; |
| 461 | bfd_vma (*getword) (const void *); |
| 462 | |
| 463 | if (!opcodes_initialized |
| 464 | || info->mach != current_mach) |
| 465 | { |
| 466 | int i; |
| 467 | |
| 468 | current_arch_mask = compute_arch_mask (info->mach); |
| 469 | |
| 470 | if (!opcodes_initialized) |
| 471 | sorted_opcodes = |
| 472 | xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *)); |
| 473 | /* Reset the sorted table so we can resort it. */ |
| 474 | for (i = 0; i < sparc_num_opcodes; ++i) |
| 475 | sorted_opcodes[i] = &sparc_opcodes[i]; |
| 476 | qsort ((char *) sorted_opcodes, sparc_num_opcodes, |
| 477 | sizeof (sorted_opcodes[0]), compare_opcodes); |
| 478 | |
| 479 | build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); |
| 480 | current_mach = info->mach; |
| 481 | opcodes_initialized = 1; |
| 482 | } |
| 483 | |
| 484 | { |
| 485 | int status = |
| 486 | (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); |
| 487 | |
| 488 | if (status != 0) |
| 489 | { |
| 490 | (*info->memory_error_func) (status, memaddr, info); |
| 491 | return -1; |
| 492 | } |
| 493 | } |
| 494 | |
| 495 | /* On SPARClite variants such as DANlite (sparc86x), instructions |
| 496 | are always big-endian even when the machine is in little-endian mode. */ |
| 497 | if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) |
| 498 | getword = bfd_getb32; |
| 499 | else |
| 500 | getword = bfd_getl32; |
| 501 | |
| 502 | insn = getword (buffer); |
| 503 | |
| 504 | info->insn_info_valid = 1; /* We do return this info. */ |
| 505 | info->insn_type = dis_nonbranch; /* Assume non branch insn. */ |
| 506 | info->branch_delay_insns = 0; /* Assume no delay. */ |
| 507 | info->target = 0; /* Assume no target known. */ |
| 508 | |
| 509 | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
| 510 | { |
| 511 | const sparc_opcode *opcode = op->opcode; |
| 512 | |
| 513 | /* If the insn isn't supported by the current architecture, skip it. */ |
| 514 | if (! (opcode->architecture & current_arch_mask)) |
| 515 | continue; |
| 516 | |
| 517 | if ((opcode->match & insn) == opcode->match |
| 518 | && (opcode->lose & insn) == 0) |
| 519 | { |
| 520 | /* Nonzero means that we have found an instruction which has |
| 521 | the effect of adding or or'ing the imm13 field to rs1. */ |
| 522 | int imm_added_to_rs1 = 0; |
| 523 | int imm_ored_to_rs1 = 0; |
| 524 | |
| 525 | /* Nonzero means that we have found a plus sign in the args |
| 526 | field of the opcode table. */ |
| 527 | int found_plus = 0; |
| 528 | |
| 529 | /* Nonzero means we have an annulled branch. */ |
| 530 | int is_annulled = 0; |
| 531 | |
| 532 | /* Do we have an `add' or `or' instruction combining an |
| 533 | immediate with rs1? */ |
| 534 | if (opcode->match == 0x80102000) /* or */ |
| 535 | imm_ored_to_rs1 = 1; |
| 536 | if (opcode->match == 0x80002000) /* add */ |
| 537 | imm_added_to_rs1 = 1; |
| 538 | |
| 539 | if (X_RS1 (insn) != X_RD (insn) |
| 540 | && strchr (opcode->args, 'r') != 0) |
| 541 | /* Can't do simple format if source and dest are different. */ |
| 542 | continue; |
| 543 | if (X_RS2 (insn) != X_RD (insn) |
| 544 | && strchr (opcode->args, 'O') != 0) |
| 545 | /* Can't do simple format if source and dest are different. */ |
| 546 | continue; |
| 547 | |
| 548 | (*info->fprintf_func) (stream, opcode->name); |
| 549 | |
| 550 | { |
| 551 | const char *s; |
| 552 | |
| 553 | if (opcode->args[0] != ',') |
| 554 | (*info->fprintf_func) (stream, " "); |
| 555 | |
| 556 | for (s = opcode->args; *s != '\0'; ++s) |
| 557 | { |
| 558 | while (*s == ',') |
| 559 | { |
| 560 | (*info->fprintf_func) (stream, ","); |
| 561 | ++s; |
| 562 | switch (*s) |
| 563 | { |
| 564 | case 'a': |
| 565 | (*info->fprintf_func) (stream, "a"); |
| 566 | is_annulled = 1; |
| 567 | ++s; |
| 568 | continue; |
| 569 | case 'N': |
| 570 | (*info->fprintf_func) (stream, "pn"); |
| 571 | ++s; |
| 572 | continue; |
| 573 | |
| 574 | case 'T': |
| 575 | (*info->fprintf_func) (stream, "pt"); |
| 576 | ++s; |
| 577 | continue; |
| 578 | |
| 579 | default: |
| 580 | break; |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | (*info->fprintf_func) (stream, " "); |
| 585 | |
| 586 | switch (*s) |
| 587 | { |
| 588 | case '+': |
| 589 | found_plus = 1; |
| 590 | /* Fall through. */ |
| 591 | |
| 592 | default: |
| 593 | (*info->fprintf_func) (stream, "%c", *s); |
| 594 | break; |
| 595 | |
| 596 | case '#': |
| 597 | (*info->fprintf_func) (stream, "0"); |
| 598 | break; |
| 599 | |
| 600 | #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) |
| 601 | case '1': |
| 602 | case 'r': |
| 603 | reg (X_RS1 (insn)); |
| 604 | break; |
| 605 | |
| 606 | case '2': |
| 607 | case 'O': |
| 608 | reg (X_RS2 (insn)); |
| 609 | break; |
| 610 | |
| 611 | case 'd': |
| 612 | reg (X_RD (insn)); |
| 613 | break; |
| 614 | #undef reg |
| 615 | |
| 616 | #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) |
| 617 | #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) |
| 618 | case 'e': |
| 619 | freg (X_RS1 (insn)); |
| 620 | break; |
| 621 | case 'v': /* Double/even. */ |
| 622 | case 'V': /* Quad/multiple of 4. */ |
| 623 | fregx (X_RS1 (insn)); |
| 624 | break; |
| 625 | |
| 626 | case 'f': |
| 627 | freg (X_RS2 (insn)); |
| 628 | break; |
| 629 | case 'B': /* Double/even. */ |
| 630 | case 'R': /* Quad/multiple of 4. */ |
| 631 | fregx (X_RS2 (insn)); |
| 632 | break; |
| 633 | |
| 634 | case 'g': |
| 635 | freg (X_RD (insn)); |
| 636 | break; |
| 637 | case 'H': /* Double/even. */ |
| 638 | case 'J': /* Quad/multiple of 4. */ |
| 639 | fregx (X_RD (insn)); |
| 640 | break; |
| 641 | #undef freg |
| 642 | #undef fregx |
| 643 | |
| 644 | #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) |
| 645 | case 'b': |
| 646 | creg (X_RS1 (insn)); |
| 647 | break; |
| 648 | |
| 649 | case 'c': |
| 650 | creg (X_RS2 (insn)); |
| 651 | break; |
| 652 | |
| 653 | case 'D': |
| 654 | creg (X_RD (insn)); |
| 655 | break; |
| 656 | #undef creg |
| 657 | |
| 658 | case 'h': |
| 659 | (*info->fprintf_func) (stream, "%%hi(%#x)", |
| 660 | ((unsigned) 0xFFFFFFFF |
| 661 | & ((int) X_IMM22 (insn) << 10))); |
| 662 | break; |
| 663 | |
| 664 | case 'i': /* 13 bit immediate. */ |
| 665 | case 'I': /* 11 bit immediate. */ |
| 666 | case 'j': /* 10 bit immediate. */ |
| 667 | { |
| 668 | int imm; |
| 669 | |
| 670 | if (*s == 'i') |
| 671 | imm = X_SIMM (insn, 13); |
| 672 | else if (*s == 'I') |
| 673 | imm = X_SIMM (insn, 11); |
| 674 | else |
| 675 | imm = X_SIMM (insn, 10); |
| 676 | |
| 677 | /* Check to see whether we have a 1+i, and take |
| 678 | note of that fact. |
| 679 | |
| 680 | Note: because of the way we sort the table, |
| 681 | we will be matching 1+i rather than i+1, |
| 682 | so it is OK to assume that i is after +, |
| 683 | not before it. */ |
| 684 | if (found_plus) |
| 685 | imm_added_to_rs1 = 1; |
| 686 | |
| 687 | if (imm <= 9) |
| 688 | (*info->fprintf_func) (stream, "%d", imm); |
| 689 | else |
| 690 | (*info->fprintf_func) (stream, "%#x", imm); |
| 691 | } |
| 692 | break; |
| 693 | |
| 694 | case 'X': /* 5 bit unsigned immediate. */ |
| 695 | case 'Y': /* 6 bit unsigned immediate. */ |
| 696 | { |
| 697 | int imm = X_IMM (insn, *s == 'X' ? 5 : 6); |
| 698 | |
| 699 | if (imm <= 9) |
| 700 | (info->fprintf_func) (stream, "%d", imm); |
| 701 | else |
| 702 | (info->fprintf_func) (stream, "%#x", (unsigned) imm); |
| 703 | } |
| 704 | break; |
| 705 | |
| 706 | case '3': |
| 707 | (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); |
| 708 | break; |
| 709 | |
| 710 | case 'K': |
| 711 | { |
| 712 | int mask = X_MEMBAR (insn); |
| 713 | int bit = 0x40, printed_one = 0; |
| 714 | const char *name; |
| 715 | |
| 716 | if (mask == 0) |
| 717 | (info->fprintf_func) (stream, "0"); |
| 718 | else |
| 719 | while (bit) |
| 720 | { |
| 721 | if (mask & bit) |
| 722 | { |
| 723 | if (printed_one) |
| 724 | (info->fprintf_func) (stream, "|"); |
| 725 | name = sparc_decode_membar (bit); |
| 726 | (info->fprintf_func) (stream, "%s", name); |
| 727 | printed_one = 1; |
| 728 | } |
| 729 | bit >>= 1; |
| 730 | } |
| 731 | break; |
| 732 | } |
| 733 | |
| 734 | case 'k': |
| 735 | info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; |
| 736 | (*info->print_address_func) (info->target, info); |
| 737 | break; |
| 738 | |
| 739 | case 'G': |
| 740 | info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; |
| 741 | (*info->print_address_func) (info->target, info); |
| 742 | break; |
| 743 | |
| 744 | case '6': |
| 745 | case '7': |
| 746 | case '8': |
| 747 | case '9': |
| 748 | (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); |
| 749 | break; |
| 750 | |
| 751 | case 'z': |
| 752 | (*info->fprintf_func) (stream, "%%icc"); |
| 753 | break; |
| 754 | |
| 755 | case 'Z': |
| 756 | (*info->fprintf_func) (stream, "%%xcc"); |
| 757 | break; |
| 758 | |
| 759 | case 'E': |
| 760 | (*info->fprintf_func) (stream, "%%ccr"); |
| 761 | break; |
| 762 | |
| 763 | case 's': |
| 764 | (*info->fprintf_func) (stream, "%%fprs"); |
| 765 | break; |
| 766 | |
| 767 | case 'o': |
| 768 | (*info->fprintf_func) (stream, "%%asi"); |
| 769 | break; |
| 770 | |
| 771 | case 'W': |
| 772 | (*info->fprintf_func) (stream, "%%tick"); |
| 773 | break; |
| 774 | |
| 775 | case 'P': |
| 776 | (*info->fprintf_func) (stream, "%%pc"); |
| 777 | break; |
| 778 | |
| 779 | case '?': |
| 780 | if (X_RS1 (insn) == 31) |
| 781 | (*info->fprintf_func) (stream, "%%ver"); |
| 782 | else if ((unsigned) X_RS1 (insn) < 17) |
| 783 | (*info->fprintf_func) (stream, "%%%s", |
| 784 | v9_priv_reg_names[X_RS1 (insn)]); |
| 785 | else |
| 786 | (*info->fprintf_func) (stream, "%%reserved"); |
| 787 | break; |
| 788 | |
| 789 | case '!': |
| 790 | if ((unsigned) X_RD (insn) < 17) |
| 791 | (*info->fprintf_func) (stream, "%%%s", |
| 792 | v9_priv_reg_names[X_RD (insn)]); |
| 793 | else |
| 794 | (*info->fprintf_func) (stream, "%%reserved"); |
| 795 | break; |
| 796 | |
| 797 | case '$': |
| 798 | if ((unsigned) X_RS1 (insn) < 32) |
| 799 | (*info->fprintf_func) (stream, "%%%s", |
| 800 | v9_hpriv_reg_names[X_RS1 (insn)]); |
| 801 | else |
| 802 | (*info->fprintf_func) (stream, "%%reserved"); |
| 803 | break; |
| 804 | |
| 805 | case '%': |
| 806 | if ((unsigned) X_RD (insn) < 32) |
| 807 | (*info->fprintf_func) (stream, "%%%s", |
| 808 | v9_hpriv_reg_names[X_RD (insn)]); |
| 809 | else |
| 810 | (*info->fprintf_func) (stream, "%%reserved"); |
| 811 | break; |
| 812 | |
| 813 | case '/': |
| 814 | if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) |
| 815 | (*info->fprintf_func) (stream, "%%reserved"); |
| 816 | else |
| 817 | (*info->fprintf_func) (stream, "%%%s", |
| 818 | v9a_asr_reg_names[X_RS1 (insn)-16]); |
| 819 | break; |
| 820 | |
| 821 | case '_': |
| 822 | if (X_RD (insn) < 16 || X_RD (insn) > 25) |
| 823 | (*info->fprintf_func) (stream, "%%reserved"); |
| 824 | else |
| 825 | (*info->fprintf_func) (stream, "%%%s", |
| 826 | v9a_asr_reg_names[X_RD (insn)-16]); |
| 827 | break; |
| 828 | |
| 829 | case '*': |
| 830 | { |
| 831 | const char *name = sparc_decode_prefetch (X_RD (insn)); |
| 832 | |
| 833 | if (name) |
| 834 | (*info->fprintf_func) (stream, "%s", name); |
| 835 | else |
| 836 | (*info->fprintf_func) (stream, "%ld", X_RD (insn)); |
| 837 | break; |
| 838 | } |
| 839 | |
| 840 | case 'M': |
| 841 | (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); |
| 842 | break; |
| 843 | |
| 844 | case 'm': |
| 845 | (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); |
| 846 | break; |
| 847 | |
| 848 | case 'L': |
| 849 | info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; |
| 850 | (*info->print_address_func) (info->target, info); |
| 851 | break; |
| 852 | |
| 853 | case 'n': |
| 854 | (*info->fprintf_func) |
| 855 | (stream, "%#x", SEX (X_DISP22 (insn), 22)); |
| 856 | break; |
| 857 | |
| 858 | case 'l': |
| 859 | info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; |
| 860 | (*info->print_address_func) (info->target, info); |
| 861 | break; |
| 862 | |
| 863 | case 'A': |
| 864 | { |
| 865 | const char *name = sparc_decode_asi (X_ASI (insn)); |
| 866 | |
| 867 | if (name) |
| 868 | (*info->fprintf_func) (stream, "%s", name); |
| 869 | else |
| 870 | (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); |
| 871 | break; |
| 872 | } |
| 873 | |
| 874 | case 'C': |
| 875 | (*info->fprintf_func) (stream, "%%csr"); |
| 876 | break; |
| 877 | |
| 878 | case 'F': |
| 879 | (*info->fprintf_func) (stream, "%%fsr"); |
| 880 | break; |
| 881 | |
| 882 | case 'p': |
| 883 | (*info->fprintf_func) (stream, "%%psr"); |
| 884 | break; |
| 885 | |
| 886 | case 'q': |
| 887 | (*info->fprintf_func) (stream, "%%fq"); |
| 888 | break; |
| 889 | |
| 890 | case 'Q': |
| 891 | (*info->fprintf_func) (stream, "%%cq"); |
| 892 | break; |
| 893 | |
| 894 | case 't': |
| 895 | (*info->fprintf_func) (stream, "%%tbr"); |
| 896 | break; |
| 897 | |
| 898 | case 'w': |
| 899 | (*info->fprintf_func) (stream, "%%wim"); |
| 900 | break; |
| 901 | |
| 902 | case 'x': |
| 903 | (*info->fprintf_func) (stream, "%ld", |
| 904 | ((X_LDST_I (insn) << 8) |
| 905 | + X_ASI (insn))); |
| 906 | break; |
| 907 | |
| 908 | case 'y': |
| 909 | (*info->fprintf_func) (stream, "%%y"); |
| 910 | break; |
| 911 | |
| 912 | case 'u': |
| 913 | case 'U': |
| 914 | { |
| 915 | int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); |
| 916 | const char *name = sparc_decode_sparclet_cpreg (val); |
| 917 | |
| 918 | if (name) |
| 919 | (*info->fprintf_func) (stream, "%s", name); |
| 920 | else |
| 921 | (*info->fprintf_func) (stream, "%%cpreg(%d)", val); |
| 922 | break; |
| 923 | } |
| 924 | } |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | /* If we are adding or or'ing something to rs1, then |
| 929 | check to see whether the previous instruction was |
| 930 | a sethi to the same register as in the sethi. |
| 931 | If so, attempt to print the result of the add or |
| 932 | or (in this context add and or do the same thing) |
| 933 | and its symbolic value. */ |
| 934 | if (imm_ored_to_rs1 || imm_added_to_rs1) |
| 935 | { |
| 936 | unsigned long prev_insn; |
| 937 | int errcode; |
| 938 | |
| 939 | if (memaddr >= 4) |
| 940 | errcode = |
| 941 | (*info->read_memory_func) |
| 942 | (memaddr - 4, buffer, sizeof (buffer), info); |
| 943 | else |
| 944 | errcode = 1; |
| 945 | |
| 946 | prev_insn = getword (buffer); |
| 947 | |
| 948 | if (errcode == 0) |
| 949 | { |
| 950 | /* If it is a delayed branch, we need to look at the |
| 951 | instruction before the delayed branch. This handles |
| 952 | sequences such as: |
| 953 | |
| 954 | sethi %o1, %hi(_foo), %o1 |
| 955 | call _printf |
| 956 | or %o1, %lo(_foo), %o1 */ |
| 957 | |
| 958 | if (is_delayed_branch (prev_insn)) |
| 959 | { |
| 960 | if (memaddr >= 8) |
| 961 | errcode = (*info->read_memory_func) |
| 962 | (memaddr - 8, buffer, sizeof (buffer), info); |
| 963 | else |
| 964 | errcode = 1; |
| 965 | |
| 966 | prev_insn = getword (buffer); |
| 967 | } |
| 968 | } |
| 969 | |
| 970 | /* If there was a problem reading memory, then assume |
| 971 | the previous instruction was not sethi. */ |
| 972 | if (errcode == 0) |
| 973 | { |
| 974 | /* Is it sethi to the same register? */ |
| 975 | if ((prev_insn & 0xc1c00000) == 0x01000000 |
| 976 | && X_RD (prev_insn) == X_RS1 (insn)) |
| 977 | { |
| 978 | (*info->fprintf_func) (stream, "\t! "); |
| 979 | info->target = |
| 980 | ((unsigned) 0xFFFFFFFF |
| 981 | & ((int) X_IMM22 (prev_insn) << 10)); |
| 982 | if (imm_added_to_rs1) |
| 983 | info->target += X_SIMM (insn, 13); |
| 984 | else |
| 985 | info->target |= X_SIMM (insn, 13); |
| 986 | (*info->print_address_func) (info->target, info); |
| 987 | info->insn_type = dis_dref; |
| 988 | info->data_size = 4; /* FIXME!!! */ |
| 989 | } |
| 990 | } |
| 991 | } |
| 992 | |
| 993 | if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) |
| 994 | { |
| 995 | /* FIXME -- check is_annulled flag. */ |
| 996 | if (opcode->flags & F_UNBR) |
| 997 | info->insn_type = dis_branch; |
| 998 | if (opcode->flags & F_CONDBR) |
| 999 | info->insn_type = dis_condbranch; |
| 1000 | if (opcode->flags & F_JSR) |
| 1001 | info->insn_type = dis_jsr; |
| 1002 | if (opcode->flags & F_DELAYED) |
| 1003 | info->branch_delay_insns = 1; |
| 1004 | } |
| 1005 | |
| 1006 | return sizeof (buffer); |
| 1007 | } |
| 1008 | } |
| 1009 | |
| 1010 | info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ |
| 1011 | (*info->fprintf_func) (stream, _("unknown")); |
| 1012 | return sizeof (buffer); |
| 1013 | } |