| 1 | /* TILE-Gx opcode information. |
| 2 | |
| 3 | Copyright 2011 Free Software Foundation, Inc. |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 3 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the Free Software |
| 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 18 | MA 02110-1301, USA. */ |
| 19 | |
| 20 | #include "sysdep.h" |
| 21 | |
| 22 | /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ |
| 23 | #define BFD_RELOC(x) BFD_RELOC_##x |
| 24 | #include "bfd.h" |
| 25 | |
| 26 | /* Special registers. */ |
| 27 | #define TREG_LR 55 |
| 28 | #define TREG_SN 56 |
| 29 | #define TREG_ZERO 63 |
| 30 | |
| 31 | #if defined(__KERNEL__) || defined(_LIBC) |
| 32 | /* FIXME: Rename this. */ |
| 33 | #include <asm/opcode-tile_64.h> |
| 34 | #define DISASM_ONLY |
| 35 | #else |
| 36 | #include "opcode/tilegx.h" |
| 37 | #endif |
| 38 | |
| 39 | #ifdef __KERNEL__ |
| 40 | #include <linux/stddef.h> |
| 41 | #else |
| 42 | #include <stddef.h> |
| 43 | #endif |
| 44 | |
| 45 | const struct tilegx_opcode tilegx_opcodes[336] = |
| 46 | { |
| 47 | { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0, |
| 48 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 49 | #ifndef DISASM_ONLY |
| 50 | { |
| 51 | 0ULL, |
| 52 | 0xffffffff80000000ULL, |
| 53 | 0ULL, |
| 54 | 0ULL, |
| 55 | 0ULL |
| 56 | }, |
| 57 | { |
| 58 | -1ULL, |
| 59 | 0x286a44ae00000000ULL, |
| 60 | -1ULL, |
| 61 | -1ULL, |
| 62 | -1ULL |
| 63 | } |
| 64 | #endif |
| 65 | }, |
| 66 | { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1, |
| 67 | { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } }, |
| 68 | #ifndef DISASM_ONLY |
| 69 | { |
| 70 | 0xc00000007ff00fffULL, |
| 71 | 0xfff807ff80000000ULL, |
| 72 | 0x0000000078000fffULL, |
| 73 | 0x3c0007ff80000000ULL, |
| 74 | 0ULL |
| 75 | }, |
| 76 | { |
| 77 | 0x0000000040300fffULL, |
| 78 | 0x181807ff80000000ULL, |
| 79 | 0x0000000010000fffULL, |
| 80 | 0x0c0007ff80000000ULL, |
| 81 | -1ULL |
| 82 | } |
| 83 | #endif |
| 84 | }, |
| 85 | { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, |
| 86 | { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } }, |
| 87 | #ifndef DISASM_ONLY |
| 88 | { |
| 89 | 0xc000000070000fffULL, |
| 90 | 0xf80007ff80000000ULL, |
| 91 | 0ULL, |
| 92 | 0ULL, |
| 93 | 0ULL |
| 94 | }, |
| 95 | { |
| 96 | 0x0000000070000fffULL, |
| 97 | 0x380007ff80000000ULL, |
| 98 | -1ULL, |
| 99 | -1ULL, |
| 100 | -1ULL |
| 101 | } |
| 102 | #endif |
| 103 | }, |
| 104 | { "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1, |
| 105 | { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 106 | #ifndef DISASM_ONLY |
| 107 | { |
| 108 | 0ULL, |
| 109 | 0xfffff80000000000ULL, |
| 110 | 0ULL, |
| 111 | 0ULL, |
| 112 | 0ULL |
| 113 | }, |
| 114 | { |
| 115 | -1ULL, |
| 116 | 0x1858000000000000ULL, |
| 117 | -1ULL, |
| 118 | -1ULL, |
| 119 | -1ULL |
| 120 | } |
| 121 | #endif |
| 122 | }, |
| 123 | { "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1, |
| 124 | { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 125 | #ifndef DISASM_ONLY |
| 126 | { |
| 127 | 0ULL, |
| 128 | 0xfffff80000000000ULL, |
| 129 | 0ULL, |
| 130 | 0ULL, |
| 131 | 0ULL |
| 132 | }, |
| 133 | { |
| 134 | -1ULL, |
| 135 | 0x18a0000000000000ULL, |
| 136 | -1ULL, |
| 137 | -1ULL, |
| 138 | -1ULL |
| 139 | } |
| 140 | #endif |
| 141 | }, |
| 142 | { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, |
| 143 | { { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } }, |
| 144 | #ifndef DISASM_ONLY |
| 145 | { |
| 146 | 0xc00000007ffff000ULL, |
| 147 | 0xfffff80000000000ULL, |
| 148 | 0x00000000780ff000ULL, |
| 149 | 0x3c07f80000000000ULL, |
| 150 | 0ULL |
| 151 | }, |
| 152 | { |
| 153 | 0x000000005107f000ULL, |
| 154 | 0x283bf80000000000ULL, |
| 155 | 0x00000000500bf000ULL, |
| 156 | 0x2c05f80000000000ULL, |
| 157 | -1ULL |
| 158 | } |
| 159 | #endif |
| 160 | }, |
| 161 | { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, |
| 162 | { { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } }, |
| 163 | #ifndef DISASM_ONLY |
| 164 | { |
| 165 | 0xc00000007ff00fc0ULL, |
| 166 | 0xfff807e000000000ULL, |
| 167 | 0x0000000078000fc0ULL, |
| 168 | 0x3c0007e000000000ULL, |
| 169 | 0ULL |
| 170 | }, |
| 171 | { |
| 172 | 0x0000000040100fc0ULL, |
| 173 | 0x180807e000000000ULL, |
| 174 | 0x0000000000000fc0ULL, |
| 175 | 0x040007e000000000ULL, |
| 176 | -1ULL |
| 177 | } |
| 178 | #endif |
| 179 | }, |
| 180 | { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, |
| 181 | { { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } }, |
| 182 | #ifndef DISASM_ONLY |
| 183 | { |
| 184 | 0xc000000070000fc0ULL, |
| 185 | 0xf80007e000000000ULL, |
| 186 | 0ULL, |
| 187 | 0ULL, |
| 188 | 0ULL |
| 189 | }, |
| 190 | { |
| 191 | 0x0000000010000fc0ULL, |
| 192 | 0x000007e000000000ULL, |
| 193 | -1ULL, |
| 194 | -1ULL, |
| 195 | -1ULL |
| 196 | } |
| 197 | #endif |
| 198 | }, |
| 199 | { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, |
| 200 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 201 | #ifndef DISASM_ONLY |
| 202 | { |
| 203 | 0ULL, |
| 204 | 0xfffff81f80000000ULL, |
| 205 | 0ULL, |
| 206 | 0ULL, |
| 207 | 0xc3f8000004000000ULL |
| 208 | }, |
| 209 | { |
| 210 | -1ULL, |
| 211 | 0x286a801f80000000ULL, |
| 212 | -1ULL, |
| 213 | -1ULL, |
| 214 | 0x41f8000004000000ULL |
| 215 | } |
| 216 | #endif |
| 217 | }, |
| 218 | { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1, |
| 219 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 220 | #ifndef DISASM_ONLY |
| 221 | { |
| 222 | 0ULL, |
| 223 | 0xfff8001f80000000ULL, |
| 224 | 0ULL, |
| 225 | 0ULL, |
| 226 | 0ULL |
| 227 | }, |
| 228 | { |
| 229 | -1ULL, |
| 230 | 0x1840001f80000000ULL, |
| 231 | -1ULL, |
| 232 | -1ULL, |
| 233 | -1ULL |
| 234 | } |
| 235 | #endif |
| 236 | }, |
| 237 | { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1, |
| 238 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 239 | #ifndef DISASM_ONLY |
| 240 | { |
| 241 | 0ULL, |
| 242 | 0xfff8001f80000000ULL, |
| 243 | 0ULL, |
| 244 | 0ULL, |
| 245 | 0ULL |
| 246 | }, |
| 247 | { |
| 248 | -1ULL, |
| 249 | 0x1838001f80000000ULL, |
| 250 | -1ULL, |
| 251 | -1ULL, |
| 252 | -1ULL |
| 253 | } |
| 254 | #endif |
| 255 | }, |
| 256 | { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1, |
| 257 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 258 | #ifndef DISASM_ONLY |
| 259 | { |
| 260 | 0ULL, |
| 261 | 0xfff8001f80000000ULL, |
| 262 | 0ULL, |
| 263 | 0ULL, |
| 264 | 0ULL |
| 265 | }, |
| 266 | { |
| 267 | -1ULL, |
| 268 | 0x1850001f80000000ULL, |
| 269 | -1ULL, |
| 270 | -1ULL, |
| 271 | -1ULL |
| 272 | } |
| 273 | #endif |
| 274 | }, |
| 275 | { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1, |
| 276 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 277 | #ifndef DISASM_ONLY |
| 278 | { |
| 279 | 0ULL, |
| 280 | 0xfff8001f80000000ULL, |
| 281 | 0ULL, |
| 282 | 0ULL, |
| 283 | 0ULL |
| 284 | }, |
| 285 | { |
| 286 | -1ULL, |
| 287 | 0x1848001f80000000ULL, |
| 288 | -1ULL, |
| 289 | -1ULL, |
| 290 | -1ULL |
| 291 | } |
| 292 | #endif |
| 293 | }, |
| 294 | { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1, |
| 295 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 296 | #ifndef DISASM_ONLY |
| 297 | { |
| 298 | 0ULL, |
| 299 | 0xfff8001f80000000ULL, |
| 300 | 0ULL, |
| 301 | 0ULL, |
| 302 | 0ULL |
| 303 | }, |
| 304 | { |
| 305 | -1ULL, |
| 306 | 0x1860001f80000000ULL, |
| 307 | -1ULL, |
| 308 | -1ULL, |
| 309 | -1ULL |
| 310 | } |
| 311 | #endif |
| 312 | }, |
| 313 | { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1, |
| 314 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 315 | #ifndef DISASM_ONLY |
| 316 | { |
| 317 | 0ULL, |
| 318 | 0xfff8001f80000000ULL, |
| 319 | 0ULL, |
| 320 | 0ULL, |
| 321 | 0ULL |
| 322 | }, |
| 323 | { |
| 324 | -1ULL, |
| 325 | 0x1858001f80000000ULL, |
| 326 | -1ULL, |
| 327 | -1ULL, |
| 328 | -1ULL |
| 329 | } |
| 330 | #endif |
| 331 | }, |
| 332 | { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1, |
| 333 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 334 | #ifndef DISASM_ONLY |
| 335 | { |
| 336 | 0ULL, |
| 337 | 0xfffff81f80000000ULL, |
| 338 | 0ULL, |
| 339 | 0ULL, |
| 340 | 0xc3f8000004000000ULL |
| 341 | }, |
| 342 | { |
| 343 | -1ULL, |
| 344 | 0x286a801f80000000ULL, |
| 345 | -1ULL, |
| 346 | -1ULL, |
| 347 | 0x41f8000004000000ULL |
| 348 | } |
| 349 | #endif |
| 350 | }, |
| 351 | { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1, |
| 352 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 353 | #ifndef DISASM_ONLY |
| 354 | { |
| 355 | 0ULL, |
| 356 | 0xfffff81f80000000ULL, |
| 357 | 0ULL, |
| 358 | 0ULL, |
| 359 | 0xc3f8000004000000ULL |
| 360 | }, |
| 361 | { |
| 362 | -1ULL, |
| 363 | 0x286a781f80000000ULL, |
| 364 | -1ULL, |
| 365 | -1ULL, |
| 366 | 0x41f8000000000000ULL |
| 367 | } |
| 368 | #endif |
| 369 | }, |
| 370 | { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1, |
| 371 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 372 | #ifndef DISASM_ONLY |
| 373 | { |
| 374 | 0ULL, |
| 375 | 0xfffff81f80000000ULL, |
| 376 | 0ULL, |
| 377 | 0ULL, |
| 378 | 0xc3f8000004000000ULL |
| 379 | }, |
| 380 | { |
| 381 | -1ULL, |
| 382 | 0x286a901f80000000ULL, |
| 383 | -1ULL, |
| 384 | -1ULL, |
| 385 | 0x43f8000004000000ULL |
| 386 | } |
| 387 | #endif |
| 388 | }, |
| 389 | { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1, |
| 390 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 391 | #ifndef DISASM_ONLY |
| 392 | { |
| 393 | 0ULL, |
| 394 | 0xfffff81f80000000ULL, |
| 395 | 0ULL, |
| 396 | 0ULL, |
| 397 | 0xc3f8000004000000ULL |
| 398 | }, |
| 399 | { |
| 400 | -1ULL, |
| 401 | 0x286a881f80000000ULL, |
| 402 | -1ULL, |
| 403 | -1ULL, |
| 404 | 0x43f8000000000000ULL |
| 405 | } |
| 406 | #endif |
| 407 | }, |
| 408 | { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1, |
| 409 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 410 | #ifndef DISASM_ONLY |
| 411 | { |
| 412 | 0ULL, |
| 413 | 0xfffff81f80000000ULL, |
| 414 | 0ULL, |
| 415 | 0ULL, |
| 416 | 0xc3f8000004000000ULL |
| 417 | }, |
| 418 | { |
| 419 | -1ULL, |
| 420 | 0x286aa01f80000000ULL, |
| 421 | -1ULL, |
| 422 | -1ULL, |
| 423 | 0x83f8000000000000ULL |
| 424 | } |
| 425 | #endif |
| 426 | }, |
| 427 | { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1, |
| 428 | { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, |
| 429 | #ifndef DISASM_ONLY |
| 430 | { |
| 431 | 0ULL, |
| 432 | 0xfffff81f80000000ULL, |
| 433 | 0ULL, |
| 434 | 0ULL, |
| 435 | 0xc3f8000004000000ULL |
| 436 | }, |
| 437 | { |
| 438 | -1ULL, |
| 439 | 0x286a981f80000000ULL, |
| 440 | -1ULL, |
| 441 | -1ULL, |
| 442 | 0x81f8000004000000ULL |
| 443 | } |
| 444 | #endif |
| 445 | }, |
| 446 | { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, |
| 447 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 448 | #ifndef DISASM_ONLY |
| 449 | { |
| 450 | 0ULL, |
| 451 | 0xffffffff80000000ULL, |
| 452 | 0ULL, |
| 453 | 0ULL, |
| 454 | 0ULL |
| 455 | }, |
| 456 | { |
| 457 | -1ULL, |
| 458 | 0x286a44ae80000000ULL, |
| 459 | -1ULL, |
| 460 | -1ULL, |
| 461 | -1ULL |
| 462 | } |
| 463 | #endif |
| 464 | }, |
| 465 | { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1, |
| 466 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 467 | #ifndef DISASM_ONLY |
| 468 | { |
| 469 | 0xc00000007ffc0000ULL, |
| 470 | 0xfffe000000000000ULL, |
| 471 | 0x00000000780c0000ULL, |
| 472 | 0x3c06000000000000ULL, |
| 473 | 0ULL |
| 474 | }, |
| 475 | { |
| 476 | 0x00000000500c0000ULL, |
| 477 | 0x2806000000000000ULL, |
| 478 | 0x0000000028040000ULL, |
| 479 | 0x1802000000000000ULL, |
| 480 | -1ULL |
| 481 | } |
| 482 | #endif |
| 483 | }, |
| 484 | { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, |
| 485 | { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, |
| 486 | #ifndef DISASM_ONLY |
| 487 | { |
| 488 | 0xc00000007ff00000ULL, |
| 489 | 0xfff8000000000000ULL, |
| 490 | 0x0000000078000000ULL, |
| 491 | 0x3c00000000000000ULL, |
| 492 | 0ULL |
| 493 | }, |
| 494 | { |
| 495 | 0x0000000040100000ULL, |
| 496 | 0x1808000000000000ULL, |
| 497 | 0ULL, |
| 498 | 0x0400000000000000ULL, |
| 499 | -1ULL |
| 500 | } |
| 501 | #endif |
| 502 | }, |
| 503 | { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, |
| 504 | { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } }, |
| 505 | #ifndef DISASM_ONLY |
| 506 | { |
| 507 | 0xc000000070000000ULL, |
| 508 | 0xf800000000000000ULL, |
| 509 | 0ULL, |
| 510 | 0ULL, |
| 511 | 0ULL |
| 512 | }, |
| 513 | { |
| 514 | 0x0000000010000000ULL, |
| 515 | 0ULL, |
| 516 | -1ULL, |
| 517 | -1ULL, |
| 518 | -1ULL |
| 519 | } |
| 520 | #endif |
| 521 | }, |
| 522 | { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1, |
| 523 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 524 | #ifndef DISASM_ONLY |
| 525 | { |
| 526 | 0xc00000007ffc0000ULL, |
| 527 | 0xfffe000000000000ULL, |
| 528 | 0x00000000780c0000ULL, |
| 529 | 0x3c06000000000000ULL, |
| 530 | 0ULL |
| 531 | }, |
| 532 | { |
| 533 | 0x0000000050080000ULL, |
| 534 | 0x2804000000000000ULL, |
| 535 | 0x0000000028000000ULL, |
| 536 | 0x1800000000000000ULL, |
| 537 | -1ULL |
| 538 | } |
| 539 | #endif |
| 540 | }, |
| 541 | { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1, |
| 542 | { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, |
| 543 | #ifndef DISASM_ONLY |
| 544 | { |
| 545 | 0xc00000007ff00000ULL, |
| 546 | 0xfff8000000000000ULL, |
| 547 | 0x0000000078000000ULL, |
| 548 | 0x3c00000000000000ULL, |
| 549 | 0ULL |
| 550 | }, |
| 551 | { |
| 552 | 0x0000000040200000ULL, |
| 553 | 0x1810000000000000ULL, |
| 554 | 0x0000000008000000ULL, |
| 555 | 0x0800000000000000ULL, |
| 556 | -1ULL |
| 557 | } |
| 558 | #endif |
| 559 | }, |
| 560 | { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1, |
| 561 | { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } }, |
| 562 | #ifndef DISASM_ONLY |
| 563 | { |
| 564 | 0xc000000070000000ULL, |
| 565 | 0xf800000000000000ULL, |
| 566 | 0ULL, |
| 567 | 0ULL, |
| 568 | 0ULL |
| 569 | }, |
| 570 | { |
| 571 | 0x0000000020000000ULL, |
| 572 | 0x0800000000000000ULL, |
| 573 | -1ULL, |
| 574 | -1ULL, |
| 575 | -1ULL |
| 576 | } |
| 577 | #endif |
| 578 | }, |
| 579 | { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1, |
| 580 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 581 | #ifndef DISASM_ONLY |
| 582 | { |
| 583 | 0xc00000007ffc0000ULL, |
| 584 | 0xfffe000000000000ULL, |
| 585 | 0ULL, |
| 586 | 0ULL, |
| 587 | 0ULL |
| 588 | }, |
| 589 | { |
| 590 | 0x0000000050040000ULL, |
| 591 | 0x2802000000000000ULL, |
| 592 | -1ULL, |
| 593 | -1ULL, |
| 594 | -1ULL |
| 595 | } |
| 596 | #endif |
| 597 | }, |
| 598 | { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1, |
| 599 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 600 | #ifndef DISASM_ONLY |
| 601 | { |
| 602 | 0xc00000007ffc0000ULL, |
| 603 | 0xfffe000000000000ULL, |
| 604 | 0x00000000780c0000ULL, |
| 605 | 0x3c06000000000000ULL, |
| 606 | 0ULL |
| 607 | }, |
| 608 | { |
| 609 | 0x0000000050100000ULL, |
| 610 | 0x2808000000000000ULL, |
| 611 | 0x0000000050000000ULL, |
| 612 | 0x2c00000000000000ULL, |
| 613 | -1ULL |
| 614 | } |
| 615 | #endif |
| 616 | }, |
| 617 | { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, |
| 618 | { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, |
| 619 | #ifndef DISASM_ONLY |
| 620 | { |
| 621 | 0xc00000007ff00000ULL, |
| 622 | 0xfff8000000000000ULL, |
| 623 | 0x0000000078000000ULL, |
| 624 | 0x3c00000000000000ULL, |
| 625 | 0ULL |
| 626 | }, |
| 627 | { |
| 628 | 0x0000000040300000ULL, |
| 629 | 0x1818000000000000ULL, |
| 630 | 0x0000000010000000ULL, |
| 631 | 0x0c00000000000000ULL, |
| 632 | -1ULL |
| 633 | } |
| 634 | #endif |
| 635 | }, |
| 636 | { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1, |
| 637 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 638 | #ifndef DISASM_ONLY |
| 639 | { |
| 640 | 0ULL, |
| 641 | 0xffc0000000000000ULL, |
| 642 | 0ULL, |
| 643 | 0ULL, |
| 644 | 0ULL |
| 645 | }, |
| 646 | { |
| 647 | -1ULL, |
| 648 | 0x1440000000000000ULL, |
| 649 | -1ULL, |
| 650 | -1ULL, |
| 651 | -1ULL |
| 652 | } |
| 653 | #endif |
| 654 | }, |
| 655 | { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1, |
| 656 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 657 | #ifndef DISASM_ONLY |
| 658 | { |
| 659 | 0ULL, |
| 660 | 0xffc0000000000000ULL, |
| 661 | 0ULL, |
| 662 | 0ULL, |
| 663 | 0ULL |
| 664 | }, |
| 665 | { |
| 666 | -1ULL, |
| 667 | 0x1400000000000000ULL, |
| 668 | -1ULL, |
| 669 | -1ULL, |
| 670 | -1ULL |
| 671 | } |
| 672 | #endif |
| 673 | }, |
| 674 | { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1, |
| 675 | { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 676 | #ifndef DISASM_ONLY |
| 677 | { |
| 678 | 0xc00000007f000000ULL, |
| 679 | 0ULL, |
| 680 | 0ULL, |
| 681 | 0ULL, |
| 682 | 0ULL |
| 683 | }, |
| 684 | { |
| 685 | 0x0000000034000000ULL, |
| 686 | -1ULL, |
| 687 | -1ULL, |
| 688 | -1ULL, |
| 689 | -1ULL |
| 690 | } |
| 691 | #endif |
| 692 | }, |
| 693 | { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1, |
| 694 | { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 695 | #ifndef DISASM_ONLY |
| 696 | { |
| 697 | 0xc00000007f000000ULL, |
| 698 | 0ULL, |
| 699 | 0ULL, |
| 700 | 0ULL, |
| 701 | 0ULL |
| 702 | }, |
| 703 | { |
| 704 | 0x0000000035000000ULL, |
| 705 | -1ULL, |
| 706 | -1ULL, |
| 707 | -1ULL, |
| 708 | -1ULL |
| 709 | } |
| 710 | #endif |
| 711 | }, |
| 712 | { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1, |
| 713 | { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 714 | #ifndef DISASM_ONLY |
| 715 | { |
| 716 | 0xc00000007f000000ULL, |
| 717 | 0ULL, |
| 718 | 0ULL, |
| 719 | 0ULL, |
| 720 | 0ULL |
| 721 | }, |
| 722 | { |
| 723 | 0x0000000036000000ULL, |
| 724 | -1ULL, |
| 725 | -1ULL, |
| 726 | -1ULL, |
| 727 | -1ULL |
| 728 | } |
| 729 | #endif |
| 730 | }, |
| 731 | { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, |
| 732 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 733 | #ifndef DISASM_ONLY |
| 734 | { |
| 735 | 0ULL, |
| 736 | 0xffc0000000000000ULL, |
| 737 | 0ULL, |
| 738 | 0ULL, |
| 739 | 0ULL |
| 740 | }, |
| 741 | { |
| 742 | -1ULL, |
| 743 | 0x14c0000000000000ULL, |
| 744 | -1ULL, |
| 745 | -1ULL, |
| 746 | -1ULL |
| 747 | } |
| 748 | #endif |
| 749 | }, |
| 750 | { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, |
| 751 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 752 | #ifndef DISASM_ONLY |
| 753 | { |
| 754 | 0ULL, |
| 755 | 0xffc0000000000000ULL, |
| 756 | 0ULL, |
| 757 | 0ULL, |
| 758 | 0ULL |
| 759 | }, |
| 760 | { |
| 761 | -1ULL, |
| 762 | 0x1480000000000000ULL, |
| 763 | -1ULL, |
| 764 | -1ULL, |
| 765 | -1ULL |
| 766 | } |
| 767 | #endif |
| 768 | }, |
| 769 | { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1, |
| 770 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 771 | #ifndef DISASM_ONLY |
| 772 | { |
| 773 | 0ULL, |
| 774 | 0xffc0000000000000ULL, |
| 775 | 0ULL, |
| 776 | 0ULL, |
| 777 | 0ULL |
| 778 | }, |
| 779 | { |
| 780 | -1ULL, |
| 781 | 0x1540000000000000ULL, |
| 782 | -1ULL, |
| 783 | -1ULL, |
| 784 | -1ULL |
| 785 | } |
| 786 | #endif |
| 787 | }, |
| 788 | { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1, |
| 789 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 790 | #ifndef DISASM_ONLY |
| 791 | { |
| 792 | 0ULL, |
| 793 | 0xffc0000000000000ULL, |
| 794 | 0ULL, |
| 795 | 0ULL, |
| 796 | 0ULL |
| 797 | }, |
| 798 | { |
| 799 | -1ULL, |
| 800 | 0x1500000000000000ULL, |
| 801 | -1ULL, |
| 802 | -1ULL, |
| 803 | -1ULL |
| 804 | } |
| 805 | #endif |
| 806 | }, |
| 807 | { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1, |
| 808 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 809 | #ifndef DISASM_ONLY |
| 810 | { |
| 811 | 0ULL, |
| 812 | 0xffc0000000000000ULL, |
| 813 | 0ULL, |
| 814 | 0ULL, |
| 815 | 0ULL |
| 816 | }, |
| 817 | { |
| 818 | -1ULL, |
| 819 | 0x15c0000000000000ULL, |
| 820 | -1ULL, |
| 821 | -1ULL, |
| 822 | -1ULL |
| 823 | } |
| 824 | #endif |
| 825 | }, |
| 826 | { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1, |
| 827 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 828 | #ifndef DISASM_ONLY |
| 829 | { |
| 830 | 0ULL, |
| 831 | 0xffc0000000000000ULL, |
| 832 | 0ULL, |
| 833 | 0ULL, |
| 834 | 0ULL |
| 835 | }, |
| 836 | { |
| 837 | -1ULL, |
| 838 | 0x1580000000000000ULL, |
| 839 | -1ULL, |
| 840 | -1ULL, |
| 841 | -1ULL |
| 842 | } |
| 843 | #endif |
| 844 | }, |
| 845 | { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1, |
| 846 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 847 | #ifndef DISASM_ONLY |
| 848 | { |
| 849 | 0ULL, |
| 850 | 0xffc0000000000000ULL, |
| 851 | 0ULL, |
| 852 | 0ULL, |
| 853 | 0ULL |
| 854 | }, |
| 855 | { |
| 856 | -1ULL, |
| 857 | 0x1640000000000000ULL, |
| 858 | -1ULL, |
| 859 | -1ULL, |
| 860 | -1ULL |
| 861 | } |
| 862 | #endif |
| 863 | }, |
| 864 | { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1, |
| 865 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 866 | #ifndef DISASM_ONLY |
| 867 | { |
| 868 | 0ULL, |
| 869 | 0xffc0000000000000ULL, |
| 870 | 0ULL, |
| 871 | 0ULL, |
| 872 | 0ULL |
| 873 | }, |
| 874 | { |
| 875 | -1ULL, |
| 876 | 0x1600000000000000ULL, |
| 877 | -1ULL, |
| 878 | -1ULL, |
| 879 | -1ULL |
| 880 | } |
| 881 | #endif |
| 882 | }, |
| 883 | { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, |
| 884 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 885 | #ifndef DISASM_ONLY |
| 886 | { |
| 887 | 0ULL, |
| 888 | 0xffc0000000000000ULL, |
| 889 | 0ULL, |
| 890 | 0ULL, |
| 891 | 0ULL |
| 892 | }, |
| 893 | { |
| 894 | -1ULL, |
| 895 | 0x16c0000000000000ULL, |
| 896 | -1ULL, |
| 897 | -1ULL, |
| 898 | -1ULL |
| 899 | } |
| 900 | #endif |
| 901 | }, |
| 902 | { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, |
| 903 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 904 | #ifndef DISASM_ONLY |
| 905 | { |
| 906 | 0ULL, |
| 907 | 0xffc0000000000000ULL, |
| 908 | 0ULL, |
| 909 | 0ULL, |
| 910 | 0ULL |
| 911 | }, |
| 912 | { |
| 913 | -1ULL, |
| 914 | 0x1680000000000000ULL, |
| 915 | -1ULL, |
| 916 | -1ULL, |
| 917 | -1ULL |
| 918 | } |
| 919 | #endif |
| 920 | }, |
| 921 | { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1, |
| 922 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 923 | #ifndef DISASM_ONLY |
| 924 | { |
| 925 | 0ULL, |
| 926 | 0xffc0000000000000ULL, |
| 927 | 0ULL, |
| 928 | 0ULL, |
| 929 | 0ULL |
| 930 | }, |
| 931 | { |
| 932 | -1ULL, |
| 933 | 0x1740000000000000ULL, |
| 934 | -1ULL, |
| 935 | -1ULL, |
| 936 | -1ULL |
| 937 | } |
| 938 | #endif |
| 939 | }, |
| 940 | { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1, |
| 941 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 942 | #ifndef DISASM_ONLY |
| 943 | { |
| 944 | 0ULL, |
| 945 | 0xffc0000000000000ULL, |
| 946 | 0ULL, |
| 947 | 0ULL, |
| 948 | 0ULL |
| 949 | }, |
| 950 | { |
| 951 | -1ULL, |
| 952 | 0x1700000000000000ULL, |
| 953 | -1ULL, |
| 954 | -1ULL, |
| 955 | -1ULL |
| 956 | } |
| 957 | #endif |
| 958 | }, |
| 959 | { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1, |
| 960 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 961 | #ifndef DISASM_ONLY |
| 962 | { |
| 963 | 0ULL, |
| 964 | 0xffc0000000000000ULL, |
| 965 | 0ULL, |
| 966 | 0ULL, |
| 967 | 0ULL |
| 968 | }, |
| 969 | { |
| 970 | -1ULL, |
| 971 | 0x17c0000000000000ULL, |
| 972 | -1ULL, |
| 973 | -1ULL, |
| 974 | -1ULL |
| 975 | } |
| 976 | #endif |
| 977 | }, |
| 978 | { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1, |
| 979 | { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, |
| 980 | #ifndef DISASM_ONLY |
| 981 | { |
| 982 | 0ULL, |
| 983 | 0xffc0000000000000ULL, |
| 984 | 0ULL, |
| 985 | 0ULL, |
| 986 | 0ULL |
| 987 | }, |
| 988 | { |
| 989 | -1ULL, |
| 990 | 0x1780000000000000ULL, |
| 991 | -1ULL, |
| 992 | -1ULL, |
| 993 | -1ULL |
| 994 | } |
| 995 | #endif |
| 996 | }, |
| 997 | { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, |
| 998 | { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, |
| 999 | #ifndef DISASM_ONLY |
| 1000 | { |
| 1001 | 0xc00000007ffff000ULL, |
| 1002 | 0ULL, |
| 1003 | 0x00000000780ff000ULL, |
| 1004 | 0ULL, |
| 1005 | 0ULL |
| 1006 | }, |
| 1007 | { |
| 1008 | 0x0000000051481000ULL, |
| 1009 | -1ULL, |
| 1010 | 0x00000000300c1000ULL, |
| 1011 | -1ULL, |
| 1012 | -1ULL |
| 1013 | } |
| 1014 | #endif |
| 1015 | }, |
| 1016 | { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1, |
| 1017 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 1018 | #ifndef DISASM_ONLY |
| 1019 | { |
| 1020 | 0xc00000007ffc0000ULL, |
| 1021 | 0ULL, |
| 1022 | 0x00000000780c0000ULL, |
| 1023 | 0ULL, |
| 1024 | 0ULL |
| 1025 | }, |
| 1026 | { |
| 1027 | 0x0000000050140000ULL, |
| 1028 | -1ULL, |
| 1029 | 0x0000000048000000ULL, |
| 1030 | -1ULL, |
| 1031 | -1ULL |
| 1032 | } |
| 1033 | #endif |
| 1034 | }, |
| 1035 | { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1, |
| 1036 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 1037 | #ifndef DISASM_ONLY |
| 1038 | { |
| 1039 | 0xc00000007ffc0000ULL, |
| 1040 | 0ULL, |
| 1041 | 0x00000000780c0000ULL, |
| 1042 | 0ULL, |
| 1043 | 0ULL |
| 1044 | }, |
| 1045 | { |
| 1046 | 0x0000000050180000ULL, |
| 1047 | -1ULL, |
| 1048 | 0x0000000048040000ULL, |
| 1049 | -1ULL, |
| 1050 | -1ULL |
| 1051 | } |
| 1052 | #endif |
| 1053 | }, |
| 1054 | { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1, |
| 1055 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 1056 | #ifndef DISASM_ONLY |
| 1057 | { |
| 1058 | 0xc00000007ffc0000ULL, |
| 1059 | 0xfffe000000000000ULL, |
| 1060 | 0x00000000780c0000ULL, |
| 1061 | 0x3c06000000000000ULL, |
| 1062 | 0ULL |
| 1063 | }, |
| 1064 | { |
| 1065 | 0x00000000501c0000ULL, |
| 1066 | 0x280a000000000000ULL, |
| 1067 | 0x0000000040000000ULL, |
| 1068 | 0x2404000000000000ULL, |
| 1069 | -1ULL |
| 1070 | } |
| 1071 | #endif |
| 1072 | }, |
| 1073 | { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1, |
| 1074 | { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, |
| 1075 | #ifndef DISASM_ONLY |
| 1076 | { |
| 1077 | 0xc00000007ff00000ULL, |
| 1078 | 0xfff8000000000000ULL, |
| 1079 | 0x0000000078000000ULL, |
| 1080 | 0x3c00000000000000ULL, |
| 1081 | 0ULL |
| 1082 | }, |
| 1083 | { |
| 1084 | 0x0000000040400000ULL, |
| 1085 | 0x1820000000000000ULL, |
| 1086 | 0x0000000018000000ULL, |
| 1087 | 0x1000000000000000ULL, |
| 1088 | -1ULL |
| 1089 | } |
| 1090 | #endif |
| 1091 | }, |
| 1092 | { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1, |
| 1093 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1094 | #ifndef DISASM_ONLY |
| 1095 | { |
| 1096 | 0ULL, |
| 1097 | 0xfffe000000000000ULL, |
| 1098 | 0ULL, |
| 1099 | 0ULL, |
| 1100 | 0ULL |
| 1101 | }, |
| 1102 | { |
| 1103 | -1ULL, |
| 1104 | 0x280e000000000000ULL, |
| 1105 | -1ULL, |
| 1106 | -1ULL, |
| 1107 | -1ULL |
| 1108 | } |
| 1109 | #endif |
| 1110 | }, |
| 1111 | { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1, |
| 1112 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1113 | #ifndef DISASM_ONLY |
| 1114 | { |
| 1115 | 0ULL, |
| 1116 | 0xfffe000000000000ULL, |
| 1117 | 0ULL, |
| 1118 | 0ULL, |
| 1119 | 0ULL |
| 1120 | }, |
| 1121 | { |
| 1122 | -1ULL, |
| 1123 | 0x280c000000000000ULL, |
| 1124 | -1ULL, |
| 1125 | -1ULL, |
| 1126 | -1ULL |
| 1127 | } |
| 1128 | #endif |
| 1129 | }, |
| 1130 | { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1, |
| 1131 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 1132 | #ifndef DISASM_ONLY |
| 1133 | { |
| 1134 | 0xc00000007ffc0000ULL, |
| 1135 | 0xfffe000000000000ULL, |
| 1136 | 0x00000000780c0000ULL, |
| 1137 | 0x3c06000000000000ULL, |
| 1138 | 0ULL |
| 1139 | }, |
| 1140 | { |
| 1141 | 0x0000000050200000ULL, |
| 1142 | 0x2810000000000000ULL, |
| 1143 | 0x0000000038000000ULL, |
| 1144 | 0x2000000000000000ULL, |
| 1145 | -1ULL |
| 1146 | } |
| 1147 | #endif |
| 1148 | }, |
| 1149 | { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1, |
| 1150 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 1151 | #ifndef DISASM_ONLY |
| 1152 | { |
| 1153 | 0xc00000007ffc0000ULL, |
| 1154 | 0xfffe000000000000ULL, |
| 1155 | 0x00000000780c0000ULL, |
| 1156 | 0x3c06000000000000ULL, |
| 1157 | 0ULL |
| 1158 | }, |
| 1159 | { |
| 1160 | 0x0000000050240000ULL, |
| 1161 | 0x2812000000000000ULL, |
| 1162 | 0x0000000038040000ULL, |
| 1163 | 0x2002000000000000ULL, |
| 1164 | -1ULL |
| 1165 | } |
| 1166 | #endif |
| 1167 | }, |
| 1168 | { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1, |
| 1169 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 1170 | #ifndef DISASM_ONLY |
| 1171 | { |
| 1172 | 0xc00000007ffc0000ULL, |
| 1173 | 0xfffe000000000000ULL, |
| 1174 | 0x00000000780c0000ULL, |
| 1175 | 0x3c06000000000000ULL, |
| 1176 | 0ULL |
| 1177 | }, |
| 1178 | { |
| 1179 | 0x0000000050280000ULL, |
| 1180 | 0x2814000000000000ULL, |
| 1181 | 0x0000000038080000ULL, |
| 1182 | 0x2004000000000000ULL, |
| 1183 | -1ULL |
| 1184 | } |
| 1185 | #endif |
| 1186 | }, |
| 1187 | { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1, |
| 1188 | { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, |
| 1189 | #ifndef DISASM_ONLY |
| 1190 | { |
| 1191 | 0xc00000007ff00000ULL, |
| 1192 | 0xfff8000000000000ULL, |
| 1193 | 0x0000000078000000ULL, |
| 1194 | 0x3c00000000000000ULL, |
| 1195 | 0ULL |
| 1196 | }, |
| 1197 | { |
| 1198 | 0x0000000040500000ULL, |
| 1199 | 0x1828000000000000ULL, |
| 1200 | 0x0000000020000000ULL, |
| 1201 | 0x1400000000000000ULL, |
| 1202 | -1ULL |
| 1203 | } |
| 1204 | #endif |
| 1205 | }, |
| 1206 | { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1, |
| 1207 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 1208 | #ifndef DISASM_ONLY |
| 1209 | { |
| 1210 | 0xc00000007ffc0000ULL, |
| 1211 | 0xfffe000000000000ULL, |
| 1212 | 0x00000000780c0000ULL, |
| 1213 | 0x3c06000000000000ULL, |
| 1214 | 0ULL |
| 1215 | }, |
| 1216 | { |
| 1217 | 0x00000000502c0000ULL, |
| 1218 | 0x2816000000000000ULL, |
| 1219 | 0x00000000380c0000ULL, |
| 1220 | 0x2006000000000000ULL, |
| 1221 | -1ULL |
| 1222 | } |
| 1223 | #endif |
| 1224 | }, |
| 1225 | { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1, |
| 1226 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 1227 | #ifndef DISASM_ONLY |
| 1228 | { |
| 1229 | 0xc00000007ff00000ULL, |
| 1230 | 0xfff8000000000000ULL, |
| 1231 | 0ULL, |
| 1232 | 0ULL, |
| 1233 | 0ULL |
| 1234 | }, |
| 1235 | { |
| 1236 | 0x0000000040600000ULL, |
| 1237 | 0x1830000000000000ULL, |
| 1238 | -1ULL, |
| 1239 | -1ULL, |
| 1240 | -1ULL |
| 1241 | } |
| 1242 | #endif |
| 1243 | }, |
| 1244 | { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1, |
| 1245 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 1246 | #ifndef DISASM_ONLY |
| 1247 | { |
| 1248 | 0xc00000007ffc0000ULL, |
| 1249 | 0xfffe000000000000ULL, |
| 1250 | 0x00000000780c0000ULL, |
| 1251 | 0x3c06000000000000ULL, |
| 1252 | 0ULL |
| 1253 | }, |
| 1254 | { |
| 1255 | 0x0000000050300000ULL, |
| 1256 | 0x2818000000000000ULL, |
| 1257 | 0x0000000040040000ULL, |
| 1258 | 0x2406000000000000ULL, |
| 1259 | -1ULL |
| 1260 | } |
| 1261 | #endif |
| 1262 | }, |
| 1263 | { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1, |
| 1264 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1265 | #ifndef DISASM_ONLY |
| 1266 | { |
| 1267 | 0xc00000007ffc0000ULL, |
| 1268 | 0ULL, |
| 1269 | 0ULL, |
| 1270 | 0ULL, |
| 1271 | 0ULL |
| 1272 | }, |
| 1273 | { |
| 1274 | 0x00000000504c0000ULL, |
| 1275 | -1ULL, |
| 1276 | -1ULL, |
| 1277 | -1ULL, |
| 1278 | -1ULL |
| 1279 | } |
| 1280 | #endif |
| 1281 | }, |
| 1282 | { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1, |
| 1283 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1284 | #ifndef DISASM_ONLY |
| 1285 | { |
| 1286 | 0xc00000007ffc0000ULL, |
| 1287 | 0ULL, |
| 1288 | 0ULL, |
| 1289 | 0ULL, |
| 1290 | 0ULL |
| 1291 | }, |
| 1292 | { |
| 1293 | 0x0000000050380000ULL, |
| 1294 | -1ULL, |
| 1295 | -1ULL, |
| 1296 | -1ULL, |
| 1297 | -1ULL |
| 1298 | } |
| 1299 | #endif |
| 1300 | }, |
| 1301 | { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1, |
| 1302 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1303 | #ifndef DISASM_ONLY |
| 1304 | { |
| 1305 | 0xc00000007ffc0000ULL, |
| 1306 | 0ULL, |
| 1307 | 0ULL, |
| 1308 | 0ULL, |
| 1309 | 0ULL |
| 1310 | }, |
| 1311 | { |
| 1312 | 0x0000000050340000ULL, |
| 1313 | -1ULL, |
| 1314 | -1ULL, |
| 1315 | -1ULL, |
| 1316 | -1ULL |
| 1317 | } |
| 1318 | #endif |
| 1319 | }, |
| 1320 | { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1, |
| 1321 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1322 | #ifndef DISASM_ONLY |
| 1323 | { |
| 1324 | 0xc00000007ffc0000ULL, |
| 1325 | 0ULL, |
| 1326 | 0ULL, |
| 1327 | 0ULL, |
| 1328 | 0ULL |
| 1329 | }, |
| 1330 | { |
| 1331 | 0x0000000050400000ULL, |
| 1332 | -1ULL, |
| 1333 | -1ULL, |
| 1334 | -1ULL, |
| 1335 | -1ULL |
| 1336 | } |
| 1337 | #endif |
| 1338 | }, |
| 1339 | { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1, |
| 1340 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1341 | #ifndef DISASM_ONLY |
| 1342 | { |
| 1343 | 0xc00000007ffc0000ULL, |
| 1344 | 0ULL, |
| 1345 | 0ULL, |
| 1346 | 0ULL, |
| 1347 | 0ULL |
| 1348 | }, |
| 1349 | { |
| 1350 | 0x00000000503c0000ULL, |
| 1351 | -1ULL, |
| 1352 | -1ULL, |
| 1353 | -1ULL, |
| 1354 | -1ULL |
| 1355 | } |
| 1356 | #endif |
| 1357 | }, |
| 1358 | { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1, |
| 1359 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1360 | #ifndef DISASM_ONLY |
| 1361 | { |
| 1362 | 0xc00000007ffc0000ULL, |
| 1363 | 0ULL, |
| 1364 | 0ULL, |
| 1365 | 0ULL, |
| 1366 | 0ULL |
| 1367 | }, |
| 1368 | { |
| 1369 | 0x0000000050480000ULL, |
| 1370 | -1ULL, |
| 1371 | -1ULL, |
| 1372 | -1ULL, |
| 1373 | -1ULL |
| 1374 | } |
| 1375 | #endif |
| 1376 | }, |
| 1377 | { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1, |
| 1378 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1379 | #ifndef DISASM_ONLY |
| 1380 | { |
| 1381 | 0xc00000007ffc0000ULL, |
| 1382 | 0ULL, |
| 1383 | 0ULL, |
| 1384 | 0ULL, |
| 1385 | 0ULL |
| 1386 | }, |
| 1387 | { |
| 1388 | 0x0000000050440000ULL, |
| 1389 | -1ULL, |
| 1390 | -1ULL, |
| 1391 | -1ULL, |
| 1392 | -1ULL |
| 1393 | } |
| 1394 | #endif |
| 1395 | }, |
| 1396 | { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, |
| 1397 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1398 | #ifndef DISASM_ONLY |
| 1399 | { |
| 1400 | 0xc00000007ffc0000ULL, |
| 1401 | 0ULL, |
| 1402 | 0ULL, |
| 1403 | 0ULL, |
| 1404 | 0ULL |
| 1405 | }, |
| 1406 | { |
| 1407 | 0x0000000050500000ULL, |
| 1408 | -1ULL, |
| 1409 | -1ULL, |
| 1410 | -1ULL, |
| 1411 | -1ULL |
| 1412 | } |
| 1413 | #endif |
| 1414 | }, |
| 1415 | { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, |
| 1416 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1417 | #ifndef DISASM_ONLY |
| 1418 | { |
| 1419 | 0xc00000007ffc0000ULL, |
| 1420 | 0ULL, |
| 1421 | 0ULL, |
| 1422 | 0ULL, |
| 1423 | 0ULL |
| 1424 | }, |
| 1425 | { |
| 1426 | 0x0000000050540000ULL, |
| 1427 | -1ULL, |
| 1428 | -1ULL, |
| 1429 | -1ULL, |
| 1430 | -1ULL |
| 1431 | } |
| 1432 | #endif |
| 1433 | }, |
| 1434 | { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, |
| 1435 | { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, |
| 1436 | #ifndef DISASM_ONLY |
| 1437 | { |
| 1438 | 0xc00000007ffff000ULL, |
| 1439 | 0ULL, |
| 1440 | 0x00000000780ff000ULL, |
| 1441 | 0ULL, |
| 1442 | 0ULL |
| 1443 | }, |
| 1444 | { |
| 1445 | 0x0000000051482000ULL, |
| 1446 | -1ULL, |
| 1447 | 0x00000000300c2000ULL, |
| 1448 | -1ULL, |
| 1449 | -1ULL |
| 1450 | } |
| 1451 | #endif |
| 1452 | }, |
| 1453 | { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1, |
| 1454 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1455 | #ifndef DISASM_ONLY |
| 1456 | { |
| 1457 | 0xc00000007ffc0000ULL, |
| 1458 | 0ULL, |
| 1459 | 0ULL, |
| 1460 | 0ULL, |
| 1461 | 0ULL |
| 1462 | }, |
| 1463 | { |
| 1464 | 0x0000000050640000ULL, |
| 1465 | -1ULL, |
| 1466 | -1ULL, |
| 1467 | -1ULL, |
| 1468 | -1ULL |
| 1469 | } |
| 1470 | #endif |
| 1471 | }, |
| 1472 | { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1, |
| 1473 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1474 | #ifndef DISASM_ONLY |
| 1475 | { |
| 1476 | 0xc00000007ffc0000ULL, |
| 1477 | 0xfffe000000000000ULL, |
| 1478 | 0ULL, |
| 1479 | 0ULL, |
| 1480 | 0ULL |
| 1481 | }, |
| 1482 | { |
| 1483 | 0x0000000050580000ULL, |
| 1484 | 0x281a000000000000ULL, |
| 1485 | -1ULL, |
| 1486 | -1ULL, |
| 1487 | -1ULL |
| 1488 | } |
| 1489 | #endif |
| 1490 | }, |
| 1491 | { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1, |
| 1492 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1493 | #ifndef DISASM_ONLY |
| 1494 | { |
| 1495 | 0xc00000007ffc0000ULL, |
| 1496 | 0xfffe000000000000ULL, |
| 1497 | 0ULL, |
| 1498 | 0ULL, |
| 1499 | 0ULL |
| 1500 | }, |
| 1501 | { |
| 1502 | 0x00000000505c0000ULL, |
| 1503 | 0x281c000000000000ULL, |
| 1504 | -1ULL, |
| 1505 | -1ULL, |
| 1506 | -1ULL |
| 1507 | } |
| 1508 | #endif |
| 1509 | }, |
| 1510 | { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1, |
| 1511 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1512 | #ifndef DISASM_ONLY |
| 1513 | { |
| 1514 | 0xc00000007ffc0000ULL, |
| 1515 | 0xfffe000000000000ULL, |
| 1516 | 0ULL, |
| 1517 | 0ULL, |
| 1518 | 0ULL |
| 1519 | }, |
| 1520 | { |
| 1521 | 0x0000000050600000ULL, |
| 1522 | 0x281e000000000000ULL, |
| 1523 | -1ULL, |
| 1524 | -1ULL, |
| 1525 | -1ULL |
| 1526 | } |
| 1527 | #endif |
| 1528 | }, |
| 1529 | { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, |
| 1530 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 1531 | #ifndef DISASM_ONLY |
| 1532 | { |
| 1533 | 0ULL, |
| 1534 | 0xfffff80000000000ULL, |
| 1535 | 0ULL, |
| 1536 | 0ULL, |
| 1537 | 0ULL |
| 1538 | }, |
| 1539 | { |
| 1540 | -1ULL, |
| 1541 | 0x286a080000000000ULL, |
| 1542 | -1ULL, |
| 1543 | -1ULL, |
| 1544 | -1ULL |
| 1545 | } |
| 1546 | #endif |
| 1547 | }, |
| 1548 | { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, |
| 1549 | { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, |
| 1550 | #ifndef DISASM_ONLY |
| 1551 | { |
| 1552 | 0ULL, |
| 1553 | 0xfffff80000000000ULL, |
| 1554 | 0ULL, |
| 1555 | 0ULL, |
| 1556 | 0ULL |
| 1557 | }, |
| 1558 | { |
| 1559 | -1ULL, |
| 1560 | 0x286a100000000000ULL, |
| 1561 | -1ULL, |
| 1562 | -1ULL, |
| 1563 | -1ULL |
| 1564 | } |
| 1565 | #endif |
| 1566 | }, |
| 1567 | { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1, |
| 1568 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1569 | #ifndef DISASM_ONLY |
| 1570 | { |
| 1571 | 0ULL, |
| 1572 | 0xfffe000000000000ULL, |
| 1573 | 0ULL, |
| 1574 | 0ULL, |
| 1575 | 0ULL |
| 1576 | }, |
| 1577 | { |
| 1578 | -1ULL, |
| 1579 | 0x2822000000000000ULL, |
| 1580 | -1ULL, |
| 1581 | -1ULL, |
| 1582 | -1ULL |
| 1583 | } |
| 1584 | #endif |
| 1585 | }, |
| 1586 | { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1, |
| 1587 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1588 | #ifndef DISASM_ONLY |
| 1589 | { |
| 1590 | 0ULL, |
| 1591 | 0xfffe000000000000ULL, |
| 1592 | 0ULL, |
| 1593 | 0ULL, |
| 1594 | 0ULL |
| 1595 | }, |
| 1596 | { |
| 1597 | -1ULL, |
| 1598 | 0x2820000000000000ULL, |
| 1599 | -1ULL, |
| 1600 | -1ULL, |
| 1601 | -1ULL |
| 1602 | } |
| 1603 | #endif |
| 1604 | }, |
| 1605 | { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1, |
| 1606 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1607 | #ifndef DISASM_ONLY |
| 1608 | { |
| 1609 | 0xc00000007ffc0000ULL, |
| 1610 | 0ULL, |
| 1611 | 0ULL, |
| 1612 | 0ULL, |
| 1613 | 0ULL |
| 1614 | }, |
| 1615 | { |
| 1616 | 0x00000000506c0000ULL, |
| 1617 | -1ULL, |
| 1618 | -1ULL, |
| 1619 | -1ULL, |
| 1620 | -1ULL |
| 1621 | } |
| 1622 | #endif |
| 1623 | }, |
| 1624 | { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1, |
| 1625 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1626 | #ifndef DISASM_ONLY |
| 1627 | { |
| 1628 | 0xc00000007ffc0000ULL, |
| 1629 | 0ULL, |
| 1630 | 0ULL, |
| 1631 | 0ULL, |
| 1632 | 0ULL |
| 1633 | }, |
| 1634 | { |
| 1635 | 0x0000000050680000ULL, |
| 1636 | -1ULL, |
| 1637 | -1ULL, |
| 1638 | -1ULL, |
| 1639 | -1ULL |
| 1640 | } |
| 1641 | #endif |
| 1642 | }, |
| 1643 | { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1, |
| 1644 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1645 | #ifndef DISASM_ONLY |
| 1646 | { |
| 1647 | 0xc00000007ffc0000ULL, |
| 1648 | 0ULL, |
| 1649 | 0ULL, |
| 1650 | 0ULL, |
| 1651 | 0ULL |
| 1652 | }, |
| 1653 | { |
| 1654 | 0x0000000050700000ULL, |
| 1655 | -1ULL, |
| 1656 | -1ULL, |
| 1657 | -1ULL, |
| 1658 | -1ULL |
| 1659 | } |
| 1660 | #endif |
| 1661 | }, |
| 1662 | { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1, |
| 1663 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1664 | #ifndef DISASM_ONLY |
| 1665 | { |
| 1666 | 0xc00000007ffc0000ULL, |
| 1667 | 0ULL, |
| 1668 | 0ULL, |
| 1669 | 0ULL, |
| 1670 | 0ULL |
| 1671 | }, |
| 1672 | { |
| 1673 | 0x0000000050740000ULL, |
| 1674 | -1ULL, |
| 1675 | -1ULL, |
| 1676 | -1ULL, |
| 1677 | -1ULL |
| 1678 | } |
| 1679 | #endif |
| 1680 | }, |
| 1681 | { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1, |
| 1682 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1683 | #ifndef DISASM_ONLY |
| 1684 | { |
| 1685 | 0xc00000007ffc0000ULL, |
| 1686 | 0ULL, |
| 1687 | 0ULL, |
| 1688 | 0ULL, |
| 1689 | 0ULL |
| 1690 | }, |
| 1691 | { |
| 1692 | 0x0000000050780000ULL, |
| 1693 | -1ULL, |
| 1694 | -1ULL, |
| 1695 | -1ULL, |
| 1696 | -1ULL |
| 1697 | } |
| 1698 | #endif |
| 1699 | }, |
| 1700 | { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1, |
| 1701 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1702 | #ifndef DISASM_ONLY |
| 1703 | { |
| 1704 | 0xc00000007ffc0000ULL, |
| 1705 | 0ULL, |
| 1706 | 0ULL, |
| 1707 | 0ULL, |
| 1708 | 0ULL |
| 1709 | }, |
| 1710 | { |
| 1711 | 0x00000000507c0000ULL, |
| 1712 | -1ULL, |
| 1713 | -1ULL, |
| 1714 | -1ULL, |
| 1715 | -1ULL |
| 1716 | } |
| 1717 | #endif |
| 1718 | }, |
| 1719 | { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1, |
| 1720 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1721 | #ifndef DISASM_ONLY |
| 1722 | { |
| 1723 | 0xc00000007ffc0000ULL, |
| 1724 | 0ULL, |
| 1725 | 0ULL, |
| 1726 | 0ULL, |
| 1727 | 0ULL |
| 1728 | }, |
| 1729 | { |
| 1730 | 0x0000000050800000ULL, |
| 1731 | -1ULL, |
| 1732 | -1ULL, |
| 1733 | -1ULL, |
| 1734 | -1ULL |
| 1735 | } |
| 1736 | #endif |
| 1737 | }, |
| 1738 | { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1, |
| 1739 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1740 | #ifndef DISASM_ONLY |
| 1741 | { |
| 1742 | 0xc00000007ffc0000ULL, |
| 1743 | 0ULL, |
| 1744 | 0ULL, |
| 1745 | 0ULL, |
| 1746 | 0ULL |
| 1747 | }, |
| 1748 | { |
| 1749 | 0x0000000050840000ULL, |
| 1750 | -1ULL, |
| 1751 | -1ULL, |
| 1752 | -1ULL, |
| 1753 | -1ULL |
| 1754 | } |
| 1755 | #endif |
| 1756 | }, |
| 1757 | { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1, |
| 1758 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1759 | #ifndef DISASM_ONLY |
| 1760 | { |
| 1761 | 0ULL, |
| 1762 | 0xfffe000000000000ULL, |
| 1763 | 0ULL, |
| 1764 | 0ULL, |
| 1765 | 0ULL |
| 1766 | }, |
| 1767 | { |
| 1768 | -1ULL, |
| 1769 | 0x282a000000000000ULL, |
| 1770 | -1ULL, |
| 1771 | -1ULL, |
| 1772 | -1ULL |
| 1773 | } |
| 1774 | #endif |
| 1775 | }, |
| 1776 | { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1, |
| 1777 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1778 | #ifndef DISASM_ONLY |
| 1779 | { |
| 1780 | 0ULL, |
| 1781 | 0xfffe000000000000ULL, |
| 1782 | 0ULL, |
| 1783 | 0ULL, |
| 1784 | 0ULL |
| 1785 | }, |
| 1786 | { |
| 1787 | -1ULL, |
| 1788 | 0x2824000000000000ULL, |
| 1789 | -1ULL, |
| 1790 | -1ULL, |
| 1791 | -1ULL |
| 1792 | } |
| 1793 | #endif |
| 1794 | }, |
| 1795 | { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1, |
| 1796 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1797 | #ifndef DISASM_ONLY |
| 1798 | { |
| 1799 | 0ULL, |
| 1800 | 0xfffe000000000000ULL, |
| 1801 | 0ULL, |
| 1802 | 0ULL, |
| 1803 | 0ULL |
| 1804 | }, |
| 1805 | { |
| 1806 | -1ULL, |
| 1807 | 0x2828000000000000ULL, |
| 1808 | -1ULL, |
| 1809 | -1ULL, |
| 1810 | -1ULL |
| 1811 | } |
| 1812 | #endif |
| 1813 | }, |
| 1814 | { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1, |
| 1815 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1816 | #ifndef DISASM_ONLY |
| 1817 | { |
| 1818 | 0ULL, |
| 1819 | 0xfffe000000000000ULL, |
| 1820 | 0ULL, |
| 1821 | 0ULL, |
| 1822 | 0ULL |
| 1823 | }, |
| 1824 | { |
| 1825 | -1ULL, |
| 1826 | 0x2826000000000000ULL, |
| 1827 | -1ULL, |
| 1828 | -1ULL, |
| 1829 | -1ULL |
| 1830 | } |
| 1831 | #endif |
| 1832 | }, |
| 1833 | { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1, |
| 1834 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1835 | #ifndef DISASM_ONLY |
| 1836 | { |
| 1837 | 0ULL, |
| 1838 | 0xfffe000000000000ULL, |
| 1839 | 0ULL, |
| 1840 | 0ULL, |
| 1841 | 0ULL |
| 1842 | }, |
| 1843 | { |
| 1844 | -1ULL, |
| 1845 | 0x282e000000000000ULL, |
| 1846 | -1ULL, |
| 1847 | -1ULL, |
| 1848 | -1ULL |
| 1849 | } |
| 1850 | #endif |
| 1851 | }, |
| 1852 | { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1, |
| 1853 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1854 | #ifndef DISASM_ONLY |
| 1855 | { |
| 1856 | 0ULL, |
| 1857 | 0xfffe000000000000ULL, |
| 1858 | 0ULL, |
| 1859 | 0ULL, |
| 1860 | 0ULL |
| 1861 | }, |
| 1862 | { |
| 1863 | -1ULL, |
| 1864 | 0x282c000000000000ULL, |
| 1865 | -1ULL, |
| 1866 | -1ULL, |
| 1867 | -1ULL |
| 1868 | } |
| 1869 | #endif |
| 1870 | }, |
| 1871 | { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1, |
| 1872 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1873 | #ifndef DISASM_ONLY |
| 1874 | { |
| 1875 | 0ULL, |
| 1876 | 0xfffe000000000000ULL, |
| 1877 | 0ULL, |
| 1878 | 0ULL, |
| 1879 | 0ULL |
| 1880 | }, |
| 1881 | { |
| 1882 | -1ULL, |
| 1883 | 0x2832000000000000ULL, |
| 1884 | -1ULL, |
| 1885 | -1ULL, |
| 1886 | -1ULL |
| 1887 | } |
| 1888 | #endif |
| 1889 | }, |
| 1890 | { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1, |
| 1891 | { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 1892 | #ifndef DISASM_ONLY |
| 1893 | { |
| 1894 | 0ULL, |
| 1895 | 0xfffe000000000000ULL, |
| 1896 | 0ULL, |
| 1897 | 0ULL, |
| 1898 | 0ULL |
| 1899 | }, |
| 1900 | { |
| 1901 | -1ULL, |
| 1902 | 0x2830000000000000ULL, |
| 1903 | -1ULL, |
| 1904 | -1ULL, |
| 1905 | -1ULL |
| 1906 | } |
| 1907 | #endif |
| 1908 | }, |
| 1909 | { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1, |
| 1910 | { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, |
| 1911 | #ifndef DISASM_ONLY |
| 1912 | { |
| 1913 | 0ULL, |
| 1914 | 0xfffff80000000000ULL, |
| 1915 | 0ULL, |
| 1916 | 0ULL, |
| 1917 | 0ULL |
| 1918 | }, |
| 1919 | { |
| 1920 | -1ULL, |
| 1921 | 0x286a180000000000ULL, |
| 1922 | -1ULL, |
| 1923 | -1ULL, |
| 1924 | -1ULL |
| 1925 | } |
| 1926 | #endif |
| 1927 | }, |
| 1928 | { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, |
| 1929 | { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, |
| 1930 | #ifndef DISASM_ONLY |
| 1931 | { |
| 1932 | 0ULL, |
| 1933 | 0xfffff80000000000ULL, |
| 1934 | 0ULL, |
| 1935 | 0ULL, |
| 1936 | 0ULL |
| 1937 | }, |
| 1938 | { |
| 1939 | -1ULL, |
| 1940 | 0x286a280000000000ULL, |
| 1941 | -1ULL, |
| 1942 | -1ULL, |
| 1943 | -1ULL |
| 1944 | } |
| 1945 | #endif |
| 1946 | }, |
| 1947 | { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1, |
| 1948 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 1949 | #ifndef DISASM_ONLY |
| 1950 | { |
| 1951 | 0ULL, |
| 1952 | 0xfffff80000000000ULL, |
| 1953 | 0ULL, |
| 1954 | 0ULL, |
| 1955 | 0ULL |
| 1956 | }, |
| 1957 | { |
| 1958 | -1ULL, |
| 1959 | 0x286a200000000000ULL, |
| 1960 | -1ULL, |
| 1961 | -1ULL, |
| 1962 | -1ULL |
| 1963 | } |
| 1964 | #endif |
| 1965 | }, |
| 1966 | { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, |
| 1967 | { { }, { }, { }, { }, { 0, } }, |
| 1968 | #ifndef DISASM_ONLY |
| 1969 | { |
| 1970 | 0xc00000007ffff000ULL, |
| 1971 | 0xfffff80000000000ULL, |
| 1972 | 0x00000000780ff000ULL, |
| 1973 | 0x3c07f80000000000ULL, |
| 1974 | 0ULL |
| 1975 | }, |
| 1976 | { |
| 1977 | 0x0000000051483000ULL, |
| 1978 | 0x286a300000000000ULL, |
| 1979 | 0x00000000300c3000ULL, |
| 1980 | 0x1c06400000000000ULL, |
| 1981 | -1ULL |
| 1982 | } |
| 1983 | #endif |
| 1984 | }, |
| 1985 | { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1, |
| 1986 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 1987 | #ifndef DISASM_ONLY |
| 1988 | { |
| 1989 | 0xc00000007ffc0000ULL, |
| 1990 | 0ULL, |
| 1991 | 0ULL, |
| 1992 | 0ULL, |
| 1993 | 0ULL |
| 1994 | }, |
| 1995 | { |
| 1996 | 0x0000000050880000ULL, |
| 1997 | -1ULL, |
| 1998 | -1ULL, |
| 1999 | -1ULL, |
| 2000 | -1ULL |
| 2001 | } |
| 2002 | #endif |
| 2003 | }, |
| 2004 | { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1, |
| 2005 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 2006 | #ifndef DISASM_ONLY |
| 2007 | { |
| 2008 | 0xc00000007ffc0000ULL, |
| 2009 | 0ULL, |
| 2010 | 0ULL, |
| 2011 | 0ULL, |
| 2012 | 0ULL |
| 2013 | }, |
| 2014 | { |
| 2015 | 0x00000000508c0000ULL, |
| 2016 | -1ULL, |
| 2017 | -1ULL, |
| 2018 | -1ULL, |
| 2019 | -1ULL |
| 2020 | } |
| 2021 | #endif |
| 2022 | }, |
| 2023 | { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1, |
| 2024 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 2025 | #ifndef DISASM_ONLY |
| 2026 | { |
| 2027 | 0xc00000007ffc0000ULL, |
| 2028 | 0ULL, |
| 2029 | 0ULL, |
| 2030 | 0ULL, |
| 2031 | 0ULL |
| 2032 | }, |
| 2033 | { |
| 2034 | 0x0000000050900000ULL, |
| 2035 | -1ULL, |
| 2036 | -1ULL, |
| 2037 | -1ULL, |
| 2038 | -1ULL |
| 2039 | } |
| 2040 | #endif |
| 2041 | }, |
| 2042 | { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1, |
| 2043 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 2044 | #ifndef DISASM_ONLY |
| 2045 | { |
| 2046 | 0xc00000007ffc0000ULL, |
| 2047 | 0ULL, |
| 2048 | 0ULL, |
| 2049 | 0ULL, |
| 2050 | 0ULL |
| 2051 | }, |
| 2052 | { |
| 2053 | 0x0000000050940000ULL, |
| 2054 | -1ULL, |
| 2055 | -1ULL, |
| 2056 | -1ULL, |
| 2057 | -1ULL |
| 2058 | } |
| 2059 | #endif |
| 2060 | }, |
| 2061 | { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1, |
| 2062 | { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, |
| 2063 | #ifndef DISASM_ONLY |
| 2064 | { |
| 2065 | 0xc00000007ffff000ULL, |
| 2066 | 0ULL, |
| 2067 | 0x00000000780ff000ULL, |
| 2068 | 0ULL, |
| 2069 | 0ULL |
| 2070 | }, |
| 2071 | { |
| 2072 | 0x0000000051484000ULL, |
| 2073 | -1ULL, |
| 2074 | 0x00000000300c4000ULL, |
| 2075 | -1ULL, |
| 2076 | -1ULL |
| 2077 | } |
| 2078 | #endif |
| 2079 | }, |
| 2080 | { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1, |
| 2081 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 2082 | #ifndef DISASM_ONLY |
| 2083 | { |
| 2084 | 0xc00000007ffc0000ULL, |
| 2085 | 0ULL, |
| 2086 | 0ULL, |
| 2087 | 0ULL, |
| 2088 | 0ULL |
| 2089 | }, |
| 2090 | { |
| 2091 | 0x0000000050980000ULL, |
| 2092 | -1ULL, |
| 2093 | -1ULL, |
| 2094 | -1ULL, |
| 2095 | -1ULL |
| 2096 | } |
| 2097 | #endif |
| 2098 | }, |
| 2099 | { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1, |
| 2100 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 2101 | #ifndef DISASM_ONLY |
| 2102 | { |
| 2103 | 0xc00000007ffc0000ULL, |
| 2104 | 0ULL, |
| 2105 | 0ULL, |
| 2106 | 0ULL, |
| 2107 | 0ULL |
| 2108 | }, |
| 2109 | { |
| 2110 | 0x00000000509c0000ULL, |
| 2111 | -1ULL, |
| 2112 | -1ULL, |
| 2113 | -1ULL, |
| 2114 | -1ULL |
| 2115 | } |
| 2116 | #endif |
| 2117 | }, |
| 2118 | { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, |
| 2119 | { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, |
| 2120 | #ifndef DISASM_ONLY |
| 2121 | { |
| 2122 | 0ULL, |
| 2123 | 0xfffff80000000000ULL, |
| 2124 | 0ULL, |
| 2125 | 0ULL, |
| 2126 | 0ULL |
| 2127 | }, |
| 2128 | { |
| 2129 | -1ULL, |
| 2130 | 0x286a380000000000ULL, |
| 2131 | -1ULL, |
| 2132 | -1ULL, |
| 2133 | -1ULL |
| 2134 | } |
| 2135 | #endif |
| 2136 | }, |
| 2137 | { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1, |
| 2138 | { { 0, }, { }, { 0, }, { }, { 0, } }, |
| 2139 | #ifndef DISASM_ONLY |
| 2140 | { |
| 2141 | 0ULL, |
| 2142 | 0xfffff80000000000ULL, |
| 2143 | 0ULL, |
| 2144 | 0x3c07f80000000000ULL, |
| 2145 | 0ULL |
| 2146 | }, |
| 2147 | { |
| 2148 | -1ULL, |
| 2149 | 0x286a400000000000ULL, |
| 2150 | -1ULL, |
| 2151 | 0x1c06480000000000ULL, |
| 2152 | -1ULL |
| 2153 | } |
| 2154 | #endif |
| 2155 | }, |
| 2156 | { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1, |
| 2157 | { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, |
| 2158 | #ifndef DISASM_ONLY |
| 2159 | { |
| 2160 | 0ULL, |
| 2161 | 0xfffff80000000000ULL, |
| 2162 | 0ULL, |
| 2163 | 0ULL, |
| 2164 | 0ULL |
| 2165 | }, |
| 2166 | { |
| 2167 | -1ULL, |
| 2168 | 0x286a480000000000ULL, |
| 2169 | -1ULL, |
| 2170 | -1ULL, |
| 2171 | -1ULL |
| 2172 | } |
| 2173 | #endif |
| 2174 | }, |
| 2175 | { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1, |
| 2176 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 2177 | #ifndef DISASM_ONLY |
| 2178 | { |
| 2179 | 0ULL, |
| 2180 | 0xfffff80000000000ULL, |
| 2181 | 0ULL, |
| 2182 | 0ULL, |
| 2183 | 0ULL |
| 2184 | }, |
| 2185 | { |
| 2186 | -1ULL, |
| 2187 | 0x286a500000000000ULL, |
| 2188 | -1ULL, |
| 2189 | -1ULL, |
| 2190 | -1ULL |
| 2191 | } |
| 2192 | #endif |
| 2193 | }, |
| 2194 | { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1, |
| 2195 | { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } }, |
| 2196 | #ifndef DISASM_ONLY |
| 2197 | { |
| 2198 | 0ULL, |
| 2199 | 0xfc00000000000000ULL, |
| 2200 | 0ULL, |
| 2201 | 0ULL, |
| 2202 | 0ULL |
| 2203 | }, |
| 2204 | { |
| 2205 | -1ULL, |
| 2206 | 0x2400000000000000ULL, |
| 2207 | -1ULL, |
| 2208 | -1ULL, |
| 2209 | -1ULL |
| 2210 | } |
| 2211 | #endif |
| 2212 | }, |
| 2213 | { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1, |
| 2214 | { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } }, |
| 2215 | #ifndef DISASM_ONLY |
| 2216 | { |
| 2217 | 0ULL, |
| 2218 | 0xfc00000000000000ULL, |
| 2219 | 0ULL, |
| 2220 | 0ULL, |
| 2221 | 0ULL |
| 2222 | }, |
| 2223 | { |
| 2224 | -1ULL, |
| 2225 | 0x2000000000000000ULL, |
| 2226 | -1ULL, |
| 2227 | -1ULL, |
| 2228 | -1ULL |
| 2229 | } |
| 2230 | #endif |
| 2231 | }, |
| 2232 | { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1, |
| 2233 | { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, |
| 2234 | #ifndef DISASM_ONLY |
| 2235 | { |
| 2236 | 0ULL, |
| 2237 | 0xfffff80000000000ULL, |
| 2238 | 0ULL, |
| 2239 | 0x3c07f80000000000ULL, |
| 2240 | 0ULL |
| 2241 | }, |
| 2242 | { |
| 2243 | -1ULL, |
| 2244 | 0x286a600000000000ULL, |
| 2245 | -1ULL, |
| 2246 | 0x1c06580000000000ULL, |
| 2247 | -1ULL |
| 2248 | } |
| 2249 | #endif |
| 2250 | }, |
| 2251 | { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1, |
| 2252 | { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, |
| 2253 | #ifndef DISASM_ONLY |
| 2254 | { |
| 2255 | 0ULL, |
| 2256 | 0xfffff80000000000ULL, |
| 2257 | 0ULL, |
| 2258 | 0x3c07f80000000000ULL, |
| 2259 | 0ULL |
| 2260 | }, |
| 2261 | { |
| 2262 | -1ULL, |
| 2263 | 0x286a580000000000ULL, |
| 2264 | -1ULL, |
| 2265 | 0x1c06500000000000ULL, |
| 2266 | -1ULL |
| 2267 | } |
| 2268 | #endif |
| 2269 | }, |
| 2270 | { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1, |
| 2271 | { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, |
| 2272 | #ifndef DISASM_ONLY |
| 2273 | { |
| 2274 | 0ULL, |
| 2275 | 0xfffff80000000000ULL, |
| 2276 | 0ULL, |
| 2277 | 0x3c07f80000000000ULL, |
| 2278 | 0ULL |
| 2279 | }, |
| 2280 | { |
| 2281 | -1ULL, |
| 2282 | 0x286a700000000000ULL, |
| 2283 | -1ULL, |
| 2284 | 0x1c06680000000000ULL, |
| 2285 | -1ULL |
| 2286 | } |
| 2287 | #endif |
| 2288 | }, |
| 2289 | { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1, |
| 2290 | { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, |
| 2291 | #ifndef DISASM_ONLY |
| 2292 | { |
| 2293 | 0ULL, |
| 2294 | 0xfffff80000000000ULL, |
| 2295 | 0ULL, |
| 2296 | 0x3c07f80000000000ULL, |
| 2297 | 0ULL |
| 2298 | }, |
| 2299 | { |
| 2300 | -1ULL, |
| 2301 | 0x286a680000000000ULL, |
| 2302 | -1ULL, |
| 2303 | 0x1c06600000000000ULL, |
| 2304 | -1ULL |
| 2305 | } |
| 2306 | #endif |
| 2307 | }, |
| 2308 | { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1, |
| 2309 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2310 | #ifndef DISASM_ONLY |
| 2311 | { |
| 2312 | 0ULL, |
| 2313 | 0xfffff80000000000ULL, |
| 2314 | 0ULL, |
| 2315 | 0ULL, |
| 2316 | 0xc200000004000000ULL |
| 2317 | }, |
| 2318 | { |
| 2319 | -1ULL, |
| 2320 | 0x286ae80000000000ULL, |
| 2321 | -1ULL, |
| 2322 | -1ULL, |
| 2323 | 0x8200000004000000ULL |
| 2324 | } |
| 2325 | #endif |
| 2326 | }, |
| 2327 | { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1, |
| 2328 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2329 | #ifndef DISASM_ONLY |
| 2330 | { |
| 2331 | 0ULL, |
| 2332 | 0xfffff80000000000ULL, |
| 2333 | 0ULL, |
| 2334 | 0ULL, |
| 2335 | 0xc200000004000000ULL |
| 2336 | }, |
| 2337 | { |
| 2338 | -1ULL, |
| 2339 | 0x286a780000000000ULL, |
| 2340 | -1ULL, |
| 2341 | -1ULL, |
| 2342 | 0x4000000000000000ULL |
| 2343 | } |
| 2344 | #endif |
| 2345 | }, |
| 2346 | { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2347 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2348 | #ifndef DISASM_ONLY |
| 2349 | { |
| 2350 | 0ULL, |
| 2351 | 0xfff8000000000000ULL, |
| 2352 | 0ULL, |
| 2353 | 0ULL, |
| 2354 | 0ULL |
| 2355 | }, |
| 2356 | { |
| 2357 | -1ULL, |
| 2358 | 0x1838000000000000ULL, |
| 2359 | -1ULL, |
| 2360 | -1ULL, |
| 2361 | -1ULL |
| 2362 | } |
| 2363 | #endif |
| 2364 | }, |
| 2365 | { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1, |
| 2366 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2367 | #ifndef DISASM_ONLY |
| 2368 | { |
| 2369 | 0ULL, |
| 2370 | 0xfffff80000000000ULL, |
| 2371 | 0ULL, |
| 2372 | 0ULL, |
| 2373 | 0xc200000004000000ULL |
| 2374 | }, |
| 2375 | { |
| 2376 | -1ULL, |
| 2377 | 0x286a800000000000ULL, |
| 2378 | -1ULL, |
| 2379 | -1ULL, |
| 2380 | 0x4000000004000000ULL |
| 2381 | } |
| 2382 | #endif |
| 2383 | }, |
| 2384 | { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2385 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2386 | #ifndef DISASM_ONLY |
| 2387 | { |
| 2388 | 0ULL, |
| 2389 | 0xfff8000000000000ULL, |
| 2390 | 0ULL, |
| 2391 | 0ULL, |
| 2392 | 0ULL |
| 2393 | }, |
| 2394 | { |
| 2395 | -1ULL, |
| 2396 | 0x1840000000000000ULL, |
| 2397 | -1ULL, |
| 2398 | -1ULL, |
| 2399 | -1ULL |
| 2400 | } |
| 2401 | #endif |
| 2402 | }, |
| 2403 | { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1, |
| 2404 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2405 | #ifndef DISASM_ONLY |
| 2406 | { |
| 2407 | 0ULL, |
| 2408 | 0xfffff80000000000ULL, |
| 2409 | 0ULL, |
| 2410 | 0ULL, |
| 2411 | 0xc200000004000000ULL |
| 2412 | }, |
| 2413 | { |
| 2414 | -1ULL, |
| 2415 | 0x286a880000000000ULL, |
| 2416 | -1ULL, |
| 2417 | -1ULL, |
| 2418 | 0x4200000000000000ULL |
| 2419 | } |
| 2420 | #endif |
| 2421 | }, |
| 2422 | { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2423 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2424 | #ifndef DISASM_ONLY |
| 2425 | { |
| 2426 | 0ULL, |
| 2427 | 0xfff8000000000000ULL, |
| 2428 | 0ULL, |
| 2429 | 0ULL, |
| 2430 | 0ULL |
| 2431 | }, |
| 2432 | { |
| 2433 | -1ULL, |
| 2434 | 0x1848000000000000ULL, |
| 2435 | -1ULL, |
| 2436 | -1ULL, |
| 2437 | -1ULL |
| 2438 | } |
| 2439 | #endif |
| 2440 | }, |
| 2441 | { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1, |
| 2442 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2443 | #ifndef DISASM_ONLY |
| 2444 | { |
| 2445 | 0ULL, |
| 2446 | 0xfffff80000000000ULL, |
| 2447 | 0ULL, |
| 2448 | 0ULL, |
| 2449 | 0xc200000004000000ULL |
| 2450 | }, |
| 2451 | { |
| 2452 | -1ULL, |
| 2453 | 0x286a900000000000ULL, |
| 2454 | -1ULL, |
| 2455 | -1ULL, |
| 2456 | 0x4200000004000000ULL |
| 2457 | } |
| 2458 | #endif |
| 2459 | }, |
| 2460 | { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2461 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2462 | #ifndef DISASM_ONLY |
| 2463 | { |
| 2464 | 0ULL, |
| 2465 | 0xfff8000000000000ULL, |
| 2466 | 0ULL, |
| 2467 | 0ULL, |
| 2468 | 0ULL |
| 2469 | }, |
| 2470 | { |
| 2471 | -1ULL, |
| 2472 | 0x1850000000000000ULL, |
| 2473 | -1ULL, |
| 2474 | -1ULL, |
| 2475 | -1ULL |
| 2476 | } |
| 2477 | #endif |
| 2478 | }, |
| 2479 | { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1, |
| 2480 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2481 | #ifndef DISASM_ONLY |
| 2482 | { |
| 2483 | 0ULL, |
| 2484 | 0xfffff80000000000ULL, |
| 2485 | 0ULL, |
| 2486 | 0ULL, |
| 2487 | 0xc200000004000000ULL |
| 2488 | }, |
| 2489 | { |
| 2490 | -1ULL, |
| 2491 | 0x286a980000000000ULL, |
| 2492 | -1ULL, |
| 2493 | -1ULL, |
| 2494 | 0x8000000004000000ULL |
| 2495 | } |
| 2496 | #endif |
| 2497 | }, |
| 2498 | { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2499 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2500 | #ifndef DISASM_ONLY |
| 2501 | { |
| 2502 | 0ULL, |
| 2503 | 0xfff8000000000000ULL, |
| 2504 | 0ULL, |
| 2505 | 0ULL, |
| 2506 | 0ULL |
| 2507 | }, |
| 2508 | { |
| 2509 | -1ULL, |
| 2510 | 0x1858000000000000ULL, |
| 2511 | -1ULL, |
| 2512 | -1ULL, |
| 2513 | -1ULL |
| 2514 | } |
| 2515 | #endif |
| 2516 | }, |
| 2517 | { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1, |
| 2518 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, |
| 2519 | #ifndef DISASM_ONLY |
| 2520 | { |
| 2521 | 0ULL, |
| 2522 | 0xfffff80000000000ULL, |
| 2523 | 0ULL, |
| 2524 | 0ULL, |
| 2525 | 0xc200000004000000ULL |
| 2526 | }, |
| 2527 | { |
| 2528 | -1ULL, |
| 2529 | 0x286aa00000000000ULL, |
| 2530 | -1ULL, |
| 2531 | -1ULL, |
| 2532 | 0x8200000000000000ULL |
| 2533 | } |
| 2534 | #endif |
| 2535 | }, |
| 2536 | { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2537 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2538 | #ifndef DISASM_ONLY |
| 2539 | { |
| 2540 | 0ULL, |
| 2541 | 0xfff8000000000000ULL, |
| 2542 | 0ULL, |
| 2543 | 0ULL, |
| 2544 | 0ULL |
| 2545 | }, |
| 2546 | { |
| 2547 | -1ULL, |
| 2548 | 0x1860000000000000ULL, |
| 2549 | -1ULL, |
| 2550 | -1ULL, |
| 2551 | -1ULL |
| 2552 | } |
| 2553 | #endif |
| 2554 | }, |
| 2555 | { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2556 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2557 | #ifndef DISASM_ONLY |
| 2558 | { |
| 2559 | 0ULL, |
| 2560 | 0xfff8000000000000ULL, |
| 2561 | 0ULL, |
| 2562 | 0ULL, |
| 2563 | 0ULL |
| 2564 | }, |
| 2565 | { |
| 2566 | -1ULL, |
| 2567 | 0x18a0000000000000ULL, |
| 2568 | -1ULL, |
| 2569 | -1ULL, |
| 2570 | -1ULL |
| 2571 | } |
| 2572 | #endif |
| 2573 | }, |
| 2574 | { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1, |
| 2575 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2576 | #ifndef DISASM_ONLY |
| 2577 | { |
| 2578 | 0ULL, |
| 2579 | 0xfffff80000000000ULL, |
| 2580 | 0ULL, |
| 2581 | 0ULL, |
| 2582 | 0ULL |
| 2583 | }, |
| 2584 | { |
| 2585 | -1ULL, |
| 2586 | 0x286aa80000000000ULL, |
| 2587 | -1ULL, |
| 2588 | -1ULL, |
| 2589 | -1ULL |
| 2590 | } |
| 2591 | #endif |
| 2592 | }, |
| 2593 | { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2594 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2595 | #ifndef DISASM_ONLY |
| 2596 | { |
| 2597 | 0ULL, |
| 2598 | 0xfff8000000000000ULL, |
| 2599 | 0ULL, |
| 2600 | 0ULL, |
| 2601 | 0ULL |
| 2602 | }, |
| 2603 | { |
| 2604 | -1ULL, |
| 2605 | 0x18a8000000000000ULL, |
| 2606 | -1ULL, |
| 2607 | -1ULL, |
| 2608 | -1ULL |
| 2609 | } |
| 2610 | #endif |
| 2611 | }, |
| 2612 | { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1, |
| 2613 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2614 | #ifndef DISASM_ONLY |
| 2615 | { |
| 2616 | 0ULL, |
| 2617 | 0xfffff80000000000ULL, |
| 2618 | 0ULL, |
| 2619 | 0ULL, |
| 2620 | 0ULL |
| 2621 | }, |
| 2622 | { |
| 2623 | -1ULL, |
| 2624 | 0x286ae00000000000ULL, |
| 2625 | -1ULL, |
| 2626 | -1ULL, |
| 2627 | -1ULL |
| 2628 | } |
| 2629 | #endif |
| 2630 | }, |
| 2631 | { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1, |
| 2632 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2633 | #ifndef DISASM_ONLY |
| 2634 | { |
| 2635 | 0ULL, |
| 2636 | 0xfffff80000000000ULL, |
| 2637 | 0ULL, |
| 2638 | 0ULL, |
| 2639 | 0ULL |
| 2640 | }, |
| 2641 | { |
| 2642 | -1ULL, |
| 2643 | 0x286ab00000000000ULL, |
| 2644 | -1ULL, |
| 2645 | -1ULL, |
| 2646 | -1ULL |
| 2647 | } |
| 2648 | #endif |
| 2649 | }, |
| 2650 | { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2651 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2652 | #ifndef DISASM_ONLY |
| 2653 | { |
| 2654 | 0ULL, |
| 2655 | 0xfff8000000000000ULL, |
| 2656 | 0ULL, |
| 2657 | 0ULL, |
| 2658 | 0ULL |
| 2659 | }, |
| 2660 | { |
| 2661 | -1ULL, |
| 2662 | 0x1868000000000000ULL, |
| 2663 | -1ULL, |
| 2664 | -1ULL, |
| 2665 | -1ULL |
| 2666 | } |
| 2667 | #endif |
| 2668 | }, |
| 2669 | { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1, |
| 2670 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2671 | #ifndef DISASM_ONLY |
| 2672 | { |
| 2673 | 0ULL, |
| 2674 | 0xfffff80000000000ULL, |
| 2675 | 0ULL, |
| 2676 | 0ULL, |
| 2677 | 0ULL |
| 2678 | }, |
| 2679 | { |
| 2680 | -1ULL, |
| 2681 | 0x286ab80000000000ULL, |
| 2682 | -1ULL, |
| 2683 | -1ULL, |
| 2684 | -1ULL |
| 2685 | } |
| 2686 | #endif |
| 2687 | }, |
| 2688 | { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2689 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2690 | #ifndef DISASM_ONLY |
| 2691 | { |
| 2692 | 0ULL, |
| 2693 | 0xfff8000000000000ULL, |
| 2694 | 0ULL, |
| 2695 | 0ULL, |
| 2696 | 0ULL |
| 2697 | }, |
| 2698 | { |
| 2699 | -1ULL, |
| 2700 | 0x1870000000000000ULL, |
| 2701 | -1ULL, |
| 2702 | -1ULL, |
| 2703 | -1ULL |
| 2704 | } |
| 2705 | #endif |
| 2706 | }, |
| 2707 | { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1, |
| 2708 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2709 | #ifndef DISASM_ONLY |
| 2710 | { |
| 2711 | 0ULL, |
| 2712 | 0xfffff80000000000ULL, |
| 2713 | 0ULL, |
| 2714 | 0ULL, |
| 2715 | 0ULL |
| 2716 | }, |
| 2717 | { |
| 2718 | -1ULL, |
| 2719 | 0x286ac00000000000ULL, |
| 2720 | -1ULL, |
| 2721 | -1ULL, |
| 2722 | -1ULL |
| 2723 | } |
| 2724 | #endif |
| 2725 | }, |
| 2726 | { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2727 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2728 | #ifndef DISASM_ONLY |
| 2729 | { |
| 2730 | 0ULL, |
| 2731 | 0xfff8000000000000ULL, |
| 2732 | 0ULL, |
| 2733 | 0ULL, |
| 2734 | 0ULL |
| 2735 | }, |
| 2736 | { |
| 2737 | -1ULL, |
| 2738 | 0x1878000000000000ULL, |
| 2739 | -1ULL, |
| 2740 | -1ULL, |
| 2741 | -1ULL |
| 2742 | } |
| 2743 | #endif |
| 2744 | }, |
| 2745 | { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1, |
| 2746 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2747 | #ifndef DISASM_ONLY |
| 2748 | { |
| 2749 | 0ULL, |
| 2750 | 0xfffff80000000000ULL, |
| 2751 | 0ULL, |
| 2752 | 0ULL, |
| 2753 | 0ULL |
| 2754 | }, |
| 2755 | { |
| 2756 | -1ULL, |
| 2757 | 0x286ac80000000000ULL, |
| 2758 | -1ULL, |
| 2759 | -1ULL, |
| 2760 | -1ULL |
| 2761 | } |
| 2762 | #endif |
| 2763 | }, |
| 2764 | { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2765 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2766 | #ifndef DISASM_ONLY |
| 2767 | { |
| 2768 | 0ULL, |
| 2769 | 0xfff8000000000000ULL, |
| 2770 | 0ULL, |
| 2771 | 0ULL, |
| 2772 | 0ULL |
| 2773 | }, |
| 2774 | { |
| 2775 | -1ULL, |
| 2776 | 0x1880000000000000ULL, |
| 2777 | -1ULL, |
| 2778 | -1ULL, |
| 2779 | -1ULL |
| 2780 | } |
| 2781 | #endif |
| 2782 | }, |
| 2783 | { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1, |
| 2784 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2785 | #ifndef DISASM_ONLY |
| 2786 | { |
| 2787 | 0ULL, |
| 2788 | 0xfffff80000000000ULL, |
| 2789 | 0ULL, |
| 2790 | 0ULL, |
| 2791 | 0ULL |
| 2792 | }, |
| 2793 | { |
| 2794 | -1ULL, |
| 2795 | 0x286ad00000000000ULL, |
| 2796 | -1ULL, |
| 2797 | -1ULL, |
| 2798 | -1ULL |
| 2799 | } |
| 2800 | #endif |
| 2801 | }, |
| 2802 | { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2803 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2804 | #ifndef DISASM_ONLY |
| 2805 | { |
| 2806 | 0ULL, |
| 2807 | 0xfff8000000000000ULL, |
| 2808 | 0ULL, |
| 2809 | 0ULL, |
| 2810 | 0ULL |
| 2811 | }, |
| 2812 | { |
| 2813 | -1ULL, |
| 2814 | 0x1888000000000000ULL, |
| 2815 | -1ULL, |
| 2816 | -1ULL, |
| 2817 | -1ULL |
| 2818 | } |
| 2819 | #endif |
| 2820 | }, |
| 2821 | { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1, |
| 2822 | { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2823 | #ifndef DISASM_ONLY |
| 2824 | { |
| 2825 | 0ULL, |
| 2826 | 0xfffff80000000000ULL, |
| 2827 | 0ULL, |
| 2828 | 0ULL, |
| 2829 | 0ULL |
| 2830 | }, |
| 2831 | { |
| 2832 | -1ULL, |
| 2833 | 0x286ad80000000000ULL, |
| 2834 | -1ULL, |
| 2835 | -1ULL, |
| 2836 | -1ULL |
| 2837 | } |
| 2838 | #endif |
| 2839 | }, |
| 2840 | { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2841 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2842 | #ifndef DISASM_ONLY |
| 2843 | { |
| 2844 | 0ULL, |
| 2845 | 0xfff8000000000000ULL, |
| 2846 | 0ULL, |
| 2847 | 0ULL, |
| 2848 | 0ULL |
| 2849 | }, |
| 2850 | { |
| 2851 | -1ULL, |
| 2852 | 0x1890000000000000ULL, |
| 2853 | -1ULL, |
| 2854 | -1ULL, |
| 2855 | -1ULL |
| 2856 | } |
| 2857 | #endif |
| 2858 | }, |
| 2859 | { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1, |
| 2860 | { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, |
| 2861 | #ifndef DISASM_ONLY |
| 2862 | { |
| 2863 | 0ULL, |
| 2864 | 0xfff8000000000000ULL, |
| 2865 | 0ULL, |
| 2866 | 0ULL, |
| 2867 | 0ULL |
| 2868 | }, |
| 2869 | { |
| 2870 | -1ULL, |
| 2871 | 0x1898000000000000ULL, |
| 2872 | -1ULL, |
| 2873 | -1ULL, |
| 2874 | -1ULL |
| 2875 | } |
| 2876 | #endif |
| 2877 | }, |
| 2878 | { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1, |
| 2879 | { { 0, }, { 6 }, { 0, }, { 12 }, { 0, } }, |
| 2880 | #ifndef DISASM_ONLY |
| 2881 | { |
| 2882 | 0ULL, |
| 2883 | 0xfffff80000000000ULL, |
| 2884 | 0ULL, |
| 2885 | 0x3c07f80000000000ULL, |
| 2886 | 0ULL |
| 2887 | }, |
| 2888 | { |
| 2889 | -1ULL, |
| 2890 | 0x286af00000000000ULL, |
| 2891 | -1ULL, |
| 2892 | 0x1c06700000000000ULL, |
| 2893 | -1ULL |
| 2894 | } |
| 2895 | #endif |
| 2896 | }, |
| 2897 | { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1, |
| 2898 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 2899 | #ifndef DISASM_ONLY |
| 2900 | { |
| 2901 | 0ULL, |
| 2902 | 0xfffff80000000000ULL, |
| 2903 | 0ULL, |
| 2904 | 0ULL, |
| 2905 | 0ULL |
| 2906 | }, |
| 2907 | { |
| 2908 | -1ULL, |
| 2909 | 0x286af80000000000ULL, |
| 2910 | -1ULL, |
| 2911 | -1ULL, |
| 2912 | -1ULL |
| 2913 | } |
| 2914 | #endif |
| 2915 | }, |
| 2916 | { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, |
| 2917 | { { 0, }, { 6, 27 }, { 0, }, { 0, }, { 0, } }, |
| 2918 | #ifndef DISASM_ONLY |
| 2919 | { |
| 2920 | 0ULL, |
| 2921 | 0xfff8000000000000ULL, |
| 2922 | 0ULL, |
| 2923 | 0ULL, |
| 2924 | 0ULL |
| 2925 | }, |
| 2926 | { |
| 2927 | -1ULL, |
| 2928 | 0x18b0000000000000ULL, |
| 2929 | -1ULL, |
| 2930 | -1ULL, |
| 2931 | -1ULL |
| 2932 | } |
| 2933 | #endif |
| 2934 | }, |
| 2935 | { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1, |
| 2936 | { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 2937 | #ifndef DISASM_ONLY |
| 2938 | { |
| 2939 | 0xc00000007f000000ULL, |
| 2940 | 0ULL, |
| 2941 | 0ULL, |
| 2942 | 0ULL, |
| 2943 | 0ULL |
| 2944 | }, |
| 2945 | { |
| 2946 | 0x0000000037000000ULL, |
| 2947 | -1ULL, |
| 2948 | -1ULL, |
| 2949 | -1ULL, |
| 2950 | -1ULL |
| 2951 | } |
| 2952 | #endif |
| 2953 | }, |
| 2954 | { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, |
| 2955 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 2956 | #ifndef DISASM_ONLY |
| 2957 | { |
| 2958 | 0xc00000007ffc0000ULL, |
| 2959 | 0xfffe000000000000ULL, |
| 2960 | 0x00000000780c0000ULL, |
| 2961 | 0x3c06000000000000ULL, |
| 2962 | 0ULL |
| 2963 | }, |
| 2964 | { |
| 2965 | 0x0000000050a00000ULL, |
| 2966 | 0x2834000000000000ULL, |
| 2967 | 0x0000000048080000ULL, |
| 2968 | 0x2804000000000000ULL, |
| 2969 | -1ULL |
| 2970 | } |
| 2971 | #endif |
| 2972 | }, |
| 2973 | { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, |
| 2974 | { { 0, }, { 28, 7 }, { 0, }, { 0, }, { 0, } }, |
| 2975 | #ifndef DISASM_ONLY |
| 2976 | { |
| 2977 | 0ULL, |
| 2978 | 0xfff8000000000000ULL, |
| 2979 | 0ULL, |
| 2980 | 0ULL, |
| 2981 | 0ULL |
| 2982 | }, |
| 2983 | { |
| 2984 | -1ULL, |
| 2985 | 0x18b8000000000000ULL, |
| 2986 | -1ULL, |
| 2987 | -1ULL, |
| 2988 | -1ULL |
| 2989 | } |
| 2990 | #endif |
| 2991 | }, |
| 2992 | { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1, |
| 2993 | { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, |
| 2994 | #ifndef DISASM_ONLY |
| 2995 | { |
| 2996 | 0xc00000007ffc0000ULL, |
| 2997 | 0ULL, |
| 2998 | 0x00000000780c0000ULL, |
| 2999 | 0ULL, |
| 3000 | 0ULL |
| 3001 | }, |
| 3002 | { |
| 3003 | 0x0000000050d40000ULL, |
| 3004 | -1ULL, |
| 3005 | 0x0000000068000000ULL, |
| 3006 | -1ULL, |
| 3007 | -1ULL |
| 3008 | } |
| 3009 | #endif |
| 3010 | }, |
| 3011 | { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1, |
| 3012 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3013 | #ifndef DISASM_ONLY |
| 3014 | { |
| 3015 | 0xc00000007ffc0000ULL, |
| 3016 | 0ULL, |
| 3017 | 0ULL, |
| 3018 | 0ULL, |
| 3019 | 0ULL |
| 3020 | }, |
| 3021 | { |
| 3022 | 0x0000000050d80000ULL, |
| 3023 | -1ULL, |
| 3024 | -1ULL, |
| 3025 | -1ULL, |
| 3026 | -1ULL |
| 3027 | } |
| 3028 | #endif |
| 3029 | }, |
| 3030 | { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1, |
| 3031 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3032 | #ifndef DISASM_ONLY |
| 3033 | { |
| 3034 | 0xc00000007ffc0000ULL, |
| 3035 | 0ULL, |
| 3036 | 0ULL, |
| 3037 | 0ULL, |
| 3038 | 0ULL |
| 3039 | }, |
| 3040 | { |
| 3041 | 0x0000000050dc0000ULL, |
| 3042 | -1ULL, |
| 3043 | -1ULL, |
| 3044 | -1ULL, |
| 3045 | -1ULL |
| 3046 | } |
| 3047 | #endif |
| 3048 | }, |
| 3049 | { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1, |
| 3050 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3051 | #ifndef DISASM_ONLY |
| 3052 | { |
| 3053 | 0xc00000007ffc0000ULL, |
| 3054 | 0ULL, |
| 3055 | 0ULL, |
| 3056 | 0ULL, |
| 3057 | 0ULL |
| 3058 | }, |
| 3059 | { |
| 3060 | 0x0000000050e00000ULL, |
| 3061 | -1ULL, |
| 3062 | -1ULL, |
| 3063 | -1ULL, |
| 3064 | -1ULL |
| 3065 | } |
| 3066 | #endif |
| 3067 | }, |
| 3068 | { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1, |
| 3069 | { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, |
| 3070 | #ifndef DISASM_ONLY |
| 3071 | { |
| 3072 | 0xc00000007ffc0000ULL, |
| 3073 | 0ULL, |
| 3074 | 0x00000000780c0000ULL, |
| 3075 | 0ULL, |
| 3076 | 0ULL |
| 3077 | }, |
| 3078 | { |
| 3079 | 0x0000000050e40000ULL, |
| 3080 | -1ULL, |
| 3081 | 0x0000000068040000ULL, |
| 3082 | -1ULL, |
| 3083 | -1ULL |
| 3084 | } |
| 3085 | #endif |
| 3086 | }, |
| 3087 | { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1, |
| 3088 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3089 | #ifndef DISASM_ONLY |
| 3090 | { |
| 3091 | 0xc00000007ffc0000ULL, |
| 3092 | 0ULL, |
| 3093 | 0ULL, |
| 3094 | 0ULL, |
| 3095 | 0ULL |
| 3096 | }, |
| 3097 | { |
| 3098 | 0x0000000050e80000ULL, |
| 3099 | -1ULL, |
| 3100 | -1ULL, |
| 3101 | -1ULL, |
| 3102 | -1ULL |
| 3103 | } |
| 3104 | #endif |
| 3105 | }, |
| 3106 | { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1, |
| 3107 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3108 | #ifndef DISASM_ONLY |
| 3109 | { |
| 3110 | 0xc00000007ffc0000ULL, |
| 3111 | 0ULL, |
| 3112 | 0ULL, |
| 3113 | 0ULL, |
| 3114 | 0ULL |
| 3115 | }, |
| 3116 | { |
| 3117 | 0x0000000050ec0000ULL, |
| 3118 | -1ULL, |
| 3119 | -1ULL, |
| 3120 | -1ULL, |
| 3121 | -1ULL |
| 3122 | } |
| 3123 | #endif |
| 3124 | }, |
| 3125 | { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1, |
| 3126 | { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, |
| 3127 | #ifndef DISASM_ONLY |
| 3128 | { |
| 3129 | 0xc00000007ffc0000ULL, |
| 3130 | 0ULL, |
| 3131 | 0x00000000780c0000ULL, |
| 3132 | 0ULL, |
| 3133 | 0ULL |
| 3134 | }, |
| 3135 | { |
| 3136 | 0x0000000050f00000ULL, |
| 3137 | -1ULL, |
| 3138 | 0x0000000068080000ULL, |
| 3139 | -1ULL, |
| 3140 | -1ULL |
| 3141 | } |
| 3142 | #endif |
| 3143 | }, |
| 3144 | { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1, |
| 3145 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3146 | #ifndef DISASM_ONLY |
| 3147 | { |
| 3148 | 0xc00000007ffc0000ULL, |
| 3149 | 0ULL, |
| 3150 | 0ULL, |
| 3151 | 0ULL, |
| 3152 | 0ULL |
| 3153 | }, |
| 3154 | { |
| 3155 | 0x0000000050f40000ULL, |
| 3156 | -1ULL, |
| 3157 | -1ULL, |
| 3158 | -1ULL, |
| 3159 | -1ULL |
| 3160 | } |
| 3161 | #endif |
| 3162 | }, |
| 3163 | { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1, |
| 3164 | { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, |
| 3165 | #ifndef DISASM_ONLY |
| 3166 | { |
| 3167 | 0xc00000007ffc0000ULL, |
| 3168 | 0ULL, |
| 3169 | 0x00000000780c0000ULL, |
| 3170 | 0ULL, |
| 3171 | 0ULL |
| 3172 | }, |
| 3173 | { |
| 3174 | 0x0000000050f80000ULL, |
| 3175 | -1ULL, |
| 3176 | 0x00000000680c0000ULL, |
| 3177 | -1ULL, |
| 3178 | -1ULL |
| 3179 | } |
| 3180 | #endif |
| 3181 | }, |
| 3182 | { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1, |
| 3183 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 3184 | #ifndef DISASM_ONLY |
| 3185 | { |
| 3186 | 0xc00000007ffc0000ULL, |
| 3187 | 0ULL, |
| 3188 | 0x00000000780c0000ULL, |
| 3189 | 0ULL, |
| 3190 | 0ULL |
| 3191 | }, |
| 3192 | { |
| 3193 | 0x0000000050a80000ULL, |
| 3194 | -1ULL, |
| 3195 | 0x0000000070000000ULL, |
| 3196 | -1ULL, |
| 3197 | -1ULL |
| 3198 | } |
| 3199 | #endif |
| 3200 | }, |
| 3201 | { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1, |
| 3202 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3203 | #ifndef DISASM_ONLY |
| 3204 | { |
| 3205 | 0xc00000007ffc0000ULL, |
| 3206 | 0ULL, |
| 3207 | 0ULL, |
| 3208 | 0ULL, |
| 3209 | 0ULL |
| 3210 | }, |
| 3211 | { |
| 3212 | 0x0000000050ac0000ULL, |
| 3213 | -1ULL, |
| 3214 | -1ULL, |
| 3215 | -1ULL, |
| 3216 | -1ULL |
| 3217 | } |
| 3218 | #endif |
| 3219 | }, |
| 3220 | { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1, |
| 3221 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3222 | #ifndef DISASM_ONLY |
| 3223 | { |
| 3224 | 0xc00000007ffc0000ULL, |
| 3225 | 0ULL, |
| 3226 | 0ULL, |
| 3227 | 0ULL, |
| 3228 | 0ULL |
| 3229 | }, |
| 3230 | { |
| 3231 | 0x0000000050b00000ULL, |
| 3232 | -1ULL, |
| 3233 | -1ULL, |
| 3234 | -1ULL, |
| 3235 | -1ULL |
| 3236 | } |
| 3237 | #endif |
| 3238 | }, |
| 3239 | { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1, |
| 3240 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3241 | #ifndef DISASM_ONLY |
| 3242 | { |
| 3243 | 0xc00000007ffc0000ULL, |
| 3244 | 0ULL, |
| 3245 | 0ULL, |
| 3246 | 0ULL, |
| 3247 | 0ULL |
| 3248 | }, |
| 3249 | { |
| 3250 | 0x0000000050b40000ULL, |
| 3251 | -1ULL, |
| 3252 | -1ULL, |
| 3253 | -1ULL, |
| 3254 | -1ULL |
| 3255 | } |
| 3256 | #endif |
| 3257 | }, |
| 3258 | { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1, |
| 3259 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 3260 | #ifndef DISASM_ONLY |
| 3261 | { |
| 3262 | 0xc00000007ffc0000ULL, |
| 3263 | 0ULL, |
| 3264 | 0x00000000780c0000ULL, |
| 3265 | 0ULL, |
| 3266 | 0ULL |
| 3267 | }, |
| 3268 | { |
| 3269 | 0x0000000050b80000ULL, |
| 3270 | -1ULL, |
| 3271 | 0x0000000070040000ULL, |
| 3272 | -1ULL, |
| 3273 | -1ULL |
| 3274 | } |
| 3275 | #endif |
| 3276 | }, |
| 3277 | { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1, |
| 3278 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3279 | #ifndef DISASM_ONLY |
| 3280 | { |
| 3281 | 0xc00000007ffc0000ULL, |
| 3282 | 0ULL, |
| 3283 | 0ULL, |
| 3284 | 0ULL, |
| 3285 | 0ULL |
| 3286 | }, |
| 3287 | { |
| 3288 | 0x0000000050bc0000ULL, |
| 3289 | -1ULL, |
| 3290 | -1ULL, |
| 3291 | -1ULL, |
| 3292 | -1ULL |
| 3293 | } |
| 3294 | #endif |
| 3295 | }, |
| 3296 | { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1, |
| 3297 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3298 | #ifndef DISASM_ONLY |
| 3299 | { |
| 3300 | 0xc00000007ffc0000ULL, |
| 3301 | 0ULL, |
| 3302 | 0ULL, |
| 3303 | 0ULL, |
| 3304 | 0ULL |
| 3305 | }, |
| 3306 | { |
| 3307 | 0x0000000050c00000ULL, |
| 3308 | -1ULL, |
| 3309 | -1ULL, |
| 3310 | -1ULL, |
| 3311 | -1ULL |
| 3312 | } |
| 3313 | #endif |
| 3314 | }, |
| 3315 | { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1, |
| 3316 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 3317 | #ifndef DISASM_ONLY |
| 3318 | { |
| 3319 | 0xc00000007ffc0000ULL, |
| 3320 | 0ULL, |
| 3321 | 0x00000000780c0000ULL, |
| 3322 | 0ULL, |
| 3323 | 0ULL |
| 3324 | }, |
| 3325 | { |
| 3326 | 0x0000000050c40000ULL, |
| 3327 | -1ULL, |
| 3328 | 0x0000000070080000ULL, |
| 3329 | -1ULL, |
| 3330 | -1ULL |
| 3331 | } |
| 3332 | #endif |
| 3333 | }, |
| 3334 | { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1, |
| 3335 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3336 | #ifndef DISASM_ONLY |
| 3337 | { |
| 3338 | 0xc00000007ffc0000ULL, |
| 3339 | 0ULL, |
| 3340 | 0ULL, |
| 3341 | 0ULL, |
| 3342 | 0ULL |
| 3343 | }, |
| 3344 | { |
| 3345 | 0x0000000050c80000ULL, |
| 3346 | -1ULL, |
| 3347 | -1ULL, |
| 3348 | -1ULL, |
| 3349 | -1ULL |
| 3350 | } |
| 3351 | #endif |
| 3352 | }, |
| 3353 | { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1, |
| 3354 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 3355 | #ifndef DISASM_ONLY |
| 3356 | { |
| 3357 | 0xc00000007ffc0000ULL, |
| 3358 | 0ULL, |
| 3359 | 0x00000000780c0000ULL, |
| 3360 | 0ULL, |
| 3361 | 0ULL |
| 3362 | }, |
| 3363 | { |
| 3364 | 0x0000000050cc0000ULL, |
| 3365 | -1ULL, |
| 3366 | 0x00000000700c0000ULL, |
| 3367 | -1ULL, |
| 3368 | -1ULL |
| 3369 | } |
| 3370 | #endif |
| 3371 | }, |
| 3372 | { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1, |
| 3373 | { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, |
| 3374 | #ifndef DISASM_ONLY |
| 3375 | { |
| 3376 | 0xc00000007ffc0000ULL, |
| 3377 | 0ULL, |
| 3378 | 0x00000000780c0000ULL, |
| 3379 | 0ULL, |
| 3380 | 0ULL |
| 3381 | }, |
| 3382 | { |
| 3383 | 0x0000000050a40000ULL, |
| 3384 | -1ULL, |
| 3385 | 0x0000000040080000ULL, |
| 3386 | -1ULL, |
| 3387 | -1ULL |
| 3388 | } |
| 3389 | #endif |
| 3390 | }, |
| 3391 | { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1, |
| 3392 | { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, |
| 3393 | #ifndef DISASM_ONLY |
| 3394 | { |
| 3395 | 0xc00000007ffc0000ULL, |
| 3396 | 0ULL, |
| 3397 | 0x00000000780c0000ULL, |
| 3398 | 0ULL, |
| 3399 | 0ULL |
| 3400 | }, |
| 3401 | { |
| 3402 | 0x0000000050d00000ULL, |
| 3403 | -1ULL, |
| 3404 | 0x00000000400c0000ULL, |
| 3405 | -1ULL, |
| 3406 | -1ULL |
| 3407 | } |
| 3408 | #endif |
| 3409 | }, |
| 3410 | { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1, |
| 3411 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3412 | #ifndef DISASM_ONLY |
| 3413 | { |
| 3414 | 0xc00000007ffc0000ULL, |
| 3415 | 0xfffe000000000000ULL, |
| 3416 | 0x00000000780c0000ULL, |
| 3417 | 0x3c06000000000000ULL, |
| 3418 | 0ULL |
| 3419 | }, |
| 3420 | { |
| 3421 | 0x0000000050fc0000ULL, |
| 3422 | 0x2836000000000000ULL, |
| 3423 | 0x00000000480c0000ULL, |
| 3424 | 0x2806000000000000ULL, |
| 3425 | -1ULL |
| 3426 | } |
| 3427 | #endif |
| 3428 | }, |
| 3429 | { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0, |
| 3430 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 3431 | #ifndef DISASM_ONLY |
| 3432 | { |
| 3433 | 0ULL, |
| 3434 | 0xfffff80000000000ULL, |
| 3435 | 0ULL, |
| 3436 | 0ULL, |
| 3437 | 0ULL |
| 3438 | }, |
| 3439 | { |
| 3440 | -1ULL, |
| 3441 | 0x286b000000000000ULL, |
| 3442 | -1ULL, |
| 3443 | -1ULL, |
| 3444 | -1ULL |
| 3445 | } |
| 3446 | #endif |
| 3447 | }, |
| 3448 | { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1, |
| 3449 | { { }, { }, { }, { }, { 0, } }, |
| 3450 | #ifndef DISASM_ONLY |
| 3451 | { |
| 3452 | 0xc00000007ffff000ULL, |
| 3453 | 0xfffff80000000000ULL, |
| 3454 | 0x00000000780ff000ULL, |
| 3455 | 0x3c07f80000000000ULL, |
| 3456 | 0ULL |
| 3457 | }, |
| 3458 | { |
| 3459 | 0x0000000051485000ULL, |
| 3460 | 0x286b080000000000ULL, |
| 3461 | 0x00000000300c5000ULL, |
| 3462 | 0x1c06780000000000ULL, |
| 3463 | -1ULL |
| 3464 | } |
| 3465 | #endif |
| 3466 | }, |
| 3467 | { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1, |
| 3468 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3469 | #ifndef DISASM_ONLY |
| 3470 | { |
| 3471 | 0xc00000007ffc0000ULL, |
| 3472 | 0xfffe000000000000ULL, |
| 3473 | 0x00000000780c0000ULL, |
| 3474 | 0x3c06000000000000ULL, |
| 3475 | 0ULL |
| 3476 | }, |
| 3477 | { |
| 3478 | 0x0000000051000000ULL, |
| 3479 | 0x2838000000000000ULL, |
| 3480 | 0x0000000050040000ULL, |
| 3481 | 0x2c02000000000000ULL, |
| 3482 | -1ULL |
| 3483 | } |
| 3484 | #endif |
| 3485 | }, |
| 3486 | { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1, |
| 3487 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3488 | #ifndef DISASM_ONLY |
| 3489 | { |
| 3490 | 0xc00000007ffc0000ULL, |
| 3491 | 0xfffe000000000000ULL, |
| 3492 | 0x00000000780c0000ULL, |
| 3493 | 0x3c06000000000000ULL, |
| 3494 | 0ULL |
| 3495 | }, |
| 3496 | { |
| 3497 | 0x0000000051040000ULL, |
| 3498 | 0x283a000000000000ULL, |
| 3499 | 0x0000000050080000ULL, |
| 3500 | 0x2c04000000000000ULL, |
| 3501 | -1ULL |
| 3502 | } |
| 3503 | #endif |
| 3504 | }, |
| 3505 | { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1, |
| 3506 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 3507 | #ifndef DISASM_ONLY |
| 3508 | { |
| 3509 | 0xc00000007ff00000ULL, |
| 3510 | 0xfff8000000000000ULL, |
| 3511 | 0ULL, |
| 3512 | 0ULL, |
| 3513 | 0ULL |
| 3514 | }, |
| 3515 | { |
| 3516 | 0x0000000040700000ULL, |
| 3517 | 0x18c0000000000000ULL, |
| 3518 | -1ULL, |
| 3519 | -1ULL, |
| 3520 | -1ULL |
| 3521 | } |
| 3522 | #endif |
| 3523 | }, |
| 3524 | { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, |
| 3525 | { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, |
| 3526 | #ifndef DISASM_ONLY |
| 3527 | { |
| 3528 | 0xc00000007ffff000ULL, |
| 3529 | 0ULL, |
| 3530 | 0x00000000780ff000ULL, |
| 3531 | 0ULL, |
| 3532 | 0ULL |
| 3533 | }, |
| 3534 | { |
| 3535 | 0x0000000051486000ULL, |
| 3536 | -1ULL, |
| 3537 | 0x00000000300c6000ULL, |
| 3538 | -1ULL, |
| 3539 | -1ULL |
| 3540 | } |
| 3541 | #endif |
| 3542 | }, |
| 3543 | { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1, |
| 3544 | { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, |
| 3545 | #ifndef DISASM_ONLY |
| 3546 | { |
| 3547 | 0xc00000007ffff000ULL, |
| 3548 | 0ULL, |
| 3549 | 0x00000000780ff000ULL, |
| 3550 | 0ULL, |
| 3551 | 0ULL |
| 3552 | }, |
| 3553 | { |
| 3554 | 0x0000000051487000ULL, |
| 3555 | -1ULL, |
| 3556 | 0x00000000300c7000ULL, |
| 3557 | -1ULL, |
| 3558 | -1ULL |
| 3559 | } |
| 3560 | #endif |
| 3561 | }, |
| 3562 | { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1, |
| 3563 | { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, |
| 3564 | #ifndef DISASM_ONLY |
| 3565 | { |
| 3566 | 0xc00000007ffff000ULL, |
| 3567 | 0ULL, |
| 3568 | 0x00000000780ff000ULL, |
| 3569 | 0ULL, |
| 3570 | 0ULL |
| 3571 | }, |
| 3572 | { |
| 3573 | 0x0000000051488000ULL, |
| 3574 | -1ULL, |
| 3575 | 0x00000000300c8000ULL, |
| 3576 | -1ULL, |
| 3577 | -1ULL |
| 3578 | } |
| 3579 | #endif |
| 3580 | }, |
| 3581 | { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1, |
| 3582 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3583 | #ifndef DISASM_ONLY |
| 3584 | { |
| 3585 | 0xc00000007ffc0000ULL, |
| 3586 | 0xfffe000000000000ULL, |
| 3587 | 0x00000000780c0000ULL, |
| 3588 | 0x3c06000000000000ULL, |
| 3589 | 0ULL |
| 3590 | }, |
| 3591 | { |
| 3592 | 0x0000000051080000ULL, |
| 3593 | 0x283c000000000000ULL, |
| 3594 | 0x0000000058000000ULL, |
| 3595 | 0x3000000000000000ULL, |
| 3596 | -1ULL |
| 3597 | } |
| 3598 | #endif |
| 3599 | }, |
| 3600 | { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1, |
| 3601 | { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, |
| 3602 | #ifndef DISASM_ONLY |
| 3603 | { |
| 3604 | 0xc00000007ffc0000ULL, |
| 3605 | 0xfffe000000000000ULL, |
| 3606 | 0x00000000780c0000ULL, |
| 3607 | 0x3c06000000000000ULL, |
| 3608 | 0ULL |
| 3609 | }, |
| 3610 | { |
| 3611 | 0x0000000060040000ULL, |
| 3612 | 0x3002000000000000ULL, |
| 3613 | 0x0000000078000000ULL, |
| 3614 | 0x3800000000000000ULL, |
| 3615 | -1ULL |
| 3616 | } |
| 3617 | #endif |
| 3618 | }, |
| 3619 | { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1, |
| 3620 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3621 | #ifndef DISASM_ONLY |
| 3622 | { |
| 3623 | 0xc00000007ffc0000ULL, |
| 3624 | 0xfffe000000000000ULL, |
| 3625 | 0x00000000780c0000ULL, |
| 3626 | 0x3c06000000000000ULL, |
| 3627 | 0ULL |
| 3628 | }, |
| 3629 | { |
| 3630 | 0x0000000051280000ULL, |
| 3631 | 0x284c000000000000ULL, |
| 3632 | 0x0000000058040000ULL, |
| 3633 | 0x3002000000000000ULL, |
| 3634 | -1ULL |
| 3635 | } |
| 3636 | #endif |
| 3637 | }, |
| 3638 | { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1, |
| 3639 | { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } }, |
| 3640 | #ifndef DISASM_ONLY |
| 3641 | { |
| 3642 | 0xc000000070000000ULL, |
| 3643 | 0xf800000000000000ULL, |
| 3644 | 0ULL, |
| 3645 | 0ULL, |
| 3646 | 0ULL |
| 3647 | }, |
| 3648 | { |
| 3649 | 0x0000000070000000ULL, |
| 3650 | 0x3800000000000000ULL, |
| 3651 | -1ULL, |
| 3652 | -1ULL, |
| 3653 | -1ULL |
| 3654 | } |
| 3655 | #endif |
| 3656 | }, |
| 3657 | { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1, |
| 3658 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3659 | #ifndef DISASM_ONLY |
| 3660 | { |
| 3661 | 0xc00000007ffc0000ULL, |
| 3662 | 0xfffe000000000000ULL, |
| 3663 | 0x00000000780c0000ULL, |
| 3664 | 0x3c06000000000000ULL, |
| 3665 | 0ULL |
| 3666 | }, |
| 3667 | { |
| 3668 | 0x0000000051100000ULL, |
| 3669 | 0x2840000000000000ULL, |
| 3670 | 0x0000000030000000ULL, |
| 3671 | 0x1c00000000000000ULL, |
| 3672 | -1ULL |
| 3673 | } |
| 3674 | #endif |
| 3675 | }, |
| 3676 | { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1, |
| 3677 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3678 | #ifndef DISASM_ONLY |
| 3679 | { |
| 3680 | 0xc00000007ffc0000ULL, |
| 3681 | 0xfffe000000000000ULL, |
| 3682 | 0x00000000780c0000ULL, |
| 3683 | 0x3c06000000000000ULL, |
| 3684 | 0ULL |
| 3685 | }, |
| 3686 | { |
| 3687 | 0x00000000510c0000ULL, |
| 3688 | 0x283e000000000000ULL, |
| 3689 | 0x0000000060040000ULL, |
| 3690 | 0x3402000000000000ULL, |
| 3691 | -1ULL |
| 3692 | } |
| 3693 | #endif |
| 3694 | }, |
| 3695 | { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1, |
| 3696 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3697 | #ifndef DISASM_ONLY |
| 3698 | { |
| 3699 | 0xc00000007ffc0000ULL, |
| 3700 | 0xfffe000000000000ULL, |
| 3701 | 0x00000000780c0000ULL, |
| 3702 | 0x3c06000000000000ULL, |
| 3703 | 0ULL |
| 3704 | }, |
| 3705 | { |
| 3706 | 0x0000000051180000ULL, |
| 3707 | 0x2844000000000000ULL, |
| 3708 | 0x0000000030040000ULL, |
| 3709 | 0x1c02000000000000ULL, |
| 3710 | -1ULL |
| 3711 | } |
| 3712 | #endif |
| 3713 | }, |
| 3714 | { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1, |
| 3715 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3716 | #ifndef DISASM_ONLY |
| 3717 | { |
| 3718 | 0xc00000007ffc0000ULL, |
| 3719 | 0xfffe000000000000ULL, |
| 3720 | 0x00000000780c0000ULL, |
| 3721 | 0x3c06000000000000ULL, |
| 3722 | 0ULL |
| 3723 | }, |
| 3724 | { |
| 3725 | 0x0000000051140000ULL, |
| 3726 | 0x2842000000000000ULL, |
| 3727 | 0x0000000060080000ULL, |
| 3728 | 0x3404000000000000ULL, |
| 3729 | -1ULL |
| 3730 | } |
| 3731 | #endif |
| 3732 | }, |
| 3733 | { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1, |
| 3734 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3735 | #ifndef DISASM_ONLY |
| 3736 | { |
| 3737 | 0xc00000007ffc0000ULL, |
| 3738 | 0xfffe000000000000ULL, |
| 3739 | 0x00000000780c0000ULL, |
| 3740 | 0x3c06000000000000ULL, |
| 3741 | 0ULL |
| 3742 | }, |
| 3743 | { |
| 3744 | 0x0000000051200000ULL, |
| 3745 | 0x2848000000000000ULL, |
| 3746 | 0x0000000030080000ULL, |
| 3747 | 0x1c04000000000000ULL, |
| 3748 | -1ULL |
| 3749 | } |
| 3750 | #endif |
| 3751 | }, |
| 3752 | { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1, |
| 3753 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3754 | #ifndef DISASM_ONLY |
| 3755 | { |
| 3756 | 0xc00000007ffc0000ULL, |
| 3757 | 0xfffe000000000000ULL, |
| 3758 | 0x00000000780c0000ULL, |
| 3759 | 0x3c06000000000000ULL, |
| 3760 | 0ULL |
| 3761 | }, |
| 3762 | { |
| 3763 | 0x00000000511c0000ULL, |
| 3764 | 0x2846000000000000ULL, |
| 3765 | 0x00000000600c0000ULL, |
| 3766 | 0x3406000000000000ULL, |
| 3767 | -1ULL |
| 3768 | } |
| 3769 | #endif |
| 3770 | }, |
| 3771 | { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, |
| 3772 | { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, |
| 3773 | #ifndef DISASM_ONLY |
| 3774 | { |
| 3775 | 0xc00000007ffc0000ULL, |
| 3776 | 0xfffe000000000000ULL, |
| 3777 | 0x00000000780c0000ULL, |
| 3778 | 0x3c06000000000000ULL, |
| 3779 | 0ULL |
| 3780 | }, |
| 3781 | { |
| 3782 | 0x0000000060080000ULL, |
| 3783 | 0x3004000000000000ULL, |
| 3784 | 0x0000000078040000ULL, |
| 3785 | 0x3802000000000000ULL, |
| 3786 | -1ULL |
| 3787 | } |
| 3788 | #endif |
| 3789 | }, |
| 3790 | { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1, |
| 3791 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 3792 | #ifndef DISASM_ONLY |
| 3793 | { |
| 3794 | 0xc00000007ffc0000ULL, |
| 3795 | 0xfffe000000000000ULL, |
| 3796 | 0ULL, |
| 3797 | 0ULL, |
| 3798 | 0ULL |
| 3799 | }, |
| 3800 | { |
| 3801 | 0x0000000051240000ULL, |
| 3802 | 0x284a000000000000ULL, |
| 3803 | -1ULL, |
| 3804 | -1ULL, |
| 3805 | -1ULL |
| 3806 | } |
| 3807 | #endif |
| 3808 | }, |
| 3809 | { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1, |
| 3810 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 3811 | #ifndef DISASM_ONLY |
| 3812 | { |
| 3813 | 0xc00000007ffc0000ULL, |
| 3814 | 0xfffe000000000000ULL, |
| 3815 | 0ULL, |
| 3816 | 0ULL, |
| 3817 | 0ULL |
| 3818 | }, |
| 3819 | { |
| 3820 | 0x00000000600c0000ULL, |
| 3821 | 0x3006000000000000ULL, |
| 3822 | -1ULL, |
| 3823 | -1ULL, |
| 3824 | -1ULL |
| 3825 | } |
| 3826 | #endif |
| 3827 | }, |
| 3828 | { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1, |
| 3829 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3830 | #ifndef DISASM_ONLY |
| 3831 | { |
| 3832 | 0xc00000007ffc0000ULL, |
| 3833 | 0xfffe000000000000ULL, |
| 3834 | 0x00000000780c0000ULL, |
| 3835 | 0x3c06000000000000ULL, |
| 3836 | 0ULL |
| 3837 | }, |
| 3838 | { |
| 3839 | 0x00000000512c0000ULL, |
| 3840 | 0x284e000000000000ULL, |
| 3841 | 0x0000000058080000ULL, |
| 3842 | 0x3004000000000000ULL, |
| 3843 | -1ULL |
| 3844 | } |
| 3845 | #endif |
| 3846 | }, |
| 3847 | { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1, |
| 3848 | { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, |
| 3849 | #ifndef DISASM_ONLY |
| 3850 | { |
| 3851 | 0xc00000007ffc0000ULL, |
| 3852 | 0xfffe000000000000ULL, |
| 3853 | 0x00000000780c0000ULL, |
| 3854 | 0x3c06000000000000ULL, |
| 3855 | 0ULL |
| 3856 | }, |
| 3857 | { |
| 3858 | 0x0000000060100000ULL, |
| 3859 | 0x3008000000000000ULL, |
| 3860 | 0x0000000078080000ULL, |
| 3861 | 0x3804000000000000ULL, |
| 3862 | -1ULL |
| 3863 | } |
| 3864 | #endif |
| 3865 | }, |
| 3866 | { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1, |
| 3867 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 3868 | #ifndef DISASM_ONLY |
| 3869 | { |
| 3870 | 0xc00000007ffc0000ULL, |
| 3871 | 0xfffe000000000000ULL, |
| 3872 | 0x00000000780c0000ULL, |
| 3873 | 0x3c06000000000000ULL, |
| 3874 | 0ULL |
| 3875 | }, |
| 3876 | { |
| 3877 | 0x0000000051340000ULL, |
| 3878 | 0x2852000000000000ULL, |
| 3879 | 0x00000000580c0000ULL, |
| 3880 | 0x3006000000000000ULL, |
| 3881 | -1ULL |
| 3882 | } |
| 3883 | #endif |
| 3884 | }, |
| 3885 | { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1, |
| 3886 | { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, |
| 3887 | #ifndef DISASM_ONLY |
| 3888 | { |
| 3889 | 0xc00000007ffc0000ULL, |
| 3890 | 0xfffe000000000000ULL, |
| 3891 | 0x00000000780c0000ULL, |
| 3892 | 0x3c06000000000000ULL, |
| 3893 | 0ULL |
| 3894 | }, |
| 3895 | { |
| 3896 | 0x0000000060140000ULL, |
| 3897 | 0x300a000000000000ULL, |
| 3898 | 0x00000000780c0000ULL, |
| 3899 | 0x3806000000000000ULL, |
| 3900 | -1ULL |
| 3901 | } |
| 3902 | #endif |
| 3903 | }, |
| 3904 | { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1, |
| 3905 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 3906 | #ifndef DISASM_ONLY |
| 3907 | { |
| 3908 | 0xc00000007ffc0000ULL, |
| 3909 | 0xfffe000000000000ULL, |
| 3910 | 0ULL, |
| 3911 | 0ULL, |
| 3912 | 0ULL |
| 3913 | }, |
| 3914 | { |
| 3915 | 0x0000000051300000ULL, |
| 3916 | 0x2850000000000000ULL, |
| 3917 | -1ULL, |
| 3918 | -1ULL, |
| 3919 | -1ULL |
| 3920 | } |
| 3921 | #endif |
| 3922 | }, |
| 3923 | { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1, |
| 3924 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 3925 | #ifndef DISASM_ONLY |
| 3926 | { |
| 3927 | 0xc00000007ffc0000ULL, |
| 3928 | 0xfffe000000000000ULL, |
| 3929 | 0ULL, |
| 3930 | 0ULL, |
| 3931 | 0ULL |
| 3932 | }, |
| 3933 | { |
| 3934 | 0x0000000060180000ULL, |
| 3935 | 0x300c000000000000ULL, |
| 3936 | -1ULL, |
| 3937 | -1ULL, |
| 3938 | -1ULL |
| 3939 | } |
| 3940 | #endif |
| 3941 | }, |
| 3942 | { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1, |
| 3943 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 3944 | #ifndef DISASM_ONLY |
| 3945 | { |
| 3946 | 0xc00000007ffc0000ULL, |
| 3947 | 0ULL, |
| 3948 | 0ULL, |
| 3949 | 0ULL, |
| 3950 | 0ULL |
| 3951 | }, |
| 3952 | { |
| 3953 | 0x0000000051380000ULL, |
| 3954 | -1ULL, |
| 3955 | -1ULL, |
| 3956 | -1ULL, |
| 3957 | -1ULL |
| 3958 | } |
| 3959 | #endif |
| 3960 | }, |
| 3961 | { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1, |
| 3962 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, |
| 3963 | #ifndef DISASM_ONLY |
| 3964 | { |
| 3965 | 0ULL, |
| 3966 | 0xfffe000000000000ULL, |
| 3967 | 0ULL, |
| 3968 | 0ULL, |
| 3969 | 0xc200000004000000ULL |
| 3970 | }, |
| 3971 | { |
| 3972 | -1ULL, |
| 3973 | 0x2862000000000000ULL, |
| 3974 | -1ULL, |
| 3975 | -1ULL, |
| 3976 | 0xc200000004000000ULL |
| 3977 | } |
| 3978 | #endif |
| 3979 | }, |
| 3980 | { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1, |
| 3981 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, |
| 3982 | #ifndef DISASM_ONLY |
| 3983 | { |
| 3984 | 0ULL, |
| 3985 | 0xfffe000000000000ULL, |
| 3986 | 0ULL, |
| 3987 | 0ULL, |
| 3988 | 0xc200000004000000ULL |
| 3989 | }, |
| 3990 | { |
| 3991 | -1ULL, |
| 3992 | 0x2854000000000000ULL, |
| 3993 | -1ULL, |
| 3994 | -1ULL, |
| 3995 | 0xc000000000000000ULL |
| 3996 | } |
| 3997 | #endif |
| 3998 | }, |
| 3999 | { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4000 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4001 | #ifndef DISASM_ONLY |
| 4002 | { |
| 4003 | 0ULL, |
| 4004 | 0xfff8000000000000ULL, |
| 4005 | 0ULL, |
| 4006 | 0ULL, |
| 4007 | 0ULL |
| 4008 | }, |
| 4009 | { |
| 4010 | -1ULL, |
| 4011 | 0x18c8000000000000ULL, |
| 4012 | -1ULL, |
| 4013 | -1ULL, |
| 4014 | -1ULL |
| 4015 | } |
| 4016 | #endif |
| 4017 | }, |
| 4018 | { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1, |
| 4019 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, |
| 4020 | #ifndef DISASM_ONLY |
| 4021 | { |
| 4022 | 0ULL, |
| 4023 | 0xfffe000000000000ULL, |
| 4024 | 0ULL, |
| 4025 | 0ULL, |
| 4026 | 0xc200000004000000ULL |
| 4027 | }, |
| 4028 | { |
| 4029 | -1ULL, |
| 4030 | 0x2856000000000000ULL, |
| 4031 | -1ULL, |
| 4032 | -1ULL, |
| 4033 | 0xc000000004000000ULL |
| 4034 | } |
| 4035 | #endif |
| 4036 | }, |
| 4037 | { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4038 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4039 | #ifndef DISASM_ONLY |
| 4040 | { |
| 4041 | 0ULL, |
| 4042 | 0xfff8000000000000ULL, |
| 4043 | 0ULL, |
| 4044 | 0ULL, |
| 4045 | 0ULL |
| 4046 | }, |
| 4047 | { |
| 4048 | -1ULL, |
| 4049 | 0x18d0000000000000ULL, |
| 4050 | -1ULL, |
| 4051 | -1ULL, |
| 4052 | -1ULL |
| 4053 | } |
| 4054 | #endif |
| 4055 | }, |
| 4056 | { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1, |
| 4057 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, |
| 4058 | #ifndef DISASM_ONLY |
| 4059 | { |
| 4060 | 0ULL, |
| 4061 | 0xfffe000000000000ULL, |
| 4062 | 0ULL, |
| 4063 | 0ULL, |
| 4064 | 0xc200000004000000ULL |
| 4065 | }, |
| 4066 | { |
| 4067 | -1ULL, |
| 4068 | 0x2858000000000000ULL, |
| 4069 | -1ULL, |
| 4070 | -1ULL, |
| 4071 | 0xc200000000000000ULL |
| 4072 | } |
| 4073 | #endif |
| 4074 | }, |
| 4075 | { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4076 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4077 | #ifndef DISASM_ONLY |
| 4078 | { |
| 4079 | 0ULL, |
| 4080 | 0xfff8000000000000ULL, |
| 4081 | 0ULL, |
| 4082 | 0ULL, |
| 4083 | 0ULL |
| 4084 | }, |
| 4085 | { |
| 4086 | -1ULL, |
| 4087 | 0x18d8000000000000ULL, |
| 4088 | -1ULL, |
| 4089 | -1ULL, |
| 4090 | -1ULL |
| 4091 | } |
| 4092 | #endif |
| 4093 | }, |
| 4094 | { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4095 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4096 | #ifndef DISASM_ONLY |
| 4097 | { |
| 4098 | 0ULL, |
| 4099 | 0xfff8000000000000ULL, |
| 4100 | 0ULL, |
| 4101 | 0ULL, |
| 4102 | 0ULL |
| 4103 | }, |
| 4104 | { |
| 4105 | -1ULL, |
| 4106 | 0x1900000000000000ULL, |
| 4107 | -1ULL, |
| 4108 | -1ULL, |
| 4109 | -1ULL |
| 4110 | } |
| 4111 | #endif |
| 4112 | }, |
| 4113 | { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1, |
| 4114 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4115 | #ifndef DISASM_ONLY |
| 4116 | { |
| 4117 | 0ULL, |
| 4118 | 0xfffe000000000000ULL, |
| 4119 | 0ULL, |
| 4120 | 0ULL, |
| 4121 | 0ULL |
| 4122 | }, |
| 4123 | { |
| 4124 | -1ULL, |
| 4125 | 0x2860000000000000ULL, |
| 4126 | -1ULL, |
| 4127 | -1ULL, |
| 4128 | -1ULL |
| 4129 | } |
| 4130 | #endif |
| 4131 | }, |
| 4132 | { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1, |
| 4133 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4134 | #ifndef DISASM_ONLY |
| 4135 | { |
| 4136 | 0ULL, |
| 4137 | 0xfffe000000000000ULL, |
| 4138 | 0ULL, |
| 4139 | 0ULL, |
| 4140 | 0ULL |
| 4141 | }, |
| 4142 | { |
| 4143 | -1ULL, |
| 4144 | 0x285a000000000000ULL, |
| 4145 | -1ULL, |
| 4146 | -1ULL, |
| 4147 | -1ULL |
| 4148 | } |
| 4149 | #endif |
| 4150 | }, |
| 4151 | { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4152 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4153 | #ifndef DISASM_ONLY |
| 4154 | { |
| 4155 | 0ULL, |
| 4156 | 0xfff8000000000000ULL, |
| 4157 | 0ULL, |
| 4158 | 0ULL, |
| 4159 | 0ULL |
| 4160 | }, |
| 4161 | { |
| 4162 | -1ULL, |
| 4163 | 0x18e0000000000000ULL, |
| 4164 | -1ULL, |
| 4165 | -1ULL, |
| 4166 | -1ULL |
| 4167 | } |
| 4168 | #endif |
| 4169 | }, |
| 4170 | { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1, |
| 4171 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4172 | #ifndef DISASM_ONLY |
| 4173 | { |
| 4174 | 0ULL, |
| 4175 | 0xfffe000000000000ULL, |
| 4176 | 0ULL, |
| 4177 | 0ULL, |
| 4178 | 0ULL |
| 4179 | }, |
| 4180 | { |
| 4181 | -1ULL, |
| 4182 | 0x285c000000000000ULL, |
| 4183 | -1ULL, |
| 4184 | -1ULL, |
| 4185 | -1ULL |
| 4186 | } |
| 4187 | #endif |
| 4188 | }, |
| 4189 | { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4190 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4191 | #ifndef DISASM_ONLY |
| 4192 | { |
| 4193 | 0ULL, |
| 4194 | 0xfff8000000000000ULL, |
| 4195 | 0ULL, |
| 4196 | 0ULL, |
| 4197 | 0ULL |
| 4198 | }, |
| 4199 | { |
| 4200 | -1ULL, |
| 4201 | 0x18e8000000000000ULL, |
| 4202 | -1ULL, |
| 4203 | -1ULL, |
| 4204 | -1ULL |
| 4205 | } |
| 4206 | #endif |
| 4207 | }, |
| 4208 | { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1, |
| 4209 | { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4210 | #ifndef DISASM_ONLY |
| 4211 | { |
| 4212 | 0ULL, |
| 4213 | 0xfffe000000000000ULL, |
| 4214 | 0ULL, |
| 4215 | 0ULL, |
| 4216 | 0ULL |
| 4217 | }, |
| 4218 | { |
| 4219 | -1ULL, |
| 4220 | 0x285e000000000000ULL, |
| 4221 | -1ULL, |
| 4222 | -1ULL, |
| 4223 | -1ULL |
| 4224 | } |
| 4225 | #endif |
| 4226 | }, |
| 4227 | { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4228 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4229 | #ifndef DISASM_ONLY |
| 4230 | { |
| 4231 | 0ULL, |
| 4232 | 0xfff8000000000000ULL, |
| 4233 | 0ULL, |
| 4234 | 0ULL, |
| 4235 | 0ULL |
| 4236 | }, |
| 4237 | { |
| 4238 | -1ULL, |
| 4239 | 0x18f0000000000000ULL, |
| 4240 | -1ULL, |
| 4241 | -1ULL, |
| 4242 | -1ULL |
| 4243 | } |
| 4244 | #endif |
| 4245 | }, |
| 4246 | { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1, |
| 4247 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, |
| 4248 | #ifndef DISASM_ONLY |
| 4249 | { |
| 4250 | 0ULL, |
| 4251 | 0xfff8000000000000ULL, |
| 4252 | 0ULL, |
| 4253 | 0ULL, |
| 4254 | 0ULL |
| 4255 | }, |
| 4256 | { |
| 4257 | -1ULL, |
| 4258 | 0x18f8000000000000ULL, |
| 4259 | -1ULL, |
| 4260 | -1ULL, |
| 4261 | -1ULL |
| 4262 | } |
| 4263 | #endif |
| 4264 | }, |
| 4265 | { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1, |
| 4266 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 4267 | #ifndef DISASM_ONLY |
| 4268 | { |
| 4269 | 0xc00000007ffc0000ULL, |
| 4270 | 0xfffe000000000000ULL, |
| 4271 | 0x00000000780c0000ULL, |
| 4272 | 0x3c06000000000000ULL, |
| 4273 | 0ULL |
| 4274 | }, |
| 4275 | { |
| 4276 | 0x0000000051440000ULL, |
| 4277 | 0x2868000000000000ULL, |
| 4278 | 0x00000000280c0000ULL, |
| 4279 | 0x1806000000000000ULL, |
| 4280 | -1ULL |
| 4281 | } |
| 4282 | #endif |
| 4283 | }, |
| 4284 | { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1, |
| 4285 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 4286 | #ifndef DISASM_ONLY |
| 4287 | { |
| 4288 | 0xc00000007ffc0000ULL, |
| 4289 | 0xfffe000000000000ULL, |
| 4290 | 0x00000000780c0000ULL, |
| 4291 | 0x3c06000000000000ULL, |
| 4292 | 0ULL |
| 4293 | }, |
| 4294 | { |
| 4295 | 0x0000000051400000ULL, |
| 4296 | 0x2866000000000000ULL, |
| 4297 | 0x0000000028080000ULL, |
| 4298 | 0x1804000000000000ULL, |
| 4299 | -1ULL |
| 4300 | } |
| 4301 | #endif |
| 4302 | }, |
| 4303 | { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1, |
| 4304 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4305 | #ifndef DISASM_ONLY |
| 4306 | { |
| 4307 | 0xc00000007ffc0000ULL, |
| 4308 | 0xfffe000000000000ULL, |
| 4309 | 0ULL, |
| 4310 | 0ULL, |
| 4311 | 0ULL |
| 4312 | }, |
| 4313 | { |
| 4314 | 0x00000000513c0000ULL, |
| 4315 | 0x2864000000000000ULL, |
| 4316 | -1ULL, |
| 4317 | -1ULL, |
| 4318 | -1ULL |
| 4319 | } |
| 4320 | #endif |
| 4321 | }, |
| 4322 | { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, |
| 4323 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 4324 | #ifndef DISASM_ONLY |
| 4325 | { |
| 4326 | 0ULL, |
| 4327 | 0xfffff80000000000ULL, |
| 4328 | 0ULL, |
| 4329 | 0ULL, |
| 4330 | 0ULL |
| 4331 | }, |
| 4332 | { |
| 4333 | -1ULL, |
| 4334 | 0x286b100000000000ULL, |
| 4335 | -1ULL, |
| 4336 | -1ULL, |
| 4337 | -1ULL |
| 4338 | } |
| 4339 | #endif |
| 4340 | }, |
| 4341 | { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, |
| 4342 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 4343 | #ifndef DISASM_ONLY |
| 4344 | { |
| 4345 | 0ULL, |
| 4346 | 0xfffff80000000000ULL, |
| 4347 | 0ULL, |
| 4348 | 0ULL, |
| 4349 | 0ULL |
| 4350 | }, |
| 4351 | { |
| 4352 | -1ULL, |
| 4353 | 0x286b180000000000ULL, |
| 4354 | -1ULL, |
| 4355 | -1ULL, |
| 4356 | -1ULL |
| 4357 | } |
| 4358 | #endif |
| 4359 | }, |
| 4360 | { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, |
| 4361 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 4362 | #ifndef DISASM_ONLY |
| 4363 | { |
| 4364 | 0ULL, |
| 4365 | 0xfffff80000000000ULL, |
| 4366 | 0ULL, |
| 4367 | 0ULL, |
| 4368 | 0ULL |
| 4369 | }, |
| 4370 | { |
| 4371 | -1ULL, |
| 4372 | 0x286b200000000000ULL, |
| 4373 | -1ULL, |
| 4374 | -1ULL, |
| 4375 | -1ULL |
| 4376 | } |
| 4377 | #endif |
| 4378 | }, |
| 4379 | { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, |
| 4380 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
| 4381 | #ifndef DISASM_ONLY |
| 4382 | { |
| 4383 | 0ULL, |
| 4384 | 0xfffff80000000000ULL, |
| 4385 | 0ULL, |
| 4386 | 0ULL, |
| 4387 | 0ULL |
| 4388 | }, |
| 4389 | { |
| 4390 | -1ULL, |
| 4391 | 0x286b280000000000ULL, |
| 4392 | -1ULL, |
| 4393 | -1ULL, |
| 4394 | -1ULL |
| 4395 | } |
| 4396 | #endif |
| 4397 | }, |
| 4398 | { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, |
| 4399 | { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, |
| 4400 | #ifndef DISASM_ONLY |
| 4401 | { |
| 4402 | 0xc00000007ffff000ULL, |
| 4403 | 0ULL, |
| 4404 | 0x00000000780ff000ULL, |
| 4405 | 0ULL, |
| 4406 | 0ULL |
| 4407 | }, |
| 4408 | { |
| 4409 | 0x0000000051489000ULL, |
| 4410 | -1ULL, |
| 4411 | 0x00000000300c9000ULL, |
| 4412 | -1ULL, |
| 4413 | -1ULL |
| 4414 | } |
| 4415 | #endif |
| 4416 | }, |
| 4417 | { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, |
| 4418 | { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, |
| 4419 | #ifndef DISASM_ONLY |
| 4420 | { |
| 4421 | 0xc00000007ffff000ULL, |
| 4422 | 0ULL, |
| 4423 | 0x00000000780ff000ULL, |
| 4424 | 0ULL, |
| 4425 | 0ULL |
| 4426 | }, |
| 4427 | { |
| 4428 | 0x000000005148a000ULL, |
| 4429 | -1ULL, |
| 4430 | 0x00000000300ca000ULL, |
| 4431 | -1ULL, |
| 4432 | -1ULL |
| 4433 | } |
| 4434 | #endif |
| 4435 | }, |
| 4436 | { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, |
| 4437 | { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, |
| 4438 | #ifndef DISASM_ONLY |
| 4439 | { |
| 4440 | 0xc00000007ffff000ULL, |
| 4441 | 0ULL, |
| 4442 | 0x00000000780ff000ULL, |
| 4443 | 0ULL, |
| 4444 | 0ULL |
| 4445 | }, |
| 4446 | { |
| 4447 | 0x000000005148b000ULL, |
| 4448 | -1ULL, |
| 4449 | 0x00000000300cb000ULL, |
| 4450 | -1ULL, |
| 4451 | -1ULL |
| 4452 | } |
| 4453 | #endif |
| 4454 | }, |
| 4455 | { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, |
| 4456 | { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, |
| 4457 | #ifndef DISASM_ONLY |
| 4458 | { |
| 4459 | 0xc00000007ffff000ULL, |
| 4460 | 0ULL, |
| 4461 | 0x00000000780ff000ULL, |
| 4462 | 0ULL, |
| 4463 | 0ULL |
| 4464 | }, |
| 4465 | { |
| 4466 | 0x000000005148c000ULL, |
| 4467 | -1ULL, |
| 4468 | 0x00000000300cc000ULL, |
| 4469 | -1ULL, |
| 4470 | -1ULL |
| 4471 | } |
| 4472 | #endif |
| 4473 | }, |
| 4474 | { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1, |
| 4475 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4476 | #ifndef DISASM_ONLY |
| 4477 | { |
| 4478 | 0xc00000007ffc0000ULL, |
| 4479 | 0xfffe000000000000ULL, |
| 4480 | 0ULL, |
| 4481 | 0ULL, |
| 4482 | 0ULL |
| 4483 | }, |
| 4484 | { |
| 4485 | 0x0000000051500000ULL, |
| 4486 | 0x286e000000000000ULL, |
| 4487 | -1ULL, |
| 4488 | -1ULL, |
| 4489 | -1ULL |
| 4490 | } |
| 4491 | #endif |
| 4492 | }, |
| 4493 | { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1, |
| 4494 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 4495 | #ifndef DISASM_ONLY |
| 4496 | { |
| 4497 | 0xc00000007ff00000ULL, |
| 4498 | 0xfff8000000000000ULL, |
| 4499 | 0ULL, |
| 4500 | 0ULL, |
| 4501 | 0ULL |
| 4502 | }, |
| 4503 | { |
| 4504 | 0x0000000040800000ULL, |
| 4505 | 0x1908000000000000ULL, |
| 4506 | -1ULL, |
| 4507 | -1ULL, |
| 4508 | -1ULL |
| 4509 | } |
| 4510 | #endif |
| 4511 | }, |
| 4512 | { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1, |
| 4513 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4514 | #ifndef DISASM_ONLY |
| 4515 | { |
| 4516 | 0xc00000007ffc0000ULL, |
| 4517 | 0xfffe000000000000ULL, |
| 4518 | 0ULL, |
| 4519 | 0ULL, |
| 4520 | 0ULL |
| 4521 | }, |
| 4522 | { |
| 4523 | 0x00000000514c0000ULL, |
| 4524 | 0x286c000000000000ULL, |
| 4525 | -1ULL, |
| 4526 | -1ULL, |
| 4527 | -1ULL |
| 4528 | } |
| 4529 | #endif |
| 4530 | }, |
| 4531 | { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1, |
| 4532 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4533 | #ifndef DISASM_ONLY |
| 4534 | { |
| 4535 | 0xc00000007ffc0000ULL, |
| 4536 | 0ULL, |
| 4537 | 0ULL, |
| 4538 | 0ULL, |
| 4539 | 0ULL |
| 4540 | }, |
| 4541 | { |
| 4542 | 0x0000000051540000ULL, |
| 4543 | -1ULL, |
| 4544 | -1ULL, |
| 4545 | -1ULL, |
| 4546 | -1ULL |
| 4547 | } |
| 4548 | #endif |
| 4549 | }, |
| 4550 | { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1, |
| 4551 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4552 | #ifndef DISASM_ONLY |
| 4553 | { |
| 4554 | 0xc00000007ffc0000ULL, |
| 4555 | 0ULL, |
| 4556 | 0ULL, |
| 4557 | 0ULL, |
| 4558 | 0ULL |
| 4559 | }, |
| 4560 | { |
| 4561 | 0x0000000051580000ULL, |
| 4562 | -1ULL, |
| 4563 | -1ULL, |
| 4564 | -1ULL, |
| 4565 | -1ULL |
| 4566 | } |
| 4567 | #endif |
| 4568 | }, |
| 4569 | { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1, |
| 4570 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4571 | #ifndef DISASM_ONLY |
| 4572 | { |
| 4573 | 0xc00000007ffc0000ULL, |
| 4574 | 0xfffe000000000000ULL, |
| 4575 | 0ULL, |
| 4576 | 0ULL, |
| 4577 | 0ULL |
| 4578 | }, |
| 4579 | { |
| 4580 | 0x00000000515c0000ULL, |
| 4581 | 0x2870000000000000ULL, |
| 4582 | -1ULL, |
| 4583 | -1ULL, |
| 4584 | -1ULL |
| 4585 | } |
| 4586 | #endif |
| 4587 | }, |
| 4588 | { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1, |
| 4589 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 4590 | #ifndef DISASM_ONLY |
| 4591 | { |
| 4592 | 0xc00000007ff00000ULL, |
| 4593 | 0xfff8000000000000ULL, |
| 4594 | 0ULL, |
| 4595 | 0ULL, |
| 4596 | 0ULL |
| 4597 | }, |
| 4598 | { |
| 4599 | 0x0000000040900000ULL, |
| 4600 | 0x1910000000000000ULL, |
| 4601 | -1ULL, |
| 4602 | -1ULL, |
| 4603 | -1ULL |
| 4604 | } |
| 4605 | #endif |
| 4606 | }, |
| 4607 | { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1, |
| 4608 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4609 | #ifndef DISASM_ONLY |
| 4610 | { |
| 4611 | 0xc00000007ffc0000ULL, |
| 4612 | 0xfffe000000000000ULL, |
| 4613 | 0ULL, |
| 4614 | 0ULL, |
| 4615 | 0ULL |
| 4616 | }, |
| 4617 | { |
| 4618 | 0x0000000051600000ULL, |
| 4619 | 0x2872000000000000ULL, |
| 4620 | -1ULL, |
| 4621 | -1ULL, |
| 4622 | -1ULL |
| 4623 | } |
| 4624 | #endif |
| 4625 | }, |
| 4626 | { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1, |
| 4627 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4628 | #ifndef DISASM_ONLY |
| 4629 | { |
| 4630 | 0xc00000007ffc0000ULL, |
| 4631 | 0xfffe000000000000ULL, |
| 4632 | 0ULL, |
| 4633 | 0ULL, |
| 4634 | 0ULL |
| 4635 | }, |
| 4636 | { |
| 4637 | 0x0000000051640000ULL, |
| 4638 | 0x2874000000000000ULL, |
| 4639 | -1ULL, |
| 4640 | -1ULL, |
| 4641 | -1ULL |
| 4642 | } |
| 4643 | #endif |
| 4644 | }, |
| 4645 | { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1, |
| 4646 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4647 | #ifndef DISASM_ONLY |
| 4648 | { |
| 4649 | 0xc00000007ffc0000ULL, |
| 4650 | 0xfffe000000000000ULL, |
| 4651 | 0ULL, |
| 4652 | 0ULL, |
| 4653 | 0ULL |
| 4654 | }, |
| 4655 | { |
| 4656 | 0x0000000051680000ULL, |
| 4657 | 0x2876000000000000ULL, |
| 4658 | -1ULL, |
| 4659 | -1ULL, |
| 4660 | -1ULL |
| 4661 | } |
| 4662 | #endif |
| 4663 | }, |
| 4664 | { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1, |
| 4665 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 4666 | #ifndef DISASM_ONLY |
| 4667 | { |
| 4668 | 0xc00000007ff00000ULL, |
| 4669 | 0xfff8000000000000ULL, |
| 4670 | 0ULL, |
| 4671 | 0ULL, |
| 4672 | 0ULL |
| 4673 | }, |
| 4674 | { |
| 4675 | 0x0000000040a00000ULL, |
| 4676 | 0x1918000000000000ULL, |
| 4677 | -1ULL, |
| 4678 | -1ULL, |
| 4679 | -1ULL |
| 4680 | } |
| 4681 | #endif |
| 4682 | }, |
| 4683 | { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1, |
| 4684 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4685 | #ifndef DISASM_ONLY |
| 4686 | { |
| 4687 | 0xc00000007ffc0000ULL, |
| 4688 | 0xfffe000000000000ULL, |
| 4689 | 0ULL, |
| 4690 | 0ULL, |
| 4691 | 0ULL |
| 4692 | }, |
| 4693 | { |
| 4694 | 0x00000000516c0000ULL, |
| 4695 | 0x2878000000000000ULL, |
| 4696 | -1ULL, |
| 4697 | -1ULL, |
| 4698 | -1ULL |
| 4699 | } |
| 4700 | #endif |
| 4701 | }, |
| 4702 | { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1, |
| 4703 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 4704 | #ifndef DISASM_ONLY |
| 4705 | { |
| 4706 | 0xc00000007ff00000ULL, |
| 4707 | 0xfff8000000000000ULL, |
| 4708 | 0ULL, |
| 4709 | 0ULL, |
| 4710 | 0ULL |
| 4711 | }, |
| 4712 | { |
| 4713 | 0x0000000040b00000ULL, |
| 4714 | 0x1920000000000000ULL, |
| 4715 | -1ULL, |
| 4716 | -1ULL, |
| 4717 | -1ULL |
| 4718 | } |
| 4719 | #endif |
| 4720 | }, |
| 4721 | { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1, |
| 4722 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4723 | #ifndef DISASM_ONLY |
| 4724 | { |
| 4725 | 0xc00000007ffc0000ULL, |
| 4726 | 0xfffe000000000000ULL, |
| 4727 | 0ULL, |
| 4728 | 0ULL, |
| 4729 | 0ULL |
| 4730 | }, |
| 4731 | { |
| 4732 | 0x0000000051700000ULL, |
| 4733 | 0x287a000000000000ULL, |
| 4734 | -1ULL, |
| 4735 | -1ULL, |
| 4736 | -1ULL |
| 4737 | } |
| 4738 | #endif |
| 4739 | }, |
| 4740 | { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1, |
| 4741 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4742 | #ifndef DISASM_ONLY |
| 4743 | { |
| 4744 | 0xc00000007ffc0000ULL, |
| 4745 | 0ULL, |
| 4746 | 0ULL, |
| 4747 | 0ULL, |
| 4748 | 0ULL |
| 4749 | }, |
| 4750 | { |
| 4751 | 0x0000000052880000ULL, |
| 4752 | -1ULL, |
| 4753 | -1ULL, |
| 4754 | -1ULL, |
| 4755 | -1ULL |
| 4756 | } |
| 4757 | #endif |
| 4758 | }, |
| 4759 | { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1, |
| 4760 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4761 | #ifndef DISASM_ONLY |
| 4762 | { |
| 4763 | 0xc00000007ffc0000ULL, |
| 4764 | 0ULL, |
| 4765 | 0ULL, |
| 4766 | 0ULL, |
| 4767 | 0ULL |
| 4768 | }, |
| 4769 | { |
| 4770 | 0x0000000052840000ULL, |
| 4771 | -1ULL, |
| 4772 | -1ULL, |
| 4773 | -1ULL, |
| 4774 | -1ULL |
| 4775 | } |
| 4776 | #endif |
| 4777 | }, |
| 4778 | { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1, |
| 4779 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4780 | #ifndef DISASM_ONLY |
| 4781 | { |
| 4782 | 0xc00000007ffc0000ULL, |
| 4783 | 0ULL, |
| 4784 | 0ULL, |
| 4785 | 0ULL, |
| 4786 | 0ULL |
| 4787 | }, |
| 4788 | { |
| 4789 | 0x0000000051780000ULL, |
| 4790 | -1ULL, |
| 4791 | -1ULL, |
| 4792 | -1ULL, |
| 4793 | -1ULL |
| 4794 | } |
| 4795 | #endif |
| 4796 | }, |
| 4797 | { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1, |
| 4798 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4799 | #ifndef DISASM_ONLY |
| 4800 | { |
| 4801 | 0xc00000007ffc0000ULL, |
| 4802 | 0ULL, |
| 4803 | 0ULL, |
| 4804 | 0ULL, |
| 4805 | 0ULL |
| 4806 | }, |
| 4807 | { |
| 4808 | 0x0000000051740000ULL, |
| 4809 | -1ULL, |
| 4810 | -1ULL, |
| 4811 | -1ULL, |
| 4812 | -1ULL |
| 4813 | } |
| 4814 | #endif |
| 4815 | }, |
| 4816 | { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1, |
| 4817 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4818 | #ifndef DISASM_ONLY |
| 4819 | { |
| 4820 | 0xc00000007ffc0000ULL, |
| 4821 | 0ULL, |
| 4822 | 0ULL, |
| 4823 | 0ULL, |
| 4824 | 0ULL |
| 4825 | }, |
| 4826 | { |
| 4827 | 0x0000000051880000ULL, |
| 4828 | -1ULL, |
| 4829 | -1ULL, |
| 4830 | -1ULL, |
| 4831 | -1ULL |
| 4832 | } |
| 4833 | #endif |
| 4834 | }, |
| 4835 | { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1, |
| 4836 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4837 | #ifndef DISASM_ONLY |
| 4838 | { |
| 4839 | 0xc00000007ffc0000ULL, |
| 4840 | 0ULL, |
| 4841 | 0ULL, |
| 4842 | 0ULL, |
| 4843 | 0ULL |
| 4844 | }, |
| 4845 | { |
| 4846 | 0x00000000517c0000ULL, |
| 4847 | -1ULL, |
| 4848 | -1ULL, |
| 4849 | -1ULL, |
| 4850 | -1ULL |
| 4851 | } |
| 4852 | #endif |
| 4853 | }, |
| 4854 | { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1, |
| 4855 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4856 | #ifndef DISASM_ONLY |
| 4857 | { |
| 4858 | 0xc00000007ffc0000ULL, |
| 4859 | 0ULL, |
| 4860 | 0ULL, |
| 4861 | 0ULL, |
| 4862 | 0ULL |
| 4863 | }, |
| 4864 | { |
| 4865 | 0x0000000052900000ULL, |
| 4866 | -1ULL, |
| 4867 | -1ULL, |
| 4868 | -1ULL, |
| 4869 | -1ULL |
| 4870 | } |
| 4871 | #endif |
| 4872 | }, |
| 4873 | { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1, |
| 4874 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4875 | #ifndef DISASM_ONLY |
| 4876 | { |
| 4877 | 0xc00000007ffc0000ULL, |
| 4878 | 0ULL, |
| 4879 | 0ULL, |
| 4880 | 0ULL, |
| 4881 | 0ULL |
| 4882 | }, |
| 4883 | { |
| 4884 | 0x00000000528c0000ULL, |
| 4885 | -1ULL, |
| 4886 | -1ULL, |
| 4887 | -1ULL, |
| 4888 | -1ULL |
| 4889 | } |
| 4890 | #endif |
| 4891 | }, |
| 4892 | { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1, |
| 4893 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4894 | #ifndef DISASM_ONLY |
| 4895 | { |
| 4896 | 0xc00000007ffc0000ULL, |
| 4897 | 0ULL, |
| 4898 | 0ULL, |
| 4899 | 0ULL, |
| 4900 | 0ULL |
| 4901 | }, |
| 4902 | { |
| 4903 | 0x0000000051840000ULL, |
| 4904 | -1ULL, |
| 4905 | -1ULL, |
| 4906 | -1ULL, |
| 4907 | -1ULL |
| 4908 | } |
| 4909 | #endif |
| 4910 | }, |
| 4911 | { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1, |
| 4912 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 4913 | #ifndef DISASM_ONLY |
| 4914 | { |
| 4915 | 0xc00000007ffc0000ULL, |
| 4916 | 0ULL, |
| 4917 | 0ULL, |
| 4918 | 0ULL, |
| 4919 | 0ULL |
| 4920 | }, |
| 4921 | { |
| 4922 | 0x0000000051800000ULL, |
| 4923 | -1ULL, |
| 4924 | -1ULL, |
| 4925 | -1ULL, |
| 4926 | -1ULL |
| 4927 | } |
| 4928 | #endif |
| 4929 | }, |
| 4930 | { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1, |
| 4931 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4932 | #ifndef DISASM_ONLY |
| 4933 | { |
| 4934 | 0xc00000007ffc0000ULL, |
| 4935 | 0xfffe000000000000ULL, |
| 4936 | 0ULL, |
| 4937 | 0ULL, |
| 4938 | 0ULL |
| 4939 | }, |
| 4940 | { |
| 4941 | 0x00000000518c0000ULL, |
| 4942 | 0x287c000000000000ULL, |
| 4943 | -1ULL, |
| 4944 | -1ULL, |
| 4945 | -1ULL |
| 4946 | } |
| 4947 | #endif |
| 4948 | }, |
| 4949 | { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1, |
| 4950 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4951 | #ifndef DISASM_ONLY |
| 4952 | { |
| 4953 | 0xc00000007ffc0000ULL, |
| 4954 | 0xfffe000000000000ULL, |
| 4955 | 0ULL, |
| 4956 | 0ULL, |
| 4957 | 0ULL |
| 4958 | }, |
| 4959 | { |
| 4960 | 0x0000000051900000ULL, |
| 4961 | 0x287e000000000000ULL, |
| 4962 | -1ULL, |
| 4963 | -1ULL, |
| 4964 | -1ULL |
| 4965 | } |
| 4966 | #endif |
| 4967 | }, |
| 4968 | { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1, |
| 4969 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 4970 | #ifndef DISASM_ONLY |
| 4971 | { |
| 4972 | 0xc00000007ffc0000ULL, |
| 4973 | 0xfffe000000000000ULL, |
| 4974 | 0ULL, |
| 4975 | 0ULL, |
| 4976 | 0ULL |
| 4977 | }, |
| 4978 | { |
| 4979 | 0x0000000051940000ULL, |
| 4980 | 0x2880000000000000ULL, |
| 4981 | -1ULL, |
| 4982 | -1ULL, |
| 4983 | -1ULL |
| 4984 | } |
| 4985 | #endif |
| 4986 | }, |
| 4987 | { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1, |
| 4988 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 4989 | #ifndef DISASM_ONLY |
| 4990 | { |
| 4991 | 0xc00000007ff00000ULL, |
| 4992 | 0xfff8000000000000ULL, |
| 4993 | 0ULL, |
| 4994 | 0ULL, |
| 4995 | 0ULL |
| 4996 | }, |
| 4997 | { |
| 4998 | 0x0000000040c00000ULL, |
| 4999 | 0x1928000000000000ULL, |
| 5000 | -1ULL, |
| 5001 | -1ULL, |
| 5002 | -1ULL |
| 5003 | } |
| 5004 | #endif |
| 5005 | }, |
| 5006 | { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1, |
| 5007 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5008 | #ifndef DISASM_ONLY |
| 5009 | { |
| 5010 | 0xc00000007ffc0000ULL, |
| 5011 | 0xfffe000000000000ULL, |
| 5012 | 0ULL, |
| 5013 | 0ULL, |
| 5014 | 0ULL |
| 5015 | }, |
| 5016 | { |
| 5017 | 0x0000000051980000ULL, |
| 5018 | 0x2882000000000000ULL, |
| 5019 | -1ULL, |
| 5020 | -1ULL, |
| 5021 | -1ULL |
| 5022 | } |
| 5023 | #endif |
| 5024 | }, |
| 5025 | { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1, |
| 5026 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5027 | #ifndef DISASM_ONLY |
| 5028 | { |
| 5029 | 0xc00000007ff00000ULL, |
| 5030 | 0xfff8000000000000ULL, |
| 5031 | 0ULL, |
| 5032 | 0ULL, |
| 5033 | 0ULL |
| 5034 | }, |
| 5035 | { |
| 5036 | 0x0000000040d00000ULL, |
| 5037 | 0x1930000000000000ULL, |
| 5038 | -1ULL, |
| 5039 | -1ULL, |
| 5040 | -1ULL |
| 5041 | } |
| 5042 | #endif |
| 5043 | }, |
| 5044 | { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1, |
| 5045 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5046 | #ifndef DISASM_ONLY |
| 5047 | { |
| 5048 | 0xc00000007ffc0000ULL, |
| 5049 | 0xfffe000000000000ULL, |
| 5050 | 0ULL, |
| 5051 | 0ULL, |
| 5052 | 0ULL |
| 5053 | }, |
| 5054 | { |
| 5055 | 0x00000000519c0000ULL, |
| 5056 | 0x2884000000000000ULL, |
| 5057 | -1ULL, |
| 5058 | -1ULL, |
| 5059 | -1ULL |
| 5060 | } |
| 5061 | #endif |
| 5062 | }, |
| 5063 | { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1, |
| 5064 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5065 | #ifndef DISASM_ONLY |
| 5066 | { |
| 5067 | 0xc00000007ffc0000ULL, |
| 5068 | 0ULL, |
| 5069 | 0ULL, |
| 5070 | 0ULL, |
| 5071 | 0ULL |
| 5072 | }, |
| 5073 | { |
| 5074 | 0x0000000051a00000ULL, |
| 5075 | -1ULL, |
| 5076 | -1ULL, |
| 5077 | -1ULL, |
| 5078 | -1ULL |
| 5079 | } |
| 5080 | #endif |
| 5081 | }, |
| 5082 | { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1, |
| 5083 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5084 | #ifndef DISASM_ONLY |
| 5085 | { |
| 5086 | 0xc00000007ffc0000ULL, |
| 5087 | 0ULL, |
| 5088 | 0ULL, |
| 5089 | 0ULL, |
| 5090 | 0ULL |
| 5091 | }, |
| 5092 | { |
| 5093 | 0x0000000051a80000ULL, |
| 5094 | -1ULL, |
| 5095 | -1ULL, |
| 5096 | -1ULL, |
| 5097 | -1ULL |
| 5098 | } |
| 5099 | #endif |
| 5100 | }, |
| 5101 | { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1, |
| 5102 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5103 | #ifndef DISASM_ONLY |
| 5104 | { |
| 5105 | 0xc00000007ffc0000ULL, |
| 5106 | 0ULL, |
| 5107 | 0ULL, |
| 5108 | 0ULL, |
| 5109 | 0ULL |
| 5110 | }, |
| 5111 | { |
| 5112 | 0x0000000051a40000ULL, |
| 5113 | -1ULL, |
| 5114 | -1ULL, |
| 5115 | -1ULL, |
| 5116 | -1ULL |
| 5117 | } |
| 5118 | #endif |
| 5119 | }, |
| 5120 | { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1, |
| 5121 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5122 | #ifndef DISASM_ONLY |
| 5123 | { |
| 5124 | 0xc00000007ffc0000ULL, |
| 5125 | 0xfffe000000000000ULL, |
| 5126 | 0ULL, |
| 5127 | 0ULL, |
| 5128 | 0ULL |
| 5129 | }, |
| 5130 | { |
| 5131 | 0x0000000051ac0000ULL, |
| 5132 | 0x2886000000000000ULL, |
| 5133 | -1ULL, |
| 5134 | -1ULL, |
| 5135 | -1ULL |
| 5136 | } |
| 5137 | #endif |
| 5138 | }, |
| 5139 | { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1, |
| 5140 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5141 | #ifndef DISASM_ONLY |
| 5142 | { |
| 5143 | 0xc00000007ffc0000ULL, |
| 5144 | 0ULL, |
| 5145 | 0ULL, |
| 5146 | 0ULL, |
| 5147 | 0ULL |
| 5148 | }, |
| 5149 | { |
| 5150 | 0x0000000051b00000ULL, |
| 5151 | -1ULL, |
| 5152 | -1ULL, |
| 5153 | -1ULL, |
| 5154 | -1ULL |
| 5155 | } |
| 5156 | #endif |
| 5157 | }, |
| 5158 | { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1, |
| 5159 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5160 | #ifndef DISASM_ONLY |
| 5161 | { |
| 5162 | 0xc00000007ffc0000ULL, |
| 5163 | 0ULL, |
| 5164 | 0ULL, |
| 5165 | 0ULL, |
| 5166 | 0ULL |
| 5167 | }, |
| 5168 | { |
| 5169 | 0x0000000051b40000ULL, |
| 5170 | -1ULL, |
| 5171 | -1ULL, |
| 5172 | -1ULL, |
| 5173 | -1ULL |
| 5174 | } |
| 5175 | #endif |
| 5176 | }, |
| 5177 | { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1, |
| 5178 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5179 | #ifndef DISASM_ONLY |
| 5180 | { |
| 5181 | 0xc00000007ffc0000ULL, |
| 5182 | 0xfffe000000000000ULL, |
| 5183 | 0ULL, |
| 5184 | 0ULL, |
| 5185 | 0ULL |
| 5186 | }, |
| 5187 | { |
| 5188 | 0x0000000051b80000ULL, |
| 5189 | 0x2888000000000000ULL, |
| 5190 | -1ULL, |
| 5191 | -1ULL, |
| 5192 | -1ULL |
| 5193 | } |
| 5194 | #endif |
| 5195 | }, |
| 5196 | { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1, |
| 5197 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 5198 | #ifndef DISASM_ONLY |
| 5199 | { |
| 5200 | 0xc00000007ffc0000ULL, |
| 5201 | 0xfffe000000000000ULL, |
| 5202 | 0ULL, |
| 5203 | 0ULL, |
| 5204 | 0ULL |
| 5205 | }, |
| 5206 | { |
| 5207 | 0x00000000601c0000ULL, |
| 5208 | 0x300e000000000000ULL, |
| 5209 | -1ULL, |
| 5210 | -1ULL, |
| 5211 | -1ULL |
| 5212 | } |
| 5213 | #endif |
| 5214 | }, |
| 5215 | { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1, |
| 5216 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5217 | #ifndef DISASM_ONLY |
| 5218 | { |
| 5219 | 0xc00000007ffc0000ULL, |
| 5220 | 0xfffe000000000000ULL, |
| 5221 | 0ULL, |
| 5222 | 0ULL, |
| 5223 | 0ULL |
| 5224 | }, |
| 5225 | { |
| 5226 | 0x0000000051bc0000ULL, |
| 5227 | 0x288a000000000000ULL, |
| 5228 | -1ULL, |
| 5229 | -1ULL, |
| 5230 | -1ULL |
| 5231 | } |
| 5232 | #endif |
| 5233 | }, |
| 5234 | { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1, |
| 5235 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 5236 | #ifndef DISASM_ONLY |
| 5237 | { |
| 5238 | 0xc00000007ffc0000ULL, |
| 5239 | 0xfffe000000000000ULL, |
| 5240 | 0ULL, |
| 5241 | 0ULL, |
| 5242 | 0ULL |
| 5243 | }, |
| 5244 | { |
| 5245 | 0x0000000060200000ULL, |
| 5246 | 0x3010000000000000ULL, |
| 5247 | -1ULL, |
| 5248 | -1ULL, |
| 5249 | -1ULL |
| 5250 | } |
| 5251 | #endif |
| 5252 | }, |
| 5253 | { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1, |
| 5254 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5255 | #ifndef DISASM_ONLY |
| 5256 | { |
| 5257 | 0xc00000007ffc0000ULL, |
| 5258 | 0xfffe000000000000ULL, |
| 5259 | 0ULL, |
| 5260 | 0ULL, |
| 5261 | 0ULL |
| 5262 | }, |
| 5263 | { |
| 5264 | 0x0000000051c00000ULL, |
| 5265 | 0x288c000000000000ULL, |
| 5266 | -1ULL, |
| 5267 | -1ULL, |
| 5268 | -1ULL |
| 5269 | } |
| 5270 | #endif |
| 5271 | }, |
| 5272 | { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1, |
| 5273 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 5274 | #ifndef DISASM_ONLY |
| 5275 | { |
| 5276 | 0xc00000007ffc0000ULL, |
| 5277 | 0xfffe000000000000ULL, |
| 5278 | 0ULL, |
| 5279 | 0ULL, |
| 5280 | 0ULL |
| 5281 | }, |
| 5282 | { |
| 5283 | 0x0000000060240000ULL, |
| 5284 | 0x3012000000000000ULL, |
| 5285 | -1ULL, |
| 5286 | -1ULL, |
| 5287 | -1ULL |
| 5288 | } |
| 5289 | #endif |
| 5290 | }, |
| 5291 | { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1, |
| 5292 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5293 | #ifndef DISASM_ONLY |
| 5294 | { |
| 5295 | 0xc00000007ffc0000ULL, |
| 5296 | 0xfffe000000000000ULL, |
| 5297 | 0ULL, |
| 5298 | 0ULL, |
| 5299 | 0ULL |
| 5300 | }, |
| 5301 | { |
| 5302 | 0x0000000051c80000ULL, |
| 5303 | 0x2890000000000000ULL, |
| 5304 | -1ULL, |
| 5305 | -1ULL, |
| 5306 | -1ULL |
| 5307 | } |
| 5308 | #endif |
| 5309 | }, |
| 5310 | { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1, |
| 5311 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5312 | #ifndef DISASM_ONLY |
| 5313 | { |
| 5314 | 0xc00000007ffc0000ULL, |
| 5315 | 0xfffe000000000000ULL, |
| 5316 | 0ULL, |
| 5317 | 0ULL, |
| 5318 | 0ULL |
| 5319 | }, |
| 5320 | { |
| 5321 | 0x0000000051c40000ULL, |
| 5322 | 0x288e000000000000ULL, |
| 5323 | -1ULL, |
| 5324 | -1ULL, |
| 5325 | -1ULL |
| 5326 | } |
| 5327 | #endif |
| 5328 | }, |
| 5329 | { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1, |
| 5330 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5331 | #ifndef DISASM_ONLY |
| 5332 | { |
| 5333 | 0xc00000007ffc0000ULL, |
| 5334 | 0xfffe000000000000ULL, |
| 5335 | 0ULL, |
| 5336 | 0ULL, |
| 5337 | 0ULL |
| 5338 | }, |
| 5339 | { |
| 5340 | 0x0000000051d00000ULL, |
| 5341 | 0x2894000000000000ULL, |
| 5342 | -1ULL, |
| 5343 | -1ULL, |
| 5344 | -1ULL |
| 5345 | } |
| 5346 | #endif |
| 5347 | }, |
| 5348 | { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1, |
| 5349 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5350 | #ifndef DISASM_ONLY |
| 5351 | { |
| 5352 | 0xc00000007ff00000ULL, |
| 5353 | 0xfff8000000000000ULL, |
| 5354 | 0ULL, |
| 5355 | 0ULL, |
| 5356 | 0ULL |
| 5357 | }, |
| 5358 | { |
| 5359 | 0x0000000040e00000ULL, |
| 5360 | 0x1938000000000000ULL, |
| 5361 | -1ULL, |
| 5362 | -1ULL, |
| 5363 | -1ULL |
| 5364 | } |
| 5365 | #endif |
| 5366 | }, |
| 5367 | { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1, |
| 5368 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5369 | #ifndef DISASM_ONLY |
| 5370 | { |
| 5371 | 0xc00000007ffc0000ULL, |
| 5372 | 0xfffe000000000000ULL, |
| 5373 | 0ULL, |
| 5374 | 0ULL, |
| 5375 | 0ULL |
| 5376 | }, |
| 5377 | { |
| 5378 | 0x0000000051cc0000ULL, |
| 5379 | 0x2892000000000000ULL, |
| 5380 | -1ULL, |
| 5381 | -1ULL, |
| 5382 | -1ULL |
| 5383 | } |
| 5384 | #endif |
| 5385 | }, |
| 5386 | { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1, |
| 5387 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5388 | #ifndef DISASM_ONLY |
| 5389 | { |
| 5390 | 0xc00000007ffc0000ULL, |
| 5391 | 0ULL, |
| 5392 | 0ULL, |
| 5393 | 0ULL, |
| 5394 | 0ULL |
| 5395 | }, |
| 5396 | { |
| 5397 | 0x0000000051d40000ULL, |
| 5398 | -1ULL, |
| 5399 | -1ULL, |
| 5400 | -1ULL, |
| 5401 | -1ULL |
| 5402 | } |
| 5403 | #endif |
| 5404 | }, |
| 5405 | { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1, |
| 5406 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5407 | #ifndef DISASM_ONLY |
| 5408 | { |
| 5409 | 0xc00000007ffc0000ULL, |
| 5410 | 0ULL, |
| 5411 | 0ULL, |
| 5412 | 0ULL, |
| 5413 | 0ULL |
| 5414 | }, |
| 5415 | { |
| 5416 | 0x0000000051d80000ULL, |
| 5417 | -1ULL, |
| 5418 | -1ULL, |
| 5419 | -1ULL, |
| 5420 | -1ULL |
| 5421 | } |
| 5422 | #endif |
| 5423 | }, |
| 5424 | { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1, |
| 5425 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5426 | #ifndef DISASM_ONLY |
| 5427 | { |
| 5428 | 0xc00000007ffc0000ULL, |
| 5429 | 0xfffe000000000000ULL, |
| 5430 | 0ULL, |
| 5431 | 0ULL, |
| 5432 | 0ULL |
| 5433 | }, |
| 5434 | { |
| 5435 | 0x0000000051dc0000ULL, |
| 5436 | 0x2896000000000000ULL, |
| 5437 | -1ULL, |
| 5438 | -1ULL, |
| 5439 | -1ULL |
| 5440 | } |
| 5441 | #endif |
| 5442 | }, |
| 5443 | { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1, |
| 5444 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5445 | #ifndef DISASM_ONLY |
| 5446 | { |
| 5447 | 0xc00000007ff00000ULL, |
| 5448 | 0xfff8000000000000ULL, |
| 5449 | 0ULL, |
| 5450 | 0ULL, |
| 5451 | 0ULL |
| 5452 | }, |
| 5453 | { |
| 5454 | 0x0000000040f00000ULL, |
| 5455 | 0x1940000000000000ULL, |
| 5456 | -1ULL, |
| 5457 | -1ULL, |
| 5458 | -1ULL |
| 5459 | } |
| 5460 | #endif |
| 5461 | }, |
| 5462 | { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1, |
| 5463 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5464 | #ifndef DISASM_ONLY |
| 5465 | { |
| 5466 | 0xc00000007ffc0000ULL, |
| 5467 | 0xfffe000000000000ULL, |
| 5468 | 0ULL, |
| 5469 | 0ULL, |
| 5470 | 0ULL |
| 5471 | }, |
| 5472 | { |
| 5473 | 0x0000000051e00000ULL, |
| 5474 | 0x2898000000000000ULL, |
| 5475 | -1ULL, |
| 5476 | -1ULL, |
| 5477 | -1ULL |
| 5478 | } |
| 5479 | #endif |
| 5480 | }, |
| 5481 | { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1, |
| 5482 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5483 | #ifndef DISASM_ONLY |
| 5484 | { |
| 5485 | 0xc00000007ffc0000ULL, |
| 5486 | 0xfffe000000000000ULL, |
| 5487 | 0ULL, |
| 5488 | 0ULL, |
| 5489 | 0ULL |
| 5490 | }, |
| 5491 | { |
| 5492 | 0x0000000051e40000ULL, |
| 5493 | 0x289a000000000000ULL, |
| 5494 | -1ULL, |
| 5495 | -1ULL, |
| 5496 | -1ULL |
| 5497 | } |
| 5498 | #endif |
| 5499 | }, |
| 5500 | { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1, |
| 5501 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5502 | #ifndef DISASM_ONLY |
| 5503 | { |
| 5504 | 0xc00000007ffc0000ULL, |
| 5505 | 0xfffe000000000000ULL, |
| 5506 | 0ULL, |
| 5507 | 0ULL, |
| 5508 | 0ULL |
| 5509 | }, |
| 5510 | { |
| 5511 | 0x0000000051e80000ULL, |
| 5512 | 0x289c000000000000ULL, |
| 5513 | -1ULL, |
| 5514 | -1ULL, |
| 5515 | -1ULL |
| 5516 | } |
| 5517 | #endif |
| 5518 | }, |
| 5519 | { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1, |
| 5520 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5521 | #ifndef DISASM_ONLY |
| 5522 | { |
| 5523 | 0xc00000007ff00000ULL, |
| 5524 | 0xfff8000000000000ULL, |
| 5525 | 0ULL, |
| 5526 | 0ULL, |
| 5527 | 0ULL |
| 5528 | }, |
| 5529 | { |
| 5530 | 0x0000000041000000ULL, |
| 5531 | 0x1948000000000000ULL, |
| 5532 | -1ULL, |
| 5533 | -1ULL, |
| 5534 | -1ULL |
| 5535 | } |
| 5536 | #endif |
| 5537 | }, |
| 5538 | { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1, |
| 5539 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5540 | #ifndef DISASM_ONLY |
| 5541 | { |
| 5542 | 0xc00000007ffc0000ULL, |
| 5543 | 0xfffe000000000000ULL, |
| 5544 | 0ULL, |
| 5545 | 0ULL, |
| 5546 | 0ULL |
| 5547 | }, |
| 5548 | { |
| 5549 | 0x0000000051ec0000ULL, |
| 5550 | 0x289e000000000000ULL, |
| 5551 | -1ULL, |
| 5552 | -1ULL, |
| 5553 | -1ULL |
| 5554 | } |
| 5555 | #endif |
| 5556 | }, |
| 5557 | { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1, |
| 5558 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5559 | #ifndef DISASM_ONLY |
| 5560 | { |
| 5561 | 0xc00000007ff00000ULL, |
| 5562 | 0xfff8000000000000ULL, |
| 5563 | 0ULL, |
| 5564 | 0ULL, |
| 5565 | 0ULL |
| 5566 | }, |
| 5567 | { |
| 5568 | 0x0000000041100000ULL, |
| 5569 | 0x1950000000000000ULL, |
| 5570 | -1ULL, |
| 5571 | -1ULL, |
| 5572 | -1ULL |
| 5573 | } |
| 5574 | #endif |
| 5575 | }, |
| 5576 | { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1, |
| 5577 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5578 | #ifndef DISASM_ONLY |
| 5579 | { |
| 5580 | 0xc00000007ffc0000ULL, |
| 5581 | 0xfffe000000000000ULL, |
| 5582 | 0ULL, |
| 5583 | 0ULL, |
| 5584 | 0ULL |
| 5585 | }, |
| 5586 | { |
| 5587 | 0x0000000051f00000ULL, |
| 5588 | 0x28a0000000000000ULL, |
| 5589 | -1ULL, |
| 5590 | -1ULL, |
| 5591 | -1ULL |
| 5592 | } |
| 5593 | #endif |
| 5594 | }, |
| 5595 | { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1, |
| 5596 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5597 | #ifndef DISASM_ONLY |
| 5598 | { |
| 5599 | 0xc00000007ffc0000ULL, |
| 5600 | 0ULL, |
| 5601 | 0ULL, |
| 5602 | 0ULL, |
| 5603 | 0ULL |
| 5604 | }, |
| 5605 | { |
| 5606 | 0x0000000051f80000ULL, |
| 5607 | -1ULL, |
| 5608 | -1ULL, |
| 5609 | -1ULL, |
| 5610 | -1ULL |
| 5611 | } |
| 5612 | #endif |
| 5613 | }, |
| 5614 | { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1, |
| 5615 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5616 | #ifndef DISASM_ONLY |
| 5617 | { |
| 5618 | 0xc00000007ffc0000ULL, |
| 5619 | 0ULL, |
| 5620 | 0ULL, |
| 5621 | 0ULL, |
| 5622 | 0ULL |
| 5623 | }, |
| 5624 | { |
| 5625 | 0x0000000051f40000ULL, |
| 5626 | -1ULL, |
| 5627 | -1ULL, |
| 5628 | -1ULL, |
| 5629 | -1ULL |
| 5630 | } |
| 5631 | #endif |
| 5632 | }, |
| 5633 | { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1, |
| 5634 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5635 | #ifndef DISASM_ONLY |
| 5636 | { |
| 5637 | 0xc00000007ffc0000ULL, |
| 5638 | 0xfffe000000000000ULL, |
| 5639 | 0ULL, |
| 5640 | 0ULL, |
| 5641 | 0ULL |
| 5642 | }, |
| 5643 | { |
| 5644 | 0x0000000051fc0000ULL, |
| 5645 | 0x28a2000000000000ULL, |
| 5646 | -1ULL, |
| 5647 | -1ULL, |
| 5648 | -1ULL |
| 5649 | } |
| 5650 | #endif |
| 5651 | }, |
| 5652 | { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1, |
| 5653 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5654 | #ifndef DISASM_ONLY |
| 5655 | { |
| 5656 | 0xc00000007ffc0000ULL, |
| 5657 | 0xfffe000000000000ULL, |
| 5658 | 0ULL, |
| 5659 | 0ULL, |
| 5660 | 0ULL |
| 5661 | }, |
| 5662 | { |
| 5663 | 0x0000000052000000ULL, |
| 5664 | 0x28a4000000000000ULL, |
| 5665 | -1ULL, |
| 5666 | -1ULL, |
| 5667 | -1ULL |
| 5668 | } |
| 5669 | #endif |
| 5670 | }, |
| 5671 | { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1, |
| 5672 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5673 | #ifndef DISASM_ONLY |
| 5674 | { |
| 5675 | 0xc00000007ffc0000ULL, |
| 5676 | 0xfffe000000000000ULL, |
| 5677 | 0ULL, |
| 5678 | 0ULL, |
| 5679 | 0ULL |
| 5680 | }, |
| 5681 | { |
| 5682 | 0x0000000052040000ULL, |
| 5683 | 0x28a6000000000000ULL, |
| 5684 | -1ULL, |
| 5685 | -1ULL, |
| 5686 | -1ULL |
| 5687 | } |
| 5688 | #endif |
| 5689 | }, |
| 5690 | { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1, |
| 5691 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5692 | #ifndef DISASM_ONLY |
| 5693 | { |
| 5694 | 0xc00000007ff00000ULL, |
| 5695 | 0xfff8000000000000ULL, |
| 5696 | 0ULL, |
| 5697 | 0ULL, |
| 5698 | 0ULL |
| 5699 | }, |
| 5700 | { |
| 5701 | 0x0000000041200000ULL, |
| 5702 | 0x1958000000000000ULL, |
| 5703 | -1ULL, |
| 5704 | -1ULL, |
| 5705 | -1ULL |
| 5706 | } |
| 5707 | #endif |
| 5708 | }, |
| 5709 | { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1, |
| 5710 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5711 | #ifndef DISASM_ONLY |
| 5712 | { |
| 5713 | 0xc00000007ffc0000ULL, |
| 5714 | 0xfffe000000000000ULL, |
| 5715 | 0ULL, |
| 5716 | 0ULL, |
| 5717 | 0ULL |
| 5718 | }, |
| 5719 | { |
| 5720 | 0x0000000052080000ULL, |
| 5721 | 0x28a8000000000000ULL, |
| 5722 | -1ULL, |
| 5723 | -1ULL, |
| 5724 | -1ULL |
| 5725 | } |
| 5726 | #endif |
| 5727 | }, |
| 5728 | { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1, |
| 5729 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 5730 | #ifndef DISASM_ONLY |
| 5731 | { |
| 5732 | 0xc00000007ff00000ULL, |
| 5733 | 0xfff8000000000000ULL, |
| 5734 | 0ULL, |
| 5735 | 0ULL, |
| 5736 | 0ULL |
| 5737 | }, |
| 5738 | { |
| 5739 | 0x0000000041300000ULL, |
| 5740 | 0x1960000000000000ULL, |
| 5741 | -1ULL, |
| 5742 | -1ULL, |
| 5743 | -1ULL |
| 5744 | } |
| 5745 | #endif |
| 5746 | }, |
| 5747 | { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1, |
| 5748 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5749 | #ifndef DISASM_ONLY |
| 5750 | { |
| 5751 | 0xc00000007ffc0000ULL, |
| 5752 | 0xfffe000000000000ULL, |
| 5753 | 0ULL, |
| 5754 | 0ULL, |
| 5755 | 0ULL |
| 5756 | }, |
| 5757 | { |
| 5758 | 0x00000000520c0000ULL, |
| 5759 | 0x28aa000000000000ULL, |
| 5760 | -1ULL, |
| 5761 | -1ULL, |
| 5762 | -1ULL |
| 5763 | } |
| 5764 | #endif |
| 5765 | }, |
| 5766 | { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1, |
| 5767 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5768 | #ifndef DISASM_ONLY |
| 5769 | { |
| 5770 | 0xc00000007ffc0000ULL, |
| 5771 | 0ULL, |
| 5772 | 0ULL, |
| 5773 | 0ULL, |
| 5774 | 0ULL |
| 5775 | }, |
| 5776 | { |
| 5777 | 0x0000000052100000ULL, |
| 5778 | -1ULL, |
| 5779 | -1ULL, |
| 5780 | -1ULL, |
| 5781 | -1ULL |
| 5782 | } |
| 5783 | #endif |
| 5784 | }, |
| 5785 | { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1, |
| 5786 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5787 | #ifndef DISASM_ONLY |
| 5788 | { |
| 5789 | 0xc00000007ffc0000ULL, |
| 5790 | 0ULL, |
| 5791 | 0ULL, |
| 5792 | 0ULL, |
| 5793 | 0ULL |
| 5794 | }, |
| 5795 | { |
| 5796 | 0x0000000052140000ULL, |
| 5797 | -1ULL, |
| 5798 | -1ULL, |
| 5799 | -1ULL, |
| 5800 | -1ULL |
| 5801 | } |
| 5802 | #endif |
| 5803 | }, |
| 5804 | { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1, |
| 5805 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5806 | #ifndef DISASM_ONLY |
| 5807 | { |
| 5808 | 0xc00000007ffc0000ULL, |
| 5809 | 0ULL, |
| 5810 | 0ULL, |
| 5811 | 0ULL, |
| 5812 | 0ULL |
| 5813 | }, |
| 5814 | { |
| 5815 | 0x0000000052180000ULL, |
| 5816 | -1ULL, |
| 5817 | -1ULL, |
| 5818 | -1ULL, |
| 5819 | -1ULL |
| 5820 | } |
| 5821 | #endif |
| 5822 | }, |
| 5823 | { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1, |
| 5824 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5825 | #ifndef DISASM_ONLY |
| 5826 | { |
| 5827 | 0xc00000007ffc0000ULL, |
| 5828 | 0xfffe000000000000ULL, |
| 5829 | 0ULL, |
| 5830 | 0ULL, |
| 5831 | 0ULL |
| 5832 | }, |
| 5833 | { |
| 5834 | 0x00000000521c0000ULL, |
| 5835 | 0x28ac000000000000ULL, |
| 5836 | -1ULL, |
| 5837 | -1ULL, |
| 5838 | -1ULL |
| 5839 | } |
| 5840 | #endif |
| 5841 | }, |
| 5842 | { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1, |
| 5843 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5844 | #ifndef DISASM_ONLY |
| 5845 | { |
| 5846 | 0xc00000007ffc0000ULL, |
| 5847 | 0xfffe000000000000ULL, |
| 5848 | 0ULL, |
| 5849 | 0ULL, |
| 5850 | 0ULL |
| 5851 | }, |
| 5852 | { |
| 5853 | 0x0000000052200000ULL, |
| 5854 | 0x28ae000000000000ULL, |
| 5855 | -1ULL, |
| 5856 | -1ULL, |
| 5857 | -1ULL |
| 5858 | } |
| 5859 | #endif |
| 5860 | }, |
| 5861 | { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1, |
| 5862 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5863 | #ifndef DISASM_ONLY |
| 5864 | { |
| 5865 | 0xc00000007ffc0000ULL, |
| 5866 | 0xfffe000000000000ULL, |
| 5867 | 0ULL, |
| 5868 | 0ULL, |
| 5869 | 0ULL |
| 5870 | }, |
| 5871 | { |
| 5872 | 0x0000000052240000ULL, |
| 5873 | 0x28b0000000000000ULL, |
| 5874 | -1ULL, |
| 5875 | -1ULL, |
| 5876 | -1ULL |
| 5877 | } |
| 5878 | #endif |
| 5879 | }, |
| 5880 | { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1, |
| 5881 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5882 | #ifndef DISASM_ONLY |
| 5883 | { |
| 5884 | 0xc00000007ffc0000ULL, |
| 5885 | 0xfffe000000000000ULL, |
| 5886 | 0ULL, |
| 5887 | 0ULL, |
| 5888 | 0ULL |
| 5889 | }, |
| 5890 | { |
| 5891 | 0x0000000052280000ULL, |
| 5892 | 0x28b2000000000000ULL, |
| 5893 | -1ULL, |
| 5894 | -1ULL, |
| 5895 | -1ULL |
| 5896 | } |
| 5897 | #endif |
| 5898 | }, |
| 5899 | { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1, |
| 5900 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5901 | #ifndef DISASM_ONLY |
| 5902 | { |
| 5903 | 0xc00000007ffc0000ULL, |
| 5904 | 0ULL, |
| 5905 | 0ULL, |
| 5906 | 0ULL, |
| 5907 | 0ULL |
| 5908 | }, |
| 5909 | { |
| 5910 | 0x00000000522c0000ULL, |
| 5911 | -1ULL, |
| 5912 | -1ULL, |
| 5913 | -1ULL, |
| 5914 | -1ULL |
| 5915 | } |
| 5916 | #endif |
| 5917 | }, |
| 5918 | { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1, |
| 5919 | { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5920 | #ifndef DISASM_ONLY |
| 5921 | { |
| 5922 | 0xc00000007ffc0000ULL, |
| 5923 | 0ULL, |
| 5924 | 0ULL, |
| 5925 | 0ULL, |
| 5926 | 0ULL |
| 5927 | }, |
| 5928 | { |
| 5929 | 0x0000000052300000ULL, |
| 5930 | -1ULL, |
| 5931 | -1ULL, |
| 5932 | -1ULL, |
| 5933 | -1ULL |
| 5934 | } |
| 5935 | #endif |
| 5936 | }, |
| 5937 | { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1, |
| 5938 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5939 | #ifndef DISASM_ONLY |
| 5940 | { |
| 5941 | 0xc00000007ffc0000ULL, |
| 5942 | 0ULL, |
| 5943 | 0ULL, |
| 5944 | 0ULL, |
| 5945 | 0ULL |
| 5946 | }, |
| 5947 | { |
| 5948 | 0x0000000052340000ULL, |
| 5949 | -1ULL, |
| 5950 | -1ULL, |
| 5951 | -1ULL, |
| 5952 | -1ULL |
| 5953 | } |
| 5954 | #endif |
| 5955 | }, |
| 5956 | { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1, |
| 5957 | { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
| 5958 | #ifndef DISASM_ONLY |
| 5959 | { |
| 5960 | 0xc00000007ffc0000ULL, |
| 5961 | 0ULL, |
| 5962 | 0ULL, |
| 5963 | 0ULL, |
| 5964 | 0ULL |
| 5965 | }, |
| 5966 | { |
| 5967 | 0x0000000052380000ULL, |
| 5968 | -1ULL, |
| 5969 | -1ULL, |
| 5970 | -1ULL, |
| 5971 | -1ULL |
| 5972 | } |
| 5973 | #endif |
| 5974 | }, |
| 5975 | { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1, |
| 5976 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 5977 | #ifndef DISASM_ONLY |
| 5978 | { |
| 5979 | 0xc00000007ffc0000ULL, |
| 5980 | 0xfffe000000000000ULL, |
| 5981 | 0ULL, |
| 5982 | 0ULL, |
| 5983 | 0ULL |
| 5984 | }, |
| 5985 | { |
| 5986 | 0x0000000052400000ULL, |
| 5987 | 0x28b6000000000000ULL, |
| 5988 | -1ULL, |
| 5989 | -1ULL, |
| 5990 | -1ULL |
| 5991 | } |
| 5992 | #endif |
| 5993 | }, |
| 5994 | { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1, |
| 5995 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 5996 | #ifndef DISASM_ONLY |
| 5997 | { |
| 5998 | 0xc00000007ffc0000ULL, |
| 5999 | 0xfffe000000000000ULL, |
| 6000 | 0ULL, |
| 6001 | 0ULL, |
| 6002 | 0ULL |
| 6003 | }, |
| 6004 | { |
| 6005 | 0x0000000060280000ULL, |
| 6006 | 0x3014000000000000ULL, |
| 6007 | -1ULL, |
| 6008 | -1ULL, |
| 6009 | -1ULL |
| 6010 | } |
| 6011 | #endif |
| 6012 | }, |
| 6013 | { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1, |
| 6014 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6015 | #ifndef DISASM_ONLY |
| 6016 | { |
| 6017 | 0xc00000007ffc0000ULL, |
| 6018 | 0xfffe000000000000ULL, |
| 6019 | 0ULL, |
| 6020 | 0ULL, |
| 6021 | 0ULL |
| 6022 | }, |
| 6023 | { |
| 6024 | 0x00000000523c0000ULL, |
| 6025 | 0x28b4000000000000ULL, |
| 6026 | -1ULL, |
| 6027 | -1ULL, |
| 6028 | -1ULL |
| 6029 | } |
| 6030 | #endif |
| 6031 | }, |
| 6032 | { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1, |
| 6033 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6034 | #ifndef DISASM_ONLY |
| 6035 | { |
| 6036 | 0xc00000007ffc0000ULL, |
| 6037 | 0xfffe000000000000ULL, |
| 6038 | 0ULL, |
| 6039 | 0ULL, |
| 6040 | 0ULL |
| 6041 | }, |
| 6042 | { |
| 6043 | 0x0000000052440000ULL, |
| 6044 | 0x28b8000000000000ULL, |
| 6045 | -1ULL, |
| 6046 | -1ULL, |
| 6047 | -1ULL |
| 6048 | } |
| 6049 | #endif |
| 6050 | }, |
| 6051 | { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1, |
| 6052 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 6053 | #ifndef DISASM_ONLY |
| 6054 | { |
| 6055 | 0xc00000007ffc0000ULL, |
| 6056 | 0xfffe000000000000ULL, |
| 6057 | 0ULL, |
| 6058 | 0ULL, |
| 6059 | 0ULL |
| 6060 | }, |
| 6061 | { |
| 6062 | 0x00000000602c0000ULL, |
| 6063 | 0x3016000000000000ULL, |
| 6064 | -1ULL, |
| 6065 | -1ULL, |
| 6066 | -1ULL |
| 6067 | } |
| 6068 | #endif |
| 6069 | }, |
| 6070 | { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1, |
| 6071 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6072 | #ifndef DISASM_ONLY |
| 6073 | { |
| 6074 | 0xc00000007ffc0000ULL, |
| 6075 | 0xfffe000000000000ULL, |
| 6076 | 0ULL, |
| 6077 | 0ULL, |
| 6078 | 0ULL |
| 6079 | }, |
| 6080 | { |
| 6081 | 0x0000000052480000ULL, |
| 6082 | 0x28ba000000000000ULL, |
| 6083 | -1ULL, |
| 6084 | -1ULL, |
| 6085 | -1ULL |
| 6086 | } |
| 6087 | #endif |
| 6088 | }, |
| 6089 | { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1, |
| 6090 | { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, |
| 6091 | #ifndef DISASM_ONLY |
| 6092 | { |
| 6093 | 0xc00000007ffc0000ULL, |
| 6094 | 0xfffe000000000000ULL, |
| 6095 | 0ULL, |
| 6096 | 0ULL, |
| 6097 | 0ULL |
| 6098 | }, |
| 6099 | { |
| 6100 | 0x0000000060300000ULL, |
| 6101 | 0x3018000000000000ULL, |
| 6102 | -1ULL, |
| 6103 | -1ULL, |
| 6104 | -1ULL |
| 6105 | } |
| 6106 | #endif |
| 6107 | }, |
| 6108 | { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1, |
| 6109 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6110 | #ifndef DISASM_ONLY |
| 6111 | { |
| 6112 | 0xc00000007ffc0000ULL, |
| 6113 | 0xfffe000000000000ULL, |
| 6114 | 0ULL, |
| 6115 | 0ULL, |
| 6116 | 0ULL |
| 6117 | }, |
| 6118 | { |
| 6119 | 0x0000000052500000ULL, |
| 6120 | 0x28be000000000000ULL, |
| 6121 | -1ULL, |
| 6122 | -1ULL, |
| 6123 | -1ULL |
| 6124 | } |
| 6125 | #endif |
| 6126 | }, |
| 6127 | { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1, |
| 6128 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6129 | #ifndef DISASM_ONLY |
| 6130 | { |
| 6131 | 0xc00000007ffc0000ULL, |
| 6132 | 0xfffe000000000000ULL, |
| 6133 | 0ULL, |
| 6134 | 0ULL, |
| 6135 | 0ULL |
| 6136 | }, |
| 6137 | { |
| 6138 | 0x00000000524c0000ULL, |
| 6139 | 0x28bc000000000000ULL, |
| 6140 | -1ULL, |
| 6141 | -1ULL, |
| 6142 | -1ULL |
| 6143 | } |
| 6144 | #endif |
| 6145 | }, |
| 6146 | { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1, |
| 6147 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6148 | #ifndef DISASM_ONLY |
| 6149 | { |
| 6150 | 0xc00000007ffc0000ULL, |
| 6151 | 0xfffe000000000000ULL, |
| 6152 | 0ULL, |
| 6153 | 0ULL, |
| 6154 | 0ULL |
| 6155 | }, |
| 6156 | { |
| 6157 | 0x0000000052580000ULL, |
| 6158 | 0x28c2000000000000ULL, |
| 6159 | -1ULL, |
| 6160 | -1ULL, |
| 6161 | -1ULL |
| 6162 | } |
| 6163 | #endif |
| 6164 | }, |
| 6165 | { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1, |
| 6166 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6167 | #ifndef DISASM_ONLY |
| 6168 | { |
| 6169 | 0xc00000007ffc0000ULL, |
| 6170 | 0xfffe000000000000ULL, |
| 6171 | 0ULL, |
| 6172 | 0ULL, |
| 6173 | 0ULL |
| 6174 | }, |
| 6175 | { |
| 6176 | 0x0000000052540000ULL, |
| 6177 | 0x28c0000000000000ULL, |
| 6178 | -1ULL, |
| 6179 | -1ULL, |
| 6180 | -1ULL |
| 6181 | } |
| 6182 | #endif |
| 6183 | }, |
| 6184 | { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1, |
| 6185 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6186 | #ifndef DISASM_ONLY |
| 6187 | { |
| 6188 | 0xc00000007ffc0000ULL, |
| 6189 | 0xfffe000000000000ULL, |
| 6190 | 0ULL, |
| 6191 | 0ULL, |
| 6192 | 0ULL |
| 6193 | }, |
| 6194 | { |
| 6195 | 0x00000000525c0000ULL, |
| 6196 | 0x28c4000000000000ULL, |
| 6197 | -1ULL, |
| 6198 | -1ULL, |
| 6199 | -1ULL |
| 6200 | } |
| 6201 | #endif |
| 6202 | }, |
| 6203 | { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1, |
| 6204 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6205 | #ifndef DISASM_ONLY |
| 6206 | { |
| 6207 | 0xc00000007ffc0000ULL, |
| 6208 | 0xfffe000000000000ULL, |
| 6209 | 0ULL, |
| 6210 | 0ULL, |
| 6211 | 0ULL |
| 6212 | }, |
| 6213 | { |
| 6214 | 0x0000000052600000ULL, |
| 6215 | 0x28c6000000000000ULL, |
| 6216 | -1ULL, |
| 6217 | -1ULL, |
| 6218 | -1ULL |
| 6219 | } |
| 6220 | #endif |
| 6221 | }, |
| 6222 | { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1, |
| 6223 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6224 | #ifndef DISASM_ONLY |
| 6225 | { |
| 6226 | 0xc00000007ffc0000ULL, |
| 6227 | 0xfffe000000000000ULL, |
| 6228 | 0ULL, |
| 6229 | 0ULL, |
| 6230 | 0ULL |
| 6231 | }, |
| 6232 | { |
| 6233 | 0x0000000052640000ULL, |
| 6234 | 0x28c8000000000000ULL, |
| 6235 | -1ULL, |
| 6236 | -1ULL, |
| 6237 | -1ULL |
| 6238 | } |
| 6239 | #endif |
| 6240 | }, |
| 6241 | { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1, |
| 6242 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6243 | #ifndef DISASM_ONLY |
| 6244 | { |
| 6245 | 0xc00000007ffc0000ULL, |
| 6246 | 0xfffe000000000000ULL, |
| 6247 | 0ULL, |
| 6248 | 0ULL, |
| 6249 | 0ULL |
| 6250 | }, |
| 6251 | { |
| 6252 | 0x00000000526c0000ULL, |
| 6253 | 0x28cc000000000000ULL, |
| 6254 | -1ULL, |
| 6255 | -1ULL, |
| 6256 | -1ULL |
| 6257 | } |
| 6258 | #endif |
| 6259 | }, |
| 6260 | { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1, |
| 6261 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6262 | #ifndef DISASM_ONLY |
| 6263 | { |
| 6264 | 0xc00000007ffc0000ULL, |
| 6265 | 0xfffe000000000000ULL, |
| 6266 | 0ULL, |
| 6267 | 0ULL, |
| 6268 | 0ULL |
| 6269 | }, |
| 6270 | { |
| 6271 | 0x0000000052680000ULL, |
| 6272 | 0x28ca000000000000ULL, |
| 6273 | -1ULL, |
| 6274 | -1ULL, |
| 6275 | -1ULL |
| 6276 | } |
| 6277 | #endif |
| 6278 | }, |
| 6279 | { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1, |
| 6280 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6281 | #ifndef DISASM_ONLY |
| 6282 | { |
| 6283 | 0xc00000007ffc0000ULL, |
| 6284 | 0xfffe000000000000ULL, |
| 6285 | 0ULL, |
| 6286 | 0ULL, |
| 6287 | 0ULL |
| 6288 | }, |
| 6289 | { |
| 6290 | 0x0000000052700000ULL, |
| 6291 | 0x28ce000000000000ULL, |
| 6292 | -1ULL, |
| 6293 | -1ULL, |
| 6294 | -1ULL |
| 6295 | } |
| 6296 | #endif |
| 6297 | }, |
| 6298 | { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1, |
| 6299 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6300 | #ifndef DISASM_ONLY |
| 6301 | { |
| 6302 | 0xc00000007ffc0000ULL, |
| 6303 | 0xfffe000000000000ULL, |
| 6304 | 0ULL, |
| 6305 | 0ULL, |
| 6306 | 0ULL |
| 6307 | }, |
| 6308 | { |
| 6309 | 0x0000000052740000ULL, |
| 6310 | 0x28d0000000000000ULL, |
| 6311 | -1ULL, |
| 6312 | -1ULL, |
| 6313 | -1ULL |
| 6314 | } |
| 6315 | #endif |
| 6316 | }, |
| 6317 | { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1, |
| 6318 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6319 | #ifndef DISASM_ONLY |
| 6320 | { |
| 6321 | 0xc00000007ffc0000ULL, |
| 6322 | 0xfffe000000000000ULL, |
| 6323 | 0ULL, |
| 6324 | 0ULL, |
| 6325 | 0ULL |
| 6326 | }, |
| 6327 | { |
| 6328 | 0x00000000527c0000ULL, |
| 6329 | 0x28d4000000000000ULL, |
| 6330 | -1ULL, |
| 6331 | -1ULL, |
| 6332 | -1ULL |
| 6333 | } |
| 6334 | #endif |
| 6335 | }, |
| 6336 | { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1, |
| 6337 | { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, |
| 6338 | #ifndef DISASM_ONLY |
| 6339 | { |
| 6340 | 0xc00000007ffc0000ULL, |
| 6341 | 0xfffe000000000000ULL, |
| 6342 | 0ULL, |
| 6343 | 0ULL, |
| 6344 | 0ULL |
| 6345 | }, |
| 6346 | { |
| 6347 | 0x0000000052780000ULL, |
| 6348 | 0x28d2000000000000ULL, |
| 6349 | -1ULL, |
| 6350 | -1ULL, |
| 6351 | -1ULL |
| 6352 | } |
| 6353 | #endif |
| 6354 | }, |
| 6355 | { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1, |
| 6356 | { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, |
| 6357 | #ifndef DISASM_ONLY |
| 6358 | { |
| 6359 | 0ULL, |
| 6360 | 0xfffff80000000000ULL, |
| 6361 | 0ULL, |
| 6362 | 0ULL, |
| 6363 | 0ULL |
| 6364 | }, |
| 6365 | { |
| 6366 | -1ULL, |
| 6367 | 0x286b300000000000ULL, |
| 6368 | -1ULL, |
| 6369 | -1ULL, |
| 6370 | -1ULL |
| 6371 | } |
| 6372 | #endif |
| 6373 | }, |
| 6374 | { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1, |
| 6375 | { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, |
| 6376 | #ifndef DISASM_ONLY |
| 6377 | { |
| 6378 | 0xc00000007ffc0000ULL, |
| 6379 | 0xfffe000000000000ULL, |
| 6380 | 0x00000000780c0000ULL, |
| 6381 | 0x3c06000000000000ULL, |
| 6382 | 0ULL |
| 6383 | }, |
| 6384 | { |
| 6385 | 0x0000000052800000ULL, |
| 6386 | 0x28d6000000000000ULL, |
| 6387 | 0x00000000500c0000ULL, |
| 6388 | 0x2c06000000000000ULL, |
| 6389 | -1ULL |
| 6390 | } |
| 6391 | #endif |
| 6392 | }, |
| 6393 | { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1, |
| 6394 | { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, |
| 6395 | #ifndef DISASM_ONLY |
| 6396 | { |
| 6397 | 0xc00000007ff00000ULL, |
| 6398 | 0xfff8000000000000ULL, |
| 6399 | 0ULL, |
| 6400 | 0ULL, |
| 6401 | 0ULL |
| 6402 | }, |
| 6403 | { |
| 6404 | 0x0000000041400000ULL, |
| 6405 | 0x1968000000000000ULL, |
| 6406 | -1ULL, |
| 6407 | -1ULL, |
| 6408 | -1ULL |
| 6409 | } |
| 6410 | #endif |
| 6411 | }, |
| 6412 | { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, |
| 6413 | #ifndef DISASM_ONLY |
| 6414 | { 0, }, { 0, } |
| 6415 | #endif |
| 6416 | } |
| 6417 | }; |
| 6418 | #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) |
| 6419 | #define CHILD(array_index) (TILEGX_OPC_NONE + (array_index)) |
| 6420 | |
| 6421 | static const unsigned short decode_X0_fsm[936] = |
| 6422 | { |
| 6423 | BITFIELD(22, 9) /* index 0 */, |
| 6424 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6425 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6426 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6427 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6428 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6429 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6430 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6431 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6432 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6433 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6434 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6435 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6436 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6437 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6438 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6439 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6440 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6441 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6442 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6443 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6444 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6445 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6446 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6447 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6448 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6449 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6450 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI, |
| 6451 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6452 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6453 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6454 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6455 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6456 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6457 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6458 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6459 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6460 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6461 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6462 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6463 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6464 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6465 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6466 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE, |
| 6467 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6468 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6469 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6470 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS, |
| 6471 | TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU, |
| 6472 | TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS, |
| 6473 | TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM, |
| 6474 | TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE, |
| 6475 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6476 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6477 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6478 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6479 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6480 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6481 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6482 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578), |
| 6483 | CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE, |
| 6484 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6485 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6486 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6487 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6488 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6489 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6490 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6491 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6492 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6493 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6494 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6495 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6496 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6497 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6498 | TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671), |
| 6499 | CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865), |
| 6500 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6501 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6502 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6503 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6504 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6505 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6506 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6507 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6508 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6509 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6510 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6511 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6512 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6513 | TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6514 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6515 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6516 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6517 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6518 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6519 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6520 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6521 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6522 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6523 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6524 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6525 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6526 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6527 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6528 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6529 | TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6530 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6531 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6532 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6533 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6534 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6535 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6536 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6537 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6538 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6539 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), |
| 6540 | BITFIELD(6, 2) /* index 513 */, |
| 6541 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518), |
| 6542 | BITFIELD(8, 2) /* index 518 */, |
| 6543 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523), |
| 6544 | BITFIELD(10, 2) /* index 523 */, |
| 6545 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI, |
| 6546 | BITFIELD(20, 2) /* index 528 */, |
| 6547 | TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548), |
| 6548 | BITFIELD(6, 2) /* index 533 */, |
| 6549 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538), |
| 6550 | BITFIELD(8, 2) /* index 538 */, |
| 6551 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543), |
| 6552 | BITFIELD(10, 2) /* index 543 */, |
| 6553 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, |
| 6554 | BITFIELD(0, 2) /* index 548 */, |
| 6555 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553), |
| 6556 | BITFIELD(2, 2) /* index 553 */, |
| 6557 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558), |
| 6558 | BITFIELD(4, 2) /* index 558 */, |
| 6559 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563), |
| 6560 | BITFIELD(6, 2) /* index 563 */, |
| 6561 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568), |
| 6562 | BITFIELD(8, 2) /* index 568 */, |
| 6563 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573), |
| 6564 | BITFIELD(10, 2) /* index 573 */, |
| 6565 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, |
| 6566 | BITFIELD(20, 2) /* index 578 */, |
| 6567 | TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI, |
| 6568 | BITFIELD(20, 2) /* index 583 */, |
| 6569 | TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI, |
| 6570 | TILEGX_OPC_V1CMPLTUI, |
| 6571 | BITFIELD(20, 2) /* index 588 */, |
| 6572 | TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI, |
| 6573 | TILEGX_OPC_V2CMPEQI, |
| 6574 | BITFIELD(20, 2) /* index 593 */, |
| 6575 | TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI, |
| 6576 | TILEGX_OPC_V2MINSI, |
| 6577 | BITFIELD(20, 2) /* index 598 */, |
| 6578 | TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6579 | BITFIELD(18, 4) /* index 603 */, |
| 6580 | TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD, |
| 6581 | TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ, |
| 6582 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, |
| 6583 | TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR, |
| 6584 | BITFIELD(18, 4) /* index 620 */, |
| 6585 | TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL, |
| 6586 | TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2, |
| 6587 | TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN, |
| 6588 | TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS, |
| 6589 | TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1, |
| 6590 | TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS, |
| 6591 | BITFIELD(18, 4) /* index 637 */, |
| 6592 | TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN, |
| 6593 | TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2, |
| 6594 | TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2, |
| 6595 | TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX, |
| 6596 | TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS, |
| 6597 | TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS, |
| 6598 | BITFIELD(18, 4) /* index 654 */, |
| 6599 | TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU, |
| 6600 | TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS, |
| 6601 | TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU, |
| 6602 | TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU, |
| 6603 | TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU, |
| 6604 | TILEGX_OPC_MZ, |
| 6605 | BITFIELD(18, 4) /* index 671 */, |
| 6606 | TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX, |
| 6607 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD, |
| 6608 | TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL, |
| 6609 | TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES, |
| 6610 | TILEGX_OPC_SUBXSC, |
| 6611 | BITFIELD(12, 2) /* index 688 */, |
| 6612 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693), |
| 6613 | BITFIELD(14, 2) /* index 693 */, |
| 6614 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698), |
| 6615 | BITFIELD(16, 2) /* index 698 */, |
| 6616 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, |
| 6617 | BITFIELD(18, 4) /* index 703 */, |
| 6618 | TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC, |
| 6619 | TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU, |
| 6620 | TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU, |
| 6621 | TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE, |
| 6622 | TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA, |
| 6623 | BITFIELD(12, 4) /* index 720 */, |
| 6624 | TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757), |
| 6625 | CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787), |
| 6626 | CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6627 | BITFIELD(16, 2) /* index 737 */, |
| 6628 | TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6629 | BITFIELD(16, 2) /* index 742 */, |
| 6630 | TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6631 | BITFIELD(16, 2) /* index 747 */, |
| 6632 | TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6633 | BITFIELD(16, 2) /* index 752 */, |
| 6634 | TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6635 | BITFIELD(16, 2) /* index 757 */, |
| 6636 | TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6637 | BITFIELD(16, 2) /* index 762 */, |
| 6638 | TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6639 | BITFIELD(16, 2) /* index 767 */, |
| 6640 | TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6641 | BITFIELD(16, 2) /* index 772 */, |
| 6642 | TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6643 | BITFIELD(16, 2) /* index 777 */, |
| 6644 | TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6645 | BITFIELD(16, 2) /* index 782 */, |
| 6646 | TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6647 | BITFIELD(16, 2) /* index 787 */, |
| 6648 | TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6649 | BITFIELD(16, 2) /* index 792 */, |
| 6650 | TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6651 | BITFIELD(18, 4) /* index 797 */, |
| 6652 | TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP, |
| 6653 | TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU, |
| 6654 | TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS, |
| 6655 | TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU, |
| 6656 | TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, |
| 6657 | BITFIELD(18, 4) /* index 814 */, |
| 6658 | TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, |
| 6659 | TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS, |
| 6660 | TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, |
| 6661 | TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE, |
| 6662 | TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H, |
| 6663 | BITFIELD(18, 4) /* index 831 */, |
| 6664 | TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, |
| 6665 | TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ, |
| 6666 | TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC, |
| 6667 | TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS, |
| 6668 | TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC, |
| 6669 | BITFIELD(18, 4) /* index 848 */, |
| 6670 | TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC, |
| 6671 | TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H, |
| 6672 | TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC, |
| 6673 | TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC, |
| 6674 | TILEGX_OPC_V4SUB, |
| 6675 | BITFIELD(18, 3) /* index 865 */, |
| 6676 | CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE, |
| 6677 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6678 | BITFIELD(21, 1) /* index 874 */, |
| 6679 | TILEGX_OPC_XOR, TILEGX_OPC_NONE, |
| 6680 | BITFIELD(21, 1) /* index 877 */, |
| 6681 | TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE, |
| 6682 | BITFIELD(21, 1) /* index 880 */, |
| 6683 | TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE, |
| 6684 | BITFIELD(21, 1) /* index 883 */, |
| 6685 | TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE, |
| 6686 | BITFIELD(21, 1) /* index 886 */, |
| 6687 | TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE, |
| 6688 | BITFIELD(18, 4) /* index 889 */, |
| 6689 | TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI, |
| 6690 | TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI, |
| 6691 | TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI, |
| 6692 | TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6693 | TILEGX_OPC_NONE, |
| 6694 | BITFIELD(0, 2) /* index 906 */, |
| 6695 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 6696 | CHILD(911), |
| 6697 | BITFIELD(2, 2) /* index 911 */, |
| 6698 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 6699 | CHILD(916), |
| 6700 | BITFIELD(4, 2) /* index 916 */, |
| 6701 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 6702 | CHILD(921), |
| 6703 | BITFIELD(6, 2) /* index 921 */, |
| 6704 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 6705 | CHILD(926), |
| 6706 | BITFIELD(8, 2) /* index 926 */, |
| 6707 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 6708 | CHILD(931), |
| 6709 | BITFIELD(10, 2) /* index 931 */, |
| 6710 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 6711 | TILEGX_OPC_INFOL, |
| 6712 | }; |
| 6713 | |
| 6714 | static const unsigned short decode_X1_fsm[1266] = |
| 6715 | { |
| 6716 | BITFIELD(53, 9) /* index 0 */, |
| 6717 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6718 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6719 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6720 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6721 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6722 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6723 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6724 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6725 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6726 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), |
| 6727 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI, |
| 6728 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6729 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6730 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6731 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6732 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6733 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6734 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6735 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6736 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6737 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6738 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6739 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6740 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6741 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6742 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, |
| 6743 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE, |
| 6744 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6745 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6746 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6747 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6748 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6749 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6750 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6751 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT, |
| 6752 | TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT, |
| 6753 | TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT, |
| 6754 | TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT, |
| 6755 | TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST, |
| 6756 | TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT, |
| 6757 | TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT, |
| 6758 | TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT, |
| 6759 | TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578), |
| 6760 | CHILD(598), CHILD(703), CHILD(723), CHILD(728), CHILD(753), CHILD(758), |
| 6761 | CHILD(763), CHILD(768), CHILD(773), CHILD(778), TILEGX_OPC_NONE, |
| 6762 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6763 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6764 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6765 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6766 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6767 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6768 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6769 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6770 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6771 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6772 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6773 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6774 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL, |
| 6775 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6776 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6777 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6778 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6779 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6780 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6781 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, |
| 6782 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6783 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6784 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6785 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6786 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6787 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6788 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, |
| 6789 | CHILD(783), CHILD(800), CHILD(832), CHILD(849), CHILD(1168), CHILD(1185), |
| 6790 | CHILD(1202), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6791 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6792 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6793 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6794 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6795 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6796 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6797 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6798 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6799 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6800 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6801 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6802 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6803 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6804 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1219), TILEGX_OPC_NONE, |
| 6805 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6806 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6807 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6808 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6809 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6810 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6811 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6812 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6813 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6814 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6815 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6816 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6817 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6818 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6819 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6820 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1236), CHILD(1236), CHILD(1236), |
| 6821 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6822 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6823 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6824 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6825 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6826 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6827 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6828 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6829 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6830 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6831 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6832 | CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), |
| 6833 | CHILD(1236), |
| 6834 | BITFIELD(37, 2) /* index 513 */, |
| 6835 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518), |
| 6836 | BITFIELD(39, 2) /* index 518 */, |
| 6837 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523), |
| 6838 | BITFIELD(41, 2) /* index 523 */, |
| 6839 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI, |
| 6840 | BITFIELD(51, 2) /* index 528 */, |
| 6841 | TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548), |
| 6842 | BITFIELD(37, 2) /* index 533 */, |
| 6843 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538), |
| 6844 | BITFIELD(39, 2) /* index 538 */, |
| 6845 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543), |
| 6846 | BITFIELD(41, 2) /* index 543 */, |
| 6847 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, |
| 6848 | BITFIELD(31, 2) /* index 548 */, |
| 6849 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553), |
| 6850 | BITFIELD(33, 2) /* index 553 */, |
| 6851 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558), |
| 6852 | BITFIELD(35, 2) /* index 558 */, |
| 6853 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563), |
| 6854 | BITFIELD(37, 2) /* index 563 */, |
| 6855 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568), |
| 6856 | BITFIELD(39, 2) /* index 568 */, |
| 6857 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573), |
| 6858 | BITFIELD(41, 2) /* index 573 */, |
| 6859 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, |
| 6860 | BITFIELD(51, 2) /* index 578 */, |
| 6861 | TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583), |
| 6862 | BITFIELD(31, 2) /* index 583 */, |
| 6863 | TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588), |
| 6864 | BITFIELD(33, 2) /* index 588 */, |
| 6865 | TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593), |
| 6866 | BITFIELD(35, 2) /* index 593 */, |
| 6867 | TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, |
| 6868 | TILEGX_OPC_PREFETCH_ADD_L1_FAULT, |
| 6869 | BITFIELD(51, 2) /* index 598 */, |
| 6870 | CHILD(603), CHILD(618), CHILD(633), CHILD(648), |
| 6871 | BITFIELD(31, 2) /* index 603 */, |
| 6872 | TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608), |
| 6873 | BITFIELD(33, 2) /* index 608 */, |
| 6874 | TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613), |
| 6875 | BITFIELD(35, 2) /* index 613 */, |
| 6876 | TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, |
| 6877 | TILEGX_OPC_PREFETCH_ADD_L1, |
| 6878 | BITFIELD(31, 2) /* index 618 */, |
| 6879 | TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623), |
| 6880 | BITFIELD(33, 2) /* index 623 */, |
| 6881 | TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628), |
| 6882 | BITFIELD(35, 2) /* index 628 */, |
| 6883 | TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, |
| 6884 | TILEGX_OPC_PREFETCH_ADD_L2_FAULT, |
| 6885 | BITFIELD(31, 2) /* index 633 */, |
| 6886 | TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638), |
| 6887 | BITFIELD(33, 2) /* index 638 */, |
| 6888 | TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643), |
| 6889 | BITFIELD(35, 2) /* index 643 */, |
| 6890 | TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, |
| 6891 | TILEGX_OPC_PREFETCH_ADD_L2, |
| 6892 | BITFIELD(31, 2) /* index 648 */, |
| 6893 | CHILD(653), CHILD(653), CHILD(653), CHILD(673), |
| 6894 | BITFIELD(43, 2) /* index 653 */, |
| 6895 | CHILD(658), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, |
| 6896 | BITFIELD(45, 2) /* index 658 */, |
| 6897 | CHILD(663), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, |
| 6898 | BITFIELD(47, 2) /* index 663 */, |
| 6899 | CHILD(668), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, |
| 6900 | BITFIELD(49, 2) /* index 668 */, |
| 6901 | TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, |
| 6902 | TILEGX_OPC_LD4S_ADD, |
| 6903 | BITFIELD(33, 2) /* index 673 */, |
| 6904 | CHILD(653), CHILD(653), CHILD(653), CHILD(678), |
| 6905 | BITFIELD(35, 2) /* index 678 */, |
| 6906 | CHILD(653), CHILD(653), CHILD(653), CHILD(683), |
| 6907 | BITFIELD(43, 2) /* index 683 */, |
| 6908 | CHILD(688), TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6909 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6910 | BITFIELD(45, 2) /* index 688 */, |
| 6911 | CHILD(693), TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6912 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6913 | BITFIELD(47, 2) /* index 693 */, |
| 6914 | CHILD(698), TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6915 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6916 | BITFIELD(49, 2) /* index 698 */, |
| 6917 | TILEGX_OPC_LD4S_TLS, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6918 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, |
| 6919 | BITFIELD(51, 2) /* index 703 */, |
| 6920 | CHILD(708), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD, |
| 6921 | TILEGX_OPC_LDNT2S_ADD, |
| 6922 | BITFIELD(31, 2) /* index 708 */, |
| 6923 | TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(713), |
| 6924 | BITFIELD(33, 2) /* index 713 */, |
| 6925 | TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(718), |
| 6926 | BITFIELD(35, 2) /* index 718 */, |
| 6927 | TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, |
| 6928 | TILEGX_OPC_PREFETCH_ADD_L3, |
| 6929 | BITFIELD(51, 2) /* index 723 */, |
| 6930 | TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD, |
| 6931 | TILEGX_OPC_LDNT_ADD, |
| 6932 | BITFIELD(51, 2) /* index 728 */, |
| 6933 | CHILD(733), TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR, |
| 6934 | BITFIELD(43, 2) /* index 733 */, |
| 6935 | CHILD(738), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, |
| 6936 | BITFIELD(45, 2) /* index 738 */, |
| 6937 | CHILD(743), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, |
| 6938 | BITFIELD(47, 2) /* index 743 */, |
| 6939 | CHILD(748), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, |
| 6940 | BITFIELD(49, 2) /* index 748 */, |
| 6941 | TILEGX_OPC_LD_TLS, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, |
| 6942 | BITFIELD(51, 2) /* index 753 */, |
| 6943 | TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD, |
| 6944 | BITFIELD(51, 2) /* index 758 */, |
| 6945 | TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD, |
| 6946 | TILEGX_OPC_STNT_ADD, |
| 6947 | BITFIELD(51, 2) /* index 763 */, |
| 6948 | TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, |
| 6949 | TILEGX_OPC_V1CMPLTSI, |
| 6950 | BITFIELD(51, 2) /* index 768 */, |
| 6951 | TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, |
| 6952 | TILEGX_OPC_V2ADDI, |
| 6953 | BITFIELD(51, 2) /* index 773 */, |
| 6954 | TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, |
| 6955 | TILEGX_OPC_V2MAXSI, |
| 6956 | BITFIELD(51, 2) /* index 778 */, |
| 6957 | TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6958 | BITFIELD(49, 4) /* index 783 */, |
| 6959 | TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD, |
| 6960 | TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH, |
| 6961 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, |
| 6962 | TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4, |
| 6963 | TILEGX_OPC_DBLALIGN6, |
| 6964 | BITFIELD(49, 4) /* index 800 */, |
| 6965 | TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4, |
| 6966 | TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD, |
| 6967 | TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4, |
| 6968 | TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR, |
| 6969 | CHILD(817), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX, |
| 6970 | BITFIELD(43, 2) /* index 817 */, |
| 6971 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(822), |
| 6972 | BITFIELD(45, 2) /* index 822 */, |
| 6973 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(827), |
| 6974 | BITFIELD(47, 2) /* index 827 */, |
| 6975 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, |
| 6976 | BITFIELD(49, 4) /* index 832 */, |
| 6977 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD, |
| 6978 | TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL, |
| 6979 | TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1, |
| 6980 | TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2, |
| 6981 | TILEGX_OPC_STNT4, |
| 6982 | BITFIELD(46, 7) /* index 849 */, |
| 6983 | TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, |
| 6984 | TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, |
| 6985 | TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, |
| 6986 | TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC, |
| 6987 | TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, |
| 6988 | TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX, |
| 6989 | TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, |
| 6990 | TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, |
| 6991 | TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, |
| 6992 | TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(978), CHILD(987), |
| 6993 | CHILD(1066), CHILD(1150), CHILD(1159), TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 6994 | TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, |
| 6995 | TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, |
| 6996 | TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, |
| 6997 | TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, |
| 6998 | TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, |
| 6999 | TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, |
| 7000 | TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, |
| 7001 | TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, |
| 7002 | TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, |
| 7003 | TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU, |
| 7004 | TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, |
| 7005 | TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, |
| 7006 | TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, |
| 7007 | TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, |
| 7008 | TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, |
| 7009 | TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, |
| 7010 | TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, |
| 7011 | TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE, |
| 7012 | TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, |
| 7013 | TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, |
| 7014 | TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, |
| 7015 | TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, |
| 7016 | TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, |
| 7017 | TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, |
| 7018 | TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, |
| 7019 | TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, |
| 7020 | BITFIELD(43, 3) /* index 978 */, |
| 7021 | TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV, |
| 7022 | TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH, |
| 7023 | BITFIELD(43, 3) /* index 987 */, |
| 7024 | CHILD(996), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP, |
| 7025 | TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(1051), |
| 7026 | BITFIELD(31, 2) /* index 996 */, |
| 7027 | CHILD(1001), CHILD(1026), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7028 | BITFIELD(33, 2) /* index 1001 */, |
| 7029 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1006), |
| 7030 | BITFIELD(35, 2) /* index 1006 */, |
| 7031 | TILEGX_OPC_ILL, CHILD(1011), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7032 | BITFIELD(37, 2) /* index 1011 */, |
| 7033 | TILEGX_OPC_ILL, CHILD(1016), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7034 | BITFIELD(39, 2) /* index 1016 */, |
| 7035 | TILEGX_OPC_ILL, CHILD(1021), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7036 | BITFIELD(41, 2) /* index 1021 */, |
| 7037 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL, |
| 7038 | BITFIELD(33, 2) /* index 1026 */, |
| 7039 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1031), |
| 7040 | BITFIELD(35, 2) /* index 1031 */, |
| 7041 | TILEGX_OPC_ILL, CHILD(1036), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7042 | BITFIELD(37, 2) /* index 1036 */, |
| 7043 | TILEGX_OPC_ILL, CHILD(1041), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7044 | BITFIELD(39, 2) /* index 1041 */, |
| 7045 | TILEGX_OPC_ILL, CHILD(1046), TILEGX_OPC_ILL, TILEGX_OPC_ILL, |
| 7046 | BITFIELD(41, 2) /* index 1046 */, |
| 7047 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL, |
| 7048 | BITFIELD(31, 2) /* index 1051 */, |
| 7049 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1056), |
| 7050 | BITFIELD(33, 2) /* index 1056 */, |
| 7051 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1061), |
| 7052 | BITFIELD(35, 2) /* index 1061 */, |
| 7053 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, |
| 7054 | TILEGX_OPC_PREFETCH_L1_FAULT, |
| 7055 | BITFIELD(43, 3) /* index 1066 */, |
| 7056 | CHILD(1075), CHILD(1090), CHILD(1105), CHILD(1120), CHILD(1135), |
| 7057 | TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U, |
| 7058 | BITFIELD(31, 2) /* index 1075 */, |
| 7059 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1080), |
| 7060 | BITFIELD(33, 2) /* index 1080 */, |
| 7061 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1085), |
| 7062 | BITFIELD(35, 2) /* index 1085 */, |
| 7063 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH, |
| 7064 | BITFIELD(31, 2) /* index 1090 */, |
| 7065 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1095), |
| 7066 | BITFIELD(33, 2) /* index 1095 */, |
| 7067 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1100), |
| 7068 | BITFIELD(35, 2) /* index 1100 */, |
| 7069 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, |
| 7070 | TILEGX_OPC_PREFETCH_L2_FAULT, |
| 7071 | BITFIELD(31, 2) /* index 1105 */, |
| 7072 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1110), |
| 7073 | BITFIELD(33, 2) /* index 1110 */, |
| 7074 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1115), |
| 7075 | BITFIELD(35, 2) /* index 1115 */, |
| 7076 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2, |
| 7077 | BITFIELD(31, 2) /* index 1120 */, |
| 7078 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1125), |
| 7079 | BITFIELD(33, 2) /* index 1125 */, |
| 7080 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1130), |
| 7081 | BITFIELD(35, 2) /* index 1130 */, |
| 7082 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, |
| 7083 | TILEGX_OPC_PREFETCH_L3_FAULT, |
| 7084 | BITFIELD(31, 2) /* index 1135 */, |
| 7085 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1140), |
| 7086 | BITFIELD(33, 2) /* index 1140 */, |
| 7087 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1145), |
| 7088 | BITFIELD(35, 2) /* index 1145 */, |
| 7089 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3, |
| 7090 | BITFIELD(43, 3) /* index 1150 */, |
| 7091 | TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U, |
| 7092 | TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF, |
| 7093 | BITFIELD(43, 3) /* index 1159 */, |
| 7094 | TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1, |
| 7095 | TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE, |
| 7096 | BITFIELD(49, 4) /* index 1168 */, |
| 7097 | TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ, |
| 7098 | TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, |
| 7099 | TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ, |
| 7100 | TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS, |
| 7101 | TILEGX_OPC_V2CMPLTU, |
| 7102 | BITFIELD(49, 4) /* index 1185 */, |
| 7103 | TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L, |
| 7104 | TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ, |
| 7105 | TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC, |
| 7106 | TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, |
| 7107 | TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB, |
| 7108 | BITFIELD(49, 4) /* index 1202 */, |
| 7109 | TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H, |
| 7110 | TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC, |
| 7111 | TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC, |
| 7112 | TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7113 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7114 | BITFIELD(49, 4) /* index 1219 */, |
| 7115 | TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI, |
| 7116 | TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI, |
| 7117 | TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI, |
| 7118 | TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7119 | TILEGX_OPC_NONE, |
| 7120 | BITFIELD(31, 2) /* index 1236 */, |
| 7121 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 7122 | CHILD(1241), |
| 7123 | BITFIELD(33, 2) /* index 1241 */, |
| 7124 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 7125 | CHILD(1246), |
| 7126 | BITFIELD(35, 2) /* index 1246 */, |
| 7127 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 7128 | CHILD(1251), |
| 7129 | BITFIELD(37, 2) /* index 1251 */, |
| 7130 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 7131 | CHILD(1256), |
| 7132 | BITFIELD(39, 2) /* index 1256 */, |
| 7133 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 7134 | CHILD(1261), |
| 7135 | BITFIELD(41, 2) /* index 1261 */, |
| 7136 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, |
| 7137 | TILEGX_OPC_INFOL, |
| 7138 | }; |
| 7139 | |
| 7140 | static const unsigned short decode_Y0_fsm[178] = |
| 7141 | { |
| 7142 | BITFIELD(27, 4) /* index 0 */, |
| 7143 | CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI, |
| 7144 | TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123), |
| 7145 | CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168), |
| 7146 | CHILD(173), |
| 7147 | BITFIELD(6, 2) /* index 17 */, |
| 7148 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22), |
| 7149 | BITFIELD(8, 2) /* index 22 */, |
| 7150 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27), |
| 7151 | BITFIELD(10, 2) /* index 27 */, |
| 7152 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, |
| 7153 | BITFIELD(0, 2) /* index 32 */, |
| 7154 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37), |
| 7155 | BITFIELD(2, 2) /* index 37 */, |
| 7156 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42), |
| 7157 | BITFIELD(4, 2) /* index 42 */, |
| 7158 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47), |
| 7159 | BITFIELD(6, 2) /* index 47 */, |
| 7160 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52), |
| 7161 | BITFIELD(8, 2) /* index 52 */, |
| 7162 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57), |
| 7163 | BITFIELD(10, 2) /* index 57 */, |
| 7164 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, |
| 7165 | BITFIELD(18, 2) /* index 62 */, |
| 7166 | TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, |
| 7167 | BITFIELD(15, 5) /* index 67 */, |
| 7168 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, |
| 7169 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, |
| 7170 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, |
| 7171 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, |
| 7172 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, |
| 7173 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, |
| 7174 | TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, |
| 7175 | TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100), |
| 7176 | CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7177 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7178 | BITFIELD(12, 3) /* index 100 */, |
| 7179 | TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP, |
| 7180 | TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT, |
| 7181 | TILEGX_OPC_REVBITS, |
| 7182 | BITFIELD(12, 3) /* index 109 */, |
| 7183 | TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1, |
| 7184 | TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7185 | TILEGX_OPC_NONE, |
| 7186 | BITFIELD(18, 2) /* index 118 */, |
| 7187 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, |
| 7188 | BITFIELD(18, 2) /* index 123 */, |
| 7189 | TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX, |
| 7190 | BITFIELD(18, 2) /* index 128 */, |
| 7191 | TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, |
| 7192 | BITFIELD(18, 2) /* index 133 */, |
| 7193 | TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR, |
| 7194 | BITFIELD(12, 2) /* index 138 */, |
| 7195 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143), |
| 7196 | BITFIELD(14, 2) /* index 143 */, |
| 7197 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148), |
| 7198 | BITFIELD(16, 2) /* index 148 */, |
| 7199 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, |
| 7200 | BITFIELD(18, 2) /* index 153 */, |
| 7201 | TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU, |
| 7202 | BITFIELD(18, 2) /* index 158 */, |
| 7203 | TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX, |
| 7204 | TILEGX_OPC_SHL3ADDX, |
| 7205 | BITFIELD(18, 2) /* index 163 */, |
| 7206 | TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS, |
| 7207 | TILEGX_OPC_MUL_LU_LU, |
| 7208 | BITFIELD(18, 2) /* index 168 */, |
| 7209 | TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS, |
| 7210 | TILEGX_OPC_MULA_LU_LU, |
| 7211 | BITFIELD(18, 2) /* index 173 */, |
| 7212 | TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, |
| 7213 | }; |
| 7214 | |
| 7215 | static const unsigned short decode_Y1_fsm[167] = |
| 7216 | { |
| 7217 | BITFIELD(58, 4) /* index 0 */, |
| 7218 | TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI, |
| 7219 | TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122), |
| 7220 | CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE, |
| 7221 | BITFIELD(37, 2) /* index 17 */, |
| 7222 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22), |
| 7223 | BITFIELD(39, 2) /* index 22 */, |
| 7224 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27), |
| 7225 | BITFIELD(41, 2) /* index 27 */, |
| 7226 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, |
| 7227 | BITFIELD(31, 2) /* index 32 */, |
| 7228 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37), |
| 7229 | BITFIELD(33, 2) /* index 37 */, |
| 7230 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42), |
| 7231 | BITFIELD(35, 2) /* index 42 */, |
| 7232 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47), |
| 7233 | BITFIELD(37, 2) /* index 47 */, |
| 7234 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52), |
| 7235 | BITFIELD(39, 2) /* index 52 */, |
| 7236 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57), |
| 7237 | BITFIELD(41, 2) /* index 57 */, |
| 7238 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, |
| 7239 | BITFIELD(49, 2) /* index 62 */, |
| 7240 | TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, |
| 7241 | BITFIELD(47, 4) /* index 67 */, |
| 7242 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, |
| 7243 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, |
| 7244 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, |
| 7245 | TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84), |
| 7246 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, |
| 7247 | BITFIELD(43, 3) /* index 84 */, |
| 7248 | CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108), |
| 7249 | CHILD(111), CHILD(114), |
| 7250 | BITFIELD(46, 1) /* index 93 */, |
| 7251 | TILEGX_OPC_NONE, TILEGX_OPC_FNOP, |
| 7252 | BITFIELD(46, 1) /* index 96 */, |
| 7253 | TILEGX_OPC_NONE, TILEGX_OPC_ILL, |
| 7254 | BITFIELD(46, 1) /* index 99 */, |
| 7255 | TILEGX_OPC_NONE, TILEGX_OPC_JALRP, |
| 7256 | BITFIELD(46, 1) /* index 102 */, |
| 7257 | TILEGX_OPC_NONE, TILEGX_OPC_JALR, |
| 7258 | BITFIELD(46, 1) /* index 105 */, |
| 7259 | TILEGX_OPC_NONE, TILEGX_OPC_JRP, |
| 7260 | BITFIELD(46, 1) /* index 108 */, |
| 7261 | TILEGX_OPC_NONE, TILEGX_OPC_JR, |
| 7262 | BITFIELD(46, 1) /* index 111 */, |
| 7263 | TILEGX_OPC_NONE, TILEGX_OPC_LNK, |
| 7264 | BITFIELD(46, 1) /* index 114 */, |
| 7265 | TILEGX_OPC_NONE, TILEGX_OPC_NOP, |
| 7266 | BITFIELD(49, 2) /* index 117 */, |
| 7267 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, |
| 7268 | BITFIELD(49, 2) /* index 122 */, |
| 7269 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, |
| 7270 | BITFIELD(49, 2) /* index 127 */, |
| 7271 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, |
| 7272 | BITFIELD(49, 2) /* index 132 */, |
| 7273 | TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR, |
| 7274 | BITFIELD(43, 2) /* index 137 */, |
| 7275 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142), |
| 7276 | BITFIELD(45, 2) /* index 142 */, |
| 7277 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147), |
| 7278 | BITFIELD(47, 2) /* index 147 */, |
| 7279 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, |
| 7280 | BITFIELD(49, 2) /* index 152 */, |
| 7281 | TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU, |
| 7282 | BITFIELD(49, 2) /* index 157 */, |
| 7283 | TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX, |
| 7284 | TILEGX_OPC_SHL3ADDX, |
| 7285 | BITFIELD(49, 2) /* index 162 */, |
| 7286 | TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, |
| 7287 | }; |
| 7288 | |
| 7289 | static const unsigned short decode_Y2_fsm[118] = |
| 7290 | { |
| 7291 | BITFIELD(62, 2) /* index 0 */, |
| 7292 | TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109), |
| 7293 | BITFIELD(55, 3) /* index 5 */, |
| 7294 | CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40), |
| 7295 | CHILD(43), |
| 7296 | BITFIELD(26, 1) /* index 14 */, |
| 7297 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1U, |
| 7298 | BITFIELD(26, 1) /* index 17 */, |
| 7299 | CHILD(20), CHILD(30), |
| 7300 | BITFIELD(51, 2) /* index 20 */, |
| 7301 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25), |
| 7302 | BITFIELD(53, 2) /* index 25 */, |
| 7303 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, |
| 7304 | TILEGX_OPC_PREFETCH_L1_FAULT, |
| 7305 | BITFIELD(51, 2) /* index 30 */, |
| 7306 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35), |
| 7307 | BITFIELD(53, 2) /* index 35 */, |
| 7308 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH, |
| 7309 | BITFIELD(26, 1) /* index 40 */, |
| 7310 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2U, |
| 7311 | BITFIELD(26, 1) /* index 43 */, |
| 7312 | CHILD(46), CHILD(56), |
| 7313 | BITFIELD(51, 2) /* index 46 */, |
| 7314 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51), |
| 7315 | BITFIELD(53, 2) /* index 51 */, |
| 7316 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, |
| 7317 | TILEGX_OPC_PREFETCH_L2_FAULT, |
| 7318 | BITFIELD(51, 2) /* index 56 */, |
| 7319 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61), |
| 7320 | BITFIELD(53, 2) /* index 61 */, |
| 7321 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2, |
| 7322 | BITFIELD(56, 2) /* index 66 */, |
| 7323 | CHILD(71), CHILD(74), CHILD(90), CHILD(93), |
| 7324 | BITFIELD(26, 1) /* index 71 */, |
| 7325 | TILEGX_OPC_NONE, TILEGX_OPC_LD4S, |
| 7326 | BITFIELD(26, 1) /* index 74 */, |
| 7327 | TILEGX_OPC_NONE, CHILD(77), |
| 7328 | BITFIELD(51, 2) /* index 77 */, |
| 7329 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82), |
| 7330 | BITFIELD(53, 2) /* index 82 */, |
| 7331 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87), |
| 7332 | BITFIELD(55, 1) /* index 87 */, |
| 7333 | TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT, |
| 7334 | BITFIELD(26, 1) /* index 90 */, |
| 7335 | TILEGX_OPC_LD4U, TILEGX_OPC_LD, |
| 7336 | BITFIELD(26, 1) /* index 93 */, |
| 7337 | CHILD(96), TILEGX_OPC_LD, |
| 7338 | BITFIELD(51, 2) /* index 96 */, |
| 7339 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101), |
| 7340 | BITFIELD(53, 2) /* index 101 */, |
| 7341 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106), |
| 7342 | BITFIELD(55, 1) /* index 106 */, |
| 7343 | TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3, |
| 7344 | BITFIELD(26, 1) /* index 109 */, |
| 7345 | CHILD(112), CHILD(115), |
| 7346 | BITFIELD(57, 1) /* index 112 */, |
| 7347 | TILEGX_OPC_ST1, TILEGX_OPC_ST4, |
| 7348 | BITFIELD(57, 1) /* index 115 */, |
| 7349 | TILEGX_OPC_ST2, TILEGX_OPC_ST, |
| 7350 | }; |
| 7351 | |
| 7352 | #undef BITFIELD |
| 7353 | #undef CHILD |
| 7354 | const unsigned short * const |
| 7355 | tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] = |
| 7356 | { |
| 7357 | decode_X0_fsm, |
| 7358 | decode_X1_fsm, |
| 7359 | decode_Y0_fsm, |
| 7360 | decode_Y1_fsm, |
| 7361 | decode_Y2_fsm |
| 7362 | }; |
| 7363 | const struct tilegx_operand tilegx_operands[35] = |
| 7364 | { |
| 7365 | { |
| 7366 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0), |
| 7367 | 8, 1, 0, 0, 0, 0, |
| 7368 | create_Imm8_X0, get_Imm8_X0 |
| 7369 | }, |
| 7370 | { |
| 7371 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1), |
| 7372 | 8, 1, 0, 0, 0, 0, |
| 7373 | create_Imm8_X1, get_Imm8_X1 |
| 7374 | }, |
| 7375 | { |
| 7376 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0), |
| 7377 | 8, 1, 0, 0, 0, 0, |
| 7378 | create_Imm8_Y0, get_Imm8_Y0 |
| 7379 | }, |
| 7380 | { |
| 7381 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1), |
| 7382 | 8, 1, 0, 0, 0, 0, |
| 7383 | create_Imm8_Y1, get_Imm8_Y1 |
| 7384 | }, |
| 7385 | { |
| 7386 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST), |
| 7387 | 16, 1, 0, 0, 0, 0, |
| 7388 | create_Imm16_X0, get_Imm16_X0 |
| 7389 | }, |
| 7390 | { |
| 7391 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST), |
| 7392 | 16, 1, 0, 0, 0, 0, |
| 7393 | create_Imm16_X1, get_Imm16_X1 |
| 7394 | }, |
| 7395 | { |
| 7396 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7397 | 6, 0, 0, 1, 0, 0, |
| 7398 | create_Dest_X1, get_Dest_X1 |
| 7399 | }, |
| 7400 | { |
| 7401 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7402 | 6, 0, 1, 0, 0, 0, |
| 7403 | create_SrcA_X1, get_SrcA_X1 |
| 7404 | }, |
| 7405 | { |
| 7406 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7407 | 6, 0, 0, 1, 0, 0, |
| 7408 | create_Dest_X0, get_Dest_X0 |
| 7409 | }, |
| 7410 | { |
| 7411 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7412 | 6, 0, 1, 0, 0, 0, |
| 7413 | create_SrcA_X0, get_SrcA_X0 |
| 7414 | }, |
| 7415 | { |
| 7416 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7417 | 6, 0, 0, 1, 0, 0, |
| 7418 | create_Dest_Y0, get_Dest_Y0 |
| 7419 | }, |
| 7420 | { |
| 7421 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7422 | 6, 0, 1, 0, 0, 0, |
| 7423 | create_SrcA_Y0, get_SrcA_Y0 |
| 7424 | }, |
| 7425 | { |
| 7426 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7427 | 6, 0, 0, 1, 0, 0, |
| 7428 | create_Dest_Y1, get_Dest_Y1 |
| 7429 | }, |
| 7430 | { |
| 7431 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7432 | 6, 0, 1, 0, 0, 0, |
| 7433 | create_SrcA_Y1, get_SrcA_Y1 |
| 7434 | }, |
| 7435 | { |
| 7436 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7437 | 6, 0, 1, 0, 0, 0, |
| 7438 | create_SrcA_Y2, get_SrcA_Y2 |
| 7439 | }, |
| 7440 | { |
| 7441 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7442 | 6, 0, 1, 1, 0, 0, |
| 7443 | create_SrcA_X1, get_SrcA_X1 |
| 7444 | }, |
| 7445 | { |
| 7446 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7447 | 6, 0, 1, 0, 0, 0, |
| 7448 | create_SrcB_X0, get_SrcB_X0 |
| 7449 | }, |
| 7450 | { |
| 7451 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7452 | 6, 0, 1, 0, 0, 0, |
| 7453 | create_SrcB_X1, get_SrcB_X1 |
| 7454 | }, |
| 7455 | { |
| 7456 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7457 | 6, 0, 1, 0, 0, 0, |
| 7458 | create_SrcB_Y0, get_SrcB_Y0 |
| 7459 | }, |
| 7460 | { |
| 7461 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7462 | 6, 0, 1, 0, 0, 0, |
| 7463 | create_SrcB_Y1, get_SrcB_Y1 |
| 7464 | }, |
| 7465 | { |
| 7466 | TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1), |
| 7467 | 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, |
| 7468 | create_BrOff_X1, get_BrOff_X1 |
| 7469 | }, |
| 7470 | { |
| 7471 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0), |
| 7472 | 6, 0, 0, 0, 0, 0, |
| 7473 | create_BFStart_X0, get_BFStart_X0 |
| 7474 | }, |
| 7475 | { |
| 7476 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0), |
| 7477 | 6, 0, 0, 0, 0, 0, |
| 7478 | create_BFEnd_X0, get_BFEnd_X0 |
| 7479 | }, |
| 7480 | { |
| 7481 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7482 | 6, 0, 1, 1, 0, 0, |
| 7483 | create_Dest_X0, get_Dest_X0 |
| 7484 | }, |
| 7485 | { |
| 7486 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7487 | 6, 0, 1, 1, 0, 0, |
| 7488 | create_Dest_Y0, get_Dest_Y0 |
| 7489 | }, |
| 7490 | { |
| 7491 | TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1), |
| 7492 | 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, |
| 7493 | create_JumpOff_X1, get_JumpOff_X1 |
| 7494 | }, |
| 7495 | { |
| 7496 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7497 | 6, 0, 0, 1, 0, 0, |
| 7498 | create_SrcBDest_Y2, get_SrcBDest_Y2 |
| 7499 | }, |
| 7500 | { |
| 7501 | TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1), |
| 7502 | 14, 0, 0, 0, 0, 0, |
| 7503 | create_MF_Imm14_X1, get_MF_Imm14_X1 |
| 7504 | }, |
| 7505 | { |
| 7506 | TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1), |
| 7507 | 14, 0, 0, 0, 0, 0, |
| 7508 | create_MT_Imm14_X1, get_MT_Imm14_X1 |
| 7509 | }, |
| 7510 | { |
| 7511 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0), |
| 7512 | 6, 0, 0, 0, 0, 0, |
| 7513 | create_ShAmt_X0, get_ShAmt_X0 |
| 7514 | }, |
| 7515 | { |
| 7516 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1), |
| 7517 | 6, 0, 0, 0, 0, 0, |
| 7518 | create_ShAmt_X1, get_ShAmt_X1 |
| 7519 | }, |
| 7520 | { |
| 7521 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0), |
| 7522 | 6, 0, 0, 0, 0, 0, |
| 7523 | create_ShAmt_Y0, get_ShAmt_Y0 |
| 7524 | }, |
| 7525 | { |
| 7526 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1), |
| 7527 | 6, 0, 0, 0, 0, 0, |
| 7528 | create_ShAmt_Y1, get_ShAmt_Y1 |
| 7529 | }, |
| 7530 | { |
| 7531 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
| 7532 | 6, 0, 1, 0, 0, 0, |
| 7533 | create_SrcBDest_Y2, get_SrcBDest_Y2 |
| 7534 | }, |
| 7535 | { |
| 7536 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1), |
| 7537 | 8, 1, 0, 0, 0, 0, |
| 7538 | create_Dest_Imm8_X1, get_Dest_Imm8_X1 |
| 7539 | } |
| 7540 | }; |
| 7541 | |
| 7542 | #ifndef DISASM_ONLY |
| 7543 | const struct tilegx_spr tilegx_sprs[] = { |
| 7544 | { 0, "MPL_MEM_ERROR_SET_0" }, |
| 7545 | { 1, "MPL_MEM_ERROR_SET_1" }, |
| 7546 | { 2, "MPL_MEM_ERROR_SET_2" }, |
| 7547 | { 3, "MPL_MEM_ERROR_SET_3" }, |
| 7548 | { 4, "MPL_MEM_ERROR" }, |
| 7549 | { 5, "MEM_ERROR_CBOX_ADDR" }, |
| 7550 | { 6, "MEM_ERROR_CBOX_STATUS" }, |
| 7551 | { 7, "MEM_ERROR_ENABLE" }, |
| 7552 | { 8, "MEM_ERROR_MBOX_ADDR" }, |
| 7553 | { 9, "MEM_ERROR_MBOX_STATUS" }, |
| 7554 | { 10, "SBOX_ERROR" }, |
| 7555 | { 11, "XDN_DEMUX_ERROR" }, |
| 7556 | { 256, "MPL_SINGLE_STEP_3_SET_0" }, |
| 7557 | { 257, "MPL_SINGLE_STEP_3_SET_1" }, |
| 7558 | { 258, "MPL_SINGLE_STEP_3_SET_2" }, |
| 7559 | { 259, "MPL_SINGLE_STEP_3_SET_3" }, |
| 7560 | { 260, "MPL_SINGLE_STEP_3" }, |
| 7561 | { 261, "SINGLE_STEP_CONTROL_3" }, |
| 7562 | { 512, "MPL_SINGLE_STEP_2_SET_0" }, |
| 7563 | { 513, "MPL_SINGLE_STEP_2_SET_1" }, |
| 7564 | { 514, "MPL_SINGLE_STEP_2_SET_2" }, |
| 7565 | { 515, "MPL_SINGLE_STEP_2_SET_3" }, |
| 7566 | { 516, "MPL_SINGLE_STEP_2" }, |
| 7567 | { 517, "SINGLE_STEP_CONTROL_2" }, |
| 7568 | { 768, "MPL_SINGLE_STEP_1_SET_0" }, |
| 7569 | { 769, "MPL_SINGLE_STEP_1_SET_1" }, |
| 7570 | { 770, "MPL_SINGLE_STEP_1_SET_2" }, |
| 7571 | { 771, "MPL_SINGLE_STEP_1_SET_3" }, |
| 7572 | { 772, "MPL_SINGLE_STEP_1" }, |
| 7573 | { 773, "SINGLE_STEP_CONTROL_1" }, |
| 7574 | { 1024, "MPL_SINGLE_STEP_0_SET_0" }, |
| 7575 | { 1025, "MPL_SINGLE_STEP_0_SET_1" }, |
| 7576 | { 1026, "MPL_SINGLE_STEP_0_SET_2" }, |
| 7577 | { 1027, "MPL_SINGLE_STEP_0_SET_3" }, |
| 7578 | { 1028, "MPL_SINGLE_STEP_0" }, |
| 7579 | { 1029, "SINGLE_STEP_CONTROL_0" }, |
| 7580 | { 1280, "MPL_IDN_COMPLETE_SET_0" }, |
| 7581 | { 1281, "MPL_IDN_COMPLETE_SET_1" }, |
| 7582 | { 1282, "MPL_IDN_COMPLETE_SET_2" }, |
| 7583 | { 1283, "MPL_IDN_COMPLETE_SET_3" }, |
| 7584 | { 1284, "MPL_IDN_COMPLETE" }, |
| 7585 | { 1285, "IDN_COMPLETE_PENDING" }, |
| 7586 | { 1536, "MPL_UDN_COMPLETE_SET_0" }, |
| 7587 | { 1537, "MPL_UDN_COMPLETE_SET_1" }, |
| 7588 | { 1538, "MPL_UDN_COMPLETE_SET_2" }, |
| 7589 | { 1539, "MPL_UDN_COMPLETE_SET_3" }, |
| 7590 | { 1540, "MPL_UDN_COMPLETE" }, |
| 7591 | { 1541, "UDN_COMPLETE_PENDING" }, |
| 7592 | { 1792, "MPL_ITLB_MISS_SET_0" }, |
| 7593 | { 1793, "MPL_ITLB_MISS_SET_1" }, |
| 7594 | { 1794, "MPL_ITLB_MISS_SET_2" }, |
| 7595 | { 1795, "MPL_ITLB_MISS_SET_3" }, |
| 7596 | { 1796, "MPL_ITLB_MISS" }, |
| 7597 | { 1797, "ITLB_TSB_BASE_ADDR_0" }, |
| 7598 | { 1798, "ITLB_TSB_BASE_ADDR_1" }, |
| 7599 | { 1920, "ITLB_CURRENT_ATTR" }, |
| 7600 | { 1921, "ITLB_CURRENT_PA" }, |
| 7601 | { 1922, "ITLB_CURRENT_VA" }, |
| 7602 | { 1923, "ITLB_INDEX" }, |
| 7603 | { 1924, "ITLB_MATCH_0" }, |
| 7604 | { 1925, "ITLB_PERF" }, |
| 7605 | { 1926, "ITLB_PR" }, |
| 7606 | { 1927, "ITLB_TSB_ADDR_0" }, |
| 7607 | { 1928, "ITLB_TSB_ADDR_1" }, |
| 7608 | { 1929, "ITLB_TSB_FILL_CURRENT_ATTR" }, |
| 7609 | { 1930, "ITLB_TSB_FILL_MATCH" }, |
| 7610 | { 1931, "NUMBER_ITLB" }, |
| 7611 | { 1932, "REPLACEMENT_ITLB" }, |
| 7612 | { 1933, "WIRED_ITLB" }, |
| 7613 | { 2048, "MPL_ILL_SET_0" }, |
| 7614 | { 2049, "MPL_ILL_SET_1" }, |
| 7615 | { 2050, "MPL_ILL_SET_2" }, |
| 7616 | { 2051, "MPL_ILL_SET_3" }, |
| 7617 | { 2052, "MPL_ILL" }, |
| 7618 | { 2304, "MPL_GPV_SET_0" }, |
| 7619 | { 2305, "MPL_GPV_SET_1" }, |
| 7620 | { 2306, "MPL_GPV_SET_2" }, |
| 7621 | { 2307, "MPL_GPV_SET_3" }, |
| 7622 | { 2308, "MPL_GPV" }, |
| 7623 | { 2309, "GPV_REASON" }, |
| 7624 | { 2560, "MPL_IDN_ACCESS_SET_0" }, |
| 7625 | { 2561, "MPL_IDN_ACCESS_SET_1" }, |
| 7626 | { 2562, "MPL_IDN_ACCESS_SET_2" }, |
| 7627 | { 2563, "MPL_IDN_ACCESS_SET_3" }, |
| 7628 | { 2564, "MPL_IDN_ACCESS" }, |
| 7629 | { 2565, "IDN_DEMUX_COUNT_0" }, |
| 7630 | { 2566, "IDN_DEMUX_COUNT_1" }, |
| 7631 | { 2567, "IDN_FLUSH_EGRESS" }, |
| 7632 | { 2568, "IDN_PENDING" }, |
| 7633 | { 2569, "IDN_ROUTE_ORDER" }, |
| 7634 | { 2570, "IDN_SP_FIFO_CNT" }, |
| 7635 | { 2688, "IDN_DATA_AVAIL" }, |
| 7636 | { 2816, "MPL_UDN_ACCESS_SET_0" }, |
| 7637 | { 2817, "MPL_UDN_ACCESS_SET_1" }, |
| 7638 | { 2818, "MPL_UDN_ACCESS_SET_2" }, |
| 7639 | { 2819, "MPL_UDN_ACCESS_SET_3" }, |
| 7640 | { 2820, "MPL_UDN_ACCESS" }, |
| 7641 | { 2821, "UDN_DEMUX_COUNT_0" }, |
| 7642 | { 2822, "UDN_DEMUX_COUNT_1" }, |
| 7643 | { 2823, "UDN_DEMUX_COUNT_2" }, |
| 7644 | { 2824, "UDN_DEMUX_COUNT_3" }, |
| 7645 | { 2825, "UDN_FLUSH_EGRESS" }, |
| 7646 | { 2826, "UDN_PENDING" }, |
| 7647 | { 2827, "UDN_ROUTE_ORDER" }, |
| 7648 | { 2828, "UDN_SP_FIFO_CNT" }, |
| 7649 | { 2944, "UDN_DATA_AVAIL" }, |
| 7650 | { 3072, "MPL_SWINT_3_SET_0" }, |
| 7651 | { 3073, "MPL_SWINT_3_SET_1" }, |
| 7652 | { 3074, "MPL_SWINT_3_SET_2" }, |
| 7653 | { 3075, "MPL_SWINT_3_SET_3" }, |
| 7654 | { 3076, "MPL_SWINT_3" }, |
| 7655 | { 3328, "MPL_SWINT_2_SET_0" }, |
| 7656 | { 3329, "MPL_SWINT_2_SET_1" }, |
| 7657 | { 3330, "MPL_SWINT_2_SET_2" }, |
| 7658 | { 3331, "MPL_SWINT_2_SET_3" }, |
| 7659 | { 3332, "MPL_SWINT_2" }, |
| 7660 | { 3584, "MPL_SWINT_1_SET_0" }, |
| 7661 | { 3585, "MPL_SWINT_1_SET_1" }, |
| 7662 | { 3586, "MPL_SWINT_1_SET_2" }, |
| 7663 | { 3587, "MPL_SWINT_1_SET_3" }, |
| 7664 | { 3588, "MPL_SWINT_1" }, |
| 7665 | { 3840, "MPL_SWINT_0_SET_0" }, |
| 7666 | { 3841, "MPL_SWINT_0_SET_1" }, |
| 7667 | { 3842, "MPL_SWINT_0_SET_2" }, |
| 7668 | { 3843, "MPL_SWINT_0_SET_3" }, |
| 7669 | { 3844, "MPL_SWINT_0" }, |
| 7670 | { 4096, "MPL_ILL_TRANS_SET_0" }, |
| 7671 | { 4097, "MPL_ILL_TRANS_SET_1" }, |
| 7672 | { 4098, "MPL_ILL_TRANS_SET_2" }, |
| 7673 | { 4099, "MPL_ILL_TRANS_SET_3" }, |
| 7674 | { 4100, "MPL_ILL_TRANS" }, |
| 7675 | { 4101, "ILL_TRANS_REASON" }, |
| 7676 | { 4102, "ILL_VA_PC" }, |
| 7677 | { 4352, "MPL_UNALIGN_DATA_SET_0" }, |
| 7678 | { 4353, "MPL_UNALIGN_DATA_SET_1" }, |
| 7679 | { 4354, "MPL_UNALIGN_DATA_SET_2" }, |
| 7680 | { 4355, "MPL_UNALIGN_DATA_SET_3" }, |
| 7681 | { 4356, "MPL_UNALIGN_DATA" }, |
| 7682 | { 4608, "MPL_DTLB_MISS_SET_0" }, |
| 7683 | { 4609, "MPL_DTLB_MISS_SET_1" }, |
| 7684 | { 4610, "MPL_DTLB_MISS_SET_2" }, |
| 7685 | { 4611, "MPL_DTLB_MISS_SET_3" }, |
| 7686 | { 4612, "MPL_DTLB_MISS" }, |
| 7687 | { 4613, "DTLB_TSB_BASE_ADDR_0" }, |
| 7688 | { 4614, "DTLB_TSB_BASE_ADDR_1" }, |
| 7689 | { 4736, "AAR" }, |
| 7690 | { 4737, "CACHE_PINNED_WAYS" }, |
| 7691 | { 4738, "DTLB_BAD_ADDR" }, |
| 7692 | { 4739, "DTLB_BAD_ADDR_REASON" }, |
| 7693 | { 4740, "DTLB_CURRENT_ATTR" }, |
| 7694 | { 4741, "DTLB_CURRENT_PA" }, |
| 7695 | { 4742, "DTLB_CURRENT_VA" }, |
| 7696 | { 4743, "DTLB_INDEX" }, |
| 7697 | { 4744, "DTLB_MATCH_0" }, |
| 7698 | { 4745, "DTLB_PERF" }, |
| 7699 | { 4746, "DTLB_TSB_ADDR_0" }, |
| 7700 | { 4747, "DTLB_TSB_ADDR_1" }, |
| 7701 | { 4748, "DTLB_TSB_FILL_CURRENT_ATTR" }, |
| 7702 | { 4749, "DTLB_TSB_FILL_MATCH" }, |
| 7703 | { 4750, "NUMBER_DTLB" }, |
| 7704 | { 4751, "REPLACEMENT_DTLB" }, |
| 7705 | { 4752, "WIRED_DTLB" }, |
| 7706 | { 4864, "MPL_DTLB_ACCESS_SET_0" }, |
| 7707 | { 4865, "MPL_DTLB_ACCESS_SET_1" }, |
| 7708 | { 4866, "MPL_DTLB_ACCESS_SET_2" }, |
| 7709 | { 4867, "MPL_DTLB_ACCESS_SET_3" }, |
| 7710 | { 4868, "MPL_DTLB_ACCESS" }, |
| 7711 | { 5120, "MPL_IDN_FIREWALL_SET_0" }, |
| 7712 | { 5121, "MPL_IDN_FIREWALL_SET_1" }, |
| 7713 | { 5122, "MPL_IDN_FIREWALL_SET_2" }, |
| 7714 | { 5123, "MPL_IDN_FIREWALL_SET_3" }, |
| 7715 | { 5124, "MPL_IDN_FIREWALL" }, |
| 7716 | { 5125, "IDN_DIRECTION_PROTECT" }, |
| 7717 | { 5376, "MPL_UDN_FIREWALL_SET_0" }, |
| 7718 | { 5377, "MPL_UDN_FIREWALL_SET_1" }, |
| 7719 | { 5378, "MPL_UDN_FIREWALL_SET_2" }, |
| 7720 | { 5379, "MPL_UDN_FIREWALL_SET_3" }, |
| 7721 | { 5380, "MPL_UDN_FIREWALL" }, |
| 7722 | { 5381, "UDN_DIRECTION_PROTECT" }, |
| 7723 | { 5632, "MPL_TILE_TIMER_SET_0" }, |
| 7724 | { 5633, "MPL_TILE_TIMER_SET_1" }, |
| 7725 | { 5634, "MPL_TILE_TIMER_SET_2" }, |
| 7726 | { 5635, "MPL_TILE_TIMER_SET_3" }, |
| 7727 | { 5636, "MPL_TILE_TIMER" }, |
| 7728 | { 5637, "TILE_TIMER_CONTROL" }, |
| 7729 | { 5888, "MPL_AUX_TILE_TIMER_SET_0" }, |
| 7730 | { 5889, "MPL_AUX_TILE_TIMER_SET_1" }, |
| 7731 | { 5890, "MPL_AUX_TILE_TIMER_SET_2" }, |
| 7732 | { 5891, "MPL_AUX_TILE_TIMER_SET_3" }, |
| 7733 | { 5892, "MPL_AUX_TILE_TIMER" }, |
| 7734 | { 5893, "AUX_TILE_TIMER_CONTROL" }, |
| 7735 | { 6144, "MPL_IDN_TIMER_SET_0" }, |
| 7736 | { 6145, "MPL_IDN_TIMER_SET_1" }, |
| 7737 | { 6146, "MPL_IDN_TIMER_SET_2" }, |
| 7738 | { 6147, "MPL_IDN_TIMER_SET_3" }, |
| 7739 | { 6148, "MPL_IDN_TIMER" }, |
| 7740 | { 6149, "IDN_DEADLOCK_COUNT" }, |
| 7741 | { 6150, "IDN_DEADLOCK_TIMEOUT" }, |
| 7742 | { 6400, "MPL_UDN_TIMER_SET_0" }, |
| 7743 | { 6401, "MPL_UDN_TIMER_SET_1" }, |
| 7744 | { 6402, "MPL_UDN_TIMER_SET_2" }, |
| 7745 | { 6403, "MPL_UDN_TIMER_SET_3" }, |
| 7746 | { 6404, "MPL_UDN_TIMER" }, |
| 7747 | { 6405, "UDN_DEADLOCK_COUNT" }, |
| 7748 | { 6406, "UDN_DEADLOCK_TIMEOUT" }, |
| 7749 | { 6656, "MPL_IDN_AVAIL_SET_0" }, |
| 7750 | { 6657, "MPL_IDN_AVAIL_SET_1" }, |
| 7751 | { 6658, "MPL_IDN_AVAIL_SET_2" }, |
| 7752 | { 6659, "MPL_IDN_AVAIL_SET_3" }, |
| 7753 | { 6660, "MPL_IDN_AVAIL" }, |
| 7754 | { 6661, "IDN_AVAIL_EN" }, |
| 7755 | { 6912, "MPL_UDN_AVAIL_SET_0" }, |
| 7756 | { 6913, "MPL_UDN_AVAIL_SET_1" }, |
| 7757 | { 6914, "MPL_UDN_AVAIL_SET_2" }, |
| 7758 | { 6915, "MPL_UDN_AVAIL_SET_3" }, |
| 7759 | { 6916, "MPL_UDN_AVAIL" }, |
| 7760 | { 6917, "UDN_AVAIL_EN" }, |
| 7761 | { 7168, "MPL_IPI_3_SET_0" }, |
| 7762 | { 7169, "MPL_IPI_3_SET_1" }, |
| 7763 | { 7170, "MPL_IPI_3_SET_2" }, |
| 7764 | { 7171, "MPL_IPI_3_SET_3" }, |
| 7765 | { 7172, "MPL_IPI_3" }, |
| 7766 | { 7173, "IPI_EVENT_3" }, |
| 7767 | { 7174, "IPI_EVENT_RESET_3" }, |
| 7768 | { 7175, "IPI_EVENT_SET_3" }, |
| 7769 | { 7176, "IPI_MASK_3" }, |
| 7770 | { 7177, "IPI_MASK_RESET_3" }, |
| 7771 | { 7178, "IPI_MASK_SET_3" }, |
| 7772 | { 7424, "MPL_IPI_2_SET_0" }, |
| 7773 | { 7425, "MPL_IPI_2_SET_1" }, |
| 7774 | { 7426, "MPL_IPI_2_SET_2" }, |
| 7775 | { 7427, "MPL_IPI_2_SET_3" }, |
| 7776 | { 7428, "MPL_IPI_2" }, |
| 7777 | { 7429, "IPI_EVENT_2" }, |
| 7778 | { 7430, "IPI_EVENT_RESET_2" }, |
| 7779 | { 7431, "IPI_EVENT_SET_2" }, |
| 7780 | { 7432, "IPI_MASK_2" }, |
| 7781 | { 7433, "IPI_MASK_RESET_2" }, |
| 7782 | { 7434, "IPI_MASK_SET_2" }, |
| 7783 | { 7680, "MPL_IPI_1_SET_0" }, |
| 7784 | { 7681, "MPL_IPI_1_SET_1" }, |
| 7785 | { 7682, "MPL_IPI_1_SET_2" }, |
| 7786 | { 7683, "MPL_IPI_1_SET_3" }, |
| 7787 | { 7684, "MPL_IPI_1" }, |
| 7788 | { 7685, "IPI_EVENT_1" }, |
| 7789 | { 7686, "IPI_EVENT_RESET_1" }, |
| 7790 | { 7687, "IPI_EVENT_SET_1" }, |
| 7791 | { 7688, "IPI_MASK_1" }, |
| 7792 | { 7689, "IPI_MASK_RESET_1" }, |
| 7793 | { 7690, "IPI_MASK_SET_1" }, |
| 7794 | { 7936, "MPL_IPI_0_SET_0" }, |
| 7795 | { 7937, "MPL_IPI_0_SET_1" }, |
| 7796 | { 7938, "MPL_IPI_0_SET_2" }, |
| 7797 | { 7939, "MPL_IPI_0_SET_3" }, |
| 7798 | { 7940, "MPL_IPI_0" }, |
| 7799 | { 7941, "IPI_EVENT_0" }, |
| 7800 | { 7942, "IPI_EVENT_RESET_0" }, |
| 7801 | { 7943, "IPI_EVENT_SET_0" }, |
| 7802 | { 7944, "IPI_MASK_0" }, |
| 7803 | { 7945, "IPI_MASK_RESET_0" }, |
| 7804 | { 7946, "IPI_MASK_SET_0" }, |
| 7805 | { 8192, "MPL_PERF_COUNT_SET_0" }, |
| 7806 | { 8193, "MPL_PERF_COUNT_SET_1" }, |
| 7807 | { 8194, "MPL_PERF_COUNT_SET_2" }, |
| 7808 | { 8195, "MPL_PERF_COUNT_SET_3" }, |
| 7809 | { 8196, "MPL_PERF_COUNT" }, |
| 7810 | { 8197, "PERF_COUNT_0" }, |
| 7811 | { 8198, "PERF_COUNT_1" }, |
| 7812 | { 8199, "PERF_COUNT_CTL" }, |
| 7813 | { 8200, "PERF_COUNT_DN_CTL" }, |
| 7814 | { 8201, "PERF_COUNT_STS" }, |
| 7815 | { 8202, "WATCH_MASK" }, |
| 7816 | { 8203, "WATCH_VAL" }, |
| 7817 | { 8448, "MPL_AUX_PERF_COUNT_SET_0" }, |
| 7818 | { 8449, "MPL_AUX_PERF_COUNT_SET_1" }, |
| 7819 | { 8450, "MPL_AUX_PERF_COUNT_SET_2" }, |
| 7820 | { 8451, "MPL_AUX_PERF_COUNT_SET_3" }, |
| 7821 | { 8452, "MPL_AUX_PERF_COUNT" }, |
| 7822 | { 8453, "AUX_PERF_COUNT_0" }, |
| 7823 | { 8454, "AUX_PERF_COUNT_1" }, |
| 7824 | { 8455, "AUX_PERF_COUNT_CTL" }, |
| 7825 | { 8456, "AUX_PERF_COUNT_STS" }, |
| 7826 | { 8704, "MPL_INTCTRL_3_SET_0" }, |
| 7827 | { 8705, "MPL_INTCTRL_3_SET_1" }, |
| 7828 | { 8706, "MPL_INTCTRL_3_SET_2" }, |
| 7829 | { 8707, "MPL_INTCTRL_3_SET_3" }, |
| 7830 | { 8708, "MPL_INTCTRL_3" }, |
| 7831 | { 8709, "INTCTRL_3_STATUS" }, |
| 7832 | { 8710, "INTERRUPT_MASK_3" }, |
| 7833 | { 8711, "INTERRUPT_MASK_RESET_3" }, |
| 7834 | { 8712, "INTERRUPT_MASK_SET_3" }, |
| 7835 | { 8713, "INTERRUPT_VECTOR_BASE_3" }, |
| 7836 | { 8714, "SINGLE_STEP_EN_0_3" }, |
| 7837 | { 8715, "SINGLE_STEP_EN_1_3" }, |
| 7838 | { 8716, "SINGLE_STEP_EN_2_3" }, |
| 7839 | { 8717, "SINGLE_STEP_EN_3_3" }, |
| 7840 | { 8832, "EX_CONTEXT_3_0" }, |
| 7841 | { 8833, "EX_CONTEXT_3_1" }, |
| 7842 | { 8834, "SYSTEM_SAVE_3_0" }, |
| 7843 | { 8835, "SYSTEM_SAVE_3_1" }, |
| 7844 | { 8836, "SYSTEM_SAVE_3_2" }, |
| 7845 | { 8837, "SYSTEM_SAVE_3_3" }, |
| 7846 | { 8960, "MPL_INTCTRL_2_SET_0" }, |
| 7847 | { 8961, "MPL_INTCTRL_2_SET_1" }, |
| 7848 | { 8962, "MPL_INTCTRL_2_SET_2" }, |
| 7849 | { 8963, "MPL_INTCTRL_2_SET_3" }, |
| 7850 | { 8964, "MPL_INTCTRL_2" }, |
| 7851 | { 8965, "INTCTRL_2_STATUS" }, |
| 7852 | { 8966, "INTERRUPT_MASK_2" }, |
| 7853 | { 8967, "INTERRUPT_MASK_RESET_2" }, |
| 7854 | { 8968, "INTERRUPT_MASK_SET_2" }, |
| 7855 | { 8969, "INTERRUPT_VECTOR_BASE_2" }, |
| 7856 | { 8970, "SINGLE_STEP_EN_0_2" }, |
| 7857 | { 8971, "SINGLE_STEP_EN_1_2" }, |
| 7858 | { 8972, "SINGLE_STEP_EN_2_2" }, |
| 7859 | { 8973, "SINGLE_STEP_EN_3_2" }, |
| 7860 | { 9088, "EX_CONTEXT_2_0" }, |
| 7861 | { 9089, "EX_CONTEXT_2_1" }, |
| 7862 | { 9090, "SYSTEM_SAVE_2_0" }, |
| 7863 | { 9091, "SYSTEM_SAVE_2_1" }, |
| 7864 | { 9092, "SYSTEM_SAVE_2_2" }, |
| 7865 | { 9093, "SYSTEM_SAVE_2_3" }, |
| 7866 | { 9216, "MPL_INTCTRL_1_SET_0" }, |
| 7867 | { 9217, "MPL_INTCTRL_1_SET_1" }, |
| 7868 | { 9218, "MPL_INTCTRL_1_SET_2" }, |
| 7869 | { 9219, "MPL_INTCTRL_1_SET_3" }, |
| 7870 | { 9220, "MPL_INTCTRL_1" }, |
| 7871 | { 9221, "INTCTRL_1_STATUS" }, |
| 7872 | { 9222, "INTERRUPT_MASK_1" }, |
| 7873 | { 9223, "INTERRUPT_MASK_RESET_1" }, |
| 7874 | { 9224, "INTERRUPT_MASK_SET_1" }, |
| 7875 | { 9225, "INTERRUPT_VECTOR_BASE_1" }, |
| 7876 | { 9226, "SINGLE_STEP_EN_0_1" }, |
| 7877 | { 9227, "SINGLE_STEP_EN_1_1" }, |
| 7878 | { 9228, "SINGLE_STEP_EN_2_1" }, |
| 7879 | { 9229, "SINGLE_STEP_EN_3_1" }, |
| 7880 | { 9344, "EX_CONTEXT_1_0" }, |
| 7881 | { 9345, "EX_CONTEXT_1_1" }, |
| 7882 | { 9346, "SYSTEM_SAVE_1_0" }, |
| 7883 | { 9347, "SYSTEM_SAVE_1_1" }, |
| 7884 | { 9348, "SYSTEM_SAVE_1_2" }, |
| 7885 | { 9349, "SYSTEM_SAVE_1_3" }, |
| 7886 | { 9472, "MPL_INTCTRL_0_SET_0" }, |
| 7887 | { 9473, "MPL_INTCTRL_0_SET_1" }, |
| 7888 | { 9474, "MPL_INTCTRL_0_SET_2" }, |
| 7889 | { 9475, "MPL_INTCTRL_0_SET_3" }, |
| 7890 | { 9476, "MPL_INTCTRL_0" }, |
| 7891 | { 9477, "INTCTRL_0_STATUS" }, |
| 7892 | { 9478, "INTERRUPT_MASK_0" }, |
| 7893 | { 9479, "INTERRUPT_MASK_RESET_0" }, |
| 7894 | { 9480, "INTERRUPT_MASK_SET_0" }, |
| 7895 | { 9481, "INTERRUPT_VECTOR_BASE_0" }, |
| 7896 | { 9482, "SINGLE_STEP_EN_0_0" }, |
| 7897 | { 9483, "SINGLE_STEP_EN_1_0" }, |
| 7898 | { 9484, "SINGLE_STEP_EN_2_0" }, |
| 7899 | { 9485, "SINGLE_STEP_EN_3_0" }, |
| 7900 | { 9600, "EX_CONTEXT_0_0" }, |
| 7901 | { 9601, "EX_CONTEXT_0_1" }, |
| 7902 | { 9602, "SYSTEM_SAVE_0_0" }, |
| 7903 | { 9603, "SYSTEM_SAVE_0_1" }, |
| 7904 | { 9604, "SYSTEM_SAVE_0_2" }, |
| 7905 | { 9605, "SYSTEM_SAVE_0_3" }, |
| 7906 | { 9728, "MPL_BOOT_ACCESS_SET_0" }, |
| 7907 | { 9729, "MPL_BOOT_ACCESS_SET_1" }, |
| 7908 | { 9730, "MPL_BOOT_ACCESS_SET_2" }, |
| 7909 | { 9731, "MPL_BOOT_ACCESS_SET_3" }, |
| 7910 | { 9732, "MPL_BOOT_ACCESS" }, |
| 7911 | { 9733, "BIG_ENDIAN_CONFIG" }, |
| 7912 | { 9734, "CACHE_INVALIDATION_COMPRESSION_MODE" }, |
| 7913 | { 9735, "CACHE_INVALIDATION_MASK_0" }, |
| 7914 | { 9736, "CACHE_INVALIDATION_MASK_1" }, |
| 7915 | { 9737, "CACHE_INVALIDATION_MASK_2" }, |
| 7916 | { 9738, "CBOX_CACHEASRAM_CONFIG" }, |
| 7917 | { 9739, "CBOX_CACHE_CONFIG" }, |
| 7918 | { 9740, "CBOX_HOME_MAP_ADDR" }, |
| 7919 | { 9741, "CBOX_HOME_MAP_DATA" }, |
| 7920 | { 9742, "CBOX_MMAP_0" }, |
| 7921 | { 9743, "CBOX_MMAP_1" }, |
| 7922 | { 9744, "CBOX_MMAP_2" }, |
| 7923 | { 9745, "CBOX_MMAP_3" }, |
| 7924 | { 9746, "CBOX_MSR" }, |
| 7925 | { 9747, "DIAG_BCST_CTL" }, |
| 7926 | { 9748, "DIAG_BCST_MASK" }, |
| 7927 | { 9749, "DIAG_BCST_TRIGGER" }, |
| 7928 | { 9750, "DIAG_MUX_CTL" }, |
| 7929 | { 9751, "DIAG_TRACE_CTL" }, |
| 7930 | { 9752, "DIAG_TRACE_DATA" }, |
| 7931 | { 9753, "DIAG_TRACE_STS" }, |
| 7932 | { 9754, "IDN_DEMUX_BUF_THRESH" }, |
| 7933 | { 9755, "L1_I_PIN_WAY_0" }, |
| 7934 | { 9756, "MEM_ROUTE_ORDER" }, |
| 7935 | { 9757, "MEM_STRIPE_CONFIG" }, |
| 7936 | { 9758, "PERF_COUNT_PLS" }, |
| 7937 | { 9759, "PSEUDO_RANDOM_NUMBER_MODIFY" }, |
| 7938 | { 9760, "QUIESCE_CTL" }, |
| 7939 | { 9761, "RSHIM_COORD" }, |
| 7940 | { 9762, "SBOX_CONFIG" }, |
| 7941 | { 9763, "UDN_DEMUX_BUF_THRESH" }, |
| 7942 | { 9764, "XDN_CORE_STARVATION_COUNT" }, |
| 7943 | { 9765, "XDN_ROUND_ROBIN_ARB_CTL" }, |
| 7944 | { 9856, "CYCLE_MODIFY" }, |
| 7945 | { 9857, "I_AAR" }, |
| 7946 | { 9984, "MPL_WORLD_ACCESS_SET_0" }, |
| 7947 | { 9985, "MPL_WORLD_ACCESS_SET_1" }, |
| 7948 | { 9986, "MPL_WORLD_ACCESS_SET_2" }, |
| 7949 | { 9987, "MPL_WORLD_ACCESS_SET_3" }, |
| 7950 | { 9988, "MPL_WORLD_ACCESS" }, |
| 7951 | { 9989, "DONE" }, |
| 7952 | { 9990, "DSTREAM_PF" }, |
| 7953 | { 9991, "FAIL" }, |
| 7954 | { 9992, "INTERRUPT_CRITICAL_SECTION" }, |
| 7955 | { 9993, "PASS" }, |
| 7956 | { 9994, "PSEUDO_RANDOM_NUMBER" }, |
| 7957 | { 9995, "TILE_COORD" }, |
| 7958 | { 9996, "TILE_RTF_HWM" }, |
| 7959 | { 10112, "CMPEXCH_VALUE" }, |
| 7960 | { 10113, "CYCLE" }, |
| 7961 | { 10114, "EVENT_BEGIN" }, |
| 7962 | { 10115, "EVENT_END" }, |
| 7963 | { 10116, "PROC_STATUS" }, |
| 7964 | { 10117, "SIM_CONTROL" }, |
| 7965 | { 10118, "SIM_SOCKET" }, |
| 7966 | { 10119, "STATUS_SATURATE" }, |
| 7967 | { 10240, "MPL_I_ASID_SET_0" }, |
| 7968 | { 10241, "MPL_I_ASID_SET_1" }, |
| 7969 | { 10242, "MPL_I_ASID_SET_2" }, |
| 7970 | { 10243, "MPL_I_ASID_SET_3" }, |
| 7971 | { 10244, "MPL_I_ASID" }, |
| 7972 | { 10245, "I_ASID" }, |
| 7973 | { 10496, "MPL_D_ASID_SET_0" }, |
| 7974 | { 10497, "MPL_D_ASID_SET_1" }, |
| 7975 | { 10498, "MPL_D_ASID_SET_2" }, |
| 7976 | { 10499, "MPL_D_ASID_SET_3" }, |
| 7977 | { 10500, "MPL_D_ASID" }, |
| 7978 | { 10501, "D_ASID" }, |
| 7979 | { 10752, "MPL_DOUBLE_FAULT_SET_0" }, |
| 7980 | { 10753, "MPL_DOUBLE_FAULT_SET_1" }, |
| 7981 | { 10754, "MPL_DOUBLE_FAULT_SET_2" }, |
| 7982 | { 10755, "MPL_DOUBLE_FAULT_SET_3" }, |
| 7983 | { 10756, "MPL_DOUBLE_FAULT" }, |
| 7984 | { 10757, "LAST_INTERRUPT_REASON" }, |
| 7985 | }; |
| 7986 | |
| 7987 | const int tilegx_num_sprs = 441; |
| 7988 | |
| 7989 | #endif /* DISASM_ONLY */ |
| 7990 | |
| 7991 | #ifndef DISASM_ONLY |
| 7992 | |
| 7993 | #include <stdlib.h> |
| 7994 | |
| 7995 | static int |
| 7996 | tilegx_spr_compare (const void *a_ptr, const void *b_ptr) |
| 7997 | { |
| 7998 | const struct tilegx_spr *a = (const struct tilegx_spr *) a_ptr; |
| 7999 | const struct tilegx_spr *b = (const struct tilegx_spr *) b_ptr; |
| 8000 | return (a->number - b->number); |
| 8001 | } |
| 8002 | |
| 8003 | const char * |
| 8004 | get_tilegx_spr_name (int num) |
| 8005 | { |
| 8006 | void *result; |
| 8007 | struct tilegx_spr key; |
| 8008 | |
| 8009 | key.number = num; |
| 8010 | result = bsearch ((const void *) &key, (const void *) tilegx_sprs, |
| 8011 | tilegx_num_sprs, sizeof (struct tilegx_spr), |
| 8012 | tilegx_spr_compare); |
| 8013 | |
| 8014 | if (result == NULL) |
| 8015 | return NULL; |
| 8016 | |
| 8017 | { |
| 8018 | struct tilegx_spr *result_ptr = (struct tilegx_spr *) result; |
| 8019 | |
| 8020 | return result_ptr->name; |
| 8021 | } |
| 8022 | } |
| 8023 | |
| 8024 | /* Canonical name of each register. */ |
| 8025 | const char * const tilegx_register_names[] = |
| 8026 | { |
| 8027 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 8028 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 8029 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 8030 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 8031 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
| 8032 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
| 8033 | "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr", |
| 8034 | "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero" |
| 8035 | }; |
| 8036 | |
| 8037 | #endif /* not DISASM_ONLY */ |
| 8038 | |
| 8039 | |
| 8040 | /* Given a set of bundle bits and the lookup FSM for a specific pipe, |
| 8041 | returns which instruction the bundle contains in that pipe. */ |
| 8042 | |
| 8043 | static const struct tilegx_opcode * |
| 8044 | find_opcode (tilegx_bundle_bits bits, const unsigned short *table) |
| 8045 | { |
| 8046 | int i = 0; |
| 8047 | |
| 8048 | while (1) |
| 8049 | { |
| 8050 | unsigned short bitspec = table[i]; |
| 8051 | unsigned int bitfield = |
| 8052 | ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6); |
| 8053 | |
| 8054 | unsigned short next = table[i + 1 + bitfield]; |
| 8055 | if (next <= TILEGX_OPC_NONE) |
| 8056 | return & tilegx_opcodes[next]; |
| 8057 | |
| 8058 | i = next - TILEGX_OPC_NONE; |
| 8059 | } |
| 8060 | } |
| 8061 | |
| 8062 | int |
| 8063 | parse_insn_tilegx (tilegx_bundle_bits bits, |
| 8064 | unsigned long long pc, |
| 8065 | struct tilegx_decoded_instruction |
| 8066 | decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]) |
| 8067 | { |
| 8068 | int num_instructions = 0; |
| 8069 | int pipe; |
| 8070 | int min_pipe, max_pipe; |
| 8071 | |
| 8072 | if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0) |
| 8073 | { |
| 8074 | min_pipe = TILEGX_PIPELINE_X0; |
| 8075 | max_pipe = TILEGX_PIPELINE_X1; |
| 8076 | } |
| 8077 | else |
| 8078 | { |
| 8079 | min_pipe = TILEGX_PIPELINE_Y0; |
| 8080 | max_pipe = TILEGX_PIPELINE_Y2; |
| 8081 | } |
| 8082 | |
| 8083 | /* For each pipe, find an instruction that fits. */ |
| 8084 | for (pipe = min_pipe; pipe <= max_pipe; pipe++) |
| 8085 | { |
| 8086 | const struct tilegx_opcode *opc; |
| 8087 | struct tilegx_decoded_instruction *d; |
| 8088 | int i; |
| 8089 | |
| 8090 | d = &decoded[num_instructions++]; |
| 8091 | opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]); |
| 8092 | d->opcode = opc; |
| 8093 | |
| 8094 | /* Decode each operand, sign extending, etc. as appropriate. */ |
| 8095 | for (i = 0; i < opc->num_operands; i++) |
| 8096 | { |
| 8097 | const struct tilegx_operand *op = |
| 8098 | &tilegx_operands[opc->operands[pipe][i]]; |
| 8099 | int raw_opval = op->extract (bits); |
| 8100 | long long opval; |
| 8101 | |
| 8102 | if (op->is_signed) |
| 8103 | { |
| 8104 | /* Sign-extend the operand. */ |
| 8105 | int shift = (int)((sizeof(int) * 8) - op->num_bits); |
| 8106 | raw_opval = (raw_opval << shift) >> shift; |
| 8107 | } |
| 8108 | |
| 8109 | /* Adjust PC-relative scaled branch offsets. */ |
| 8110 | if (op->type == TILEGX_OP_TYPE_ADDRESS) |
| 8111 | opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc; |
| 8112 | else |
| 8113 | opval = raw_opval; |
| 8114 | |
| 8115 | /* Record the final value. */ |
| 8116 | d->operands[i] = op; |
| 8117 | d->operand_values[i] = opval; |
| 8118 | } |
| 8119 | } |
| 8120 | |
| 8121 | return num_instructions; |
| 8122 | } |