| 1 | /* Assemble V850 instructions. |
| 2 | Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the Free Software |
| 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 18 | MA 02110-1301, USA. */ |
| 19 | |
| 20 | #include "sysdep.h" |
| 21 | #include "opcode/v850.h" |
| 22 | #include <stdio.h> |
| 23 | #include "opintl.h" |
| 24 | |
| 25 | /* Regular opcodes. */ |
| 26 | #define OP(x) ((x & 0x3f) << 5) |
| 27 | #define OP_MASK OP (0x3f) |
| 28 | |
| 29 | /* Conditional branch opcodes. */ |
| 30 | #define BOP(x) ((0x0b << 7) | (x & 0x0f)) |
| 31 | #define BOP_MASK ((0x0f << 7) | 0x0f) |
| 32 | |
| 33 | /* One-word opcodes. */ |
| 34 | #define one(x) ((unsigned int) (x)) |
| 35 | |
| 36 | /* Two-word opcodes. */ |
| 37 | #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) |
| 38 | \f |
| 39 | /* The functions used to insert and extract complicated operands. */ |
| 40 | |
| 41 | /* Note: There is a conspiracy between these functions and |
| 42 | v850_insert_operand() in gas/config/tc-v850.c. Error messages |
| 43 | containing the string 'out of range' will be ignored unless a |
| 44 | specific command line option is given to GAS. */ |
| 45 | |
| 46 | static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); |
| 47 | static const char * out_of_range = N_ ("displacement value is out of range"); |
| 48 | static const char * not_aligned = N_ ("displacement value is not aligned"); |
| 49 | |
| 50 | static const char * immediate_out_of_range = N_ ("immediate value is out of range"); |
| 51 | |
| 52 | static unsigned long |
| 53 | insert_d9 (unsigned long insn, long value, const char ** errmsg) |
| 54 | { |
| 55 | if (value > 0xff || value < -0x100) |
| 56 | { |
| 57 | if ((value % 2) != 0) |
| 58 | * errmsg = _("branch value not in range and to odd offset"); |
| 59 | else |
| 60 | * errmsg = _("branch value out of range"); |
| 61 | } |
| 62 | else if ((value % 2) != 0) |
| 63 | * errmsg = _("branch to odd offset"); |
| 64 | |
| 65 | return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); |
| 66 | } |
| 67 | |
| 68 | static unsigned long |
| 69 | extract_d9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 70 | { |
| 71 | unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); |
| 72 | |
| 73 | if ((insn & 0x8000) != 0) |
| 74 | ret -= 0x0200; |
| 75 | |
| 76 | return ret; |
| 77 | } |
| 78 | |
| 79 | static unsigned long |
| 80 | insert_d22 (unsigned long insn, long value, const char ** errmsg) |
| 81 | { |
| 82 | if (value > 0x1fffff || value < -0x200000) |
| 83 | { |
| 84 | if ((value % 2) != 0) |
| 85 | * errmsg = _("branch value not in range and to an odd offset"); |
| 86 | else |
| 87 | * errmsg = _("branch value out of range"); |
| 88 | } |
| 89 | else if ((value % 2) != 0) |
| 90 | * errmsg = _("branch to odd offset"); |
| 91 | |
| 92 | return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); |
| 93 | } |
| 94 | |
| 95 | static unsigned long |
| 96 | extract_d22 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 97 | { |
| 98 | signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); |
| 99 | |
| 100 | return (unsigned long) ((ret << 10) >> 10); |
| 101 | } |
| 102 | |
| 103 | static unsigned long |
| 104 | insert_d16_15 (unsigned long insn, long value, const char ** errmsg) |
| 105 | { |
| 106 | if (value > 0x7fff || value < -0x8000) |
| 107 | { |
| 108 | if ((value % 2) != 0) |
| 109 | * errmsg = _(not_valid); |
| 110 | else |
| 111 | * errmsg = _(out_of_range); |
| 112 | } |
| 113 | else if ((value % 2) != 0) |
| 114 | * errmsg = _(not_aligned); |
| 115 | |
| 116 | return insn | ((value & 0xfffe) << 16); |
| 117 | } |
| 118 | |
| 119 | static unsigned long |
| 120 | extract_d16_15 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 121 | { |
| 122 | signed long ret = (insn & 0xfffe0000); |
| 123 | |
| 124 | return ret >> 16; |
| 125 | } |
| 126 | |
| 127 | static unsigned long |
| 128 | insert_d8_7 (unsigned long insn, long value, const char ** errmsg) |
| 129 | { |
| 130 | if (value > 0xff || value < 0) |
| 131 | { |
| 132 | if ((value % 2) != 0) |
| 133 | * errmsg = _(not_valid); |
| 134 | else |
| 135 | * errmsg = _(out_of_range); |
| 136 | } |
| 137 | else if ((value % 2) != 0) |
| 138 | * errmsg = _(not_aligned); |
| 139 | |
| 140 | value >>= 1; |
| 141 | |
| 142 | return insn | (value & 0x7f); |
| 143 | } |
| 144 | |
| 145 | static unsigned long |
| 146 | extract_d8_7 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 147 | { |
| 148 | unsigned long ret = (insn & 0x7f); |
| 149 | |
| 150 | return ret << 1; |
| 151 | } |
| 152 | |
| 153 | static unsigned long |
| 154 | insert_d8_6 (unsigned long insn, long value, const char ** errmsg) |
| 155 | { |
| 156 | if (value > 0xff || value < 0) |
| 157 | { |
| 158 | if ((value % 4) != 0) |
| 159 | *errmsg = _(not_valid); |
| 160 | else |
| 161 | * errmsg = _(out_of_range); |
| 162 | } |
| 163 | else if ((value % 4) != 0) |
| 164 | * errmsg = _(not_aligned); |
| 165 | |
| 166 | value >>= 1; |
| 167 | |
| 168 | return insn | (value & 0x7e); |
| 169 | } |
| 170 | |
| 171 | static unsigned long |
| 172 | extract_d8_6 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 173 | { |
| 174 | unsigned long ret = (insn & 0x7e); |
| 175 | |
| 176 | return ret << 1; |
| 177 | } |
| 178 | |
| 179 | static unsigned long |
| 180 | insert_d5_4 (unsigned long insn, long value, const char ** errmsg) |
| 181 | { |
| 182 | if (value > 0x1f || value < 0) |
| 183 | { |
| 184 | if (value & 1) |
| 185 | * errmsg = _(not_valid); |
| 186 | else |
| 187 | *errmsg = _(out_of_range); |
| 188 | } |
| 189 | else if (value & 1) |
| 190 | * errmsg = _(not_aligned); |
| 191 | |
| 192 | value >>= 1; |
| 193 | |
| 194 | return insn | (value & 0x0f); |
| 195 | } |
| 196 | |
| 197 | static unsigned long |
| 198 | extract_d5_4 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 199 | { |
| 200 | unsigned long ret = (insn & 0x0f); |
| 201 | |
| 202 | return ret << 1; |
| 203 | } |
| 204 | |
| 205 | static unsigned long |
| 206 | insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg) |
| 207 | { |
| 208 | if (value > 0x7fff || value < -0x8000) |
| 209 | * errmsg = _(out_of_range); |
| 210 | |
| 211 | return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); |
| 212 | } |
| 213 | |
| 214 | static unsigned long |
| 215 | extract_d16_16 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 216 | { |
| 217 | signed long ret = insn & 0xfffe0000; |
| 218 | |
| 219 | ret >>= 16; |
| 220 | |
| 221 | ret |= ((insn & 0x20) >> 5); |
| 222 | |
| 223 | return ret; |
| 224 | } |
| 225 | |
| 226 | static unsigned long |
| 227 | insert_i9 (unsigned long insn, signed long value, const char ** errmsg) |
| 228 | { |
| 229 | if (value > 0xff || value < -0x100) |
| 230 | * errmsg = _(immediate_out_of_range); |
| 231 | |
| 232 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); |
| 233 | } |
| 234 | |
| 235 | static unsigned long |
| 236 | extract_i9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 237 | { |
| 238 | signed long ret = insn & 0x003c0000; |
| 239 | |
| 240 | ret <<= 10; |
| 241 | ret >>= 23; |
| 242 | |
| 243 | ret |= (insn & 0x1f); |
| 244 | |
| 245 | return ret; |
| 246 | } |
| 247 | |
| 248 | static unsigned long |
| 249 | insert_u9 (unsigned long insn, long v, const char ** errmsg) |
| 250 | { |
| 251 | unsigned long value = (unsigned long) v; |
| 252 | |
| 253 | if (value > 0x1ff) |
| 254 | * errmsg = _(immediate_out_of_range); |
| 255 | |
| 256 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); |
| 257 | } |
| 258 | |
| 259 | static unsigned long |
| 260 | extract_u9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 261 | { |
| 262 | unsigned long ret = insn & 0x003c0000; |
| 263 | |
| 264 | ret >>= 13; |
| 265 | |
| 266 | ret |= (insn & 0x1f); |
| 267 | |
| 268 | return ret; |
| 269 | } |
| 270 | |
| 271 | static unsigned long |
| 272 | insert_spe (unsigned long insn, long v, const char ** errmsg) |
| 273 | { |
| 274 | unsigned long value = (unsigned long) v; |
| 275 | |
| 276 | if (value != 3) |
| 277 | * errmsg = _("invalid register for stack adjustment"); |
| 278 | |
| 279 | return insn & (~ 0x180000); |
| 280 | } |
| 281 | |
| 282 | static unsigned long |
| 283 | extract_spe (unsigned long insn ATTRIBUTE_UNUSED, |
| 284 | int * invalid ATTRIBUTE_UNUSED) |
| 285 | { |
| 286 | return 3; |
| 287 | } |
| 288 | |
| 289 | static unsigned long |
| 290 | insert_i5div (unsigned long insn, long v, const char ** errmsg) |
| 291 | { |
| 292 | unsigned long value = (unsigned long) v; |
| 293 | |
| 294 | if (value > 0x1ff) |
| 295 | { |
| 296 | if (value & 1) |
| 297 | * errmsg = _("immediate value not in range and not even"); |
| 298 | else |
| 299 | * errmsg = _(immediate_out_of_range); |
| 300 | } |
| 301 | else if (value & 1) |
| 302 | * errmsg = _("immediate value must be even"); |
| 303 | |
| 304 | value = 32 - value; |
| 305 | |
| 306 | return insn | ((value & 0x1e) << 17); |
| 307 | } |
| 308 | |
| 309 | static unsigned long |
| 310 | extract_i5div (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) |
| 311 | { |
| 312 | unsigned long ret = insn & 0x3c0000; |
| 313 | |
| 314 | ret >>= 17; |
| 315 | |
| 316 | ret = 32 - ret; |
| 317 | |
| 318 | return ret; |
| 319 | } |
| 320 | |
| 321 | \f |
| 322 | /* Warning: code in gas/config/tc-v850.c examines the contents of this array. |
| 323 | If you change any of the values here, be sure to look for side effects in |
| 324 | that code. */ |
| 325 | const struct v850_operand v850_operands[] = |
| 326 | { |
| 327 | #define UNUSED 0 |
| 328 | { 0, 0, NULL, NULL, 0 }, |
| 329 | |
| 330 | /* The R1 field in a format 1, 6, 7, or 9 insn. */ |
| 331 | #define R1 (UNUSED + 1) |
| 332 | { 5, 0, NULL, NULL, V850_OPERAND_REG }, |
| 333 | |
| 334 | /* As above, but register 0 is not allowed. */ |
| 335 | #define R1_NOTR0 (R1 + 1) |
| 336 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
| 337 | |
| 338 | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ |
| 339 | #define R2 (R1_NOTR0 + 1) |
| 340 | { 5, 11, NULL, NULL, V850_OPERAND_REG }, |
| 341 | |
| 342 | /* As above, but register 0 is not allowed. */ |
| 343 | #define R2_NOTR0 (R2 + 1) |
| 344 | { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
| 345 | |
| 346 | /* The imm5 field in a format 2 insn. */ |
| 347 | #define I5 (R2_NOTR0 + 1) |
| 348 | { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, |
| 349 | |
| 350 | /* The unsigned imm5 field in a format 2 insn. */ |
| 351 | #define I5U (I5 + 1) |
| 352 | { 5, 0, NULL, NULL, 0 }, |
| 353 | |
| 354 | /* The imm16 field in a format 6 insn. */ |
| 355 | #define I16 (I5U + 1) |
| 356 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, |
| 357 | |
| 358 | /* The signed disp7 field in a format 4 insn. */ |
| 359 | #define D7 (I16 + 1) |
| 360 | { 7, 0, NULL, NULL, 0}, |
| 361 | |
| 362 | /* The disp16 field in a format 6 insn. */ |
| 363 | #define D16_15 (D7 + 1) |
| 364 | { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, |
| 365 | |
| 366 | /* The 3 bit immediate field in format 8 insn. */ |
| 367 | #define B3 (D16_15 + 1) |
| 368 | { 3, 11, NULL, NULL, 0 }, |
| 369 | |
| 370 | /* The 4 bit condition code in a setf instruction */ |
| 371 | #define CCCC (B3 + 1) |
| 372 | { 4, 0, NULL, NULL, V850_OPERAND_CC }, |
| 373 | |
| 374 | /* The unsigned DISP8 field in a format 4 insn. */ |
| 375 | #define D8_7 (CCCC + 1) |
| 376 | { 7, 0, insert_d8_7, extract_d8_7, 0 }, |
| 377 | |
| 378 | /* The unsigned DISP8 field in a format 4 insn. */ |
| 379 | #define D8_6 (D8_7 + 1) |
| 380 | { 6, 1, insert_d8_6, extract_d8_6, 0 }, |
| 381 | |
| 382 | /* System register operands. */ |
| 383 | #define SR1 (D8_6 + 1) |
| 384 | { 5, 0, NULL, NULL, V850_OPERAND_SRG }, |
| 385 | |
| 386 | /* EP Register. */ |
| 387 | #define EP (SR1 + 1) |
| 388 | { 0, 0, NULL, NULL, V850_OPERAND_EP }, |
| 389 | |
| 390 | /* The imm16 field (unsigned) in a format 6 insn. */ |
| 391 | #define I16U (EP + 1) |
| 392 | { 16, 16, NULL, NULL, 0}, |
| 393 | |
| 394 | /* The R2 field as a system register. */ |
| 395 | #define SR2 (I16U + 1) |
| 396 | { 5, 11, NULL, NULL, V850_OPERAND_SRG }, |
| 397 | |
| 398 | /* The disp16 field in a format 8 insn. */ |
| 399 | #define D16 (SR2 + 1) |
| 400 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, |
| 401 | |
| 402 | /* The DISP9 field in a format 3 insn, relaxable. */ |
| 403 | #define D9_RELAX (D16 + 1) |
| 404 | { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, |
| 405 | |
| 406 | /* The DISP22 field in a format 4 insn, relaxable. |
| 407 | This _must_ follow D9_RELAX; the assembler assumes that the longer |
| 408 | version immediately follows the shorter version for relaxing. */ |
| 409 | #define D22 (D9_RELAX + 1) |
| 410 | { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, |
| 411 | |
| 412 | /* The signed disp4 field in a format 4 insn. */ |
| 413 | #define D4 (D22 + 1) |
| 414 | { 4, 0, NULL, NULL, 0}, |
| 415 | |
| 416 | /* The unsigned disp5 field in a format 4 insn. */ |
| 417 | #define D5_4 (D4 + 1) |
| 418 | { 4, 0, insert_d5_4, extract_d5_4, 0 }, |
| 419 | |
| 420 | /* The disp16 field in an format 7 unsigned byte load insn. */ |
| 421 | #define D16_16 (D5_4 + 1) |
| 422 | { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, |
| 423 | |
| 424 | /* Third register in conditional moves. */ |
| 425 | #define R3 (D16_16 + 1) |
| 426 | { 5, 27, NULL, NULL, V850_OPERAND_REG }, |
| 427 | |
| 428 | /* Condition code in conditional moves. */ |
| 429 | #define MOVCC (R3 + 1) |
| 430 | { 4, 17, NULL, NULL, V850_OPERAND_CC }, |
| 431 | |
| 432 | /* The imm9 field in a multiply word. */ |
| 433 | #define I9 (MOVCC + 1) |
| 434 | { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, |
| 435 | |
| 436 | /* The unsigned imm9 field in a multiply word. */ |
| 437 | #define U9 (I9 + 1) |
| 438 | { 9, 0, insert_u9, extract_u9, 0 }, |
| 439 | |
| 440 | /* A list of registers in a prepare/dispose instruction. */ |
| 441 | #define LIST12 (U9 + 1) |
| 442 | { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, |
| 443 | |
| 444 | /* The IMM6 field in a call instruction. */ |
| 445 | #define I6 (LIST12 + 1) |
| 446 | { 6, 0, NULL, NULL, 0 }, |
| 447 | |
| 448 | /* The 16 bit immediate following a 32 bit instruction. */ |
| 449 | #define IMM16 (I6 + 1) |
| 450 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, |
| 451 | |
| 452 | /* The 32 bit immediate following a 32 bit instruction. */ |
| 453 | #define IMM32 (IMM16 + 1) |
| 454 | { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, |
| 455 | |
| 456 | /* The imm5 field in a push/pop instruction. */ |
| 457 | #define IMM5 (IMM32 + 1) |
| 458 | { 5, 1, NULL, NULL, 0 }, |
| 459 | |
| 460 | /* Reg2 in dispose instruction. */ |
| 461 | #define R2DISPOSE (IMM5 + 1) |
| 462 | { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
| 463 | |
| 464 | /* Stack pointer in prepare instruction. */ |
| 465 | #define SP (R2DISPOSE + 1) |
| 466 | { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, |
| 467 | |
| 468 | /* The IMM5 field in a divide N step instruction. */ |
| 469 | #define I5DIV (SP + 1) |
| 470 | { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, |
| 471 | |
| 472 | /* The list of registers in a PUSHMH/POPMH instruction. */ |
| 473 | #define LIST18_H (I5DIV + 1) |
| 474 | { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, |
| 475 | |
| 476 | /* The list of registers in a PUSHML/POPML instruction. */ |
| 477 | #define LIST18_L (LIST18_H + 1) |
| 478 | /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */ |
| 479 | { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, |
| 480 | }; |
| 481 | |
| 482 | \f |
| 483 | /* Reg - Reg instruction format (Format I). */ |
| 484 | #define IF1 {R1, R2} |
| 485 | |
| 486 | /* Imm - Reg instruction format (Format II). */ |
| 487 | #define IF2 {I5, R2} |
| 488 | |
| 489 | /* Conditional branch instruction format (Format III). */ |
| 490 | #define IF3 {D9_RELAX} |
| 491 | |
| 492 | /* 3 operand instruction (Format VI). */ |
| 493 | #define IF6 {I16, R1, R2} |
| 494 | |
| 495 | /* 3 operand instruction (Format VI). */ |
| 496 | #define IF6U {I16U, R1, R2} |
| 497 | |
| 498 | |
| 499 | \f |
| 500 | /* The opcode table. |
| 501 | |
| 502 | The format of the opcode table is: |
| 503 | |
| 504 | NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR |
| 505 | |
| 506 | NAME is the name of the instruction. |
| 507 | OPCODE is the instruction opcode. |
| 508 | MASK is the opcode mask; this is used to tell the disassembler |
| 509 | which bits in the actual opcode must match OPCODE. |
| 510 | OPERANDS is the list of operands. |
| 511 | MEMOP specifies which operand (if any) is a memory operand. |
| 512 | PROCESSORS specifies which CPU(s) support the opcode. |
| 513 | |
| 514 | The disassembler reads the table in order and prints the first |
| 515 | instruction which matches, so this table is sorted to put more |
| 516 | specific instructions before more general instructions. It is also |
| 517 | sorted by major opcode. |
| 518 | |
| 519 | The table is also sorted by name. This is used by the assembler. |
| 520 | When parsing an instruction the assembler finds the first occurance |
| 521 | of the name of the instruciton in this table and then attempts to |
| 522 | match the instruction's arguments with description of the operands |
| 523 | associated with the entry it has just found in this table. If the |
| 524 | match fails the assembler looks at the next entry in this table. |
| 525 | If that entry has the same name as the previous entry, then it |
| 526 | tries to match the instruction against that entry and so on. This |
| 527 | is how the assembler copes with multiple, different formats of the |
| 528 | same instruction. */ |
| 529 | |
| 530 | const struct v850_opcode v850_opcodes[] = |
| 531 | { |
| 532 | { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, |
| 533 | { "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, |
| 534 | |
| 535 | { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, |
| 536 | |
| 537 | /* Load/store instructions. */ |
| 538 | { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, |
| 539 | { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, |
| 540 | |
| 541 | { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, |
| 542 | { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, |
| 543 | |
| 544 | { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E1 }, |
| 545 | { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, |
| 546 | { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, |
| 547 | |
| 548 | { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E1 }, |
| 549 | { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, |
| 550 | { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, |
| 551 | { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, |
| 552 | { "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, |
| 553 | { "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, |
| 554 | { "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, |
| 555 | |
| 556 | { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, |
| 557 | { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, |
| 558 | { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, |
| 559 | { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, |
| 560 | { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, |
| 561 | { "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, |
| 562 | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, |
| 563 | |
| 564 | { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, |
| 565 | { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, |
| 566 | { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, |
| 567 | { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, |
| 568 | { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, |
| 569 | { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, |
| 570 | { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, |
| 571 | { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, |
| 572 | |
| 573 | /* Byte swap/extend instructions. */ |
| 574 | { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
| 575 | { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
| 576 | { "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
| 577 | { "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
| 578 | { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 579 | { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 580 | { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 581 | |
| 582 | /* Jump table instructions. */ |
| 583 | { "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, |
| 584 | { "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, |
| 585 | { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
| 586 | |
| 587 | /* Arithmetic operation instructions. */ |
| 588 | { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, |
| 589 | { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 590 | { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 591 | |
| 592 | { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 593 | { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 594 | { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 595 | { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 596 | |
| 597 | { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 598 | { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 599 | { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 600 | { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
| 601 | { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 602 | |
| 603 | { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, |
| 604 | { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 605 | { "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
| 606 | { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 607 | { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 608 | { "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 609 | { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 610 | { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, |
| 611 | { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, |
| 612 | { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 613 | { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 614 | { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 615 | { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 616 | { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 617 | { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 618 | { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, |
| 619 | |
| 620 | /* Saturated operation instructions. */ |
| 621 | { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 622 | { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 623 | { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 624 | { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 625 | { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
| 626 | |
| 627 | /* Logical operation instructions. */ |
| 628 | { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 629 | { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 630 | { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
| 631 | { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 632 | { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
| 633 | { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 634 | { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
| 635 | { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
| 636 | { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
| 637 | { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
| 638 | { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
| 639 | { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
| 640 | { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
| 641 | { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
| 642 | { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, |
| 643 | |
| 644 | /* Branch instructions. */ |
| 645 | /* Signed integer. */ |
| 646 | { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 647 | { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 648 | { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 649 | { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 650 | /* Unsigned integer. */ |
| 651 | { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 652 | { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 653 | { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 654 | { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 655 | /* Common. */ |
| 656 | { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 657 | { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 658 | /* Others. */ |
| 659 | { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 660 | { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 661 | { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 662 | { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 663 | { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 664 | { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 665 | { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 666 | { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 667 | { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 668 | { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 669 | |
| 670 | /* Branch macros. |
| 671 | |
| 672 | We use the short form in the opcode/mask fields. The assembler |
| 673 | will twiddle bits as necessary if the long form is needed. */ |
| 674 | |
| 675 | /* Signed integer. */ |
| 676 | { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 677 | { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 678 | { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 679 | { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 680 | /* Unsigned integer. */ |
| 681 | { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 682 | { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 683 | { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 684 | { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 685 | /* Common. */ |
| 686 | { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 687 | { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 688 | /* Others. */ |
| 689 | { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 690 | { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 691 | { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 692 | { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 693 | { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 694 | { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 695 | { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 696 | { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 697 | { "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 698 | { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
| 699 | |
| 700 | { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, |
| 701 | { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL }, |
| 702 | |
| 703 | /* Bit manipulation instructions. */ |
| 704 | { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
| 705 | { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, |
| 706 | { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
| 707 | { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, |
| 708 | { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
| 709 | { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, |
| 710 | { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
| 711 | { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, |
| 712 | |
| 713 | /* Special instructions. */ |
| 714 | { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
| 715 | { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
| 716 | { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
| 717 | { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
| 718 | { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, |
| 719 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, |
| 720 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, |
| 721 | { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, |
| 722 | { 0, 0, 0, {0}, 0, 0 }, |
| 723 | |
| 724 | } ; |
| 725 | |
| 726 | const int v850_num_opcodes = |
| 727 | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); |