| 1 | #include "ansidecl.h" |
| 2 | #include "opcode/v850.h" |
| 3 | |
| 4 | /* Local insertion and extraction functions. */ |
| 5 | static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **)); |
| 6 | static long extract_d9 PARAMS ((unsigned long, int *)); |
| 7 | |
| 8 | /* regular opcode */ |
| 9 | #define OP(x) ((x & 0x3f) << 5) |
| 10 | #define OP_MASK OP(0x3f) |
| 11 | |
| 12 | /* conditional branch opcode */ |
| 13 | #define BOP(x) ((0x0b << 7) | (x & 0x0f)) |
| 14 | #define BOP_MASK ((0x0b << 7) | 0x0f) |
| 15 | |
| 16 | /* one-word opcodes */ |
| 17 | #define one(x) ((unsigned int) (x)) |
| 18 | |
| 19 | /* two-word opcodes */ |
| 20 | #define two(x,y) ((unsigned int) (y) | ((unsigned int) (x) << 16)) |
| 21 | |
| 22 | |
| 23 | \f |
| 24 | const struct v850_operand v850_operands[] = { |
| 25 | #define UNUSED 0 |
| 26 | { 0, 0, 0, 0, 0 }, |
| 27 | |
| 28 | /* The R1 field in a format 1, 6, 7, or 9 insn. */ |
| 29 | #define R1 (UNUSED+1) |
| 30 | { 5, 0, 0, 0, V850_OPERAND_REG }, |
| 31 | |
| 32 | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ |
| 33 | #define R2 (R1+1) |
| 34 | { 5, 11, 0, 0, V850_OPERAND_REG }, |
| 35 | |
| 36 | /* The IMM5 field in a format 2 insn. */ |
| 37 | #define I5 (R2+1) |
| 38 | { 5, 0, 0, 0, V850_OPERAND_SIGNED }, |
| 39 | |
| 40 | #define I5U (I5+1) |
| 41 | { 5, 0, 0, 0, 0 }, |
| 42 | |
| 43 | /* The IMM16 field in a format 6 insn. */ |
| 44 | #define I16 (I5U+1) |
| 45 | { 16, 0, 0, 0, 0 }, |
| 46 | |
| 47 | /* The DISP6 field in a format 4 insn. */ |
| 48 | #define D6 (I16+1) |
| 49 | { 6, 1, 0, 0, 0 }, |
| 50 | |
| 51 | /* The DISP9 field in a format 3 insn. */ |
| 52 | #define D9 (D6+1) |
| 53 | { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED }, |
| 54 | |
| 55 | /* The DISP16 field in a format 6 insn. */ |
| 56 | #define D16 (D9+1) |
| 57 | { 16, 0, 0, 0, V850_OPERAND_SIGNED }, |
| 58 | |
| 59 | /* The DISP22 field in a format 4 insn. */ |
| 60 | #define D22 (D16+1) |
| 61 | { 16, 0, 0, 0, 0 }, |
| 62 | |
| 63 | #define B3 (D22+1) |
| 64 | /* The 3 bit immediate field in format 8 insn. */ |
| 65 | { 3, 11, 0, 0, 0 }, |
| 66 | |
| 67 | #define CCCC (B3+1) |
| 68 | /* The 4 bit condition code in a setf instruction */ |
| 69 | { 4, 0, 0, 0, V850_OPERAND_CC } |
| 70 | } ; |
| 71 | |
| 72 | \f |
| 73 | /* reg-reg instruction format (Format I) */ |
| 74 | #define IF1 {R1, R2} |
| 75 | |
| 76 | /* imm-reg instruction format (Format II) */ |
| 77 | #define IF2 {I5, R2} |
| 78 | |
| 79 | /* conditional branch instruction format (Format III) */ |
| 80 | #define IF3 {D9} |
| 81 | |
| 82 | /* 16-bit load/store instruction (Format IV) */ |
| 83 | #define IF4A {D6, R2} |
| 84 | #define IF4B {R2, D6} |
| 85 | |
| 86 | /* Jump instruction (Format V) */ |
| 87 | #define IF5 {D22} |
| 88 | |
| 89 | /* 3 operand instruction (Format VI) */ |
| 90 | #define IF6 {I16, R1, R2} |
| 91 | |
| 92 | /* 32-bit load/store instruction (Format VII) */ |
| 93 | #define IF7A {D16, R1, R2} |
| 94 | #define IF7B {R2, D16, R1} |
| 95 | |
| 96 | /* Bit manipulation function. */ |
| 97 | |
| 98 | |
| 99 | \f |
| 100 | /* The opcode table. |
| 101 | |
| 102 | The format of the opcode table is: |
| 103 | |
| 104 | NAME OPCODE MASK { OPERANDS } |
| 105 | |
| 106 | NAME is the name of the instruction. |
| 107 | OPCODE is the instruction opcode. |
| 108 | MASK is the opcode mask; this is used to tell the disassembler |
| 109 | which bits in the actual opcode must match OPCODE. |
| 110 | OPERANDS is the list of operands. |
| 111 | |
| 112 | The disassembler reads the table in order and prints the first |
| 113 | instruction which matches, so this table is sorted to put more |
| 114 | specific instructions before more general instructions. It is also |
| 115 | sorted by major opcode. */ |
| 116 | |
| 117 | const struct v850_opcode v850_opcodes[] = { |
| 118 | /* load/store instructions */ |
| 119 | { "sld.b", OP(0x00), OP_MASK, IF4A }, |
| 120 | { "sld.h", OP(0x00), OP_MASK, IF4A }, |
| 121 | { "sld.w", OP(0x00), OP_MASK, IF4A }, |
| 122 | { "sst.b", OP(0x00), OP_MASK, IF4B }, |
| 123 | { "sst.h", OP(0x00), OP_MASK, IF4B }, |
| 124 | { "sst.w", OP(0x00), OP_MASK, IF4B }, |
| 125 | |
| 126 | { "ld.b", OP(0x00), OP_MASK, IF7A }, |
| 127 | { "ld.h", OP(0x00), OP_MASK, IF7A }, |
| 128 | { "ld.w", OP(0x00), OP_MASK, IF7A }, |
| 129 | { "st.b", OP(0x00), OP_MASK, IF7B }, |
| 130 | { "st.h", OP(0x00), OP_MASK, IF7B }, |
| 131 | { "st.w", OP(0x00), OP_MASK, IF7B }, |
| 132 | |
| 133 | /* arithmetic operation instructions */ |
| 134 | { "mov", OP(0x00), OP_MASK, IF1 }, |
| 135 | { "mov", OP(0x08), OP_MASK, IF2 }, |
| 136 | { "movea", OP(0x31), OP_MASK, IF6 }, |
| 137 | { "movhi", OP(0x31), OP_MASK, IF6 }, |
| 138 | { "add", OP(0x0e), OP_MASK, IF1 }, |
| 139 | { "add", OP(0x12), OP_MASK, IF2 }, |
| 140 | { "addi", OP(0x30), OP_MASK, IF6 }, |
| 141 | { "sub", OP(0x0d), OP_MASK, IF1 }, |
| 142 | { "subr", OP(0x0c), OP_MASK, IF1 }, |
| 143 | { "mulh", OP(0x07), OP_MASK, IF1 }, |
| 144 | { "mulh", OP(0x17), OP_MASK, IF2 }, |
| 145 | { "mulhi", OP(0x37), OP_MASK, IF6 }, |
| 146 | { "divh", OP(0x02), OP_MASK, IF1 }, |
| 147 | { "cmp", OP(0x0f), OP_MASK, IF1 }, |
| 148 | { "cmp", OP(0x13), OP_MASK, IF2 }, |
| 149 | { "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} }, |
| 150 | |
| 151 | /* saturated operation instructions */ |
| 152 | { "satadd", OP(0x06), OP_MASK, IF1 }, |
| 153 | { "satadd", OP(0x11), OP_MASK, IF2 }, |
| 154 | { "satsub", OP(0x05), OP_MASK, IF1 }, |
| 155 | { "satsubi", OP(0x33), OP_MASK, IF6 }, |
| 156 | { "satsubr", OP(0x04), OP_MASK, IF1 }, |
| 157 | |
| 158 | /* logical operation instructions */ |
| 159 | { "tst", OP(0x0b), OP_MASK, IF1 }, |
| 160 | { "or", OP(0x08), OP_MASK, IF1 }, |
| 161 | { "ori", OP(0x34), OP_MASK, IF6 }, |
| 162 | { "and", OP(0x0a), OP_MASK, IF1 }, |
| 163 | { "andi", OP(0x36), OP_MASK, IF6 }, |
| 164 | { "xor", OP(0x09), OP_MASK, IF1 }, |
| 165 | { "xori", OP(0x35), OP_MASK, IF6 }, |
| 166 | { "not", OP(0x01), OP_MASK, IF1 }, |
| 167 | { "sar", OP(0x15), OP_MASK, {I5U, R2} }, |
| 168 | { "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} }, |
| 169 | { "shl", OP(0x16), OP_MASK, {I5U, R2} }, |
| 170 | { "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} }, |
| 171 | { "shr", OP(0x14), OP_MASK, {I5U, R2} }, |
| 172 | { "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} }, |
| 173 | |
| 174 | /* branch instructions */ |
| 175 | /* signed integer */ |
| 176 | { "bgt", BOP(0xf), BOP_MASK, IF3 }, |
| 177 | { "bge", BOP(0xe), BOP_MASK, IF3 }, |
| 178 | { "blt", BOP(0x6), BOP_MASK, IF3 }, |
| 179 | { "ble", BOP(0x7), BOP_MASK, IF3 }, |
| 180 | /* unsigned integer */ |
| 181 | { "bh", BOP(0xb), BOP_MASK, IF3 }, |
| 182 | { "bnh", BOP(0x3), BOP_MASK, IF3 }, |
| 183 | { "bl", BOP(0x1), BOP_MASK, IF3 }, |
| 184 | { "bnl", BOP(0x9), BOP_MASK, IF3 }, |
| 185 | /* common */ |
| 186 | { "be", BOP(0x2), BOP_MASK, IF3 }, |
| 187 | { "bne", BOP(0xa), BOP_MASK, IF3 }, |
| 188 | /* others */ |
| 189 | { "bv", BOP(0x0), BOP_MASK, IF3 }, |
| 190 | { "bnv", BOP(0x8), BOP_MASK, IF3 }, |
| 191 | { "bn", BOP(0x4), BOP_MASK, IF3 }, |
| 192 | { "bp", BOP(0xc), BOP_MASK, IF3 }, |
| 193 | { "bc", BOP(0x1), BOP_MASK, IF3 }, |
| 194 | { "bnc", BOP(0x9), BOP_MASK, IF3 }, |
| 195 | { "bz", BOP(0x2), BOP_MASK, IF3 }, |
| 196 | { "bnz", BOP(0xa), BOP_MASK, IF3 }, |
| 197 | { "br", BOP(0x5), BOP_MASK, IF3 }, |
| 198 | { "bsa", BOP(0xd), BOP_MASK, IF3 }, |
| 199 | |
| 200 | { "jmp", one(0x0060), one(0xffe0), R1 }, |
| 201 | { "jarl", one(0x0780), one(0xf83f), { D22, R2 } }, |
| 202 | { "jr", one(0x0780), one(0xffe0), { D22 } }, |
| 203 | |
| 204 | /* bit manipulation instructions */ |
| 205 | { "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, |
| 206 | { "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, |
| 207 | { "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, |
| 208 | { "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} }, |
| 209 | |
| 210 | /* special instructions */ |
| 211 | { "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} }, |
| 212 | { "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} }, |
| 213 | { "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} }, |
| 214 | { "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} }, |
| 215 | { "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} }, |
| 216 | { "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} }, |
| 217 | { "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} }, |
| 218 | { "nop", one(0x00), one(0xff), {0} }, |
| 219 | |
| 220 | } ; |
| 221 | |
| 222 | const int v850_num_opcodes = |
| 223 | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); |
| 224 | |
| 225 | \f |
| 226 | /* The functions used to insert and extract complicated operands. */ |
| 227 | |
| 228 | static unsigned long |
| 229 | insert_d9 (insn, value, errmsg) |
| 230 | unsigned long insn; |
| 231 | long value; |
| 232 | const char **errmsg; |
| 233 | { |
| 234 | if (value > 511 || value <= -512) |
| 235 | *errmsg = "value out of range"; |
| 236 | |
| 237 | return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); |
| 238 | } |
| 239 | |
| 240 | static long |
| 241 | extract_d9 (insn, invalid) |
| 242 | unsigned long insn; |
| 243 | int *invalid; |
| 244 | { |
| 245 | long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); |
| 246 | |
| 247 | if ((insn & 0x8000) != 0) |
| 248 | ret -= 0x0200; |
| 249 | |
| 250 | return ret; |
| 251 | } |