| 1 | /* CPU data for xstormy16. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2009 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| 22 | |
| 23 | */ |
| 24 | |
| 25 | #include "sysdep.h" |
| 26 | #include <stdio.h> |
| 27 | #include <stdarg.h> |
| 28 | #include "ansidecl.h" |
| 29 | #include "bfd.h" |
| 30 | #include "symcat.h" |
| 31 | #include "xstormy16-desc.h" |
| 32 | #include "xstormy16-opc.h" |
| 33 | #include "opintl.h" |
| 34 | #include "libiberty.h" |
| 35 | #include "xregex.h" |
| 36 | |
| 37 | /* Attributes. */ |
| 38 | |
| 39 | static const CGEN_ATTR_ENTRY bool_attr[] = |
| 40 | { |
| 41 | { "#f", 0 }, |
| 42 | { "#t", 1 }, |
| 43 | { 0, 0 } |
| 44 | }; |
| 45 | |
| 46 | static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = |
| 47 | { |
| 48 | { "base", MACH_BASE }, |
| 49 | { "xstormy16", MACH_XSTORMY16 }, |
| 50 | { "max", MACH_MAX }, |
| 51 | { 0, 0 } |
| 52 | }; |
| 53 | |
| 54 | static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = |
| 55 | { |
| 56 | { "xstormy16", ISA_XSTORMY16 }, |
| 57 | { "max", ISA_MAX }, |
| 58 | { 0, 0 } |
| 59 | }; |
| 60 | |
| 61 | const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] = |
| 62 | { |
| 63 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 64 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 65 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 66 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 67 | { "RESERVED", &bool_attr[0], &bool_attr[0] }, |
| 68 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, |
| 69 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, |
| 70 | { 0, 0, 0 } |
| 71 | }; |
| 72 | |
| 73 | const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] = |
| 74 | { |
| 75 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 76 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 77 | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 78 | { "PC", &bool_attr[0], &bool_attr[0] }, |
| 79 | { "PROFILE", &bool_attr[0], &bool_attr[0] }, |
| 80 | { 0, 0, 0 } |
| 81 | }; |
| 82 | |
| 83 | const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] = |
| 84 | { |
| 85 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 86 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 87 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 88 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, |
| 89 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, |
| 90 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, |
| 91 | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, |
| 92 | { "RELAX", &bool_attr[0], &bool_attr[0] }, |
| 93 | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, |
| 94 | { 0, 0, 0 } |
| 95 | }; |
| 96 | |
| 97 | const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] = |
| 98 | { |
| 99 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
| 100 | { "ALIAS", &bool_attr[0], &bool_attr[0] }, |
| 101 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
| 102 | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, |
| 103 | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, |
| 104 | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, |
| 105 | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, |
| 106 | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, |
| 107 | { "RELAXED", &bool_attr[0], &bool_attr[0] }, |
| 108 | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, |
| 109 | { "PBB", &bool_attr[0], &bool_attr[0] }, |
| 110 | { 0, 0, 0 } |
| 111 | }; |
| 112 | |
| 113 | /* Instruction set variants. */ |
| 114 | |
| 115 | static const CGEN_ISA xstormy16_cgen_isa_table[] = { |
| 116 | { "xstormy16", 32, 32, 16, 32 }, |
| 117 | { 0, 0, 0, 0, 0 } |
| 118 | }; |
| 119 | |
| 120 | /* Machine variants. */ |
| 121 | |
| 122 | static const CGEN_MACH xstormy16_cgen_mach_table[] = { |
| 123 | { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 }, |
| 124 | { 0, 0, 0, 0 } |
| 125 | }; |
| 126 | |
| 127 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] = |
| 128 | { |
| 129 | { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, |
| 130 | { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, |
| 131 | { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, |
| 132 | { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, |
| 133 | { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, |
| 134 | { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, |
| 135 | { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, |
| 136 | { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, |
| 137 | { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, |
| 138 | { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, |
| 139 | { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, |
| 140 | { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, |
| 141 | { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, |
| 142 | { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, |
| 143 | { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, |
| 144 | { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, |
| 145 | { "psw", 14, {0, {{{0, 0}}}}, 0, 0 }, |
| 146 | { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } |
| 147 | }; |
| 148 | |
| 149 | CGEN_KEYWORD xstormy16_cgen_opval_gr_names = |
| 150 | { |
| 151 | & xstormy16_cgen_opval_gr_names_entries[0], |
| 152 | 18, |
| 153 | 0, 0, 0, 0, "" |
| 154 | }; |
| 155 | |
| 156 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] = |
| 157 | { |
| 158 | { "r8", 0, {0, {{{0, 0}}}}, 0, 0 }, |
| 159 | { "r9", 1, {0, {{{0, 0}}}}, 0, 0 }, |
| 160 | { "r10", 2, {0, {{{0, 0}}}}, 0, 0 }, |
| 161 | { "r11", 3, {0, {{{0, 0}}}}, 0, 0 }, |
| 162 | { "r12", 4, {0, {{{0, 0}}}}, 0, 0 }, |
| 163 | { "r13", 5, {0, {{{0, 0}}}}, 0, 0 }, |
| 164 | { "r14", 6, {0, {{{0, 0}}}}, 0, 0 }, |
| 165 | { "r15", 7, {0, {{{0, 0}}}}, 0, 0 }, |
| 166 | { "psw", 6, {0, {{{0, 0}}}}, 0, 0 }, |
| 167 | { "sp", 7, {0, {{{0, 0}}}}, 0, 0 } |
| 168 | }; |
| 169 | |
| 170 | CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names = |
| 171 | { |
| 172 | & xstormy16_cgen_opval_gr_Rb_names_entries[0], |
| 173 | 10, |
| 174 | 0, 0, 0, 0, "" |
| 175 | }; |
| 176 | |
| 177 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] = |
| 178 | { |
| 179 | { "ge", 0, {0, {{{0, 0}}}}, 0, 0 }, |
| 180 | { "nc", 1, {0, {{{0, 0}}}}, 0, 0 }, |
| 181 | { "lt", 2, {0, {{{0, 0}}}}, 0, 0 }, |
| 182 | { "c", 3, {0, {{{0, 0}}}}, 0, 0 }, |
| 183 | { "gt", 4, {0, {{{0, 0}}}}, 0, 0 }, |
| 184 | { "hi", 5, {0, {{{0, 0}}}}, 0, 0 }, |
| 185 | { "le", 6, {0, {{{0, 0}}}}, 0, 0 }, |
| 186 | { "ls", 7, {0, {{{0, 0}}}}, 0, 0 }, |
| 187 | { "pl", 8, {0, {{{0, 0}}}}, 0, 0 }, |
| 188 | { "nv", 9, {0, {{{0, 0}}}}, 0, 0 }, |
| 189 | { "mi", 10, {0, {{{0, 0}}}}, 0, 0 }, |
| 190 | { "v", 11, {0, {{{0, 0}}}}, 0, 0 }, |
| 191 | { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 }, |
| 192 | { "nz", 13, {0, {{{0, 0}}}}, 0, 0 }, |
| 193 | { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 }, |
| 194 | { "z", 15, {0, {{{0, 0}}}}, 0, 0 } |
| 195 | }; |
| 196 | |
| 197 | CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond = |
| 198 | { |
| 199 | & xstormy16_cgen_opval_h_branchcond_entries[0], |
| 200 | 16, |
| 201 | 0, 0, 0, 0, "" |
| 202 | }; |
| 203 | |
| 204 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] = |
| 205 | { |
| 206 | { ".b", 0, {0, {{{0, 0}}}}, 0, 0 }, |
| 207 | { ".w", 1, {0, {{{0, 0}}}}, 0, 0 }, |
| 208 | { "", 1, {0, {{{0, 0}}}}, 0, 0 } |
| 209 | }; |
| 210 | |
| 211 | CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize = |
| 212 | { |
| 213 | & xstormy16_cgen_opval_h_wordsize_entries[0], |
| 214 | 3, |
| 215 | 0, 0, 0, 0, "" |
| 216 | }; |
| 217 | |
| 218 | |
| 219 | /* The hardware table. */ |
| 220 | |
| 221 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 222 | #define A(a) (1 << CGEN_HW_##a) |
| 223 | #else |
| 224 | #define A(a) (1 << CGEN_HW_/**/a) |
| 225 | #endif |
| 226 | |
| 227 | const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] = |
| 228 | { |
| 229 | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 230 | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 231 | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 232 | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 233 | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 234 | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, |
| 235 | { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 236 | { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 237 | { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 238 | { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 239 | { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 240 | { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 241 | { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 242 | { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 243 | { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 244 | { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 245 | { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 246 | { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 247 | { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 248 | { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } |
| 249 | }; |
| 250 | |
| 251 | #undef A |
| 252 | |
| 253 | |
| 254 | /* The instruction field table. */ |
| 255 | |
| 256 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 257 | #define A(a) (1 << CGEN_IFLD_##a) |
| 258 | #else |
| 259 | #define A(a) (1 << CGEN_IFLD_/**/a) |
| 260 | #endif |
| 261 | |
| 262 | const CGEN_IFLD xstormy16_cgen_ifld_table[] = |
| 263 | { |
| 264 | { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 265 | { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 266 | { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 267 | { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 268 | { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 269 | { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 270 | { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 271 | { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 272 | { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 273 | { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 274 | { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 275 | { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 276 | { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 277 | { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 278 | { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 279 | { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 280 | { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 281 | { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 282 | { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 283 | { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 284 | { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 285 | { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 286 | { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 287 | { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 288 | { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 289 | { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 290 | { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 291 | { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, |
| 292 | { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 293 | { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 294 | { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 295 | { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 296 | { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 297 | { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 298 | { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 299 | { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 300 | { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 301 | { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } |
| 302 | }; |
| 303 | |
| 304 | #undef A |
| 305 | |
| 306 | |
| 307 | |
| 308 | /* multi ifield declarations */ |
| 309 | |
| 310 | const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD []; |
| 311 | |
| 312 | |
| 313 | /* multi ifield definitions */ |
| 314 | |
| 315 | const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] = |
| 316 | { |
| 317 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } }, |
| 318 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } }, |
| 319 | { 0, { (const PTR) 0 } } |
| 320 | }; |
| 321 | |
| 322 | /* The operand table. */ |
| 323 | |
| 324 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 325 | #define A(a) (1 << CGEN_OPERAND_##a) |
| 326 | #else |
| 327 | #define A(a) (1 << CGEN_OPERAND_/**/a) |
| 328 | #endif |
| 329 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 330 | #define OPERAND(op) XSTORMY16_OPERAND_##op |
| 331 | #else |
| 332 | #define OPERAND(op) XSTORMY16_OPERAND_/**/op |
| 333 | #endif |
| 334 | |
| 335 | const CGEN_OPERAND xstormy16_cgen_operand_table[] = |
| 336 | { |
| 337 | /* pc: program counter */ |
| 338 | { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0, |
| 339 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } }, |
| 340 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 341 | /* psw-z8: */ |
| 342 | { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0, |
| 343 | { 0, { (const PTR) 0 } }, |
| 344 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 345 | /* psw-z16: */ |
| 346 | { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0, |
| 347 | { 0, { (const PTR) 0 } }, |
| 348 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 349 | /* psw-cy: */ |
| 350 | { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0, |
| 351 | { 0, { (const PTR) 0 } }, |
| 352 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 353 | /* psw-hc: */ |
| 354 | { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0, |
| 355 | { 0, { (const PTR) 0 } }, |
| 356 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 357 | /* psw-ov: */ |
| 358 | { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0, |
| 359 | { 0, { (const PTR) 0 } }, |
| 360 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 361 | /* psw-pt: */ |
| 362 | { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0, |
| 363 | { 0, { (const PTR) 0 } }, |
| 364 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 365 | /* psw-s: */ |
| 366 | { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0, |
| 367 | { 0, { (const PTR) 0 } }, |
| 368 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 369 | /* Rd: general register destination */ |
| 370 | { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4, |
| 371 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } }, |
| 372 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 373 | /* Rdm: general register destination */ |
| 374 | { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3, |
| 375 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } }, |
| 376 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 377 | /* Rm: general register for memory */ |
| 378 | { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3, |
| 379 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } }, |
| 380 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 381 | /* Rs: general register source */ |
| 382 | { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4, |
| 383 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } }, |
| 384 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 385 | /* Rb: base register */ |
| 386 | { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3, |
| 387 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } }, |
| 388 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 389 | /* Rbj: base register for jump */ |
| 390 | { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1, |
| 391 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } }, |
| 392 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 393 | /* bcond2: branch condition opcode */ |
| 394 | { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4, |
| 395 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } }, |
| 396 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 397 | /* ws2: word size opcode */ |
| 398 | { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1, |
| 399 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } }, |
| 400 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 401 | /* bcond5: branch condition opcode */ |
| 402 | { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4, |
| 403 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } }, |
| 404 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 405 | /* imm2: 2 bit unsigned immediate */ |
| 406 | { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2, |
| 407 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } }, |
| 408 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 409 | /* imm3: 3 bit unsigned immediate */ |
| 410 | { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3, |
| 411 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } }, |
| 412 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 413 | /* imm3b: 3 bit unsigned immediate for bit tests */ |
| 414 | { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3, |
| 415 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } }, |
| 416 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 417 | /* imm4: 4 bit unsigned immediate */ |
| 418 | { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4, |
| 419 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } }, |
| 420 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 421 | /* imm8: 8 bit unsigned immediate */ |
| 422 | { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8, |
| 423 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, |
| 424 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 425 | /* imm8small: 8 bit unsigned immediate */ |
| 426 | { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8, |
| 427 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, |
| 428 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 429 | /* imm12: 12 bit signed immediate */ |
| 430 | { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12, |
| 431 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } }, |
| 432 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 433 | /* imm16: 16 bit immediate */ |
| 434 | { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16, |
| 435 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } }, |
| 436 | { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, |
| 437 | /* lmem8: 8 bit unsigned immediate low memory */ |
| 438 | { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8, |
| 439 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } }, |
| 440 | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 441 | /* hmem8: 8 bit unsigned immediate high memory */ |
| 442 | { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8, |
| 443 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } }, |
| 444 | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 445 | /* rel8-2: 8 bit relative address */ |
| 446 | { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8, |
| 447 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } }, |
| 448 | { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 449 | /* rel8-4: 8 bit relative address */ |
| 450 | { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8, |
| 451 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } }, |
| 452 | { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 453 | /* rel12: 12 bit relative address */ |
| 454 | { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12, |
| 455 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } }, |
| 456 | { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 457 | /* rel12a: 12 bit relative address */ |
| 458 | { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11, |
| 459 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } }, |
| 460 | { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
| 461 | /* abs24: 24 bit absolute address */ |
| 462 | { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24, |
| 463 | { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } }, |
| 464 | { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
| 465 | /* psw: program status word */ |
| 466 | { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0, |
| 467 | { 0, { (const PTR) 0 } }, |
| 468 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 469 | /* Rpsw: N0-N3 of the program status word */ |
| 470 | { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0, |
| 471 | { 0, { (const PTR) 0 } }, |
| 472 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 473 | /* sp: stack pointer */ |
| 474 | { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0, |
| 475 | { 0, { (const PTR) 0 } }, |
| 476 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 477 | /* R0: R0 */ |
| 478 | { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0, |
| 479 | { 0, { (const PTR) 0 } }, |
| 480 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 481 | /* R1: R1 */ |
| 482 | { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0, |
| 483 | { 0, { (const PTR) 0 } }, |
| 484 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 485 | /* R2: R2 */ |
| 486 | { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0, |
| 487 | { 0, { (const PTR) 0 } }, |
| 488 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 489 | /* R8: R8 */ |
| 490 | { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0, |
| 491 | { 0, { (const PTR) 0 } }, |
| 492 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
| 493 | /* sentinel */ |
| 494 | { 0, 0, 0, 0, 0, |
| 495 | { 0, { (const PTR) 0 } }, |
| 496 | { 0, { { { (1<<MACH_BASE), 0 } } } } } |
| 497 | }; |
| 498 | |
| 499 | #undef A |
| 500 | |
| 501 | |
| 502 | /* The instruction table. */ |
| 503 | |
| 504 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) |
| 505 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
| 506 | #define A(a) (1 << CGEN_INSN_##a) |
| 507 | #else |
| 508 | #define A(a) (1 << CGEN_INSN_/**/a) |
| 509 | #endif |
| 510 | |
| 511 | static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] = |
| 512 | { |
| 513 | /* Special null first entry. |
| 514 | A `num' value of zero is thus invalid. |
| 515 | Also, the special `invalid' insn resides here. */ |
| 516 | { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
| 517 | /* mov$ws2 $lmem8,#$imm16 */ |
| 518 | { |
| 519 | XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32, |
| 520 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 521 | }, |
| 522 | /* mov$ws2 $hmem8,#$imm16 */ |
| 523 | { |
| 524 | XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32, |
| 525 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 526 | }, |
| 527 | /* mov$ws2 $Rm,$lmem8 */ |
| 528 | { |
| 529 | XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16, |
| 530 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 531 | }, |
| 532 | /* mov$ws2 $Rm,$hmem8 */ |
| 533 | { |
| 534 | XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16, |
| 535 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 536 | }, |
| 537 | /* mov$ws2 $lmem8,$Rm */ |
| 538 | { |
| 539 | XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16, |
| 540 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 541 | }, |
| 542 | /* mov$ws2 $hmem8,$Rm */ |
| 543 | { |
| 544 | XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16, |
| 545 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 546 | }, |
| 547 | /* mov$ws2 $Rdm,($Rs) */ |
| 548 | { |
| 549 | XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16, |
| 550 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 551 | }, |
| 552 | /* mov$ws2 $Rdm,($Rs++) */ |
| 553 | { |
| 554 | XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16, |
| 555 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 556 | }, |
| 557 | /* mov$ws2 $Rdm,(--$Rs) */ |
| 558 | { |
| 559 | XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16, |
| 560 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 561 | }, |
| 562 | /* mov$ws2 ($Rs),$Rdm */ |
| 563 | { |
| 564 | XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16, |
| 565 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 566 | }, |
| 567 | /* mov$ws2 ($Rs++),$Rdm */ |
| 568 | { |
| 569 | XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16, |
| 570 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 571 | }, |
| 572 | /* mov$ws2 (--$Rs),$Rdm */ |
| 573 | { |
| 574 | XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16, |
| 575 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 576 | }, |
| 577 | /* mov$ws2 $Rdm,($Rs,$imm12) */ |
| 578 | { |
| 579 | XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32, |
| 580 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 581 | }, |
| 582 | /* mov$ws2 $Rdm,($Rs++,$imm12) */ |
| 583 | { |
| 584 | XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32, |
| 585 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 586 | }, |
| 587 | /* mov$ws2 $Rdm,(--$Rs,$imm12) */ |
| 588 | { |
| 589 | XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32, |
| 590 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 591 | }, |
| 592 | /* mov$ws2 ($Rs,$imm12),$Rdm */ |
| 593 | { |
| 594 | XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32, |
| 595 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 596 | }, |
| 597 | /* mov$ws2 ($Rs++,$imm12),$Rdm */ |
| 598 | { |
| 599 | XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32, |
| 600 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 601 | }, |
| 602 | /* mov$ws2 (--$Rs,$imm12),$Rdm */ |
| 603 | { |
| 604 | XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32, |
| 605 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 606 | }, |
| 607 | /* mov $Rd,$Rs */ |
| 608 | { |
| 609 | XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16, |
| 610 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 611 | }, |
| 612 | /* mov.w Rx,#$imm8 */ |
| 613 | { |
| 614 | XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16, |
| 615 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 616 | }, |
| 617 | /* mov.w $Rm,#$imm8small */ |
| 618 | { |
| 619 | XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16, |
| 620 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 621 | }, |
| 622 | /* mov.w $Rd,#$imm16 */ |
| 623 | { |
| 624 | XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32, |
| 625 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 626 | }, |
| 627 | /* mov.b $Rd,RxL */ |
| 628 | { |
| 629 | XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16, |
| 630 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 631 | }, |
| 632 | /* mov.b $Rd,RxH */ |
| 633 | { |
| 634 | XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16, |
| 635 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 636 | }, |
| 637 | /* movf$ws2 $Rdm,($Rs) */ |
| 638 | { |
| 639 | XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16, |
| 640 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 641 | }, |
| 642 | /* movf$ws2 $Rdm,($Rs++) */ |
| 643 | { |
| 644 | XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16, |
| 645 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 646 | }, |
| 647 | /* movf$ws2 $Rdm,(--$Rs) */ |
| 648 | { |
| 649 | XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16, |
| 650 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 651 | }, |
| 652 | /* movf$ws2 ($Rs),$Rdm */ |
| 653 | { |
| 654 | XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16, |
| 655 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 656 | }, |
| 657 | /* movf$ws2 ($Rs++),$Rdm */ |
| 658 | { |
| 659 | XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16, |
| 660 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 661 | }, |
| 662 | /* movf$ws2 (--$Rs),$Rdm */ |
| 663 | { |
| 664 | XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16, |
| 665 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 666 | }, |
| 667 | /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */ |
| 668 | { |
| 669 | XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32, |
| 670 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 671 | }, |
| 672 | /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */ |
| 673 | { |
| 674 | XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32, |
| 675 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 676 | }, |
| 677 | /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */ |
| 678 | { |
| 679 | XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32, |
| 680 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 681 | }, |
| 682 | /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */ |
| 683 | { |
| 684 | XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32, |
| 685 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 686 | }, |
| 687 | /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */ |
| 688 | { |
| 689 | XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32, |
| 690 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 691 | }, |
| 692 | /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */ |
| 693 | { |
| 694 | XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32, |
| 695 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 696 | }, |
| 697 | /* mask $Rd,$Rs */ |
| 698 | { |
| 699 | XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16, |
| 700 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 701 | }, |
| 702 | /* mask $Rd,#$imm16 */ |
| 703 | { |
| 704 | XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32, |
| 705 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 706 | }, |
| 707 | /* push $Rd */ |
| 708 | { |
| 709 | XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16, |
| 710 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 711 | }, |
| 712 | /* pop $Rd */ |
| 713 | { |
| 714 | XSTORMY16_INSN_POPGR, "popgr", "pop", 16, |
| 715 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 716 | }, |
| 717 | /* swpn $Rd */ |
| 718 | { |
| 719 | XSTORMY16_INSN_SWPN, "swpn", "swpn", 16, |
| 720 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 721 | }, |
| 722 | /* swpb $Rd */ |
| 723 | { |
| 724 | XSTORMY16_INSN_SWPB, "swpb", "swpb", 16, |
| 725 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 726 | }, |
| 727 | /* swpw $Rd,$Rs */ |
| 728 | { |
| 729 | XSTORMY16_INSN_SWPW, "swpw", "swpw", 16, |
| 730 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 731 | }, |
| 732 | /* and $Rd,$Rs */ |
| 733 | { |
| 734 | XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16, |
| 735 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 736 | }, |
| 737 | /* and Rx,#$imm8 */ |
| 738 | { |
| 739 | XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16, |
| 740 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 741 | }, |
| 742 | /* and $Rd,#$imm16 */ |
| 743 | { |
| 744 | XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32, |
| 745 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 746 | }, |
| 747 | /* or $Rd,$Rs */ |
| 748 | { |
| 749 | XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16, |
| 750 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 751 | }, |
| 752 | /* or Rx,#$imm8 */ |
| 753 | { |
| 754 | XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16, |
| 755 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 756 | }, |
| 757 | /* or $Rd,#$imm16 */ |
| 758 | { |
| 759 | XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32, |
| 760 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 761 | }, |
| 762 | /* xor $Rd,$Rs */ |
| 763 | { |
| 764 | XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16, |
| 765 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 766 | }, |
| 767 | /* xor Rx,#$imm8 */ |
| 768 | { |
| 769 | XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16, |
| 770 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 771 | }, |
| 772 | /* xor $Rd,#$imm16 */ |
| 773 | { |
| 774 | XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32, |
| 775 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 776 | }, |
| 777 | /* not $Rd */ |
| 778 | { |
| 779 | XSTORMY16_INSN_NOTGR, "notgr", "not", 16, |
| 780 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 781 | }, |
| 782 | /* add $Rd,$Rs */ |
| 783 | { |
| 784 | XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16, |
| 785 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 786 | }, |
| 787 | /* add $Rd,#$imm4 */ |
| 788 | { |
| 789 | XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16, |
| 790 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 791 | }, |
| 792 | /* add Rx,#$imm8 */ |
| 793 | { |
| 794 | XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16, |
| 795 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 796 | }, |
| 797 | /* add $Rd,#$imm16 */ |
| 798 | { |
| 799 | XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32, |
| 800 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 801 | }, |
| 802 | /* adc $Rd,$Rs */ |
| 803 | { |
| 804 | XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16, |
| 805 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 806 | }, |
| 807 | /* adc $Rd,#$imm4 */ |
| 808 | { |
| 809 | XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16, |
| 810 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 811 | }, |
| 812 | /* adc Rx,#$imm8 */ |
| 813 | { |
| 814 | XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16, |
| 815 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 816 | }, |
| 817 | /* adc $Rd,#$imm16 */ |
| 818 | { |
| 819 | XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32, |
| 820 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 821 | }, |
| 822 | /* sub $Rd,$Rs */ |
| 823 | { |
| 824 | XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16, |
| 825 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 826 | }, |
| 827 | /* sub $Rd,#$imm4 */ |
| 828 | { |
| 829 | XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16, |
| 830 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 831 | }, |
| 832 | /* sub Rx,#$imm8 */ |
| 833 | { |
| 834 | XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16, |
| 835 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 836 | }, |
| 837 | /* sub $Rd,#$imm16 */ |
| 838 | { |
| 839 | XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32, |
| 840 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 841 | }, |
| 842 | /* sbc $Rd,$Rs */ |
| 843 | { |
| 844 | XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16, |
| 845 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 846 | }, |
| 847 | /* sbc $Rd,#$imm4 */ |
| 848 | { |
| 849 | XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16, |
| 850 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 851 | }, |
| 852 | /* sbc Rx,#$imm8 */ |
| 853 | { |
| 854 | XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16, |
| 855 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 856 | }, |
| 857 | /* sbc $Rd,#$imm16 */ |
| 858 | { |
| 859 | XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32, |
| 860 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 861 | }, |
| 862 | /* inc $Rd,#$imm2 */ |
| 863 | { |
| 864 | XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16, |
| 865 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 866 | }, |
| 867 | /* dec $Rd,#$imm2 */ |
| 868 | { |
| 869 | XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16, |
| 870 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 871 | }, |
| 872 | /* rrc $Rd,$Rs */ |
| 873 | { |
| 874 | XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16, |
| 875 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 876 | }, |
| 877 | /* rrc $Rd,#$imm4 */ |
| 878 | { |
| 879 | XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16, |
| 880 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 881 | }, |
| 882 | /* rlc $Rd,$Rs */ |
| 883 | { |
| 884 | XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16, |
| 885 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 886 | }, |
| 887 | /* rlc $Rd,#$imm4 */ |
| 888 | { |
| 889 | XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16, |
| 890 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 891 | }, |
| 892 | /* shr $Rd,$Rs */ |
| 893 | { |
| 894 | XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16, |
| 895 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 896 | }, |
| 897 | /* shr $Rd,#$imm4 */ |
| 898 | { |
| 899 | XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16, |
| 900 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 901 | }, |
| 902 | /* shl $Rd,$Rs */ |
| 903 | { |
| 904 | XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16, |
| 905 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 906 | }, |
| 907 | /* shl $Rd,#$imm4 */ |
| 908 | { |
| 909 | XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16, |
| 910 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 911 | }, |
| 912 | /* asr $Rd,$Rs */ |
| 913 | { |
| 914 | XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16, |
| 915 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 916 | }, |
| 917 | /* asr $Rd,#$imm4 */ |
| 918 | { |
| 919 | XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16, |
| 920 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 921 | }, |
| 922 | /* set1 $Rd,#$imm4 */ |
| 923 | { |
| 924 | XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16, |
| 925 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 926 | }, |
| 927 | /* set1 $Rd,$Rs */ |
| 928 | { |
| 929 | XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16, |
| 930 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 931 | }, |
| 932 | /* set1 $lmem8,#$imm3 */ |
| 933 | { |
| 934 | XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16, |
| 935 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 936 | }, |
| 937 | /* set1 $hmem8,#$imm3 */ |
| 938 | { |
| 939 | XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16, |
| 940 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 941 | }, |
| 942 | /* clr1 $Rd,#$imm4 */ |
| 943 | { |
| 944 | XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16, |
| 945 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 946 | }, |
| 947 | /* clr1 $Rd,$Rs */ |
| 948 | { |
| 949 | XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16, |
| 950 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 951 | }, |
| 952 | /* clr1 $lmem8,#$imm3 */ |
| 953 | { |
| 954 | XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16, |
| 955 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 956 | }, |
| 957 | /* clr1 $hmem8,#$imm3 */ |
| 958 | { |
| 959 | XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16, |
| 960 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 961 | }, |
| 962 | /* cbw $Rd */ |
| 963 | { |
| 964 | XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16, |
| 965 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 966 | }, |
| 967 | /* rev $Rd */ |
| 968 | { |
| 969 | XSTORMY16_INSN_REVGR, "revgr", "rev", 16, |
| 970 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 971 | }, |
| 972 | /* b$bcond5 $Rd,$Rs,$rel12 */ |
| 973 | { |
| 974 | XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32, |
| 975 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 976 | }, |
| 977 | /* b$bcond5 $Rm,#$imm8,$rel12 */ |
| 978 | { |
| 979 | XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32, |
| 980 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 981 | }, |
| 982 | /* b$bcond2 Rx,#$imm16,${rel8-4} */ |
| 983 | { |
| 984 | XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32, |
| 985 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 986 | }, |
| 987 | /* bn $Rd,#$imm4,$rel12 */ |
| 988 | { |
| 989 | XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32, |
| 990 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 991 | }, |
| 992 | /* bn $Rd,$Rs,$rel12 */ |
| 993 | { |
| 994 | XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32, |
| 995 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 996 | }, |
| 997 | /* bn $lmem8,#$imm3b,$rel12 */ |
| 998 | { |
| 999 | XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32, |
| 1000 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1001 | }, |
| 1002 | /* bn $hmem8,#$imm3b,$rel12 */ |
| 1003 | { |
| 1004 | XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32, |
| 1005 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1006 | }, |
| 1007 | /* bp $Rd,#$imm4,$rel12 */ |
| 1008 | { |
| 1009 | XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32, |
| 1010 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1011 | }, |
| 1012 | /* bp $Rd,$Rs,$rel12 */ |
| 1013 | { |
| 1014 | XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32, |
| 1015 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1016 | }, |
| 1017 | /* bp $lmem8,#$imm3b,$rel12 */ |
| 1018 | { |
| 1019 | XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32, |
| 1020 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1021 | }, |
| 1022 | /* bp $hmem8,#$imm3b,$rel12 */ |
| 1023 | { |
| 1024 | XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32, |
| 1025 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1026 | }, |
| 1027 | /* b$bcond2 ${rel8-2} */ |
| 1028 | { |
| 1029 | XSTORMY16_INSN_BCC, "bcc", "b", 16, |
| 1030 | { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1031 | }, |
| 1032 | /* br $Rd */ |
| 1033 | { |
| 1034 | XSTORMY16_INSN_BGR, "bgr", "br", 16, |
| 1035 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1036 | }, |
| 1037 | /* br $rel12a */ |
| 1038 | { |
| 1039 | XSTORMY16_INSN_BR, "br", "br", 16, |
| 1040 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1041 | }, |
| 1042 | /* jmp $Rbj,$Rd */ |
| 1043 | { |
| 1044 | XSTORMY16_INSN_JMP, "jmp", "jmp", 16, |
| 1045 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1046 | }, |
| 1047 | /* jmpf $abs24 */ |
| 1048 | { |
| 1049 | XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32, |
| 1050 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1051 | }, |
| 1052 | /* callr $Rd */ |
| 1053 | { |
| 1054 | XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16, |
| 1055 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1056 | }, |
| 1057 | /* callr $rel12a */ |
| 1058 | { |
| 1059 | XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16, |
| 1060 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1061 | }, |
| 1062 | /* call $Rbj,$Rd */ |
| 1063 | { |
| 1064 | XSTORMY16_INSN_CALLGR, "callgr", "call", 16, |
| 1065 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1066 | }, |
| 1067 | /* callf $abs24 */ |
| 1068 | { |
| 1069 | XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32, |
| 1070 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1071 | }, |
| 1072 | /* icallr $Rd */ |
| 1073 | { |
| 1074 | XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16, |
| 1075 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1076 | }, |
| 1077 | /* icall $Rbj,$Rd */ |
| 1078 | { |
| 1079 | XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16, |
| 1080 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1081 | }, |
| 1082 | /* icallf $abs24 */ |
| 1083 | { |
| 1084 | XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32, |
| 1085 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1086 | }, |
| 1087 | /* iret */ |
| 1088 | { |
| 1089 | XSTORMY16_INSN_IRET, "iret", "iret", 16, |
| 1090 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1091 | }, |
| 1092 | /* ret */ |
| 1093 | { |
| 1094 | XSTORMY16_INSN_RET, "ret", "ret", 16, |
| 1095 | { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } |
| 1096 | }, |
| 1097 | /* mul */ |
| 1098 | { |
| 1099 | XSTORMY16_INSN_MUL, "mul", "mul", 16, |
| 1100 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1101 | }, |
| 1102 | /* div */ |
| 1103 | { |
| 1104 | XSTORMY16_INSN_DIV, "div", "div", 16, |
| 1105 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1106 | }, |
| 1107 | /* sdiv */ |
| 1108 | { |
| 1109 | XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16, |
| 1110 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1111 | }, |
| 1112 | /* sdivlh */ |
| 1113 | { |
| 1114 | XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16, |
| 1115 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1116 | }, |
| 1117 | /* divlh */ |
| 1118 | { |
| 1119 | XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16, |
| 1120 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1121 | }, |
| 1122 | /* reset */ |
| 1123 | { |
| 1124 | XSTORMY16_INSN_RESET, "reset", "reset", 16, |
| 1125 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1126 | }, |
| 1127 | /* nop */ |
| 1128 | { |
| 1129 | XSTORMY16_INSN_NOP, "nop", "nop", 16, |
| 1130 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1131 | }, |
| 1132 | /* halt */ |
| 1133 | { |
| 1134 | XSTORMY16_INSN_HALT, "halt", "halt", 16, |
| 1135 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1136 | }, |
| 1137 | /* hold */ |
| 1138 | { |
| 1139 | XSTORMY16_INSN_HOLD, "hold", "hold", 16, |
| 1140 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1141 | }, |
| 1142 | /* holdx */ |
| 1143 | { |
| 1144 | XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16, |
| 1145 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1146 | }, |
| 1147 | /* brk */ |
| 1148 | { |
| 1149 | XSTORMY16_INSN_BRK, "brk", "brk", 16, |
| 1150 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1151 | }, |
| 1152 | /* --unused-- */ |
| 1153 | { |
| 1154 | XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16, |
| 1155 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
| 1156 | }, |
| 1157 | }; |
| 1158 | |
| 1159 | #undef OP |
| 1160 | #undef A |
| 1161 | |
| 1162 | /* Initialize anything needed to be done once, before any cpu_open call. */ |
| 1163 | |
| 1164 | static void |
| 1165 | init_tables (void) |
| 1166 | { |
| 1167 | } |
| 1168 | |
| 1169 | static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); |
| 1170 | static void build_hw_table (CGEN_CPU_TABLE *); |
| 1171 | static void build_ifield_table (CGEN_CPU_TABLE *); |
| 1172 | static void build_operand_table (CGEN_CPU_TABLE *); |
| 1173 | static void build_insn_table (CGEN_CPU_TABLE *); |
| 1174 | static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *); |
| 1175 | |
| 1176 | /* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */ |
| 1177 | |
| 1178 | static const CGEN_MACH * |
| 1179 | lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) |
| 1180 | { |
| 1181 | while (table->name) |
| 1182 | { |
| 1183 | if (strcmp (name, table->bfd_name) == 0) |
| 1184 | return table; |
| 1185 | ++table; |
| 1186 | } |
| 1187 | abort (); |
| 1188 | } |
| 1189 | |
| 1190 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ |
| 1191 | |
| 1192 | static void |
| 1193 | build_hw_table (CGEN_CPU_TABLE *cd) |
| 1194 | { |
| 1195 | int i; |
| 1196 | int machs = cd->machs; |
| 1197 | const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0]; |
| 1198 | /* MAX_HW is only an upper bound on the number of selected entries. |
| 1199 | However each entry is indexed by it's enum so there can be holes in |
| 1200 | the table. */ |
| 1201 | const CGEN_HW_ENTRY **selected = |
| 1202 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); |
| 1203 | |
| 1204 | cd->hw_table.init_entries = init; |
| 1205 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); |
| 1206 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); |
| 1207 | /* ??? For now we just use machs to determine which ones we want. */ |
| 1208 | for (i = 0; init[i].name != NULL; ++i) |
| 1209 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) |
| 1210 | & machs) |
| 1211 | selected[init[i].type] = &init[i]; |
| 1212 | cd->hw_table.entries = selected; |
| 1213 | cd->hw_table.num_entries = MAX_HW; |
| 1214 | } |
| 1215 | |
| 1216 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ |
| 1217 | |
| 1218 | static void |
| 1219 | build_ifield_table (CGEN_CPU_TABLE *cd) |
| 1220 | { |
| 1221 | cd->ifld_table = & xstormy16_cgen_ifld_table[0]; |
| 1222 | } |
| 1223 | |
| 1224 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ |
| 1225 | |
| 1226 | static void |
| 1227 | build_operand_table (CGEN_CPU_TABLE *cd) |
| 1228 | { |
| 1229 | int i; |
| 1230 | int machs = cd->machs; |
| 1231 | const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0]; |
| 1232 | /* MAX_OPERANDS is only an upper bound on the number of selected entries. |
| 1233 | However each entry is indexed by it's enum so there can be holes in |
| 1234 | the table. */ |
| 1235 | const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); |
| 1236 | |
| 1237 | cd->operand_table.init_entries = init; |
| 1238 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); |
| 1239 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); |
| 1240 | /* ??? For now we just use mach to determine which ones we want. */ |
| 1241 | for (i = 0; init[i].name != NULL; ++i) |
| 1242 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) |
| 1243 | & machs) |
| 1244 | selected[init[i].type] = &init[i]; |
| 1245 | cd->operand_table.entries = selected; |
| 1246 | cd->operand_table.num_entries = MAX_OPERANDS; |
| 1247 | } |
| 1248 | |
| 1249 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. |
| 1250 | ??? This could leave out insns not supported by the specified mach/isa, |
| 1251 | but that would cause errors like "foo only supported by bar" to become |
| 1252 | "unknown insn", so for now we include all insns and require the app to |
| 1253 | do the checking later. |
| 1254 | ??? On the other hand, parsing of such insns may require their hardware or |
| 1255 | operand elements to be in the table [which they mightn't be]. */ |
| 1256 | |
| 1257 | static void |
| 1258 | build_insn_table (CGEN_CPU_TABLE *cd) |
| 1259 | { |
| 1260 | int i; |
| 1261 | const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0]; |
| 1262 | CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); |
| 1263 | |
| 1264 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); |
| 1265 | for (i = 0; i < MAX_INSNS; ++i) |
| 1266 | insns[i].base = &ib[i]; |
| 1267 | cd->insn_table.init_entries = insns; |
| 1268 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); |
| 1269 | cd->insn_table.num_init_entries = MAX_INSNS; |
| 1270 | } |
| 1271 | |
| 1272 | /* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */ |
| 1273 | |
| 1274 | static void |
| 1275 | xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) |
| 1276 | { |
| 1277 | int i; |
| 1278 | CGEN_BITSET *isas = cd->isas; |
| 1279 | unsigned int machs = cd->machs; |
| 1280 | |
| 1281 | cd->int_insn_p = CGEN_INT_INSN_P; |
| 1282 | |
| 1283 | /* Data derived from the isa spec. */ |
| 1284 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) |
| 1285 | cd->default_insn_bitsize = UNSET; |
| 1286 | cd->base_insn_bitsize = UNSET; |
| 1287 | cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ |
| 1288 | cd->max_insn_bitsize = 0; |
| 1289 | for (i = 0; i < MAX_ISAS; ++i) |
| 1290 | if (cgen_bitset_contains (isas, i)) |
| 1291 | { |
| 1292 | const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i]; |
| 1293 | |
| 1294 | /* Default insn sizes of all selected isas must be |
| 1295 | equal or we set the result to 0, meaning "unknown". */ |
| 1296 | if (cd->default_insn_bitsize == UNSET) |
| 1297 | cd->default_insn_bitsize = isa->default_insn_bitsize; |
| 1298 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) |
| 1299 | ; /* This is ok. */ |
| 1300 | else |
| 1301 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; |
| 1302 | |
| 1303 | /* Base insn sizes of all selected isas must be equal |
| 1304 | or we set the result to 0, meaning "unknown". */ |
| 1305 | if (cd->base_insn_bitsize == UNSET) |
| 1306 | cd->base_insn_bitsize = isa->base_insn_bitsize; |
| 1307 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) |
| 1308 | ; /* This is ok. */ |
| 1309 | else |
| 1310 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; |
| 1311 | |
| 1312 | /* Set min,max insn sizes. */ |
| 1313 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) |
| 1314 | cd->min_insn_bitsize = isa->min_insn_bitsize; |
| 1315 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) |
| 1316 | cd->max_insn_bitsize = isa->max_insn_bitsize; |
| 1317 | } |
| 1318 | |
| 1319 | /* Data derived from the mach spec. */ |
| 1320 | for (i = 0; i < MAX_MACHS; ++i) |
| 1321 | if (((1 << i) & machs) != 0) |
| 1322 | { |
| 1323 | const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i]; |
| 1324 | |
| 1325 | if (mach->insn_chunk_bitsize != 0) |
| 1326 | { |
| 1327 | if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) |
| 1328 | { |
| 1329 | fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", |
| 1330 | cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); |
| 1331 | abort (); |
| 1332 | } |
| 1333 | |
| 1334 | cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; |
| 1335 | } |
| 1336 | } |
| 1337 | |
| 1338 | /* Determine which hw elements are used by MACH. */ |
| 1339 | build_hw_table (cd); |
| 1340 | |
| 1341 | /* Build the ifield table. */ |
| 1342 | build_ifield_table (cd); |
| 1343 | |
| 1344 | /* Determine which operands are used by MACH/ISA. */ |
| 1345 | build_operand_table (cd); |
| 1346 | |
| 1347 | /* Build the instruction table. */ |
| 1348 | build_insn_table (cd); |
| 1349 | } |
| 1350 | |
| 1351 | /* Initialize a cpu table and return a descriptor. |
| 1352 | It's much like opening a file, and must be the first function called. |
| 1353 | The arguments are a set of (type/value) pairs, terminated with |
| 1354 | CGEN_CPU_OPEN_END. |
| 1355 | |
| 1356 | Currently supported values: |
| 1357 | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr |
| 1358 | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr |
| 1359 | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name |
| 1360 | CGEN_CPU_OPEN_ENDIAN: specify endian choice |
| 1361 | CGEN_CPU_OPEN_END: terminates arguments |
| 1362 | |
| 1363 | ??? Simultaneous multiple isas might not make sense, but it's not (yet) |
| 1364 | precluded. |
| 1365 | |
| 1366 | ??? We only support ISO C stdargs here, not K&R. |
| 1367 | Laziness, plus experiment to see if anything requires K&R - eventually |
| 1368 | K&R will no longer be supported - e.g. GDB is currently trying this. */ |
| 1369 | |
| 1370 | CGEN_CPU_DESC |
| 1371 | xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) |
| 1372 | { |
| 1373 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); |
| 1374 | static int init_p; |
| 1375 | CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ |
| 1376 | unsigned int machs = 0; /* 0 = "unspecified" */ |
| 1377 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; |
| 1378 | va_list ap; |
| 1379 | |
| 1380 | if (! init_p) |
| 1381 | { |
| 1382 | init_tables (); |
| 1383 | init_p = 1; |
| 1384 | } |
| 1385 | |
| 1386 | memset (cd, 0, sizeof (*cd)); |
| 1387 | |
| 1388 | va_start (ap, arg_type); |
| 1389 | while (arg_type != CGEN_CPU_OPEN_END) |
| 1390 | { |
| 1391 | switch (arg_type) |
| 1392 | { |
| 1393 | case CGEN_CPU_OPEN_ISAS : |
| 1394 | isas = va_arg (ap, CGEN_BITSET *); |
| 1395 | break; |
| 1396 | case CGEN_CPU_OPEN_MACHS : |
| 1397 | machs = va_arg (ap, unsigned int); |
| 1398 | break; |
| 1399 | case CGEN_CPU_OPEN_BFDMACH : |
| 1400 | { |
| 1401 | const char *name = va_arg (ap, const char *); |
| 1402 | const CGEN_MACH *mach = |
| 1403 | lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name); |
| 1404 | |
| 1405 | machs |= 1 << mach->num; |
| 1406 | break; |
| 1407 | } |
| 1408 | case CGEN_CPU_OPEN_ENDIAN : |
| 1409 | endian = va_arg (ap, enum cgen_endian); |
| 1410 | break; |
| 1411 | default : |
| 1412 | fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n", |
| 1413 | arg_type); |
| 1414 | abort (); /* ??? return NULL? */ |
| 1415 | } |
| 1416 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); |
| 1417 | } |
| 1418 | va_end (ap); |
| 1419 | |
| 1420 | /* Mach unspecified means "all". */ |
| 1421 | if (machs == 0) |
| 1422 | machs = (1 << MAX_MACHS) - 1; |
| 1423 | /* Base mach is always selected. */ |
| 1424 | machs |= 1; |
| 1425 | if (endian == CGEN_ENDIAN_UNKNOWN) |
| 1426 | { |
| 1427 | /* ??? If target has only one, could have a default. */ |
| 1428 | fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n"); |
| 1429 | abort (); |
| 1430 | } |
| 1431 | |
| 1432 | cd->isas = cgen_bitset_copy (isas); |
| 1433 | cd->machs = machs; |
| 1434 | cd->endian = endian; |
| 1435 | /* FIXME: for the sparc case we can determine insn-endianness statically. |
| 1436 | The worry here is where both data and insn endian can be independently |
| 1437 | chosen, in which case this function will need another argument. |
| 1438 | Actually, will want to allow for more arguments in the future anyway. */ |
| 1439 | cd->insn_endian = endian; |
| 1440 | |
| 1441 | /* Table (re)builder. */ |
| 1442 | cd->rebuild_tables = xstormy16_cgen_rebuild_tables; |
| 1443 | xstormy16_cgen_rebuild_tables (cd); |
| 1444 | |
| 1445 | /* Default to not allowing signed overflow. */ |
| 1446 | cd->signed_overflow_ok_p = 0; |
| 1447 | |
| 1448 | return (CGEN_CPU_DESC) cd; |
| 1449 | } |
| 1450 | |
| 1451 | /* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. |
| 1452 | MACH_NAME is the bfd name of the mach. */ |
| 1453 | |
| 1454 | CGEN_CPU_DESC |
| 1455 | xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) |
| 1456 | { |
| 1457 | return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, |
| 1458 | CGEN_CPU_OPEN_ENDIAN, endian, |
| 1459 | CGEN_CPU_OPEN_END); |
| 1460 | } |
| 1461 | |
| 1462 | /* Close a cpu table. |
| 1463 | ??? This can live in a machine independent file, but there's currently |
| 1464 | no place to put this file (there's no libcgen). libopcodes is the wrong |
| 1465 | place as some simulator ports use this but they don't use libopcodes. */ |
| 1466 | |
| 1467 | void |
| 1468 | xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd) |
| 1469 | { |
| 1470 | unsigned int i; |
| 1471 | const CGEN_INSN *insns; |
| 1472 | |
| 1473 | if (cd->macro_insn_table.init_entries) |
| 1474 | { |
| 1475 | insns = cd->macro_insn_table.init_entries; |
| 1476 | for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) |
| 1477 | if (CGEN_INSN_RX ((insns))) |
| 1478 | regfree (CGEN_INSN_RX (insns)); |
| 1479 | } |
| 1480 | |
| 1481 | if (cd->insn_table.init_entries) |
| 1482 | { |
| 1483 | insns = cd->insn_table.init_entries; |
| 1484 | for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) |
| 1485 | if (CGEN_INSN_RX (insns)) |
| 1486 | regfree (CGEN_INSN_RX (insns)); |
| 1487 | } |
| 1488 | |
| 1489 | if (cd->macro_insn_table.init_entries) |
| 1490 | free ((CGEN_INSN *) cd->macro_insn_table.init_entries); |
| 1491 | |
| 1492 | if (cd->insn_table.init_entries) |
| 1493 | free ((CGEN_INSN *) cd->insn_table.init_entries); |
| 1494 | |
| 1495 | if (cd->hw_table.entries) |
| 1496 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); |
| 1497 | |
| 1498 | if (cd->operand_table.entries) |
| 1499 | free ((CGEN_HW_ENTRY *) cd->operand_table.entries); |
| 1500 | |
| 1501 | free (cd); |
| 1502 | } |
| 1503 | |