| 1 | /* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. |
| 2 | Copyright (C) 1994 Advanced RISC Machines Ltd. |
| 3 | |
| 4 | This program is free software; you can redistribute it and/or modify |
| 5 | it under the terms of the GNU General Public License as published by |
| 6 | the Free Software Foundation; either version 3 of the License, or |
| 7 | (at your option) any later version. |
| 8 | |
| 9 | This program is distributed in the hope that it will be useful, |
| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | GNU General Public License for more details. |
| 13 | |
| 14 | You should have received a copy of the GNU General Public License |
| 15 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
| 16 | |
| 17 | #include <string.h> |
| 18 | |
| 19 | #include "armdefs.h" |
| 20 | #include "armemu.h" |
| 21 | #include "dbg_rdi.h" |
| 22 | |
| 23 | /***************************************************************************\ |
| 24 | * Definitions for the emulator architecture * |
| 25 | \***************************************************************************/ |
| 26 | |
| 27 | void ARMul_EmulateInit (void); |
| 28 | ARMul_State *ARMul_NewState (void); |
| 29 | void ARMul_Reset (ARMul_State * state); |
| 30 | ARMword ARMul_DoCycle (ARMul_State * state); |
| 31 | unsigned ARMul_DoCoPro (ARMul_State * state); |
| 32 | ARMword ARMul_DoProg (ARMul_State * state); |
| 33 | ARMword ARMul_DoInstr (ARMul_State * state); |
| 34 | void ARMul_Abort (ARMul_State * state, ARMword address); |
| 35 | |
| 36 | unsigned ARMul_MultTable[32] = |
| 37 | { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, |
| 38 | 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 |
| 39 | }; |
| 40 | ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ |
| 41 | char ARMul_BitList[256]; /* number of bits in a byte table */ |
| 42 | |
| 43 | /* The PC pipeline value depends on whether ARM |
| 44 | or Thumb instructions are being executed. */ |
| 45 | ARMword isize; |
| 46 | |
| 47 | /***************************************************************************\ |
| 48 | * Call this routine once to set up the emulator's tables. * |
| 49 | \***************************************************************************/ |
| 50 | |
| 51 | void |
| 52 | ARMul_EmulateInit (void) |
| 53 | { |
| 54 | unsigned long i, j; |
| 55 | |
| 56 | for (i = 0; i < 4096; i++) |
| 57 | { /* the values of 12 bit dp rhs's */ |
| 58 | ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); |
| 59 | } |
| 60 | |
| 61 | for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ |
| 62 | for (j = 1; j < 256; j <<= 1) |
| 63 | for (i = 0; i < 256; i++) |
| 64 | if ((i & j) > 0) |
| 65 | ARMul_BitList[i]++; |
| 66 | |
| 67 | for (i = 0; i < 256; i++) |
| 68 | ARMul_BitList[i] *= 4; /* you always need 4 times these values */ |
| 69 | |
| 70 | } |
| 71 | |
| 72 | /***************************************************************************\ |
| 73 | * Returns a new instantiation of the ARMulator's state * |
| 74 | \***************************************************************************/ |
| 75 | |
| 76 | ARMul_State * |
| 77 | ARMul_NewState (void) |
| 78 | { |
| 79 | ARMul_State *state; |
| 80 | unsigned i, j; |
| 81 | |
| 82 | state = (ARMul_State *) malloc (sizeof (ARMul_State)); |
| 83 | memset (state, 0, sizeof (ARMul_State)); |
| 84 | |
| 85 | state->Emulate = RUN; |
| 86 | for (i = 0; i < 16; i++) |
| 87 | { |
| 88 | state->Reg[i] = 0; |
| 89 | for (j = 0; j < 7; j++) |
| 90 | state->RegBank[j][i] = 0; |
| 91 | } |
| 92 | for (i = 0; i < 7; i++) |
| 93 | state->Spsr[i] = 0; |
| 94 | |
| 95 | /* state->Mode = USER26MODE; */ |
| 96 | state->Mode = USER32MODE; |
| 97 | |
| 98 | state->CallDebug = FALSE; |
| 99 | state->Debug = FALSE; |
| 100 | state->VectorCatch = 0; |
| 101 | state->Aborted = FALSE; |
| 102 | state->Reseted = FALSE; |
| 103 | state->Inted = 3; |
| 104 | state->LastInted = 3; |
| 105 | |
| 106 | state->MemDataPtr = NULL; |
| 107 | state->MemInPtr = NULL; |
| 108 | state->MemOutPtr = NULL; |
| 109 | state->MemSparePtr = NULL; |
| 110 | state->MemSize = 0; |
| 111 | |
| 112 | state->OSptr = NULL; |
| 113 | state->CommandLine = NULL; |
| 114 | |
| 115 | state->CP14R0_CCD = -1; |
| 116 | state->LastTime = 0; |
| 117 | |
| 118 | state->EventSet = 0; |
| 119 | state->Now = 0; |
| 120 | state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * |
| 121 | sizeof (struct EventNode |
| 122 | *)); |
| 123 | for (i = 0; i < EVENTLISTSIZE; i++) |
| 124 | *(state->EventPtr + i) = NULL; |
| 125 | |
| 126 | state->prog32Sig = HIGH; |
| 127 | state->data32Sig = HIGH; |
| 128 | |
| 129 | state->lateabtSig = LOW; |
| 130 | state->bigendSig = LOW; |
| 131 | |
| 132 | state->is_v4 = LOW; |
| 133 | state->is_v5 = LOW; |
| 134 | state->is_v5e = LOW; |
| 135 | state->is_XScale = LOW; |
| 136 | state->is_iWMMXt = LOW; |
| 137 | state->is_v6 = LOW; |
| 138 | |
| 139 | ARMul_Reset (state); |
| 140 | |
| 141 | return state; |
| 142 | } |
| 143 | |
| 144 | /***************************************************************************\ |
| 145 | Call this routine to set ARMulator to model certain processor properities |
| 146 | \***************************************************************************/ |
| 147 | |
| 148 | void |
| 149 | ARMul_SelectProcessor (ARMul_State * state, unsigned properties) |
| 150 | { |
| 151 | if (properties & ARM_Fix26_Prop) |
| 152 | { |
| 153 | state->prog32Sig = LOW; |
| 154 | state->data32Sig = LOW; |
| 155 | } |
| 156 | else |
| 157 | { |
| 158 | state->prog32Sig = HIGH; |
| 159 | state->data32Sig = HIGH; |
| 160 | } |
| 161 | |
| 162 | state->lateabtSig = LOW; |
| 163 | |
| 164 | state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; |
| 165 | state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; |
| 166 | state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; |
| 167 | state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; |
| 168 | state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; |
| 169 | state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; |
| 170 | state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; |
| 171 | |
| 172 | /* Only initialse the coprocessor support once we |
| 173 | know what kind of chip we are dealing with. */ |
| 174 | ARMul_CoProInit (state); |
| 175 | } |
| 176 | |
| 177 | /***************************************************************************\ |
| 178 | * Call this routine to set up the initial machine state (or perform a RESET * |
| 179 | \***************************************************************************/ |
| 180 | |
| 181 | void |
| 182 | ARMul_Reset (ARMul_State * state) |
| 183 | { |
| 184 | state->NextInstr = 0; |
| 185 | |
| 186 | if (state->prog32Sig) |
| 187 | { |
| 188 | state->Reg[15] = 0; |
| 189 | state->Cpsr = INTBITS | SVC32MODE; |
| 190 | state->Mode = SVC32MODE; |
| 191 | } |
| 192 | else |
| 193 | { |
| 194 | state->Reg[15] = R15INTBITS | SVC26MODE; |
| 195 | state->Cpsr = INTBITS | SVC26MODE; |
| 196 | state->Mode = SVC26MODE; |
| 197 | } |
| 198 | |
| 199 | ARMul_CPSRAltered (state); |
| 200 | state->Bank = SVCBANK; |
| 201 | |
| 202 | FLUSHPIPE; |
| 203 | |
| 204 | state->EndCondition = 0; |
| 205 | |
| 206 | state->Exception = FALSE; |
| 207 | state->NresetSig = HIGH; |
| 208 | state->NfiqSig = HIGH; |
| 209 | state->NirqSig = HIGH; |
| 210 | state->NtransSig = (state->Mode & 3) ? HIGH : LOW; |
| 211 | state->abortSig = LOW; |
| 212 | state->AbortAddr = 1; |
| 213 | |
| 214 | state->NumInstrs = 0; |
| 215 | state->NumNcycles = 0; |
| 216 | state->NumScycles = 0; |
| 217 | state->NumIcycles = 0; |
| 218 | state->NumCcycles = 0; |
| 219 | state->NumFcycles = 0; |
| 220 | #ifdef ASIM |
| 221 | (void) ARMul_MemoryInit (); |
| 222 | ARMul_OSInit (state); |
| 223 | #endif |
| 224 | } |
| 225 | |
| 226 | |
| 227 | /***************************************************************************\ |
| 228 | * Emulate the execution of an entire program. Start the correct emulator * |
| 229 | * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * |
| 230 | * address of the last instruction that is executed. * |
| 231 | \***************************************************************************/ |
| 232 | |
| 233 | ARMword |
| 234 | ARMul_DoProg (ARMul_State * state) |
| 235 | { |
| 236 | ARMword pc = 0; |
| 237 | |
| 238 | state->Emulate = RUN; |
| 239 | while (state->Emulate != STOP) |
| 240 | { |
| 241 | state->Emulate = RUN; |
| 242 | if (state->prog32Sig && ARMul_MODE32BIT) |
| 243 | pc = ARMul_Emulate32 (state); |
| 244 | else |
| 245 | pc = ARMul_Emulate26 (state); |
| 246 | } |
| 247 | return (pc); |
| 248 | } |
| 249 | |
| 250 | /***************************************************************************\ |
| 251 | * Emulate the execution of one instruction. Start the correct emulator * |
| 252 | * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * |
| 253 | * address of the instruction that is executed. * |
| 254 | \***************************************************************************/ |
| 255 | |
| 256 | ARMword |
| 257 | ARMul_DoInstr (ARMul_State * state) |
| 258 | { |
| 259 | ARMword pc = 0; |
| 260 | |
| 261 | state->Emulate = ONCE; |
| 262 | if (state->prog32Sig && ARMul_MODE32BIT) |
| 263 | pc = ARMul_Emulate32 (state); |
| 264 | else |
| 265 | pc = ARMul_Emulate26 (state); |
| 266 | |
| 267 | return (pc); |
| 268 | } |
| 269 | |
| 270 | /***************************************************************************\ |
| 271 | * This routine causes an Abort to occur, including selecting the correct * |
| 272 | * mode, register bank, and the saving of registers. Call with the * |
| 273 | * appropriate vector's memory address (0,4,8 ....) * |
| 274 | \***************************************************************************/ |
| 275 | |
| 276 | void |
| 277 | ARMul_Abort (ARMul_State * state, ARMword vector) |
| 278 | { |
| 279 | ARMword temp; |
| 280 | int isize = INSN_SIZE; |
| 281 | int esize = (TFLAG ? 0 : 4); |
| 282 | int e2size = (TFLAG ? -4 : 0); |
| 283 | |
| 284 | state->Aborted = FALSE; |
| 285 | |
| 286 | if (state->prog32Sig) |
| 287 | if (ARMul_MODE26BIT) |
| 288 | temp = R15PC; |
| 289 | else |
| 290 | temp = state->Reg[15]; |
| 291 | else |
| 292 | temp = R15PC | ECC | ER15INT | EMODE; |
| 293 | |
| 294 | switch (vector) |
| 295 | { |
| 296 | case ARMul_ResetV: /* RESET */ |
| 297 | SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0); |
| 298 | break; |
| 299 | case ARMul_UndefinedInstrV: /* Undefined Instruction */ |
| 300 | SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize); |
| 301 | break; |
| 302 | case ARMul_SWIV: /* Software Interrupt */ |
| 303 | SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); |
| 304 | break; |
| 305 | case ARMul_PrefetchAbortV: /* Prefetch Abort */ |
| 306 | state->AbortAddr = 1; |
| 307 | SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize); |
| 308 | break; |
| 309 | case ARMul_DataAbortV: /* Data Abort */ |
| 310 | SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size); |
| 311 | break; |
| 312 | case ARMul_AddrExceptnV: /* Address Exception */ |
| 313 | SETABORT (IBIT, SVC26MODE, isize); |
| 314 | break; |
| 315 | case ARMul_IRQV: /* IRQ */ |
| 316 | if ( ! state->is_XScale |
| 317 | || ! state->CPRead[13] (state, 0, & temp) |
| 318 | || (temp & ARMul_CP13_R0_IRQ)) |
| 319 | SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize); |
| 320 | break; |
| 321 | case ARMul_FIQV: /* FIQ */ |
| 322 | if ( ! state->is_XScale |
| 323 | || ! state->CPRead[13] (state, 0, & temp) |
| 324 | || (temp & ARMul_CP13_R0_FIQ)) |
| 325 | SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize); |
| 326 | break; |
| 327 | } |
| 328 | if (ARMul_MODE32BIT) |
| 329 | ARMul_SetR15 (state, vector); |
| 330 | else |
| 331 | ARMul_SetR15 (state, R15CCINTMODE | vector); |
| 332 | |
| 333 | if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) |
| 334 | { |
| 335 | /* No vector has been installed. Rather than simulating whatever |
| 336 | random bits might happen to be at address 0x20 onwards we elect |
| 337 | to stop. */ |
| 338 | switch (vector) |
| 339 | { |
| 340 | case ARMul_ResetV: state->EndCondition = RDIError_Reset; break; |
| 341 | case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break; |
| 342 | case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break; |
| 343 | case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break; |
| 344 | case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break; |
| 345 | case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break; |
| 346 | case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break; |
| 347 | case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break; |
| 348 | default: break; |
| 349 | } |
| 350 | state->Emulate = FALSE; |
| 351 | } |
| 352 | } |