| 1 | /* The common simulator framework for GDB, the GNU Debugger. |
| 2 | |
| 3 | Copyright 2002-2020 Free Software Foundation, Inc. |
| 4 | |
| 5 | Contributed by Andrew Cagney and Red Hat. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | |
| 23 | #ifndef SIM_CORE_H |
| 24 | #define SIM_CORE_H |
| 25 | |
| 26 | |
| 27 | /* core signals (error conditions) |
| 28 | Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for |
| 29 | details. */ |
| 30 | |
| 31 | typedef enum { |
| 32 | sim_core_unmapped_signal, |
| 33 | sim_core_unaligned_signal, |
| 34 | nr_sim_core_signals, |
| 35 | } sim_core_signals; |
| 36 | |
| 37 | /* Type of SIM_CORE_SIGNAL handler. */ |
| 38 | typedef void (SIM_CORE_SIGNAL_FN) |
| 39 | (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes, |
| 40 | address_word addr, transfer_type transfer, sim_core_signals sig); |
| 41 | |
| 42 | extern SIM_CORE_SIGNAL_FN sim_core_signal; |
| 43 | |
| 44 | |
| 45 | /* basic types */ |
| 46 | |
| 47 | typedef struct _sim_core_mapping sim_core_mapping; |
| 48 | struct _sim_core_mapping { |
| 49 | /* common */ |
| 50 | int level; |
| 51 | int space; |
| 52 | unsigned_word base; |
| 53 | unsigned_word bound; |
| 54 | unsigned_word nr_bytes; |
| 55 | unsigned mask; |
| 56 | /* memory map */ |
| 57 | void *free_buffer; |
| 58 | void *buffer; |
| 59 | /* callback map */ |
| 60 | struct hw *device; |
| 61 | /* tracing */ |
| 62 | int trace; |
| 63 | /* growth */ |
| 64 | sim_core_mapping *next; |
| 65 | }; |
| 66 | |
| 67 | typedef struct _sim_core_map sim_core_map; |
| 68 | struct _sim_core_map { |
| 69 | sim_core_mapping *first; |
| 70 | }; |
| 71 | |
| 72 | |
| 73 | typedef struct _sim_core_common { |
| 74 | sim_core_map map[nr_maps]; |
| 75 | } sim_core_common; |
| 76 | |
| 77 | |
| 78 | /* Main core structure */ |
| 79 | |
| 80 | typedef struct _sim_core sim_core; |
| 81 | struct _sim_core { |
| 82 | sim_core_common common; |
| 83 | address_word byte_xor; /* apply xor universally */ |
| 84 | }; |
| 85 | |
| 86 | |
| 87 | /* Per CPU distributed component of the core. At present this is |
| 88 | mostly a clone of the global core data structure. */ |
| 89 | |
| 90 | typedef struct _sim_cpu_core { |
| 91 | sim_core_common common; |
| 92 | address_word byte_xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ |
| 93 | } sim_cpu_core; |
| 94 | |
| 95 | |
| 96 | /* Install the "core" module. */ |
| 97 | |
| 98 | extern SIM_RC sim_core_install (SIM_DESC sd); |
| 99 | |
| 100 | |
| 101 | |
| 102 | /* Create a memory region within the core. |
| 103 | |
| 104 | CPU - when non NULL, specifes the single processor that the memory |
| 105 | space is to be attached to. (INIMPLEMENTED). |
| 106 | |
| 107 | LEVEL - specifies the ordering of the memory region. Lower regions |
| 108 | are searched first. Within a level, memory regions can not |
| 109 | overlap. |
| 110 | |
| 111 | MAPMASK - Bitmask specifying the memory maps that the region is to |
| 112 | be attached to. Typically the enums sim-basics.h:access_* are used. |
| 113 | |
| 114 | ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is |
| 115 | translated into ADDRESS_SPACE:OFFSET before being passed to the |
| 116 | client device. |
| 117 | |
| 118 | MODULO - Specifies that accesses to the region [ADDR .. ADDR+NR_BYTES) |
| 119 | should be mapped onto the sub region [ADDR .. ADDR+MODULO). The modulo |
| 120 | value must be a power of two. |
| 121 | |
| 122 | DEVICE - When non NULL, indicates that this is a callback memory |
| 123 | space and specified device's memory callback handler should be |
| 124 | called. |
| 125 | |
| 126 | OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for |
| 127 | data read & written to the region. Normally a more efficient |
| 128 | internal structure is used. It is assumed that buffer is allocated |
| 129 | such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis |
| 130 | (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal |
| 131 | hook that allows clients to do nasty things that the interface doesn't |
| 132 | accomodate. */ |
| 133 | |
| 134 | extern void sim_core_attach |
| 135 | (SIM_DESC sd, |
| 136 | sim_cpu *cpu, |
| 137 | int level, |
| 138 | unsigned mapmask, |
| 139 | int address_space, |
| 140 | address_word addr, |
| 141 | address_word nr_bytes, |
| 142 | unsigned modulo, |
| 143 | struct hw *client, |
| 144 | void *optional_buffer); |
| 145 | |
| 146 | |
| 147 | /* Delete a memory section within the core. |
| 148 | |
| 149 | */ |
| 150 | |
| 151 | extern void sim_core_detach |
| 152 | (SIM_DESC sd, |
| 153 | sim_cpu *cpu, |
| 154 | int level, |
| 155 | int address_space, |
| 156 | address_word addr); |
| 157 | |
| 158 | |
| 159 | /* Variable sized read/write |
| 160 | |
| 161 | Transfer a variable sized block of raw data between the host and |
| 162 | target. Should any problems occur, the number of bytes |
| 163 | successfully transfered is returned. |
| 164 | |
| 165 | No host/target byte endian conversion is performed. No xor-endian |
| 166 | conversion is performed. |
| 167 | |
| 168 | If CPU argument, when non NULL, specifies the processor specific |
| 169 | address map that is to be used in the transfer. */ |
| 170 | |
| 171 | |
| 172 | extern unsigned sim_core_read_buffer |
| 173 | (SIM_DESC sd, |
| 174 | sim_cpu *cpu, |
| 175 | unsigned map, |
| 176 | void *buffer, |
| 177 | address_word addr, |
| 178 | unsigned nr_bytes); |
| 179 | |
| 180 | extern unsigned sim_core_write_buffer |
| 181 | (SIM_DESC sd, |
| 182 | sim_cpu *cpu, |
| 183 | unsigned map, |
| 184 | const void *buffer, |
| 185 | address_word addr, |
| 186 | unsigned nr_bytes); |
| 187 | |
| 188 | |
| 189 | |
| 190 | /* Configure the core's XOR endian transfer mode. Only applicable |
| 191 | when WITH_XOR_ENDIAN is enabled. |
| 192 | |
| 193 | Targets suporting XOR endian, shall notify the core of any changes |
| 194 | in state via this call. |
| 195 | |
| 196 | The CPU argument, when non NULL, specifes the single processor that |
| 197 | the xor-endian configuration is to be applied to. */ |
| 198 | |
| 199 | extern void sim_core_set_xor |
| 200 | (SIM_DESC sd, |
| 201 | sim_cpu *cpu, |
| 202 | int is_xor); |
| 203 | |
| 204 | |
| 205 | /* XOR version of variable sized read/write. |
| 206 | |
| 207 | Transfer a variable sized block of raw data between the host and |
| 208 | target. Should any problems occur, the number of bytes |
| 209 | successfully transfered is returned. |
| 210 | |
| 211 | No host/target byte endian conversion is performed. If applicable |
| 212 | (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is* |
| 213 | performed. |
| 214 | |
| 215 | If CPU argument, when non NULL, specifies the processor specific |
| 216 | address map that is to be used in the transfer. */ |
| 217 | |
| 218 | extern unsigned sim_core_xor_read_buffer |
| 219 | (SIM_DESC sd, |
| 220 | sim_cpu *cpu, |
| 221 | unsigned map, |
| 222 | void *buffer, |
| 223 | address_word addr, |
| 224 | unsigned nr_bytes); |
| 225 | |
| 226 | extern unsigned sim_core_xor_write_buffer |
| 227 | (SIM_DESC sd, |
| 228 | sim_cpu *cpu, |
| 229 | unsigned map, |
| 230 | const void *buffer, |
| 231 | address_word addr, |
| 232 | unsigned nr_bytes); |
| 233 | |
| 234 | |
| 235 | /* Translate an address based on a map. */ |
| 236 | |
| 237 | extern void *sim_core_trans_addr |
| 238 | (SIM_DESC sd, |
| 239 | sim_cpu *cpu, |
| 240 | unsigned map, |
| 241 | address_word addr); |
| 242 | |
| 243 | |
| 244 | /* Fixed sized, processor oriented, read/write. |
| 245 | |
| 246 | Transfer a fixed amout of memory between the host and target. The |
| 247 | data transfered is translated from/to host to/from target byte |
| 248 | order (including xor endian). Should the transfer fail, the |
| 249 | operation shall abort (no return). |
| 250 | |
| 251 | ALIGNED assumes yhat the specified ADDRESS is correctly alligned |
| 252 | for an N byte transfer (no alignment checks are made). Passing an |
| 253 | incorrectly aligned ADDRESS is erroneous. |
| 254 | |
| 255 | UNALIGNED checks/modifies the ADDRESS according to the requirements |
| 256 | of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being |
| 257 | taken should the check fail. |
| 258 | |
| 259 | MISSALIGNED transfers the data regardless. |
| 260 | |
| 261 | Misaligned xor-endian accesses are broken into a sequence of |
| 262 | transfers each <= WITH_XOR_ENDIAN bytes */ |
| 263 | |
| 264 | |
| 265 | #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \ |
| 266 | INLINE_SIM_CORE\ |
| 267 | (void) sim_core_write_##ALIGNMENT##_##N \ |
| 268 | (sim_cpu *cpu, \ |
| 269 | sim_cia cia, \ |
| 270 | unsigned map, \ |
| 271 | address_word addr, \ |
| 272 | unsigned_##M val); |
| 273 | |
| 274 | DECLARE_SIM_CORE_WRITE_N(aligned,1,1) |
| 275 | DECLARE_SIM_CORE_WRITE_N(aligned,2,2) |
| 276 | DECLARE_SIM_CORE_WRITE_N(aligned,4,4) |
| 277 | DECLARE_SIM_CORE_WRITE_N(aligned,8,8) |
| 278 | DECLARE_SIM_CORE_WRITE_N(aligned,16,16) |
| 279 | |
| 280 | #define sim_core_write_unaligned_1 sim_core_write_aligned_1 |
| 281 | DECLARE_SIM_CORE_WRITE_N(unaligned,2,2) |
| 282 | DECLARE_SIM_CORE_WRITE_N(unaligned,4,4) |
| 283 | DECLARE_SIM_CORE_WRITE_N(unaligned,8,8) |
| 284 | DECLARE_SIM_CORE_WRITE_N(unaligned,16,16) |
| 285 | |
| 286 | DECLARE_SIM_CORE_WRITE_N(misaligned,3,4) |
| 287 | DECLARE_SIM_CORE_WRITE_N(misaligned,5,8) |
| 288 | DECLARE_SIM_CORE_WRITE_N(misaligned,6,8) |
| 289 | DECLARE_SIM_CORE_WRITE_N(misaligned,7,8) |
| 290 | |
| 291 | #define sim_core_write_1 sim_core_write_aligned_1 |
| 292 | #define sim_core_write_2 sim_core_write_aligned_2 |
| 293 | #define sim_core_write_4 sim_core_write_aligned_4 |
| 294 | #define sim_core_write_8 sim_core_write_aligned_8 |
| 295 | #define sim_core_write_16 sim_core_write_aligned_16 |
| 296 | |
| 297 | #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE) |
| 298 | #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE) |
| 299 | #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE) |
| 300 | |
| 301 | #undef DECLARE_SIM_CORE_WRITE_N |
| 302 | |
| 303 | |
| 304 | #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \ |
| 305 | INLINE_SIM_CORE\ |
| 306 | (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \ |
| 307 | (sim_cpu *cpu, \ |
| 308 | sim_cia cia, \ |
| 309 | unsigned map, \ |
| 310 | address_word addr); |
| 311 | |
| 312 | DECLARE_SIM_CORE_READ_N(aligned,1,1) |
| 313 | DECLARE_SIM_CORE_READ_N(aligned,2,2) |
| 314 | DECLARE_SIM_CORE_READ_N(aligned,4,4) |
| 315 | DECLARE_SIM_CORE_READ_N(aligned,8,8) |
| 316 | DECLARE_SIM_CORE_READ_N(aligned,16,16) |
| 317 | |
| 318 | #define sim_core_read_unaligned_1 sim_core_read_aligned_1 |
| 319 | DECLARE_SIM_CORE_READ_N(unaligned,2,2) |
| 320 | DECLARE_SIM_CORE_READ_N(unaligned,4,4) |
| 321 | DECLARE_SIM_CORE_READ_N(unaligned,8,8) |
| 322 | DECLARE_SIM_CORE_READ_N(unaligned,16,16) |
| 323 | |
| 324 | DECLARE_SIM_CORE_READ_N(misaligned,3,4) |
| 325 | DECLARE_SIM_CORE_READ_N(misaligned,5,8) |
| 326 | DECLARE_SIM_CORE_READ_N(misaligned,6,8) |
| 327 | DECLARE_SIM_CORE_READ_N(misaligned,7,8) |
| 328 | |
| 329 | |
| 330 | #define sim_core_read_1 sim_core_read_aligned_1 |
| 331 | #define sim_core_read_2 sim_core_read_aligned_2 |
| 332 | #define sim_core_read_4 sim_core_read_aligned_4 |
| 333 | #define sim_core_read_8 sim_core_read_aligned_8 |
| 334 | #define sim_core_read_16 sim_core_read_aligned_16 |
| 335 | |
| 336 | #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE) |
| 337 | #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE) |
| 338 | #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE) |
| 339 | |
| 340 | #undef DECLARE_SIM_CORE_READ_N |
| 341 | |
| 342 | #endif |