| 1 | /* CPU family header for crisv10f. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2015 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU simulators. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | |
| 22 | */ |
| 23 | |
| 24 | #ifndef CPU_CRISV10F_H |
| 25 | #define CPU_CRISV10F_H |
| 26 | |
| 27 | /* Maximum number of instructions that are fetched at a time. |
| 28 | This is for LIW type instructions sets (e.g. m32r). */ |
| 29 | #define MAX_LIW_INSNS 1 |
| 30 | |
| 31 | /* Maximum number of instructions that can be executed in parallel. */ |
| 32 | #define MAX_PARALLEL_INSNS 1 |
| 33 | |
| 34 | /* The size of an "int" needed to hold an instruction word. |
| 35 | This is usually 32 bits, but some architectures needs 64 bits. */ |
| 36 | typedef CGEN_INSN_INT CGEN_INSN_WORD; |
| 37 | |
| 38 | #include "cgen-engine.h" |
| 39 | |
| 40 | /* CPU state information. */ |
| 41 | typedef struct { |
| 42 | /* Hardware elements. */ |
| 43 | struct { |
| 44 | /* program counter */ |
| 45 | USI h_pc; |
| 46 | #define GET_H_PC() CPU (h_pc) |
| 47 | #define SET_H_PC(x) \ |
| 48 | do { \ |
| 49 | CPU (h_pc) = ANDSI ((x), (~ (1)));\ |
| 50 | ;} while (0) |
| 51 | /* General purpose registers */ |
| 52 | SI h_gr_real_pc[16]; |
| 53 | #define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1] |
| 54 | #define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x)) |
| 55 | /* Special registers for v10 */ |
| 56 | SI h_sr_v10[16]; |
| 57 | #define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index])) |
| 58 | #define SET_H_SR_V10(index, x) \ |
| 59 | do { \ |
| 60 | if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\ |
| 61 | ((void) 0); /*nop*/\ |
| 62 | }\ |
| 63 | else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\ |
| 64 | {\ |
| 65 | CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\ |
| 66 | CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\ |
| 67 | CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\ |
| 68 | CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\ |
| 69 | CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\ |
| 70 | SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\ |
| 71 | SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\ |
| 72 | CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\ |
| 73 | CPU (h_sr_v10[((UINT) 5)]) = (x);\ |
| 74 | CPU (h_sr_v10[((UINT) 13)]) = (x);\ |
| 75 | }\ |
| 76 | }\ |
| 77 | else {\ |
| 78 | CPU (h_sr_v10[(index)]) = (x);\ |
| 79 | }\ |
| 80 | ;} while (0) |
| 81 | /* carry bit */ |
| 82 | BI h_cbit; |
| 83 | #define GET_H_CBIT() CPU (h_cbit) |
| 84 | #define SET_H_CBIT(x) (CPU (h_cbit) = (x)) |
| 85 | /* overflow bit */ |
| 86 | BI h_vbit; |
| 87 | #define GET_H_VBIT() CPU (h_vbit) |
| 88 | #define SET_H_VBIT(x) (CPU (h_vbit) = (x)) |
| 89 | /* zero bit */ |
| 90 | BI h_zbit; |
| 91 | #define GET_H_ZBIT() CPU (h_zbit) |
| 92 | #define SET_H_ZBIT(x) (CPU (h_zbit) = (x)) |
| 93 | /* sign bit */ |
| 94 | BI h_nbit; |
| 95 | #define GET_H_NBIT() CPU (h_nbit) |
| 96 | #define SET_H_NBIT(x) (CPU (h_nbit) = (x)) |
| 97 | /* extended-arithmetic bit */ |
| 98 | BI h_xbit; |
| 99 | #define GET_H_XBIT() CPU (h_xbit) |
| 100 | #define SET_H_XBIT(x) (CPU (h_xbit) = (x)) |
| 101 | /* interrupt-enable bit */ |
| 102 | BI h_ibit_pre_v32; |
| 103 | #define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32) |
| 104 | #define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x)) |
| 105 | /* sequence-broken bit */ |
| 106 | BI h_pbit; |
| 107 | #define GET_H_PBIT() CPU (h_pbit) |
| 108 | #define SET_H_PBIT(x) (CPU (h_pbit) = (x)) |
| 109 | /* user mode bit */ |
| 110 | BI h_ubit_pre_v32; |
| 111 | #define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32) |
| 112 | #define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x)) |
| 113 | /* instruction-is-prefixed bit */ |
| 114 | BI h_insn_prefixed_p_pre_v32; |
| 115 | #define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32) |
| 116 | #define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x)) |
| 117 | /* Prefix-address register */ |
| 118 | SI h_prefixreg_pre_v32; |
| 119 | #define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32) |
| 120 | #define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x)) |
| 121 | } hardware; |
| 122 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) |
| 123 | } CRISV10F_CPU_DATA; |
| 124 | |
| 125 | /* Virtual regs. */ |
| 126 | |
| 127 | #define GET_H_V32_NON_V32() 0 |
| 128 | #define SET_H_V32_NON_V32(x) \ |
| 129 | do { \ |
| 130 | cgen_rtx_error (current_cpu, "Can't set h-v32");\ |
| 131 | ;} while (0) |
| 132 | #define GET_H_GR(index) GET_H_GR_PC (index) |
| 133 | #define SET_H_GR(index, x) \ |
| 134 | do { \ |
| 135 | SET_H_GR_PC ((index), (x));\ |
| 136 | ;} while (0) |
| 137 | #define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index]))) |
| 138 | #define SET_H_GR_PC(index, x) \ |
| 139 | do { \ |
| 140 | {\ |
| 141 | if ((((index)) == (15))) {\ |
| 142 | cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\ |
| 143 | }\ |
| 144 | CPU (h_gr_real_pc[(index)]) = (x);\ |
| 145 | }\ |
| 146 | ;} while (0) |
| 147 | #define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index]) |
| 148 | #define SET_H_RAW_GR_PC(index, x) \ |
| 149 | do { \ |
| 150 | CPU (h_gr_real_pc[(index)]) = (x);\ |
| 151 | ;} while (0) |
| 152 | #define GET_H_SR(index) GET_H_SR_V10 (index) |
| 153 | #define SET_H_SR(index, x) \ |
| 154 | do { \ |
| 155 | SET_H_SR_V10 ((index), (x));\ |
| 156 | ;} while (0) |
| 157 | #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 () |
| 158 | #define SET_H_CBIT_MOVE(x) \ |
| 159 | do { \ |
| 160 | SET_H_CBIT_MOVE_PRE_V32 ((x));\ |
| 161 | ;} while (0) |
| 162 | #define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit) |
| 163 | #define SET_H_CBIT_MOVE_PRE_V32(x) \ |
| 164 | do { \ |
| 165 | CPU (h_cbit) = (x);\ |
| 166 | ;} while (0) |
| 167 | #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 () |
| 168 | #define SET_H_VBIT_MOVE(x) \ |
| 169 | do { \ |
| 170 | SET_H_VBIT_MOVE_PRE_V32 ((x));\ |
| 171 | ;} while (0) |
| 172 | #define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit) |
| 173 | #define SET_H_VBIT_MOVE_PRE_V32(x) \ |
| 174 | do { \ |
| 175 | CPU (h_vbit) = (x);\ |
| 176 | ;} while (0) |
| 177 | #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 () |
| 178 | #define SET_H_ZBIT_MOVE(x) \ |
| 179 | do { \ |
| 180 | SET_H_ZBIT_MOVE_PRE_V32 ((x));\ |
| 181 | ;} while (0) |
| 182 | #define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit) |
| 183 | #define SET_H_ZBIT_MOVE_PRE_V32(x) \ |
| 184 | do { \ |
| 185 | CPU (h_zbit) = (x);\ |
| 186 | ;} while (0) |
| 187 | #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 () |
| 188 | #define SET_H_NBIT_MOVE(x) \ |
| 189 | do { \ |
| 190 | SET_H_NBIT_MOVE_PRE_V32 ((x));\ |
| 191 | ;} while (0) |
| 192 | #define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit) |
| 193 | #define SET_H_NBIT_MOVE_PRE_V32(x) \ |
| 194 | do { \ |
| 195 | CPU (h_nbit) = (x);\ |
| 196 | ;} while (0) |
| 197 | #define GET_H_IBIT() CPU (h_ibit_pre_v32) |
| 198 | #define SET_H_IBIT(x) \ |
| 199 | do { \ |
| 200 | CPU (h_ibit_pre_v32) = (x);\ |
| 201 | ;} while (0) |
| 202 | #define GET_H_UBIT() CPU (h_ubit_pre_v32) |
| 203 | #define SET_H_UBIT(x) \ |
| 204 | do { \ |
| 205 | CPU (h_ubit_pre_v32) = (x);\ |
| 206 | ;} while (0) |
| 207 | #define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32) |
| 208 | #define SET_H_INSN_PREFIXED_P(x) \ |
| 209 | do { \ |
| 210 | CPU (h_insn_prefixed_p_pre_v32) = (x);\ |
| 211 | ;} while (0) |
| 212 | |
| 213 | /* Cover fns for register access. */ |
| 214 | BI crisv10f_h_v32_non_v32_get (SIM_CPU *); |
| 215 | void crisv10f_h_v32_non_v32_set (SIM_CPU *, BI); |
| 216 | USI crisv10f_h_pc_get (SIM_CPU *); |
| 217 | void crisv10f_h_pc_set (SIM_CPU *, USI); |
| 218 | SI crisv10f_h_gr_get (SIM_CPU *, UINT); |
| 219 | void crisv10f_h_gr_set (SIM_CPU *, UINT, SI); |
| 220 | SI crisv10f_h_gr_pc_get (SIM_CPU *, UINT); |
| 221 | void crisv10f_h_gr_pc_set (SIM_CPU *, UINT, SI); |
| 222 | SI crisv10f_h_gr_real_pc_get (SIM_CPU *, UINT); |
| 223 | void crisv10f_h_gr_real_pc_set (SIM_CPU *, UINT, SI); |
| 224 | SI crisv10f_h_raw_gr_pc_get (SIM_CPU *, UINT); |
| 225 | void crisv10f_h_raw_gr_pc_set (SIM_CPU *, UINT, SI); |
| 226 | SI crisv10f_h_sr_get (SIM_CPU *, UINT); |
| 227 | void crisv10f_h_sr_set (SIM_CPU *, UINT, SI); |
| 228 | SI crisv10f_h_sr_v10_get (SIM_CPU *, UINT); |
| 229 | void crisv10f_h_sr_v10_set (SIM_CPU *, UINT, SI); |
| 230 | BI crisv10f_h_cbit_get (SIM_CPU *); |
| 231 | void crisv10f_h_cbit_set (SIM_CPU *, BI); |
| 232 | BI crisv10f_h_cbit_move_get (SIM_CPU *); |
| 233 | void crisv10f_h_cbit_move_set (SIM_CPU *, BI); |
| 234 | BI crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *); |
| 235 | void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *, BI); |
| 236 | BI crisv10f_h_vbit_get (SIM_CPU *); |
| 237 | void crisv10f_h_vbit_set (SIM_CPU *, BI); |
| 238 | BI crisv10f_h_vbit_move_get (SIM_CPU *); |
| 239 | void crisv10f_h_vbit_move_set (SIM_CPU *, BI); |
| 240 | BI crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *); |
| 241 | void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *, BI); |
| 242 | BI crisv10f_h_zbit_get (SIM_CPU *); |
| 243 | void crisv10f_h_zbit_set (SIM_CPU *, BI); |
| 244 | BI crisv10f_h_zbit_move_get (SIM_CPU *); |
| 245 | void crisv10f_h_zbit_move_set (SIM_CPU *, BI); |
| 246 | BI crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *); |
| 247 | void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *, BI); |
| 248 | BI crisv10f_h_nbit_get (SIM_CPU *); |
| 249 | void crisv10f_h_nbit_set (SIM_CPU *, BI); |
| 250 | BI crisv10f_h_nbit_move_get (SIM_CPU *); |
| 251 | void crisv10f_h_nbit_move_set (SIM_CPU *, BI); |
| 252 | BI crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *); |
| 253 | void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *, BI); |
| 254 | BI crisv10f_h_xbit_get (SIM_CPU *); |
| 255 | void crisv10f_h_xbit_set (SIM_CPU *, BI); |
| 256 | BI crisv10f_h_ibit_get (SIM_CPU *); |
| 257 | void crisv10f_h_ibit_set (SIM_CPU *, BI); |
| 258 | BI crisv10f_h_ibit_pre_v32_get (SIM_CPU *); |
| 259 | void crisv10f_h_ibit_pre_v32_set (SIM_CPU *, BI); |
| 260 | BI crisv10f_h_pbit_get (SIM_CPU *); |
| 261 | void crisv10f_h_pbit_set (SIM_CPU *, BI); |
| 262 | BI crisv10f_h_ubit_get (SIM_CPU *); |
| 263 | void crisv10f_h_ubit_set (SIM_CPU *, BI); |
| 264 | BI crisv10f_h_ubit_pre_v32_get (SIM_CPU *); |
| 265 | void crisv10f_h_ubit_pre_v32_set (SIM_CPU *, BI); |
| 266 | BI crisv10f_h_insn_prefixed_p_get (SIM_CPU *); |
| 267 | void crisv10f_h_insn_prefixed_p_set (SIM_CPU *, BI); |
| 268 | BI crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *); |
| 269 | void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *, BI); |
| 270 | SI crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *); |
| 271 | void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *, SI); |
| 272 | |
| 273 | /* These must be hand-written. */ |
| 274 | extern CPUREG_FETCH_FN crisv10f_fetch_register; |
| 275 | extern CPUREG_STORE_FN crisv10f_store_register; |
| 276 | |
| 277 | typedef struct { |
| 278 | int empty; |
| 279 | } MODEL_CRISV10_DATA; |
| 280 | |
| 281 | /* Instruction argument buffer. */ |
| 282 | |
| 283 | union sem_fields { |
| 284 | struct { /* no operands */ |
| 285 | int empty; |
| 286 | } sfmt_empty; |
| 287 | struct { /* */ |
| 288 | UINT f_u4; |
| 289 | } sfmt_break; |
| 290 | struct { /* */ |
| 291 | UINT f_dstsrc; |
| 292 | } sfmt_setf; |
| 293 | struct { /* */ |
| 294 | IADDR i_o_word_pcrel; |
| 295 | UINT f_operand2; |
| 296 | } sfmt_bcc_w; |
| 297 | struct { /* */ |
| 298 | IADDR i_o_pcrel; |
| 299 | UINT f_operand2; |
| 300 | } sfmt_bcc_b; |
| 301 | struct { /* */ |
| 302 | UINT f_memmode; |
| 303 | unsigned char in_h_gr_SI_14; |
| 304 | unsigned char out_h_gr_SI_14; |
| 305 | } sfmt_move_m_spplus_p8; |
| 306 | struct { /* */ |
| 307 | INT f_s8; |
| 308 | UINT f_operand2; |
| 309 | unsigned char in_Rd; |
| 310 | } sfmt_addoq; |
| 311 | struct { /* */ |
| 312 | INT f_indir_pc__dword; |
| 313 | UINT f_operand2; |
| 314 | unsigned char out_Pd; |
| 315 | } sfmt_move_c_sprv10_p9; |
| 316 | struct { /* */ |
| 317 | INT f_indir_pc__word; |
| 318 | UINT f_operand2; |
| 319 | unsigned char out_Pd; |
| 320 | } sfmt_move_c_sprv10_p5; |
| 321 | struct { /* */ |
| 322 | INT f_s6; |
| 323 | UINT f_operand2; |
| 324 | unsigned char out_Rd; |
| 325 | } sfmt_moveq; |
| 326 | struct { /* */ |
| 327 | INT f_indir_pc__dword; |
| 328 | UINT f_operand2; |
| 329 | unsigned char in_Rd; |
| 330 | unsigned char out_Rd; |
| 331 | } sfmt_bound_cd; |
| 332 | struct { /* */ |
| 333 | INT f_indir_pc__word; |
| 334 | UINT f_operand2; |
| 335 | unsigned char in_Rd; |
| 336 | unsigned char out_Rd; |
| 337 | } sfmt_bound_cw; |
| 338 | struct { /* */ |
| 339 | INT f_indir_pc__byte; |
| 340 | UINT f_operand2; |
| 341 | unsigned char in_Rd; |
| 342 | unsigned char out_Rd; |
| 343 | } sfmt_bound_cb; |
| 344 | struct { /* */ |
| 345 | UINT f_operand2; |
| 346 | UINT f_u5; |
| 347 | unsigned char in_Rd; |
| 348 | unsigned char out_Rd; |
| 349 | } sfmt_asrq; |
| 350 | struct { /* */ |
| 351 | INT f_s6; |
| 352 | UINT f_operand2; |
| 353 | unsigned char in_Rd; |
| 354 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 355 | } sfmt_andq; |
| 356 | struct { /* */ |
| 357 | INT f_indir_pc__dword; |
| 358 | UINT f_operand2; |
| 359 | unsigned char in_Rd; |
| 360 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 361 | } sfmt_addcdr; |
| 362 | struct { /* */ |
| 363 | INT f_indir_pc__word; |
| 364 | UINT f_operand2; |
| 365 | unsigned char in_Rd; |
| 366 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 367 | } sfmt_addcwr; |
| 368 | struct { /* */ |
| 369 | INT f_indir_pc__byte; |
| 370 | UINT f_operand2; |
| 371 | unsigned char in_Rd; |
| 372 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 373 | } sfmt_addcbr; |
| 374 | struct { /* */ |
| 375 | UINT f_operand1; |
| 376 | UINT f_operand2; |
| 377 | unsigned char in_Ps; |
| 378 | unsigned char out_h_gr_SI_index_of__INT_Rs; |
| 379 | } sfmt_move_spr_rv10; |
| 380 | struct { /* */ |
| 381 | UINT f_operand2; |
| 382 | UINT f_u6; |
| 383 | unsigned char in_Rd; |
| 384 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 385 | } sfmt_addq; |
| 386 | struct { /* */ |
| 387 | UINT f_operand1; |
| 388 | UINT f_operand2; |
| 389 | unsigned char in_Rd; |
| 390 | unsigned char in_Rs; |
| 391 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 392 | } sfmt_add_b_r; |
| 393 | struct { /* */ |
| 394 | UINT f_operand1; |
| 395 | UINT f_operand2; |
| 396 | unsigned char in_Rd; |
| 397 | unsigned char in_Rs; |
| 398 | unsigned char out_Rd; |
| 399 | unsigned char out_h_sr_SI_7; |
| 400 | } sfmt_muls_b; |
| 401 | struct { /* */ |
| 402 | UINT f_memmode; |
| 403 | UINT f_operand1; |
| 404 | UINT f_operand2; |
| 405 | unsigned char in_Ps; |
| 406 | unsigned char in_Rs; |
| 407 | unsigned char out_Rs; |
| 408 | } sfmt_move_spr_mv10; |
| 409 | struct { /* */ |
| 410 | UINT f_memmode; |
| 411 | UINT f_operand1; |
| 412 | UINT f_operand2; |
| 413 | unsigned char in_Rs; |
| 414 | unsigned char out_Pd; |
| 415 | unsigned char out_Rs; |
| 416 | } sfmt_move_m_sprv10; |
| 417 | struct { /* */ |
| 418 | UINT f_memmode; |
| 419 | UINT f_operand1; |
| 420 | UINT f_operand2; |
| 421 | unsigned char in_Rd; |
| 422 | unsigned char in_Rs; |
| 423 | unsigned char out_Rd; |
| 424 | unsigned char out_Rs; |
| 425 | } sfmt_bound_m_b_m; |
| 426 | struct { /* */ |
| 427 | UINT f_memmode; |
| 428 | UINT f_operand1; |
| 429 | UINT f_operand2; |
| 430 | unsigned char in_Rd; |
| 431 | unsigned char in_Rs; |
| 432 | unsigned char out_Rs; |
| 433 | unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd; |
| 434 | } sfmt_add_m_b_m; |
| 435 | struct { /* */ |
| 436 | UINT f_memmode; |
| 437 | UINT f_operand1; |
| 438 | UINT f_operand2; |
| 439 | unsigned char in_Rd; |
| 440 | unsigned char in_Rs; |
| 441 | unsigned char out_Rs; |
| 442 | unsigned char out_h_gr_SI_0; |
| 443 | unsigned char out_h_gr_SI_1; |
| 444 | unsigned char out_h_gr_SI_10; |
| 445 | unsigned char out_h_gr_SI_11; |
| 446 | unsigned char out_h_gr_SI_12; |
| 447 | unsigned char out_h_gr_SI_13; |
| 448 | unsigned char out_h_gr_SI_14; |
| 449 | unsigned char out_h_gr_SI_2; |
| 450 | unsigned char out_h_gr_SI_3; |
| 451 | unsigned char out_h_gr_SI_4; |
| 452 | unsigned char out_h_gr_SI_5; |
| 453 | unsigned char out_h_gr_SI_6; |
| 454 | unsigned char out_h_gr_SI_7; |
| 455 | unsigned char out_h_gr_SI_8; |
| 456 | unsigned char out_h_gr_SI_9; |
| 457 | } sfmt_movem_m_r; |
| 458 | struct { /* */ |
| 459 | UINT f_memmode; |
| 460 | UINT f_operand1; |
| 461 | UINT f_operand2; |
| 462 | unsigned char in_Rd; |
| 463 | unsigned char in_Rs; |
| 464 | unsigned char in_h_gr_SI_0; |
| 465 | unsigned char in_h_gr_SI_1; |
| 466 | unsigned char in_h_gr_SI_10; |
| 467 | unsigned char in_h_gr_SI_11; |
| 468 | unsigned char in_h_gr_SI_12; |
| 469 | unsigned char in_h_gr_SI_13; |
| 470 | unsigned char in_h_gr_SI_14; |
| 471 | unsigned char in_h_gr_SI_15; |
| 472 | unsigned char in_h_gr_SI_2; |
| 473 | unsigned char in_h_gr_SI_3; |
| 474 | unsigned char in_h_gr_SI_4; |
| 475 | unsigned char in_h_gr_SI_5; |
| 476 | unsigned char in_h_gr_SI_6; |
| 477 | unsigned char in_h_gr_SI_7; |
| 478 | unsigned char in_h_gr_SI_8; |
| 479 | unsigned char in_h_gr_SI_9; |
| 480 | unsigned char out_Rs; |
| 481 | } sfmt_movem_r_m; |
| 482 | #if WITH_SCACHE_PBB |
| 483 | /* Writeback handler. */ |
| 484 | struct { |
| 485 | /* Pointer to argbuf entry for insn whose results need writing back. */ |
| 486 | const struct argbuf *abuf; |
| 487 | } write; |
| 488 | /* x-before handler */ |
| 489 | struct { |
| 490 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ |
| 491 | int first_p; |
| 492 | } before; |
| 493 | /* x-after handler */ |
| 494 | struct { |
| 495 | int empty; |
| 496 | } after; |
| 497 | /* This entry is used to terminate each pbb. */ |
| 498 | struct { |
| 499 | /* Number of insns in pbb. */ |
| 500 | int insn_count; |
| 501 | /* Next pbb to execute. */ |
| 502 | SCACHE *next; |
| 503 | SCACHE *branch_target; |
| 504 | } chain; |
| 505 | #endif |
| 506 | }; |
| 507 | |
| 508 | /* The ARGBUF struct. */ |
| 509 | struct argbuf { |
| 510 | /* These are the baseclass definitions. */ |
| 511 | IADDR addr; |
| 512 | const IDESC *idesc; |
| 513 | char trace_p; |
| 514 | char profile_p; |
| 515 | /* ??? Temporary hack for skip insns. */ |
| 516 | char skip_count; |
| 517 | char unused; |
| 518 | /* cpu specific data follows */ |
| 519 | union sem semantic; |
| 520 | int written; |
| 521 | union sem_fields fields; |
| 522 | }; |
| 523 | |
| 524 | /* A cached insn. |
| 525 | |
| 526 | ??? SCACHE used to contain more than just argbuf. We could delete the |
| 527 | type entirely and always just use ARGBUF, but for future concerns and as |
| 528 | a level of abstraction it is left in. */ |
| 529 | |
| 530 | struct scache { |
| 531 | struct argbuf argbuf; |
| 532 | }; |
| 533 | |
| 534 | /* Macros to simplify extraction, reading and semantic code. |
| 535 | These define and assign the local vars that contain the insn's fields. */ |
| 536 | |
| 537 | #define EXTRACT_IFMT_EMPTY_VARS \ |
| 538 | unsigned int length; |
| 539 | #define EXTRACT_IFMT_EMPTY_CODE \ |
| 540 | length = 0; \ |
| 541 | |
| 542 | #define EXTRACT_IFMT_NOP_VARS \ |
| 543 | UINT f_operand2; \ |
| 544 | UINT f_mode; \ |
| 545 | UINT f_opcode; \ |
| 546 | UINT f_size; \ |
| 547 | UINT f_operand1; \ |
| 548 | unsigned int length; |
| 549 | #define EXTRACT_IFMT_NOP_CODE \ |
| 550 | length = 2; \ |
| 551 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 552 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 553 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 554 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 555 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 556 | |
| 557 | #define EXTRACT_IFMT_MOVE_B_R_VARS \ |
| 558 | UINT f_operand2; \ |
| 559 | UINT f_mode; \ |
| 560 | UINT f_opcode; \ |
| 561 | UINT f_size; \ |
| 562 | UINT f_operand1; \ |
| 563 | unsigned int length; |
| 564 | #define EXTRACT_IFMT_MOVE_B_R_CODE \ |
| 565 | length = 2; \ |
| 566 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 567 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 568 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 569 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 570 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 571 | |
| 572 | #define EXTRACT_IFMT_MOVEPCR_VARS \ |
| 573 | UINT f_operand2; \ |
| 574 | UINT f_mode; \ |
| 575 | UINT f_opcode; \ |
| 576 | UINT f_size; \ |
| 577 | UINT f_operand1; \ |
| 578 | unsigned int length; |
| 579 | #define EXTRACT_IFMT_MOVEPCR_CODE \ |
| 580 | length = 2; \ |
| 581 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 582 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 583 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 584 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 585 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 586 | |
| 587 | #define EXTRACT_IFMT_MOVEQ_VARS \ |
| 588 | UINT f_operand2; \ |
| 589 | UINT f_mode; \ |
| 590 | UINT f_opcode; \ |
| 591 | INT f_s6; \ |
| 592 | unsigned int length; |
| 593 | #define EXTRACT_IFMT_MOVEQ_CODE \ |
| 594 | length = 2; \ |
| 595 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 596 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 597 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 598 | f_s6 = EXTRACT_LSB0_SINT (insn, 16, 5, 6); \ |
| 599 | |
| 600 | #define EXTRACT_IFMT_MOVECBR_VARS \ |
| 601 | UINT f_operand2; \ |
| 602 | INT f_indir_pc__byte; \ |
| 603 | UINT f_mode; \ |
| 604 | UINT f_opcode; \ |
| 605 | UINT f_size; \ |
| 606 | UINT f_operand1; \ |
| 607 | /* Contents of trailing part of insn. */ \ |
| 608 | UINT word_1; \ |
| 609 | unsigned int length; |
| 610 | #define EXTRACT_IFMT_MOVECBR_CODE \ |
| 611 | length = 4; \ |
| 612 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 613 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 614 | f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 615 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 616 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 617 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 618 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 619 | |
| 620 | #define EXTRACT_IFMT_MOVECWR_VARS \ |
| 621 | UINT f_operand2; \ |
| 622 | INT f_indir_pc__word; \ |
| 623 | UINT f_mode; \ |
| 624 | UINT f_opcode; \ |
| 625 | UINT f_size; \ |
| 626 | UINT f_operand1; \ |
| 627 | /* Contents of trailing part of insn. */ \ |
| 628 | UINT word_1; \ |
| 629 | unsigned int length; |
| 630 | #define EXTRACT_IFMT_MOVECWR_CODE \ |
| 631 | length = 4; \ |
| 632 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 633 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 634 | f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 635 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 636 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 637 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 638 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 639 | |
| 640 | #define EXTRACT_IFMT_MOVECDR_VARS \ |
| 641 | INT f_indir_pc__dword; \ |
| 642 | UINT f_operand2; \ |
| 643 | UINT f_mode; \ |
| 644 | UINT f_opcode; \ |
| 645 | UINT f_size; \ |
| 646 | UINT f_operand1; \ |
| 647 | /* Contents of trailing part of insn. */ \ |
| 648 | UINT word_1; \ |
| 649 | unsigned int length; |
| 650 | #define EXTRACT_IFMT_MOVECDR_CODE \ |
| 651 | length = 6; \ |
| 652 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 653 | f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ |
| 654 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 655 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 656 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 657 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 658 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 659 | |
| 660 | #define EXTRACT_IFMT_MOVUCBR_VARS \ |
| 661 | UINT f_operand2; \ |
| 662 | INT f_indir_pc__byte; \ |
| 663 | UINT f_mode; \ |
| 664 | UINT f_opcode; \ |
| 665 | UINT f_size; \ |
| 666 | UINT f_operand1; \ |
| 667 | /* Contents of trailing part of insn. */ \ |
| 668 | UINT word_1; \ |
| 669 | unsigned int length; |
| 670 | #define EXTRACT_IFMT_MOVUCBR_CODE \ |
| 671 | length = 4; \ |
| 672 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 673 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 674 | f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 675 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 676 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 677 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 678 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 679 | |
| 680 | #define EXTRACT_IFMT_MOVUCWR_VARS \ |
| 681 | UINT f_operand2; \ |
| 682 | INT f_indir_pc__word; \ |
| 683 | UINT f_mode; \ |
| 684 | UINT f_opcode; \ |
| 685 | UINT f_size; \ |
| 686 | UINT f_operand1; \ |
| 687 | /* Contents of trailing part of insn. */ \ |
| 688 | UINT word_1; \ |
| 689 | unsigned int length; |
| 690 | #define EXTRACT_IFMT_MOVUCWR_CODE \ |
| 691 | length = 4; \ |
| 692 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 693 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 694 | f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 695 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 696 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 697 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 698 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 699 | |
| 700 | #define EXTRACT_IFMT_ADDQ_VARS \ |
| 701 | UINT f_operand2; \ |
| 702 | UINT f_mode; \ |
| 703 | UINT f_opcode; \ |
| 704 | UINT f_u6; \ |
| 705 | unsigned int length; |
| 706 | #define EXTRACT_IFMT_ADDQ_CODE \ |
| 707 | length = 2; \ |
| 708 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 709 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 710 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 711 | f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \ |
| 712 | |
| 713 | #define EXTRACT_IFMT_CMP_M_B_M_VARS \ |
| 714 | UINT f_operand2; \ |
| 715 | UINT f_membit; \ |
| 716 | UINT f_memmode; \ |
| 717 | UINT f_opcode; \ |
| 718 | UINT f_size; \ |
| 719 | UINT f_operand1; \ |
| 720 | unsigned int length; |
| 721 | #define EXTRACT_IFMT_CMP_M_B_M_CODE \ |
| 722 | length = 2; \ |
| 723 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 724 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 725 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 726 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 727 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 728 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 729 | |
| 730 | #define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \ |
| 731 | UINT f_operand2; \ |
| 732 | UINT f_mode; \ |
| 733 | UINT f_opcode; \ |
| 734 | UINT f_size; \ |
| 735 | UINT f_operand1; \ |
| 736 | unsigned int length; |
| 737 | #define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \ |
| 738 | length = 2; \ |
| 739 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 740 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 741 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 742 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 743 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 744 | |
| 745 | #define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \ |
| 746 | UINT f_operand2; \ |
| 747 | UINT f_mode; \ |
| 748 | UINT f_opcode; \ |
| 749 | UINT f_size; \ |
| 750 | UINT f_operand1; \ |
| 751 | unsigned int length; |
| 752 | #define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \ |
| 753 | length = 2; \ |
| 754 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 755 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 756 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 757 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 758 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 759 | |
| 760 | #define EXTRACT_IFMT_RET_TYPE_VARS \ |
| 761 | UINT f_operand2; \ |
| 762 | UINT f_mode; \ |
| 763 | UINT f_opcode; \ |
| 764 | UINT f_size; \ |
| 765 | UINT f_operand1; \ |
| 766 | unsigned int length; |
| 767 | #define EXTRACT_IFMT_RET_TYPE_CODE \ |
| 768 | length = 2; \ |
| 769 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 770 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 771 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 772 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 773 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 774 | |
| 775 | #define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \ |
| 776 | UINT f_operand2; \ |
| 777 | UINT f_membit; \ |
| 778 | UINT f_memmode; \ |
| 779 | UINT f_opcode; \ |
| 780 | UINT f_size; \ |
| 781 | UINT f_operand1; \ |
| 782 | unsigned int length; |
| 783 | #define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \ |
| 784 | length = 2; \ |
| 785 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 786 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 787 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 788 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 789 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 790 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 791 | |
| 792 | #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \ |
| 793 | UINT f_operand2; \ |
| 794 | INT f_indir_pc__word; \ |
| 795 | UINT f_mode; \ |
| 796 | UINT f_opcode; \ |
| 797 | UINT f_size; \ |
| 798 | UINT f_operand1; \ |
| 799 | /* Contents of trailing part of insn. */ \ |
| 800 | UINT word_1; \ |
| 801 | unsigned int length; |
| 802 | #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \ |
| 803 | length = 4; \ |
| 804 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 805 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 806 | f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 807 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 808 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 809 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 810 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 811 | |
| 812 | #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \ |
| 813 | INT f_indir_pc__dword; \ |
| 814 | UINT f_operand2; \ |
| 815 | UINT f_mode; \ |
| 816 | UINT f_opcode; \ |
| 817 | UINT f_size; \ |
| 818 | UINT f_operand1; \ |
| 819 | /* Contents of trailing part of insn. */ \ |
| 820 | UINT word_1; \ |
| 821 | unsigned int length; |
| 822 | #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \ |
| 823 | length = 6; \ |
| 824 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 825 | f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ |
| 826 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 827 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 828 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 829 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 830 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 831 | |
| 832 | #define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \ |
| 833 | UINT f_operand2; \ |
| 834 | UINT f_membit; \ |
| 835 | UINT f_memmode; \ |
| 836 | UINT f_opcode; \ |
| 837 | UINT f_size; \ |
| 838 | UINT f_operand1; \ |
| 839 | unsigned int length; |
| 840 | #define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \ |
| 841 | length = 2; \ |
| 842 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 843 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 844 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 845 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 846 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 847 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 848 | |
| 849 | #define EXTRACT_IFMT_SBFS_VARS \ |
| 850 | UINT f_operand2; \ |
| 851 | UINT f_membit; \ |
| 852 | UINT f_memmode; \ |
| 853 | UINT f_opcode; \ |
| 854 | UINT f_size; \ |
| 855 | UINT f_operand1; \ |
| 856 | unsigned int length; |
| 857 | #define EXTRACT_IFMT_SBFS_CODE \ |
| 858 | length = 2; \ |
| 859 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 860 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 861 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 862 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 863 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 864 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 865 | |
| 866 | #define EXTRACT_IFMT_SWAP_VARS \ |
| 867 | UINT f_operand2; \ |
| 868 | UINT f_mode; \ |
| 869 | UINT f_opcode; \ |
| 870 | UINT f_size; \ |
| 871 | UINT f_operand1; \ |
| 872 | unsigned int length; |
| 873 | #define EXTRACT_IFMT_SWAP_CODE \ |
| 874 | length = 2; \ |
| 875 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 876 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 877 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 878 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 879 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 880 | |
| 881 | #define EXTRACT_IFMT_ASRQ_VARS \ |
| 882 | UINT f_operand2; \ |
| 883 | UINT f_mode; \ |
| 884 | UINT f_opcode; \ |
| 885 | UINT f_b5; \ |
| 886 | UINT f_u5; \ |
| 887 | unsigned int length; |
| 888 | #define EXTRACT_IFMT_ASRQ_CODE \ |
| 889 | length = 2; \ |
| 890 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 891 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 892 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 893 | f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \ |
| 894 | f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \ |
| 895 | |
| 896 | #define EXTRACT_IFMT_SETF_VARS \ |
| 897 | UINT f_mode; \ |
| 898 | UINT f_opcode; \ |
| 899 | UINT f_size; \ |
| 900 | UINT f_operand2; \ |
| 901 | UINT f_operand1; \ |
| 902 | UINT f_dstsrc; \ |
| 903 | unsigned int length; |
| 904 | #define EXTRACT_IFMT_SETF_CODE \ |
| 905 | length = 2; \ |
| 906 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 907 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 908 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 909 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 910 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 911 | f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\ |
| 912 | |
| 913 | #define EXTRACT_IFMT_BCC_B_VARS \ |
| 914 | UINT f_operand2; \ |
| 915 | UINT f_mode; \ |
| 916 | UINT f_opcode_hi; \ |
| 917 | INT f_disp9_hi; \ |
| 918 | UINT f_disp9_lo; \ |
| 919 | INT f_disp9; \ |
| 920 | unsigned int length; |
| 921 | #define EXTRACT_IFMT_BCC_B_CODE \ |
| 922 | length = 2; \ |
| 923 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 924 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 925 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 926 | f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \ |
| 927 | f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \ |
| 928 | {\ |
| 929 | SI tmp_abslo;\ |
| 930 | SI tmp_absval;\ |
| 931 | tmp_abslo = ((f_disp9_lo) << (1));\ |
| 932 | tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\ |
| 933 | f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\ |
| 934 | }\ |
| 935 | |
| 936 | #define EXTRACT_IFMT_BA_B_VARS \ |
| 937 | UINT f_operand2; \ |
| 938 | UINT f_mode; \ |
| 939 | UINT f_opcode_hi; \ |
| 940 | INT f_disp9_hi; \ |
| 941 | UINT f_disp9_lo; \ |
| 942 | INT f_disp9; \ |
| 943 | unsigned int length; |
| 944 | #define EXTRACT_IFMT_BA_B_CODE \ |
| 945 | length = 2; \ |
| 946 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 947 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 948 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 949 | f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \ |
| 950 | f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \ |
| 951 | {\ |
| 952 | SI tmp_abslo;\ |
| 953 | SI tmp_absval;\ |
| 954 | tmp_abslo = ((f_disp9_lo) << (1));\ |
| 955 | tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\ |
| 956 | f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\ |
| 957 | }\ |
| 958 | |
| 959 | #define EXTRACT_IFMT_BCC_W_VARS \ |
| 960 | UINT f_operand2; \ |
| 961 | SI f_indir_pc__word_pcrel; \ |
| 962 | UINT f_mode; \ |
| 963 | UINT f_opcode; \ |
| 964 | UINT f_size; \ |
| 965 | UINT f_operand1; \ |
| 966 | /* Contents of trailing part of insn. */ \ |
| 967 | UINT word_1; \ |
| 968 | unsigned int length; |
| 969 | #define EXTRACT_IFMT_BCC_W_CODE \ |
| 970 | length = 4; \ |
| 971 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 972 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 973 | f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \ |
| 974 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 975 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 976 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 977 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 978 | |
| 979 | #define EXTRACT_IFMT_BA_W_VARS \ |
| 980 | UINT f_operand2; \ |
| 981 | SI f_indir_pc__word_pcrel; \ |
| 982 | UINT f_mode; \ |
| 983 | UINT f_opcode; \ |
| 984 | UINT f_size; \ |
| 985 | UINT f_operand1; \ |
| 986 | /* Contents of trailing part of insn. */ \ |
| 987 | UINT word_1; \ |
| 988 | unsigned int length; |
| 989 | #define EXTRACT_IFMT_BA_W_CODE \ |
| 990 | length = 4; \ |
| 991 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 992 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 993 | f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \ |
| 994 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 995 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 996 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 997 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 998 | |
| 999 | #define EXTRACT_IFMT_JUMP_C_VARS \ |
| 1000 | INT f_indir_pc__dword; \ |
| 1001 | UINT f_operand2; \ |
| 1002 | UINT f_mode; \ |
| 1003 | UINT f_opcode; \ |
| 1004 | UINT f_size; \ |
| 1005 | UINT f_operand1; \ |
| 1006 | /* Contents of trailing part of insn. */ \ |
| 1007 | UINT word_1; \ |
| 1008 | unsigned int length; |
| 1009 | #define EXTRACT_IFMT_JUMP_C_CODE \ |
| 1010 | length = 6; \ |
| 1011 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 1012 | f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ |
| 1013 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1014 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1015 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1016 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1017 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1018 | |
| 1019 | #define EXTRACT_IFMT_BREAK_VARS \ |
| 1020 | UINT f_operand2; \ |
| 1021 | UINT f_mode; \ |
| 1022 | UINT f_opcode; \ |
| 1023 | UINT f_size; \ |
| 1024 | UINT f_u4; \ |
| 1025 | unsigned int length; |
| 1026 | #define EXTRACT_IFMT_BREAK_CODE \ |
| 1027 | length = 2; \ |
| 1028 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1029 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1030 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1031 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1032 | f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1033 | |
| 1034 | #define EXTRACT_IFMT_SCC_VARS \ |
| 1035 | UINT f_operand2; \ |
| 1036 | UINT f_mode; \ |
| 1037 | UINT f_opcode; \ |
| 1038 | UINT f_size; \ |
| 1039 | UINT f_operand1; \ |
| 1040 | unsigned int length; |
| 1041 | #define EXTRACT_IFMT_SCC_CODE \ |
| 1042 | length = 2; \ |
| 1043 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1044 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1045 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1046 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1047 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1048 | |
| 1049 | #define EXTRACT_IFMT_ADDOQ_VARS \ |
| 1050 | UINT f_operand2; \ |
| 1051 | UINT f_mode; \ |
| 1052 | UINT f_opcode_hi; \ |
| 1053 | INT f_s8; \ |
| 1054 | unsigned int length; |
| 1055 | #define EXTRACT_IFMT_ADDOQ_CODE \ |
| 1056 | length = 2; \ |
| 1057 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1058 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1059 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 1060 | f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \ |
| 1061 | |
| 1062 | #define EXTRACT_IFMT_BDAPQPC_VARS \ |
| 1063 | UINT f_operand2; \ |
| 1064 | UINT f_mode; \ |
| 1065 | UINT f_opcode_hi; \ |
| 1066 | INT f_s8; \ |
| 1067 | unsigned int length; |
| 1068 | #define EXTRACT_IFMT_BDAPQPC_CODE \ |
| 1069 | length = 2; \ |
| 1070 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1071 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1072 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 1073 | f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \ |
| 1074 | |
| 1075 | /* Collection of various things for the trace handler to use. */ |
| 1076 | |
| 1077 | typedef struct trace_record { |
| 1078 | IADDR pc; |
| 1079 | /* FIXME:wip */ |
| 1080 | } TRACE_RECORD; |
| 1081 | |
| 1082 | #endif /* CPU_CRISV10F_H */ |