| 1 | /* CPU family header for crisv32f. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2013 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU simulators. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | |
| 22 | */ |
| 23 | |
| 24 | #ifndef CPU_CRISV32F_H |
| 25 | #define CPU_CRISV32F_H |
| 26 | |
| 27 | /* Maximum number of instructions that are fetched at a time. |
| 28 | This is for LIW type instructions sets (e.g. m32r). */ |
| 29 | #define MAX_LIW_INSNS 1 |
| 30 | |
| 31 | /* Maximum number of instructions that can be executed in parallel. */ |
| 32 | #define MAX_PARALLEL_INSNS 1 |
| 33 | |
| 34 | /* The size of an "int" needed to hold an instruction word. |
| 35 | This is usually 32 bits, but some architectures needs 64 bits. */ |
| 36 | typedef CGEN_INSN_INT CGEN_INSN_WORD; |
| 37 | |
| 38 | #include "cgen-engine.h" |
| 39 | |
| 40 | /* CPU state information. */ |
| 41 | typedef struct { |
| 42 | /* Hardware elements. */ |
| 43 | struct { |
| 44 | /* program counter */ |
| 45 | USI h_pc; |
| 46 | #define GET_H_PC() CPU (h_pc) |
| 47 | #define SET_H_PC(x) \ |
| 48 | do { \ |
| 49 | CPU (h_pc) = ANDSI ((x), (~ (1)));\ |
| 50 | ;} while (0) |
| 51 | /* General purpose registers */ |
| 52 | SI h_gr_acr[16]; |
| 53 | #define GET_H_GR_ACR(a1) CPU (h_gr_acr)[a1] |
| 54 | #define SET_H_GR_ACR(a1, x) (CPU (h_gr_acr)[a1] = (x)) |
| 55 | /* Special registers for v32 */ |
| 56 | SI h_sr_v32[16]; |
| 57 | #define GET_H_SR_V32(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (32) : (((index) == (((UINT) 13)))) ? (ORSI (ANDSI (CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), ORSI (SLLSI (ZEXTBISI (CPU (h_rbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_sbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_mbit)), 30), ORSI (SLLSI (ZEXTBISI (CPU (h_qbit)), 31), 0)))))))))))))) : (((index) == (((UINT) 14)))) ? (((GET_H_UBIT ()) ? (CPU (h_gr_acr[((UINT) 14)])) : (CPU (h_sr_v32[((UINT) 14)])))) : (CPU (h_sr_v32[index])) |
| 58 | #define SET_H_SR_V32(index, x) \ |
| 59 | do { \ |
| 60 | if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\ |
| 61 | ((void) 0); /*nop*/\ |
| 62 | }\ |
| 63 | else if ((((index)) == (((UINT) 13)))) {\ |
| 64 | {\ |
| 65 | CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\ |
| 66 | CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\ |
| 67 | CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\ |
| 68 | CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\ |
| 69 | CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\ |
| 70 | SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\ |
| 71 | SET_H_SBIT (((NESI (ANDSI ((x), ((1) << (9))), 0)) ? (1) : (0)));\ |
| 72 | SET_H_MBIT (((NESI (ANDSI ((x), ((1) << (30))), 0)) ? (1) : (0)));\ |
| 73 | CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\ |
| 74 | CPU (h_rbit) = ((NESI (ANDSI ((x), ((1) << (8))), 0)) ? (1) : (0));\ |
| 75 | SET_H_QBIT (((NESI (ANDSI ((x), ((1) << (31))), 0)) ? (1) : (0)));\ |
| 76 | SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\ |
| 77 | CPU (h_sr_v32[(index)]) = (x);\ |
| 78 | }\ |
| 79 | }\ |
| 80 | else if ((((index)) == (((UINT) 14)))) {\ |
| 81 | {\ |
| 82 | if (GET_H_UBIT ()) {\ |
| 83 | CPU (h_gr_acr[((UINT) 14)]) = (x);\ |
| 84 | }\ |
| 85 | CPU (h_sr_v32[((UINT) 14)]) = (x);\ |
| 86 | }\ |
| 87 | }\ |
| 88 | else if ((((index)) == (((UINT) 3)))) {\ |
| 89 | if (NOTBI (GET_H_UBIT ())) {\ |
| 90 | CPU (h_sr_v32[((UINT) 3)]) = (x);\ |
| 91 | }\ |
| 92 | }\ |
| 93 | else if ((((index)) == (((UINT) 9)))) {\ |
| 94 | if (NOTBI (GET_H_UBIT ())) {\ |
| 95 | CPU (h_sr_v32[((UINT) 9)]) = (x);\ |
| 96 | }\ |
| 97 | }\ |
| 98 | else if ((((index)) == (((UINT) 2)))) {\ |
| 99 | if (NOTBI (GET_H_UBIT ())) {\ |
| 100 | {\ |
| 101 | crisv32f_write_pid_handler (current_cpu, (x));\ |
| 102 | CPU (h_sr_v32[((UINT) 2)]) = (x);\ |
| 103 | }\ |
| 104 | }\ |
| 105 | }\ |
| 106 | else if ((((index)) == (((UINT) 15)))) {\ |
| 107 | if (NOTBI (GET_H_UBIT ())) {\ |
| 108 | CPU (h_sr_v32[((UINT) 15)]) = (x);\ |
| 109 | }\ |
| 110 | }\ |
| 111 | else {\ |
| 112 | CPU (h_sr_v32[(index)]) = (x);\ |
| 113 | }\ |
| 114 | ;} while (0) |
| 115 | /* carry bit */ |
| 116 | BI h_cbit; |
| 117 | #define GET_H_CBIT() CPU (h_cbit) |
| 118 | #define SET_H_CBIT(x) (CPU (h_cbit) = (x)) |
| 119 | /* overflow bit */ |
| 120 | BI h_vbit; |
| 121 | #define GET_H_VBIT() CPU (h_vbit) |
| 122 | #define SET_H_VBIT(x) (CPU (h_vbit) = (x)) |
| 123 | /* zero bit */ |
| 124 | BI h_zbit; |
| 125 | #define GET_H_ZBIT() CPU (h_zbit) |
| 126 | #define SET_H_ZBIT(x) (CPU (h_zbit) = (x)) |
| 127 | /* sign bit */ |
| 128 | BI h_nbit; |
| 129 | #define GET_H_NBIT() CPU (h_nbit) |
| 130 | #define SET_H_NBIT(x) (CPU (h_nbit) = (x)) |
| 131 | /* extended-arithmetic bit */ |
| 132 | BI h_xbit; |
| 133 | #define GET_H_XBIT() CPU (h_xbit) |
| 134 | #define SET_H_XBIT(x) (CPU (h_xbit) = (x)) |
| 135 | /* sequence-broken bit */ |
| 136 | BI h_pbit; |
| 137 | #define GET_H_PBIT() CPU (h_pbit) |
| 138 | #define SET_H_PBIT(x) (CPU (h_pbit) = (x)) |
| 139 | /* carry bit for MCP+restore-p bit */ |
| 140 | BI h_rbit; |
| 141 | #define GET_H_RBIT() CPU (h_rbit) |
| 142 | #define SET_H_RBIT(x) (CPU (h_rbit) = (x)) |
| 143 | /* guru mode bit */ |
| 144 | BI h_gbit; |
| 145 | #define GET_H_GBIT() CPU (h_gbit) |
| 146 | #define SET_H_GBIT(x) (CPU (h_gbit) = (x)) |
| 147 | /* Kernel stack pointer during user mode */ |
| 148 | SI h_kernel_sp; |
| 149 | #define GET_H_KERNEL_SP() CPU (h_kernel_sp) |
| 150 | #define SET_H_KERNEL_SP(x) (CPU (h_kernel_sp) = (x)) |
| 151 | /* User mode bit */ |
| 152 | BI h_ubit_v32; |
| 153 | #define GET_H_UBIT_V32() CPU (h_ubit_v32) |
| 154 | #define SET_H_UBIT_V32(x) \ |
| 155 | do { \ |
| 156 | {\ |
| 157 | if (ANDIF ((x), NOTBI (CPU (h_ubit_v32)))) {\ |
| 158 | {\ |
| 159 | CPU (h_kernel_sp) = CPU (h_gr_acr[((UINT) 14)]);\ |
| 160 | CPU (h_gr_acr[((UINT) 14)]) = CPU (h_sr_v32[((UINT) 14)]);\ |
| 161 | CPU (h_ubit_v32) = (x);\ |
| 162 | crisv32f_usermode_enabled (current_cpu);\ |
| 163 | }\ |
| 164 | }\ |
| 165 | }\ |
| 166 | ;} while (0) |
| 167 | /* Interrupt-enable bit */ |
| 168 | BI h_ibit_v32; |
| 169 | #define GET_H_IBIT_V32() CPU (h_ibit_v32) |
| 170 | #define SET_H_IBIT_V32(x) \ |
| 171 | do { \ |
| 172 | {\ |
| 173 | if (NOTBI (GET_H_UBIT ())) {\ |
| 174 | {\ |
| 175 | BI tmp_enabled;\ |
| 176 | tmp_enabled = ANDIF ((x), NOTBI (CPU (h_ibit_v32)));\ |
| 177 | CPU (h_ibit_v32) = (x);\ |
| 178 | if (tmp_enabled) {\ |
| 179 | crisv32f_interrupts_enabled (current_cpu);\ |
| 180 | }\ |
| 181 | }\ |
| 182 | }\ |
| 183 | }\ |
| 184 | ;} while (0) |
| 185 | /* NMI enable bit */ |
| 186 | BI h_mbit; |
| 187 | #define GET_H_MBIT() CPU (h_mbit) |
| 188 | #define SET_H_MBIT(x) \ |
| 189 | do { \ |
| 190 | {\ |
| 191 | if (ANDIF ((x), ANDIF (NOTBI (CPU (h_mbit)), NOTBI (GET_H_UBIT ())))) {\ |
| 192 | {\ |
| 193 | CPU (h_mbit) = 1;\ |
| 194 | crisv32f_nmi_enabled (current_cpu);\ |
| 195 | }\ |
| 196 | }\ |
| 197 | }\ |
| 198 | ;} while (0) |
| 199 | /* Pending single-step bit */ |
| 200 | BI h_qbit; |
| 201 | #define GET_H_QBIT() CPU (h_qbit) |
| 202 | #define SET_H_QBIT(x) \ |
| 203 | do { \ |
| 204 | {\ |
| 205 | if (NOTBI (GET_H_UBIT ())) {\ |
| 206 | CPU (h_qbit) = (x);\ |
| 207 | }\ |
| 208 | }\ |
| 209 | ;} while (0) |
| 210 | /* Cause single step exception on ... [see CRISv32 ref] bit */ |
| 211 | BI h_sbit; |
| 212 | #define GET_H_SBIT() CPU (h_sbit) |
| 213 | #define SET_H_SBIT(x) \ |
| 214 | do { \ |
| 215 | {\ |
| 216 | if (NOTBI (GET_H_UBIT ())) {\ |
| 217 | {\ |
| 218 | BI tmp_enabled;\ |
| 219 | tmp_enabled = ANDIF ((x), NOTBI (CPU (h_sbit)));\ |
| 220 | CPU (h_sbit) = (x);\ |
| 221 | if (tmp_enabled) {\ |
| 222 | crisv32f_single_step_enabled (current_cpu);\ |
| 223 | }\ |
| 224 | }\ |
| 225 | }\ |
| 226 | }\ |
| 227 | ;} while (0) |
| 228 | } hardware; |
| 229 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) |
| 230 | } CRISV32F_CPU_DATA; |
| 231 | |
| 232 | /* Virtual regs. */ |
| 233 | |
| 234 | #define GET_H_V32_V32() 1 |
| 235 | #define SET_H_V32_V32(x) \ |
| 236 | do { \ |
| 237 | cgen_rtx_error (current_cpu, "Can't set h-v32");\ |
| 238 | ;} while (0) |
| 239 | #define GET_H_GR(index) CPU (h_gr_acr[index]) |
| 240 | #define SET_H_GR(index, x) \ |
| 241 | do { \ |
| 242 | CPU (h_gr_acr[(index)]) = (x);\ |
| 243 | ;} while (0) |
| 244 | #define GET_H_RAW_GR_ACR(index) CPU (h_gr_acr[index]) |
| 245 | #define SET_H_RAW_GR_ACR(index, x) \ |
| 246 | do { \ |
| 247 | CPU (h_gr_acr[(index)]) = (x);\ |
| 248 | ;} while (0) |
| 249 | #define GET_H_SR(index) GET_H_SR_V32 (index) |
| 250 | #define SET_H_SR(index, x) \ |
| 251 | do { \ |
| 252 | SET_H_SR_V32 ((index), (x));\ |
| 253 | ;} while (0) |
| 254 | #define GET_H_SUPR(index) crisv32f_read_supr (current_cpu, index) |
| 255 | #define SET_H_SUPR(index, x) \ |
| 256 | do { \ |
| 257 | crisv32f_write_supr (current_cpu, (index), (x));\ |
| 258 | ;} while (0) |
| 259 | #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_V32 () |
| 260 | #define SET_H_CBIT_MOVE(x) \ |
| 261 | do { \ |
| 262 | SET_H_CBIT_MOVE_V32 ((x));\ |
| 263 | ;} while (0) |
| 264 | #define GET_H_CBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-cbit-move on CRISv32"), 0) |
| 265 | #define SET_H_CBIT_MOVE_V32(x) \ |
| 266 | do { \ |
| 267 | ((void) 0); /*nop*/\ |
| 268 | ;} while (0) |
| 269 | #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_V32 () |
| 270 | #define SET_H_VBIT_MOVE(x) \ |
| 271 | do { \ |
| 272 | SET_H_VBIT_MOVE_V32 ((x));\ |
| 273 | ;} while (0) |
| 274 | #define GET_H_VBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-vbit-move on CRISv32"), 0) |
| 275 | #define SET_H_VBIT_MOVE_V32(x) \ |
| 276 | do { \ |
| 277 | ((void) 0); /*nop*/\ |
| 278 | ;} while (0) |
| 279 | #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_V32 () |
| 280 | #define SET_H_ZBIT_MOVE(x) \ |
| 281 | do { \ |
| 282 | SET_H_ZBIT_MOVE_V32 ((x));\ |
| 283 | ;} while (0) |
| 284 | #define GET_H_ZBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-zbit-move on CRISv32"), 0) |
| 285 | #define SET_H_ZBIT_MOVE_V32(x) \ |
| 286 | do { \ |
| 287 | ((void) 0); /*nop*/\ |
| 288 | ;} while (0) |
| 289 | #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_V32 () |
| 290 | #define SET_H_NBIT_MOVE(x) \ |
| 291 | do { \ |
| 292 | SET_H_NBIT_MOVE_V32 ((x));\ |
| 293 | ;} while (0) |
| 294 | #define GET_H_NBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-nbit-move on CRISv32"), 0) |
| 295 | #define SET_H_NBIT_MOVE_V32(x) \ |
| 296 | do { \ |
| 297 | ((void) 0); /*nop*/\ |
| 298 | ;} while (0) |
| 299 | #define GET_H_IBIT() CPU (h_ibit_v32) |
| 300 | #define SET_H_IBIT(x) \ |
| 301 | do { \ |
| 302 | SET_H_IBIT_V32 ((x));\ |
| 303 | ;} while (0) |
| 304 | #define GET_H_UBIT() CPU (h_ubit_v32) |
| 305 | #define SET_H_UBIT(x) \ |
| 306 | do { \ |
| 307 | SET_H_UBIT_V32 ((x));\ |
| 308 | ;} while (0) |
| 309 | #define GET_H_INSN_PREFIXED_P() GET_H_INSN_PREFIXED_P_V32 () |
| 310 | #define SET_H_INSN_PREFIXED_P(x) \ |
| 311 | do { \ |
| 312 | SET_H_INSN_PREFIXED_P_V32 ((x));\ |
| 313 | ;} while (0) |
| 314 | #define GET_H_INSN_PREFIXED_P_V32() 0 |
| 315 | #define SET_H_INSN_PREFIXED_P_V32(x) \ |
| 316 | do { \ |
| 317 | ((void) 0); /*nop*/\ |
| 318 | ;} while (0) |
| 319 | #define GET_H_PREFIXREG_V32() GET_H_GR (((UINT) 15)) |
| 320 | #define SET_H_PREFIXREG_V32(x) \ |
| 321 | do { \ |
| 322 | SET_H_GR (((UINT) 15), (x));\ |
| 323 | ;} while (0) |
| 324 | |
| 325 | /* Cover fns for register access. */ |
| 326 | BI crisv32f_h_v32_v32_get (SIM_CPU *); |
| 327 | void crisv32f_h_v32_v32_set (SIM_CPU *, BI); |
| 328 | USI crisv32f_h_pc_get (SIM_CPU *); |
| 329 | void crisv32f_h_pc_set (SIM_CPU *, USI); |
| 330 | SI crisv32f_h_gr_get (SIM_CPU *, UINT); |
| 331 | void crisv32f_h_gr_set (SIM_CPU *, UINT, SI); |
| 332 | SI crisv32f_h_gr_acr_get (SIM_CPU *, UINT); |
| 333 | void crisv32f_h_gr_acr_set (SIM_CPU *, UINT, SI); |
| 334 | SI crisv32f_h_raw_gr_acr_get (SIM_CPU *, UINT); |
| 335 | void crisv32f_h_raw_gr_acr_set (SIM_CPU *, UINT, SI); |
| 336 | SI crisv32f_h_sr_get (SIM_CPU *, UINT); |
| 337 | void crisv32f_h_sr_set (SIM_CPU *, UINT, SI); |
| 338 | SI crisv32f_h_sr_v32_get (SIM_CPU *, UINT); |
| 339 | void crisv32f_h_sr_v32_set (SIM_CPU *, UINT, SI); |
| 340 | SI crisv32f_h_supr_get (SIM_CPU *, UINT); |
| 341 | void crisv32f_h_supr_set (SIM_CPU *, UINT, SI); |
| 342 | BI crisv32f_h_cbit_get (SIM_CPU *); |
| 343 | void crisv32f_h_cbit_set (SIM_CPU *, BI); |
| 344 | BI crisv32f_h_cbit_move_get (SIM_CPU *); |
| 345 | void crisv32f_h_cbit_move_set (SIM_CPU *, BI); |
| 346 | BI crisv32f_h_cbit_move_v32_get (SIM_CPU *); |
| 347 | void crisv32f_h_cbit_move_v32_set (SIM_CPU *, BI); |
| 348 | BI crisv32f_h_vbit_get (SIM_CPU *); |
| 349 | void crisv32f_h_vbit_set (SIM_CPU *, BI); |
| 350 | BI crisv32f_h_vbit_move_get (SIM_CPU *); |
| 351 | void crisv32f_h_vbit_move_set (SIM_CPU *, BI); |
| 352 | BI crisv32f_h_vbit_move_v32_get (SIM_CPU *); |
| 353 | void crisv32f_h_vbit_move_v32_set (SIM_CPU *, BI); |
| 354 | BI crisv32f_h_zbit_get (SIM_CPU *); |
| 355 | void crisv32f_h_zbit_set (SIM_CPU *, BI); |
| 356 | BI crisv32f_h_zbit_move_get (SIM_CPU *); |
| 357 | void crisv32f_h_zbit_move_set (SIM_CPU *, BI); |
| 358 | BI crisv32f_h_zbit_move_v32_get (SIM_CPU *); |
| 359 | void crisv32f_h_zbit_move_v32_set (SIM_CPU *, BI); |
| 360 | BI crisv32f_h_nbit_get (SIM_CPU *); |
| 361 | void crisv32f_h_nbit_set (SIM_CPU *, BI); |
| 362 | BI crisv32f_h_nbit_move_get (SIM_CPU *); |
| 363 | void crisv32f_h_nbit_move_set (SIM_CPU *, BI); |
| 364 | BI crisv32f_h_nbit_move_v32_get (SIM_CPU *); |
| 365 | void crisv32f_h_nbit_move_v32_set (SIM_CPU *, BI); |
| 366 | BI crisv32f_h_xbit_get (SIM_CPU *); |
| 367 | void crisv32f_h_xbit_set (SIM_CPU *, BI); |
| 368 | BI crisv32f_h_ibit_get (SIM_CPU *); |
| 369 | void crisv32f_h_ibit_set (SIM_CPU *, BI); |
| 370 | BI crisv32f_h_pbit_get (SIM_CPU *); |
| 371 | void crisv32f_h_pbit_set (SIM_CPU *, BI); |
| 372 | BI crisv32f_h_rbit_get (SIM_CPU *); |
| 373 | void crisv32f_h_rbit_set (SIM_CPU *, BI); |
| 374 | BI crisv32f_h_ubit_get (SIM_CPU *); |
| 375 | void crisv32f_h_ubit_set (SIM_CPU *, BI); |
| 376 | BI crisv32f_h_gbit_get (SIM_CPU *); |
| 377 | void crisv32f_h_gbit_set (SIM_CPU *, BI); |
| 378 | SI crisv32f_h_kernel_sp_get (SIM_CPU *); |
| 379 | void crisv32f_h_kernel_sp_set (SIM_CPU *, SI); |
| 380 | BI crisv32f_h_ubit_v32_get (SIM_CPU *); |
| 381 | void crisv32f_h_ubit_v32_set (SIM_CPU *, BI); |
| 382 | BI crisv32f_h_ibit_v32_get (SIM_CPU *); |
| 383 | void crisv32f_h_ibit_v32_set (SIM_CPU *, BI); |
| 384 | BI crisv32f_h_mbit_get (SIM_CPU *); |
| 385 | void crisv32f_h_mbit_set (SIM_CPU *, BI); |
| 386 | BI crisv32f_h_qbit_get (SIM_CPU *); |
| 387 | void crisv32f_h_qbit_set (SIM_CPU *, BI); |
| 388 | BI crisv32f_h_sbit_get (SIM_CPU *); |
| 389 | void crisv32f_h_sbit_set (SIM_CPU *, BI); |
| 390 | BI crisv32f_h_insn_prefixed_p_get (SIM_CPU *); |
| 391 | void crisv32f_h_insn_prefixed_p_set (SIM_CPU *, BI); |
| 392 | BI crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *); |
| 393 | void crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *, BI); |
| 394 | SI crisv32f_h_prefixreg_v32_get (SIM_CPU *); |
| 395 | void crisv32f_h_prefixreg_v32_set (SIM_CPU *, SI); |
| 396 | |
| 397 | /* These must be hand-written. */ |
| 398 | extern CPUREG_FETCH_FN crisv32f_fetch_register; |
| 399 | extern CPUREG_STORE_FN crisv32f_store_register; |
| 400 | |
| 401 | typedef struct { |
| 402 | UINT prev_prev_prev_modf_regs; |
| 403 | UINT prev_prev_modf_regs; |
| 404 | UINT prev_modf_regs; |
| 405 | UINT modf_regs; |
| 406 | UINT prev_prev_prev_movem_dest_regs; |
| 407 | UINT prev_prev_movem_dest_regs; |
| 408 | UINT prev_movem_dest_regs; |
| 409 | UINT movem_dest_regs; |
| 410 | } MODEL_CRISV32_DATA; |
| 411 | |
| 412 | /* Instruction argument buffer. */ |
| 413 | |
| 414 | union sem_fields { |
| 415 | struct { /* no operands */ |
| 416 | int empty; |
| 417 | } sfmt_empty; |
| 418 | struct { /* */ |
| 419 | UINT f_u4; |
| 420 | } sfmt_break; |
| 421 | struct { /* */ |
| 422 | UINT f_dstsrc; |
| 423 | } sfmt_setf; |
| 424 | struct { /* */ |
| 425 | IADDR i_o_word_pcrel; |
| 426 | UINT f_operand2; |
| 427 | } sfmt_bcc_w; |
| 428 | struct { /* */ |
| 429 | IADDR i_o_pcrel; |
| 430 | UINT f_operand2; |
| 431 | } sfmt_bcc_b; |
| 432 | struct { /* */ |
| 433 | unsigned char in_h_sr_SI_13; |
| 434 | unsigned char out_h_sr_SI_13; |
| 435 | } sfmt_rfe; |
| 436 | struct { /* */ |
| 437 | INT f_s8; |
| 438 | UINT f_operand2; |
| 439 | unsigned char in_Rd; |
| 440 | } sfmt_addoq; |
| 441 | struct { /* */ |
| 442 | ADDR i_const32_pcrel; |
| 443 | UINT f_operand2; |
| 444 | unsigned char out_Pd; |
| 445 | } sfmt_bas_c; |
| 446 | struct { /* */ |
| 447 | ADDR i_qo; |
| 448 | UINT f_operand2; |
| 449 | unsigned char out_Rd; |
| 450 | } sfmt_lapcq; |
| 451 | struct { /* */ |
| 452 | ADDR i_const32_pcrel; |
| 453 | UINT f_operand2; |
| 454 | unsigned char out_Rd; |
| 455 | } sfmt_lapc_d; |
| 456 | struct { /* */ |
| 457 | INT f_indir_pc__dword; |
| 458 | UINT f_operand2; |
| 459 | unsigned char out_Pd; |
| 460 | } sfmt_move_c_sprv32_p2; |
| 461 | struct { /* */ |
| 462 | INT f_s6; |
| 463 | UINT f_operand2; |
| 464 | unsigned char out_Rd; |
| 465 | } sfmt_moveq; |
| 466 | struct { /* */ |
| 467 | INT f_indir_pc__dword; |
| 468 | UINT f_operand2; |
| 469 | unsigned char in_Rd; |
| 470 | unsigned char out_Rd; |
| 471 | } sfmt_bound_cd; |
| 472 | struct { /* */ |
| 473 | INT f_indir_pc__word; |
| 474 | UINT f_operand2; |
| 475 | unsigned char in_Rd; |
| 476 | unsigned char out_Rd; |
| 477 | } sfmt_bound_cw; |
| 478 | struct { /* */ |
| 479 | INT f_indir_pc__byte; |
| 480 | UINT f_operand2; |
| 481 | unsigned char in_Rd; |
| 482 | unsigned char out_Rd; |
| 483 | } sfmt_bound_cb; |
| 484 | struct { /* */ |
| 485 | UINT f_operand2; |
| 486 | UINT f_u5; |
| 487 | unsigned char in_Rd; |
| 488 | unsigned char out_Rd; |
| 489 | } sfmt_asrq; |
| 490 | struct { /* */ |
| 491 | INT f_s6; |
| 492 | UINT f_operand2; |
| 493 | unsigned char in_Rd; |
| 494 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 495 | } sfmt_andq; |
| 496 | struct { /* */ |
| 497 | INT f_indir_pc__dword; |
| 498 | UINT f_operand2; |
| 499 | unsigned char in_Rd; |
| 500 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 501 | } sfmt_addcdr; |
| 502 | struct { /* */ |
| 503 | INT f_indir_pc__word; |
| 504 | UINT f_operand2; |
| 505 | unsigned char in_Rd; |
| 506 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 507 | } sfmt_addcwr; |
| 508 | struct { /* */ |
| 509 | INT f_indir_pc__byte; |
| 510 | UINT f_operand2; |
| 511 | unsigned char in_Rd; |
| 512 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 513 | } sfmt_addcbr; |
| 514 | struct { /* */ |
| 515 | UINT f_operand2; |
| 516 | UINT f_u6; |
| 517 | unsigned char in_Rd; |
| 518 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 519 | } sfmt_addq; |
| 520 | struct { /* */ |
| 521 | UINT f_operand1; |
| 522 | UINT f_operand2; |
| 523 | unsigned char in_Ps; |
| 524 | unsigned char in_Rs; |
| 525 | unsigned char out_h_gr_SI_index_of__INT_Rs; |
| 526 | } sfmt_mcp; |
| 527 | struct { /* */ |
| 528 | UINT f_operand1; |
| 529 | UINT f_operand2; |
| 530 | unsigned char in_Rd; |
| 531 | unsigned char in_Rs; |
| 532 | unsigned char out_Rd; |
| 533 | unsigned char out_h_sr_SI_7; |
| 534 | } sfmt_muls_b; |
| 535 | struct { /* */ |
| 536 | UINT f_memmode; |
| 537 | UINT f_operand1; |
| 538 | UINT f_operand2; |
| 539 | unsigned char in_Ps; |
| 540 | unsigned char in_Rs; |
| 541 | unsigned char out_Rs; |
| 542 | } sfmt_move_spr_mv32; |
| 543 | struct { /* */ |
| 544 | UINT f_memmode; |
| 545 | UINT f_operand1; |
| 546 | UINT f_operand2; |
| 547 | unsigned char in_Rs; |
| 548 | unsigned char out_Pd; |
| 549 | unsigned char out_Rs; |
| 550 | } sfmt_move_m_sprv32; |
| 551 | struct { /* */ |
| 552 | UINT f_memmode; |
| 553 | UINT f_operand1; |
| 554 | UINT f_operand2; |
| 555 | unsigned char in_Rs; |
| 556 | unsigned char out_Rd; |
| 557 | unsigned char out_Rs; |
| 558 | } sfmt_movs_m_b_m; |
| 559 | struct { /* */ |
| 560 | UINT f_memmode; |
| 561 | UINT f_operand1; |
| 562 | UINT f_operand2; |
| 563 | unsigned char in_Rd; |
| 564 | unsigned char in_Rs; |
| 565 | unsigned char out_Rs; |
| 566 | unsigned char out_h_gr_SI_index_of__INT_Rd; |
| 567 | } sfmt_addc_m; |
| 568 | struct { /* */ |
| 569 | UINT f_memmode; |
| 570 | UINT f_operand1; |
| 571 | UINT f_operand2; |
| 572 | unsigned char in_Rd; |
| 573 | unsigned char in_Rs; |
| 574 | unsigned char out_Rs; |
| 575 | unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd; |
| 576 | } sfmt_add_m_b_m; |
| 577 | struct { /* */ |
| 578 | UINT f_memmode; |
| 579 | UINT f_operand1; |
| 580 | UINT f_operand2; |
| 581 | unsigned char in_Rd; |
| 582 | unsigned char in_Rs; |
| 583 | unsigned char out_Rs; |
| 584 | unsigned char out_h_gr_SI_0; |
| 585 | unsigned char out_h_gr_SI_1; |
| 586 | unsigned char out_h_gr_SI_10; |
| 587 | unsigned char out_h_gr_SI_11; |
| 588 | unsigned char out_h_gr_SI_12; |
| 589 | unsigned char out_h_gr_SI_13; |
| 590 | unsigned char out_h_gr_SI_14; |
| 591 | unsigned char out_h_gr_SI_15; |
| 592 | unsigned char out_h_gr_SI_2; |
| 593 | unsigned char out_h_gr_SI_3; |
| 594 | unsigned char out_h_gr_SI_4; |
| 595 | unsigned char out_h_gr_SI_5; |
| 596 | unsigned char out_h_gr_SI_6; |
| 597 | unsigned char out_h_gr_SI_7; |
| 598 | unsigned char out_h_gr_SI_8; |
| 599 | unsigned char out_h_gr_SI_9; |
| 600 | } sfmt_movem_m_r_v32; |
| 601 | struct { /* */ |
| 602 | UINT f_memmode; |
| 603 | UINT f_operand1; |
| 604 | UINT f_operand2; |
| 605 | unsigned char in_Rd; |
| 606 | unsigned char in_Rs; |
| 607 | unsigned char in_h_gr_SI_0; |
| 608 | unsigned char in_h_gr_SI_1; |
| 609 | unsigned char in_h_gr_SI_10; |
| 610 | unsigned char in_h_gr_SI_11; |
| 611 | unsigned char in_h_gr_SI_12; |
| 612 | unsigned char in_h_gr_SI_13; |
| 613 | unsigned char in_h_gr_SI_14; |
| 614 | unsigned char in_h_gr_SI_15; |
| 615 | unsigned char in_h_gr_SI_2; |
| 616 | unsigned char in_h_gr_SI_3; |
| 617 | unsigned char in_h_gr_SI_4; |
| 618 | unsigned char in_h_gr_SI_5; |
| 619 | unsigned char in_h_gr_SI_6; |
| 620 | unsigned char in_h_gr_SI_7; |
| 621 | unsigned char in_h_gr_SI_8; |
| 622 | unsigned char in_h_gr_SI_9; |
| 623 | unsigned char out_Rs; |
| 624 | } sfmt_movem_r_m_v32; |
| 625 | #if WITH_SCACHE_PBB |
| 626 | /* Writeback handler. */ |
| 627 | struct { |
| 628 | /* Pointer to argbuf entry for insn whose results need writing back. */ |
| 629 | const struct argbuf *abuf; |
| 630 | } write; |
| 631 | /* x-before handler */ |
| 632 | struct { |
| 633 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ |
| 634 | int first_p; |
| 635 | } before; |
| 636 | /* x-after handler */ |
| 637 | struct { |
| 638 | int empty; |
| 639 | } after; |
| 640 | /* This entry is used to terminate each pbb. */ |
| 641 | struct { |
| 642 | /* Number of insns in pbb. */ |
| 643 | int insn_count; |
| 644 | /* Next pbb to execute. */ |
| 645 | SCACHE *next; |
| 646 | SCACHE *branch_target; |
| 647 | } chain; |
| 648 | #endif |
| 649 | }; |
| 650 | |
| 651 | /* The ARGBUF struct. */ |
| 652 | struct argbuf { |
| 653 | /* These are the baseclass definitions. */ |
| 654 | IADDR addr; |
| 655 | const IDESC *idesc; |
| 656 | char trace_p; |
| 657 | char profile_p; |
| 658 | /* ??? Temporary hack for skip insns. */ |
| 659 | char skip_count; |
| 660 | char unused; |
| 661 | /* cpu specific data follows */ |
| 662 | union sem semantic; |
| 663 | int written; |
| 664 | union sem_fields fields; |
| 665 | }; |
| 666 | |
| 667 | /* A cached insn. |
| 668 | |
| 669 | ??? SCACHE used to contain more than just argbuf. We could delete the |
| 670 | type entirely and always just use ARGBUF, but for future concerns and as |
| 671 | a level of abstraction it is left in. */ |
| 672 | |
| 673 | struct scache { |
| 674 | struct argbuf argbuf; |
| 675 | }; |
| 676 | |
| 677 | /* Macros to simplify extraction, reading and semantic code. |
| 678 | These define and assign the local vars that contain the insn's fields. */ |
| 679 | |
| 680 | #define EXTRACT_IFMT_EMPTY_VARS \ |
| 681 | unsigned int length; |
| 682 | #define EXTRACT_IFMT_EMPTY_CODE \ |
| 683 | length = 0; \ |
| 684 | |
| 685 | #define EXTRACT_IFMT_MOVE_B_R_VARS \ |
| 686 | UINT f_operand2; \ |
| 687 | UINT f_mode; \ |
| 688 | UINT f_opcode; \ |
| 689 | UINT f_size; \ |
| 690 | UINT f_operand1; \ |
| 691 | unsigned int length; |
| 692 | #define EXTRACT_IFMT_MOVE_B_R_CODE \ |
| 693 | length = 2; \ |
| 694 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 695 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 696 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 697 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 698 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 699 | |
| 700 | #define EXTRACT_IFMT_MOVEQ_VARS \ |
| 701 | UINT f_operand2; \ |
| 702 | UINT f_mode; \ |
| 703 | UINT f_opcode; \ |
| 704 | INT f_s6; \ |
| 705 | unsigned int length; |
| 706 | #define EXTRACT_IFMT_MOVEQ_CODE \ |
| 707 | length = 2; \ |
| 708 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 709 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 710 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 711 | f_s6 = EXTRACT_LSB0_SINT (insn, 16, 5, 6); \ |
| 712 | |
| 713 | #define EXTRACT_IFMT_MOVECBR_VARS \ |
| 714 | UINT f_operand2; \ |
| 715 | INT f_indir_pc__byte; \ |
| 716 | UINT f_mode; \ |
| 717 | UINT f_opcode; \ |
| 718 | UINT f_size; \ |
| 719 | UINT f_operand1; \ |
| 720 | /* Contents of trailing part of insn. */ \ |
| 721 | UINT word_1; \ |
| 722 | unsigned int length; |
| 723 | #define EXTRACT_IFMT_MOVECBR_CODE \ |
| 724 | length = 4; \ |
| 725 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 726 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 727 | f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 728 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 729 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 730 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 731 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 732 | |
| 733 | #define EXTRACT_IFMT_MOVECWR_VARS \ |
| 734 | UINT f_operand2; \ |
| 735 | INT f_indir_pc__word; \ |
| 736 | UINT f_mode; \ |
| 737 | UINT f_opcode; \ |
| 738 | UINT f_size; \ |
| 739 | UINT f_operand1; \ |
| 740 | /* Contents of trailing part of insn. */ \ |
| 741 | UINT word_1; \ |
| 742 | unsigned int length; |
| 743 | #define EXTRACT_IFMT_MOVECWR_CODE \ |
| 744 | length = 4; \ |
| 745 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 746 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 747 | f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 748 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 749 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 750 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 751 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 752 | |
| 753 | #define EXTRACT_IFMT_MOVECDR_VARS \ |
| 754 | INT f_indir_pc__dword; \ |
| 755 | UINT f_operand2; \ |
| 756 | UINT f_mode; \ |
| 757 | UINT f_opcode; \ |
| 758 | UINT f_size; \ |
| 759 | UINT f_operand1; \ |
| 760 | /* Contents of trailing part of insn. */ \ |
| 761 | UINT word_1; \ |
| 762 | unsigned int length; |
| 763 | #define EXTRACT_IFMT_MOVECDR_CODE \ |
| 764 | length = 6; \ |
| 765 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 766 | f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ |
| 767 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 768 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 769 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 770 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 771 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 772 | |
| 773 | #define EXTRACT_IFMT_MOVUCBR_VARS \ |
| 774 | UINT f_operand2; \ |
| 775 | INT f_indir_pc__byte; \ |
| 776 | UINT f_mode; \ |
| 777 | UINT f_opcode; \ |
| 778 | UINT f_size; \ |
| 779 | UINT f_operand1; \ |
| 780 | /* Contents of trailing part of insn. */ \ |
| 781 | UINT word_1; \ |
| 782 | unsigned int length; |
| 783 | #define EXTRACT_IFMT_MOVUCBR_CODE \ |
| 784 | length = 4; \ |
| 785 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 786 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 787 | f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 788 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 789 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 790 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 791 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 792 | |
| 793 | #define EXTRACT_IFMT_MOVUCWR_VARS \ |
| 794 | UINT f_operand2; \ |
| 795 | INT f_indir_pc__word; \ |
| 796 | UINT f_mode; \ |
| 797 | UINT f_opcode; \ |
| 798 | UINT f_size; \ |
| 799 | UINT f_operand1; \ |
| 800 | /* Contents of trailing part of insn. */ \ |
| 801 | UINT word_1; \ |
| 802 | unsigned int length; |
| 803 | #define EXTRACT_IFMT_MOVUCWR_CODE \ |
| 804 | length = 4; \ |
| 805 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 806 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 807 | f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ |
| 808 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 809 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 810 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 811 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 812 | |
| 813 | #define EXTRACT_IFMT_ADDQ_VARS \ |
| 814 | UINT f_operand2; \ |
| 815 | UINT f_mode; \ |
| 816 | UINT f_opcode; \ |
| 817 | UINT f_u6; \ |
| 818 | unsigned int length; |
| 819 | #define EXTRACT_IFMT_ADDQ_CODE \ |
| 820 | length = 2; \ |
| 821 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 822 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 823 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 824 | f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \ |
| 825 | |
| 826 | #define EXTRACT_IFMT_CMP_M_B_M_VARS \ |
| 827 | UINT f_operand2; \ |
| 828 | UINT f_membit; \ |
| 829 | UINT f_memmode; \ |
| 830 | UINT f_opcode; \ |
| 831 | UINT f_size; \ |
| 832 | UINT f_operand1; \ |
| 833 | unsigned int length; |
| 834 | #define EXTRACT_IFMT_CMP_M_B_M_CODE \ |
| 835 | length = 2; \ |
| 836 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 837 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 838 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 839 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 840 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 841 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 842 | |
| 843 | #define EXTRACT_IFMT_MOVE_R_SPRV32_VARS \ |
| 844 | UINT f_operand2; \ |
| 845 | UINT f_mode; \ |
| 846 | UINT f_opcode; \ |
| 847 | UINT f_size; \ |
| 848 | UINT f_operand1; \ |
| 849 | unsigned int length; |
| 850 | #define EXTRACT_IFMT_MOVE_R_SPRV32_CODE \ |
| 851 | length = 2; \ |
| 852 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 853 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 854 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 855 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 856 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 857 | |
| 858 | #define EXTRACT_IFMT_MOVE_SPR_RV32_VARS \ |
| 859 | UINT f_operand2; \ |
| 860 | UINT f_mode; \ |
| 861 | UINT f_opcode; \ |
| 862 | UINT f_size; \ |
| 863 | UINT f_operand1; \ |
| 864 | unsigned int length; |
| 865 | #define EXTRACT_IFMT_MOVE_SPR_RV32_CODE \ |
| 866 | length = 2; \ |
| 867 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 868 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 869 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 870 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 871 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 872 | |
| 873 | #define EXTRACT_IFMT_MOVE_M_SPRV32_VARS \ |
| 874 | UINT f_operand2; \ |
| 875 | UINT f_membit; \ |
| 876 | UINT f_memmode; \ |
| 877 | UINT f_opcode; \ |
| 878 | UINT f_size; \ |
| 879 | UINT f_operand1; \ |
| 880 | unsigned int length; |
| 881 | #define EXTRACT_IFMT_MOVE_M_SPRV32_CODE \ |
| 882 | length = 2; \ |
| 883 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 884 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 885 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 886 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 887 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 888 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 889 | |
| 890 | #define EXTRACT_IFMT_MOVE_C_SPRV32_P2_VARS \ |
| 891 | INT f_indir_pc__dword; \ |
| 892 | UINT f_operand2; \ |
| 893 | UINT f_mode; \ |
| 894 | UINT f_opcode; \ |
| 895 | UINT f_size; \ |
| 896 | UINT f_operand1; \ |
| 897 | /* Contents of trailing part of insn. */ \ |
| 898 | UINT word_1; \ |
| 899 | unsigned int length; |
| 900 | #define EXTRACT_IFMT_MOVE_C_SPRV32_P2_CODE \ |
| 901 | length = 6; \ |
| 902 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 903 | f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ |
| 904 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 905 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 906 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 907 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 908 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 909 | |
| 910 | #define EXTRACT_IFMT_MOVE_SPR_MV32_VARS \ |
| 911 | UINT f_operand2; \ |
| 912 | UINT f_membit; \ |
| 913 | UINT f_memmode; \ |
| 914 | UINT f_opcode; \ |
| 915 | UINT f_size; \ |
| 916 | UINT f_operand1; \ |
| 917 | unsigned int length; |
| 918 | #define EXTRACT_IFMT_MOVE_SPR_MV32_CODE \ |
| 919 | length = 2; \ |
| 920 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 921 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 922 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 923 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 924 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 925 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 926 | |
| 927 | #define EXTRACT_IFMT_MOVE_SS_R_VARS \ |
| 928 | UINT f_operand2; \ |
| 929 | UINT f_mode; \ |
| 930 | UINT f_opcode; \ |
| 931 | UINT f_size; \ |
| 932 | UINT f_operand1; \ |
| 933 | unsigned int length; |
| 934 | #define EXTRACT_IFMT_MOVE_SS_R_CODE \ |
| 935 | length = 2; \ |
| 936 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 937 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 938 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 939 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 940 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 941 | |
| 942 | #define EXTRACT_IFMT_MOVE_R_SS_VARS \ |
| 943 | UINT f_operand2; \ |
| 944 | UINT f_mode; \ |
| 945 | UINT f_opcode; \ |
| 946 | UINT f_size; \ |
| 947 | UINT f_operand1; \ |
| 948 | unsigned int length; |
| 949 | #define EXTRACT_IFMT_MOVE_R_SS_CODE \ |
| 950 | length = 2; \ |
| 951 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 952 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 953 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 954 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 955 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 956 | |
| 957 | #define EXTRACT_IFMT_LAPC_D_VARS \ |
| 958 | SI f_indir_pc__dword_pcrel; \ |
| 959 | UINT f_operand2; \ |
| 960 | UINT f_mode; \ |
| 961 | UINT f_opcode; \ |
| 962 | UINT f_size; \ |
| 963 | UINT f_operand1; \ |
| 964 | /* Contents of trailing part of insn. */ \ |
| 965 | UINT word_1; \ |
| 966 | unsigned int length; |
| 967 | #define EXTRACT_IFMT_LAPC_D_CODE \ |
| 968 | length = 6; \ |
| 969 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 970 | f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \ |
| 971 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 972 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 973 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 974 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 975 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 976 | |
| 977 | #define EXTRACT_IFMT_LAPCQ_VARS \ |
| 978 | UINT f_operand2; \ |
| 979 | UINT f_mode; \ |
| 980 | UINT f_opcode; \ |
| 981 | UINT f_size; \ |
| 982 | SI f_qo; \ |
| 983 | unsigned int length; |
| 984 | #define EXTRACT_IFMT_LAPCQ_CODE \ |
| 985 | length = 2; \ |
| 986 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 987 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 988 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 989 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 990 | f_qo = ((pc) + (((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)))); \ |
| 991 | |
| 992 | #define EXTRACT_IFMT_TEST_M_B_M_VARS \ |
| 993 | UINT f_operand2; \ |
| 994 | UINT f_membit; \ |
| 995 | UINT f_memmode; \ |
| 996 | UINT f_opcode; \ |
| 997 | UINT f_size; \ |
| 998 | UINT f_operand1; \ |
| 999 | unsigned int length; |
| 1000 | #define EXTRACT_IFMT_TEST_M_B_M_CODE \ |
| 1001 | length = 2; \ |
| 1002 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1003 | f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ |
| 1004 | f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ |
| 1005 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1006 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1007 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1008 | |
| 1009 | #define EXTRACT_IFMT_SWAP_VARS \ |
| 1010 | UINT f_operand2; \ |
| 1011 | UINT f_mode; \ |
| 1012 | UINT f_opcode; \ |
| 1013 | UINT f_size; \ |
| 1014 | UINT f_operand1; \ |
| 1015 | unsigned int length; |
| 1016 | #define EXTRACT_IFMT_SWAP_CODE \ |
| 1017 | length = 2; \ |
| 1018 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1019 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1020 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1021 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1022 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1023 | |
| 1024 | #define EXTRACT_IFMT_ASRQ_VARS \ |
| 1025 | UINT f_operand2; \ |
| 1026 | UINT f_mode; \ |
| 1027 | UINT f_opcode; \ |
| 1028 | UINT f_b5; \ |
| 1029 | UINT f_u5; \ |
| 1030 | unsigned int length; |
| 1031 | #define EXTRACT_IFMT_ASRQ_CODE \ |
| 1032 | length = 2; \ |
| 1033 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1034 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1035 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1036 | f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \ |
| 1037 | f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \ |
| 1038 | |
| 1039 | #define EXTRACT_IFMT_SETF_VARS \ |
| 1040 | UINT f_mode; \ |
| 1041 | UINT f_opcode; \ |
| 1042 | UINT f_size; \ |
| 1043 | UINT f_operand2; \ |
| 1044 | UINT f_operand1; \ |
| 1045 | UINT f_dstsrc; \ |
| 1046 | unsigned int length; |
| 1047 | #define EXTRACT_IFMT_SETF_CODE \ |
| 1048 | length = 2; \ |
| 1049 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1050 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1051 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1052 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1053 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1054 | f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\ |
| 1055 | |
| 1056 | #define EXTRACT_IFMT_RFE_VARS \ |
| 1057 | UINT f_operand2; \ |
| 1058 | UINT f_mode; \ |
| 1059 | UINT f_opcode; \ |
| 1060 | UINT f_size; \ |
| 1061 | UINT f_operand1; \ |
| 1062 | unsigned int length; |
| 1063 | #define EXTRACT_IFMT_RFE_CODE \ |
| 1064 | length = 2; \ |
| 1065 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1066 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1067 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1068 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1069 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1070 | |
| 1071 | #define EXTRACT_IFMT_BCC_B_VARS \ |
| 1072 | UINT f_operand2; \ |
| 1073 | UINT f_mode; \ |
| 1074 | UINT f_opcode_hi; \ |
| 1075 | INT f_disp9_hi; \ |
| 1076 | UINT f_disp9_lo; \ |
| 1077 | INT f_disp9; \ |
| 1078 | unsigned int length; |
| 1079 | #define EXTRACT_IFMT_BCC_B_CODE \ |
| 1080 | length = 2; \ |
| 1081 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1082 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1083 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 1084 | f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \ |
| 1085 | f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \ |
| 1086 | {\ |
| 1087 | SI tmp_abslo;\ |
| 1088 | SI tmp_absval;\ |
| 1089 | tmp_abslo = ((f_disp9_lo) << (1));\ |
| 1090 | tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\ |
| 1091 | f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\ |
| 1092 | }\ |
| 1093 | |
| 1094 | #define EXTRACT_IFMT_BA_B_VARS \ |
| 1095 | UINT f_operand2; \ |
| 1096 | UINT f_mode; \ |
| 1097 | UINT f_opcode_hi; \ |
| 1098 | INT f_disp9_hi; \ |
| 1099 | UINT f_disp9_lo; \ |
| 1100 | INT f_disp9; \ |
| 1101 | unsigned int length; |
| 1102 | #define EXTRACT_IFMT_BA_B_CODE \ |
| 1103 | length = 2; \ |
| 1104 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1105 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1106 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 1107 | f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \ |
| 1108 | f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \ |
| 1109 | {\ |
| 1110 | SI tmp_abslo;\ |
| 1111 | SI tmp_absval;\ |
| 1112 | tmp_abslo = ((f_disp9_lo) << (1));\ |
| 1113 | tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\ |
| 1114 | f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\ |
| 1115 | }\ |
| 1116 | |
| 1117 | #define EXTRACT_IFMT_BCC_W_VARS \ |
| 1118 | UINT f_operand2; \ |
| 1119 | SI f_indir_pc__word_pcrel; \ |
| 1120 | UINT f_mode; \ |
| 1121 | UINT f_opcode; \ |
| 1122 | UINT f_size; \ |
| 1123 | UINT f_operand1; \ |
| 1124 | /* Contents of trailing part of insn. */ \ |
| 1125 | UINT word_1; \ |
| 1126 | unsigned int length; |
| 1127 | #define EXTRACT_IFMT_BCC_W_CODE \ |
| 1128 | length = 4; \ |
| 1129 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 1130 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1131 | f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \ |
| 1132 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1133 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1134 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1135 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1136 | |
| 1137 | #define EXTRACT_IFMT_BA_W_VARS \ |
| 1138 | UINT f_operand2; \ |
| 1139 | SI f_indir_pc__word_pcrel; \ |
| 1140 | UINT f_mode; \ |
| 1141 | UINT f_opcode; \ |
| 1142 | UINT f_size; \ |
| 1143 | UINT f_operand1; \ |
| 1144 | /* Contents of trailing part of insn. */ \ |
| 1145 | UINT word_1; \ |
| 1146 | unsigned int length; |
| 1147 | #define EXTRACT_IFMT_BA_W_CODE \ |
| 1148 | length = 4; \ |
| 1149 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 1150 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1151 | f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \ |
| 1152 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1153 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1154 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1155 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1156 | |
| 1157 | #define EXTRACT_IFMT_JAS_C_VARS \ |
| 1158 | INT f_indir_pc__dword; \ |
| 1159 | UINT f_operand2; \ |
| 1160 | UINT f_mode; \ |
| 1161 | UINT f_opcode; \ |
| 1162 | UINT f_size; \ |
| 1163 | UINT f_operand1; \ |
| 1164 | /* Contents of trailing part of insn. */ \ |
| 1165 | UINT word_1; \ |
| 1166 | unsigned int length; |
| 1167 | #define EXTRACT_IFMT_JAS_C_CODE \ |
| 1168 | length = 6; \ |
| 1169 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 1170 | f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ |
| 1171 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1172 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1173 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1174 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1175 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1176 | |
| 1177 | #define EXTRACT_IFMT_JUMP_P_VARS \ |
| 1178 | UINT f_operand2; \ |
| 1179 | UINT f_mode; \ |
| 1180 | UINT f_opcode; \ |
| 1181 | UINT f_size; \ |
| 1182 | UINT f_operand1; \ |
| 1183 | unsigned int length; |
| 1184 | #define EXTRACT_IFMT_JUMP_P_CODE \ |
| 1185 | length = 2; \ |
| 1186 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1187 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1188 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1189 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1190 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1191 | |
| 1192 | #define EXTRACT_IFMT_BAS_C_VARS \ |
| 1193 | SI f_indir_pc__dword_pcrel; \ |
| 1194 | UINT f_operand2; \ |
| 1195 | UINT f_mode; \ |
| 1196 | UINT f_opcode; \ |
| 1197 | UINT f_size; \ |
| 1198 | UINT f_operand1; \ |
| 1199 | /* Contents of trailing part of insn. */ \ |
| 1200 | UINT word_1; \ |
| 1201 | unsigned int length; |
| 1202 | #define EXTRACT_IFMT_BAS_C_CODE \ |
| 1203 | length = 6; \ |
| 1204 | word_1 = GETIMEMUSI (current_cpu, pc + 2); \ |
| 1205 | f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \ |
| 1206 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1207 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1208 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1209 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1210 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1211 | |
| 1212 | #define EXTRACT_IFMT_BREAK_VARS \ |
| 1213 | UINT f_operand2; \ |
| 1214 | UINT f_mode; \ |
| 1215 | UINT f_opcode; \ |
| 1216 | UINT f_size; \ |
| 1217 | UINT f_u4; \ |
| 1218 | unsigned int length; |
| 1219 | #define EXTRACT_IFMT_BREAK_CODE \ |
| 1220 | length = 2; \ |
| 1221 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1222 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1223 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1224 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1225 | f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1226 | |
| 1227 | #define EXTRACT_IFMT_SCC_VARS \ |
| 1228 | UINT f_operand2; \ |
| 1229 | UINT f_mode; \ |
| 1230 | UINT f_opcode; \ |
| 1231 | UINT f_size; \ |
| 1232 | UINT f_operand1; \ |
| 1233 | unsigned int length; |
| 1234 | #define EXTRACT_IFMT_SCC_CODE \ |
| 1235 | length = 2; \ |
| 1236 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1237 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1238 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1239 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1240 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1241 | |
| 1242 | #define EXTRACT_IFMT_ADDOQ_VARS \ |
| 1243 | UINT f_operand2; \ |
| 1244 | UINT f_mode; \ |
| 1245 | UINT f_opcode_hi; \ |
| 1246 | INT f_s8; \ |
| 1247 | unsigned int length; |
| 1248 | #define EXTRACT_IFMT_ADDOQ_CODE \ |
| 1249 | length = 2; \ |
| 1250 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1251 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1252 | f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ |
| 1253 | f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \ |
| 1254 | |
| 1255 | #define EXTRACT_IFMT_FIDXI_VARS \ |
| 1256 | UINT f_operand2; \ |
| 1257 | UINT f_mode; \ |
| 1258 | UINT f_opcode; \ |
| 1259 | UINT f_size; \ |
| 1260 | UINT f_operand1; \ |
| 1261 | unsigned int length; |
| 1262 | #define EXTRACT_IFMT_FIDXI_CODE \ |
| 1263 | length = 2; \ |
| 1264 | f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ |
| 1265 | f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ |
| 1266 | f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ |
| 1267 | f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ |
| 1268 | f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ |
| 1269 | |
| 1270 | /* Collection of various things for the trace handler to use. */ |
| 1271 | |
| 1272 | typedef struct trace_record { |
| 1273 | IADDR pc; |
| 1274 | /* FIXME:wip */ |
| 1275 | } TRACE_RECORD; |
| 1276 | |
| 1277 | #endif /* CPU_CRISV32F_H */ |