| 1 | /* Collection of junk for CRIS. |
| 2 | Copyright (C) 2004-2020 Free Software Foundation, Inc. |
| 3 | Contributed by Axis Communications. |
| 4 | |
| 5 | This file is part of the GNU simulators. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | /* For other arch:s, this file is described as a "collection of junk", so |
| 21 | let's collect some nice junk of our own. Keep it; it might be useful |
| 22 | some day! */ |
| 23 | |
| 24 | #ifndef CRIS_SIM_H |
| 25 | #define CRIS_SIM_H |
| 26 | |
| 27 | typedef struct { |
| 28 | /* Whether the branch for the current insn was taken. Placed first |
| 29 | here, in hope it'll get closer to the main simulator data. */ |
| 30 | USI branch_taken; |
| 31 | |
| 32 | /* PC of the insn of the branch. */ |
| 33 | USI old_pc; |
| 34 | |
| 35 | /* Static cycle count for all insns executed so far, including |
| 36 | non-context-specific stall cycles, for example when adding to PC. */ |
| 37 | unsigned64 basic_cycle_count; |
| 38 | |
| 39 | /* Stall cycles for unaligned access of memory operands. FIXME: |
| 40 | Should or should not include unaligned [PC+] operands? */ |
| 41 | unsigned64 unaligned_mem_dword_count; |
| 42 | |
| 43 | /* Context-specific stall cycles. */ |
| 44 | unsigned64 memsrc_stall_count; |
| 45 | unsigned64 memraw_stall_count; |
| 46 | unsigned64 movemsrc_stall_count; |
| 47 | unsigned64 movemaddr_stall_count; |
| 48 | unsigned64 movemdst_stall_count; |
| 49 | unsigned64 mulsrc_stall_count; |
| 50 | unsigned64 jumpsrc_stall_count; |
| 51 | unsigned64 branch_stall_count; |
| 52 | unsigned64 jumptarget_stall_count; |
| 53 | |
| 54 | /* What kind of target-specific trace to perform. */ |
| 55 | int flags; |
| 56 | |
| 57 | /* Just the basic cycle count. */ |
| 58 | #define FLAG_CRIS_MISC_PROFILE_SIMPLE 1 |
| 59 | |
| 60 | /* Show unaligned accesses. */ |
| 61 | #define FLAG_CRIS_MISC_PROFILE_UNALIGNED 2 |
| 62 | |
| 63 | /* Show schedulable entities. */ |
| 64 | #define FLAG_CRIS_MISC_PROFILE_SCHEDULABLE 4 |
| 65 | |
| 66 | /* Show everything. */ |
| 67 | #define FLAG_CRIS_MISC_PROFILE_ALL \ |
| 68 | (FLAG_CRIS_MISC_PROFILE_SIMPLE \ |
| 69 | | FLAG_CRIS_MISC_PROFILE_UNALIGNED \ |
| 70 | | FLAG_CRIS_MISC_PROFILE_SCHEDULABLE) |
| 71 | |
| 72 | /* Emit trace of each insn, xsim style. */ |
| 73 | #define FLAG_CRIS_MISC_PROFILE_XSIM_TRACE 8 |
| 74 | |
| 75 | #define N_CRISV32_BRANCH_PREDICTORS 256 |
| 76 | unsigned char branch_predictors[N_CRISV32_BRANCH_PREDICTORS]; |
| 77 | |
| 78 | } CRIS_MISC_PROFILE; |
| 79 | |
| 80 | /* Handler prototypes for functions called from the CGEN description. */ |
| 81 | |
| 82 | extern USI cris_bmod_handler (SIM_CPU *, UINT, USI); |
| 83 | extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI); |
| 84 | extern USI crisv10f_break_handler (SIM_CPU *, USI, USI); |
| 85 | extern USI crisv32f_break_handler (SIM_CPU *, USI, USI); |
| 86 | extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI, |
| 87 | USI, USI); |
| 88 | extern char cris_have_900000xxif; |
| 89 | enum cris_unknown_syscall_action_type |
| 90 | { CRIS_USYSC_MSG_STOP, CRIS_USYSC_MSG_ENOSYS, CRIS_USYSC_QUIET_ENOSYS }; |
| 91 | extern enum cris_unknown_syscall_action_type cris_unknown_syscall_action; |
| 92 | enum cris_interrupt_type { CRIS_INT_NMI, CRIS_INT_RESET, CRIS_INT_INT }; |
| 93 | extern int crisv10deliver_interrupt (SIM_CPU *, |
| 94 | enum cris_interrupt_type, |
| 95 | unsigned int); |
| 96 | extern int crisv32deliver_interrupt (SIM_CPU *, |
| 97 | enum cris_interrupt_type, |
| 98 | unsigned int); |
| 99 | |
| 100 | /* Using GNU syntax (not C99) so we can compile this on RH 6.2 |
| 101 | (egcs-1.1.2/gcc-2.91.66). */ |
| 102 | #define cris_trace_printf(SD, CPU, FMT...) \ |
| 103 | do \ |
| 104 | { \ |
| 105 | if (TRACE_FILE (STATE_TRACE_DATA (SD)) != NULL) \ |
| 106 | fprintf (TRACE_FILE (CPU_TRACE_DATA (CPU)), FMT); \ |
| 107 | else \ |
| 108 | sim_io_printf (SD, FMT); \ |
| 109 | } \ |
| 110 | while (0) |
| 111 | |
| 112 | #if WITH_PROFILE_MODEL_P |
| 113 | #define crisv32f_branch_taken(cpu, oldpc, newpc, taken) \ |
| 114 | do \ |
| 115 | { \ |
| 116 | CPU_CRIS_MISC_PROFILE (cpu)->old_pc = oldpc; \ |
| 117 | CPU_CRIS_MISC_PROFILE (cpu)->branch_taken = taken; \ |
| 118 | } \ |
| 119 | while (0) |
| 120 | #else |
| 121 | #define crisv32f_branch_taken(cpu, oldpc, newpc, taken) |
| 122 | #endif |
| 123 | |
| 124 | #define crisv10f_branch_taken(cpu, oldpc, newpc, taken) |
| 125 | |
| 126 | #define crisv32f_read_supr(cpu, index) \ |
| 127 | (cgen_rtx_error (current_cpu, \ |
| 128 | "Read of support register is unimplemented"), \ |
| 129 | 0) |
| 130 | |
| 131 | #define crisv32f_write_supr(cpu, index, val) \ |
| 132 | cgen_rtx_error (current_cpu, \ |
| 133 | "Write to support register is unimplemented") \ |
| 134 | |
| 135 | #define crisv32f_rfg_handler(cpu, pc) \ |
| 136 | cgen_rtx_error (current_cpu, "RFG isn't implemented") |
| 137 | |
| 138 | #define crisv32f_halt_handler(cpu, pc) \ |
| 139 | (cgen_rtx_error (current_cpu, "HALT isn't implemented"), 0) |
| 140 | |
| 141 | #define crisv32f_fidxi_handler(cpu, pc, indx) \ |
| 142 | (cgen_rtx_error (current_cpu, "FIDXI isn't implemented"), 0) |
| 143 | |
| 144 | #define crisv32f_ftagi_handler(cpu, pc, indx) \ |
| 145 | (cgen_rtx_error (current_cpu, "FTAGI isn't implemented"), 0) |
| 146 | |
| 147 | #define crisv32f_fidxd_handler(cpu, pc, indx) \ |
| 148 | (cgen_rtx_error (current_cpu, "FIDXD isn't implemented"), 0) |
| 149 | |
| 150 | #define crisv32f_ftagd_handler(cpu, pc, indx) \ |
| 151 | (cgen_rtx_error (current_cpu, "FTAGD isn't implemented"), 0) |
| 152 | |
| 153 | /* We have nothing special to do when interrupts or NMI are enabled |
| 154 | after having been disabled, so empty macros are enough for these |
| 155 | hooks. */ |
| 156 | #define crisv32f_interrupts_enabled(cpu) |
| 157 | #define crisv32f_nmi_enabled(cpu) |
| 158 | |
| 159 | /* Better warn for this case here, because everything needed is |
| 160 | somewhere within the CPU. Compare to trying to use interrupts and |
| 161 | NMI, which would fail earlier, when trying to make nonexistent |
| 162 | external components generate those exceptions. */ |
| 163 | #define crisv32f_single_step_enabled(cpu) \ |
| 164 | ((crisv32f_h_qbit_get (cpu) != 0 \ |
| 165 | || (crisv32f_h_sr_get (cpu, H_SR_SPC) & ~1) != 0) \ |
| 166 | ? (cgen_rtx_error (cpu, \ |
| 167 | "single-stepping isn't implemented"), 0) \ |
| 168 | : 0) |
| 169 | |
| 170 | /* We don't need to track the value of the PID register here. */ |
| 171 | #define crisv32f_write_pid_handler(cpu, val) |
| 172 | |
| 173 | /* Neither do we need to know of transitions to user mode. */ |
| 174 | #define crisv32f_usermode_enabled(cpu) |
| 175 | |
| 176 | /* House-keeping exported from traps.c */ |
| 177 | extern void cris_set_callbacks (host_callback *); |
| 178 | |
| 179 | /* FIXME: Add more junk. */ |
| 180 | #endif |