| 1 | |
| 2 | SIS - Sparc Instruction Simulator README file (v2.0, 05-02-1996) |
| 3 | ------------------------------------------------------------------- |
| 4 | |
| 5 | 1. Introduction |
| 6 | |
| 7 | The SIS is a SPARC V7 architecture simulator. It consist of two parts, |
| 8 | the simulator core and a user defined memory module. The simulator |
| 9 | core executes the instructions while the memory module emulates memory |
| 10 | and peripherals. |
| 11 | |
| 12 | 2. Usage |
| 13 | |
| 14 | The simulator is started as follows: |
| 15 | |
| 16 | sis [-uart1 uart_device1] [-uart2 uart_device2] |
| 17 | [-nfp] [-freq frequency] [-c batch_file] [files] |
| 18 | |
| 19 | The default uart devices for SIS are /dev/ptypc and /dev/ptypd. The |
| 20 | -uart[1,2] switch can be used to connect the uarts to other devices. |
| 21 | Use 'tip /dev/ttypc' to connect a terminal emulator to the uarts. |
| 22 | The '-nfp' will disable the simulated FPU, so each FPU instruction will |
| 23 | generate a FPU disabled trap. The '-freq' switch can be used to define |
| 24 | which "frequency" the simulator runs at. This is used by the 'perf' |
| 25 | command to calculated the MIPS figure for a particular configuration. |
| 26 | The give frequency must be an integer indicating the frequency in MHz. |
| 27 | |
| 28 | The -c option indicates that sis commands should be read from 'batch_file' |
| 29 | at startup. |
| 30 | |
| 31 | Files to be loaded must be in one of the supported formats (see INSTALLATION), |
| 32 | and will be loaded into the simulated memory. The file formats are |
| 33 | automatically recognised. |
| 34 | |
| 35 | The script 'startsim' will start the simulator in one xterm window and |
| 36 | open a terminal emulator (tip) connected to the UART A in a second |
| 37 | xterm window. Below is description of commands that are recognized by |
| 38 | the simulator. The command-line is parsed using GNU readline. A command |
| 39 | history of 64 commands is maintained. Use the up/down arrows to recall |
| 40 | previous commands. For more details, see the readline documentation. |
| 41 | |
| 42 | batch <file> |
| 43 | |
| 44 | Execute a batch file of SIS commands. |
| 45 | |
| 46 | +bp <address> |
| 47 | |
| 48 | Adds an breakpoint at address <address>. |
| 49 | |
| 50 | bp |
| 51 | |
| 52 | Prints all breakpoints |
| 53 | |
| 54 | -bp <num> |
| 55 | |
| 56 | Deletes breakpoint <num>. Use 'bp' to see which number is assigned to the |
| 57 | breakpoints. |
| 58 | |
| 59 | cont [inst_count] |
| 60 | |
| 61 | Continue execution at present position, optionally for [inst_count] |
| 62 | instructions. |
| 63 | |
| 64 | dis [addr] [count] |
| 65 | |
| 66 | Disassemble [count] instructions at address [addr]. Default values for |
| 67 | count is 16 and addr is the present address. |
| 68 | |
| 69 | echo <string> |
| 70 | |
| 71 | Print <string> to the simulator window. |
| 72 | |
| 73 | float |
| 74 | |
| 75 | Prints the FPU registers |
| 76 | |
| 77 | go <address> [inst_count] |
| 78 | |
| 79 | The go command will set pc to <address> and npc to <address> + 4, and start |
| 80 | execution. No other initialisation will be done. If inst_count is given, |
| 81 | execution will stop after the specified number of instructions. |
| 82 | |
| 83 | help |
| 84 | |
| 85 | Print a small help menu for the SIS commands. |
| 86 | |
| 87 | hist [trace_length] |
| 88 | |
| 89 | Enable the instruction trace buffer. The 'trace_length' last executed |
| 90 | instructions will be placed in the trace buffer. A 'hist' command without |
| 91 | a trace_length will display the trace buffer. Specifying a zero trace |
| 92 | length will disable the trace buffer. |
| 93 | |
| 94 | load <file_name> |
| 95 | |
| 96 | Loads a file into simulator memory. |
| 97 | |
| 98 | mem [addr] [count] |
| 99 | |
| 100 | Display memory at [addr] for [count] bytes. Same default values as above. |
| 101 | |
| 102 | quit |
| 103 | |
| 104 | Exits the simulator. |
| 105 | |
| 106 | perf [reset] |
| 107 | |
| 108 | The 'perf' command will display various execution statistics. A 'perf reset' |
| 109 | command will reset the statistics. This can be used if statistics shall |
| 110 | be calculated only over a part of the program. The 'run' and 'reset' |
| 111 | command also resets the statistic information. |
| 112 | |
| 113 | reg [reg_name] [value] |
| 114 | |
| 115 | Prints and sets the IU regiters. 'reg' without parameters prints the IU |
| 116 | registers. 'reg [reg_name] [value]' sets the corresponding register to |
| 117 | [value]. Valid register names are psr, tbr, wim, y, g1-g7, o0-o7 and |
| 118 | l0-l7. |
| 119 | |
| 120 | reset |
| 121 | |
| 122 | Performs a power-on reset. This command is equal to 'run 0'. |
| 123 | |
| 124 | run [inst_count] |
| 125 | |
| 126 | Resets the simulator and starts execution from address 0. If an instruction |
| 127 | count is given (inst_count), the simulator will stop after the specified |
| 128 | number of instructions. The event queue is emptied but any set breakpoints |
| 129 | remain. |
| 130 | |
| 131 | step |
| 132 | |
| 133 | Equal to 'trace 1' |
| 134 | |
| 135 | tra [inst_count] |
| 136 | |
| 137 | Starts the simulator at the present position and prints each instruction |
| 138 | it executes. If an instruction count is given (inst_count), the simulator |
| 139 | will stop after the specified number of instructions. |
| 140 | |
| 141 | Typing a 'Ctrl-C' will interrupt a running simulator. |
| 142 | |
| 143 | Short forms of the commands are allowed, e.g 'c' 'co' or 'con' are all |
| 144 | interpreted as 'cont'. |
| 145 | |
| 146 | |
| 147 | 3. Simulator core |
| 148 | |
| 149 | The SIS emulates the behavior of the 90C601E and 90C602E sparc IU and |
| 150 | FPU from Matra MHS. These are roughly equivalent to the Cypress C601 |
| 151 | and C602. The simulator is cycle true, i.e a simulator time is |
| 152 | maintained and inremented according the IU and FPU instruction timing. |
| 153 | The parallel execution between the IU and FPU is modelled, as well as |
| 154 | stalls due to operand dependencies (FPU). The core interacts with the |
| 155 | user-defined memory modules through a number of functions. The memory |
| 156 | module must provide the following functions: |
| 157 | |
| 158 | int memory_read(asi,addr,data,ws) |
| 159 | int asi; |
| 160 | unsigned int addr; |
| 161 | unsigned int *data; |
| 162 | int *ws; |
| 163 | |
| 164 | int memory_write(asi,addr,data,sz,ws) |
| 165 | int asi; |
| 166 | unsigned int addr; |
| 167 | unsigned int *data; |
| 168 | int sz; |
| 169 | int *ws; |
| 170 | |
| 171 | int sis_memory_read(addr, data, length) |
| 172 | unsigned int addr; |
| 173 | char *data; |
| 174 | unsigned int length; |
| 175 | |
| 176 | int sis_memory_write(addr, data, length) |
| 177 | unsigned int addr; |
| 178 | char *data; |
| 179 | unsigned int length; |
| 180 | |
| 181 | int init_sim() |
| 182 | |
| 183 | int reset() |
| 184 | |
| 185 | int error_mode(pc) |
| 186 | unsigned int pc; |
| 187 | |
| 188 | memory_read() is used by the simulator to fetch instructions and |
| 189 | operands. The address space identifier (asi) and address is passed as |
| 190 | parameters. The read data should be assigned to the data pointer |
| 191 | (*data) and the number of waitstate to *ws. 'memory_read' should return |
| 192 | 0 on success and 1 on failure. A failure will cause a data or |
| 193 | instruction fetch trap. memory_read() always reads one 32-bit word. |
| 194 | |
| 195 | sis_memory_read() is used by the simulator to display and disassemble |
| 196 | memory contants. The function should copy 'length' bytes of the simulated |
| 197 | memory starting at 'addr' to '*data'. |
| 198 | The sis_memory_read() should return 1 on success and 0 on failure. |
| 199 | Failure should only be indicated if access to unimplemented memory is attempted. |
| 200 | |
| 201 | memory_write() is used to write to memory. In addition to the asi |
| 202 | and address parameters, the size of the written data is given by 'sz'. |
| 203 | The pointer *data points to the data to be written. The 'sz' is coded |
| 204 | as follows: |
| 205 | |
| 206 | sz access type |
| 207 | 0 byte |
| 208 | 1 halfword |
| 209 | 2 word |
| 210 | 3 double-word |
| 211 | |
| 212 | If a double word is written, the most significant word is in data[0] and |
| 213 | the least significant in data[1]. |
| 214 | |
| 215 | sis_memory_write() is used by the simulator during loading of programs. |
| 216 | The function should copy 'length' bytes from *data to the simulated |
| 217 | memory starting at 'addr'. sis_memory_write() should return 1 on |
| 218 | success and 0 on failure. Failure should only be indicated if access |
| 219 | to unimplemented memory is attempted. See erc32.c for more details |
| 220 | on how to define the memory emulation functions. |
| 221 | |
| 222 | The 'init_sim' is called once when the simulator is started. This function |
| 223 | should be used to perform initialisations of user defined memory or |
| 224 | peripherals that only have to be done once, such as opening files etc. |
| 225 | |
| 226 | The 'reset' is called every time the simulator is reset, i.e. when a |
| 227 | 'run' command is given. This function should be used to simulate a power |
| 228 | on reset of memory and peripherals. |
| 229 | |
| 230 | error_mode() is called by the simulator when the IU goes into error mode, |
| 231 | typically if a trap is caused when traps are disabled. The memory module |
| 232 | can then take actions, such as issue a reset. |
| 233 | |
| 234 | sys_reset() can be called by the memory module to reset the simulator. A |
| 235 | reset will empty the event queue and perform a power-on reset. |
| 236 | |
| 237 | 4. Events and interrupts |
| 238 | |
| 239 | The simulator supports an event queue and the generation of processor |
| 240 | interrupts. The following functions are available to the user-defined |
| 241 | memory module: |
| 242 | |
| 243 | event(cfunc,arg,delta) |
| 244 | void (*cfunc)(); |
| 245 | int arg; |
| 246 | unsigned int delta; |
| 247 | |
| 248 | set_int(level,callback,arg) |
| 249 | int level; |
| 250 | void (*callback)(); |
| 251 | int arg; |
| 252 | |
| 253 | clear_int(level) |
| 254 | int level; |
| 255 | |
| 256 | sim_stop() |
| 257 | |
| 258 | The 'event' functions will schedule the execution of the function 'cfunc' |
| 259 | at time 'now + delta' clock cycles. The parameter 'arg' is passed as a |
| 260 | parameter to 'cfunc'. |
| 261 | |
| 262 | The 'set_int' function set the processor interrupt 'level'. When the interrupt |
| 263 | is taken, the function 'callback' is called with the argument 'arg'. This |
| 264 | will also clear the interrupt. An interrupt can be cleared before it is |
| 265 | taken by calling 'clear_int' with the appropriate interrupt level. |
| 266 | |
| 267 | The sim_stop function is called each time the simulator stops execution. |
| 268 | It can be used to flush buffered devices to get a clean state during |
| 269 | single stepping etc. |
| 270 | |
| 271 | See 'erc32.c' for examples on how to use events and interrupts. |
| 272 | |
| 273 | 5. Memory module |
| 274 | |
| 275 | The supplied memory module (erc32.c) emulates the functions of memory and |
| 276 | the MEC asic developed for the 90C601/2. It includes the following functions: |
| 277 | |
| 278 | * UART A & B |
| 279 | * Real-time clock |
| 280 | * General purpose timer |
| 281 | * Interrupt controller |
| 282 | * Breakpoint register |
| 283 | * Watchpoint register |
| 284 | * 512 Kbyte ROM |
| 285 | * 4 Mbyte RAM |
| 286 | |
| 287 | See README.erc32 on how the MEC functions are emulated. For a detailed MEC |
| 288 | specification, look at the ERC32 home page at URL: |
| 289 | |
| 290 | http://www.estec.esa.nl/wsmwww/erc32 |
| 291 | |
| 292 | 6. Compile and linking programs |
| 293 | |
| 294 | The directory 'examples' contain some code fragments for SIS. |
| 295 | The script gccx indicates how the native sunos gcc and linker can be used |
| 296 | to produce executables for the simulator. To compile and link the provided |
| 297 | 'hello.c', type 'gccx hello.c'. This will build the executable 'hello'. |
| 298 | Start the simulator by running 'startsim hello', and issue the command 'run. |
| 299 | After the program is terminated, the IU will be force to error mode through |
| 300 | a software trap and halt. |
| 301 | |
| 302 | The programs are linked with a start-up file, srt0.S. This file includes |
| 303 | the traptable and window underflow/overflow trap routines. |
| 304 | |
| 305 | 7. IU and FPU instruction timing. |
| 306 | |
| 307 | The simulator provides cycle true simulation. The following table shows |
| 308 | the emulated instruction timing for 90C601E & 90C602E: |
| 309 | |
| 310 | Instructions Cycles |
| 311 | |
| 312 | jmpl, rett 2 |
| 313 | load 2 |
| 314 | store 3 |
| 315 | load double 3 |
| 316 | store double 4 |
| 317 | other integer ops 1 |
| 318 | fabs 2 |
| 319 | fadds 4 |
| 320 | faddd 4 |
| 321 | fcmps 4 |
| 322 | fcmpd 4 |
| 323 | fdivs 20 |
| 324 | fdivd 35 |
| 325 | fmovs 2 |
| 326 | fmuls 5 |
| 327 | fmuld 9 |
| 328 | fnegs 2 |
| 329 | fsqrts 37 |
| 330 | fsqrtd 65 |
| 331 | fsubs 4 |
| 332 | fsubd 4 |
| 333 | fdtoi 7 |
| 334 | fdots 3 |
| 335 | fitos 6 |
| 336 | fitod 6 |
| 337 | fstoi 6 |
| 338 | fstod 2 |
| 339 | |
| 340 | The parallel operation between the IU and FPU is modelled. This means |
| 341 | that a FPU instruction will execute in parallel with other instructions as |
| 342 | long as no data or resource dependency is detected. See the 90C602E data |
| 343 | sheet for the various types of dependencies. Tracing using the 'trace' |
| 344 | command will display the current simulator time in the left column. This |
| 345 | time indicates when the instruction is fetched. If a dependency is detetected, |
| 346 | the following fetch will be delayed until the conflict is resolved. |
| 347 | |
| 348 | The load dependency in the 90C601E is also modelled - if the destination |
| 349 | register of a load instruction is used by the following instruction, an |
| 350 | idle cycle is inserted. |
| 351 | |
| 352 | 8. FPU implementation |
| 353 | |
| 354 | The simulator maps floating-point operations on the hosts floating point |
| 355 | capabilities. This means that accuracy and generation of IEEE exceptions is |
| 356 | host dependent. |