| 1 | /* frv simulator support code |
| 2 | Copyright (C) 1998-2019 Free Software Foundation, Inc. |
| 3 | Contributed by Red Hat. |
| 4 | |
| 5 | This file is part of the GNU simulators. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | /* Main header for the frv. */ |
| 21 | |
| 22 | /* sim-basics.h includes config.h but cgen-types.h must be included before |
| 23 | sim-basics.h and cgen-types.h needs config.h. */ |
| 24 | #include "config.h" |
| 25 | |
| 26 | /* This is a global setting. Different cpu families can't mix-n-match -scache |
| 27 | and -pbb. However some cpu families may use -simple while others use |
| 28 | one of -scache/-pbb. ???? */ |
| 29 | #define WITH_SCACHE_PBB 0 |
| 30 | |
| 31 | #include "symcat.h" |
| 32 | #include "sim-basics.h" |
| 33 | #include "cgen-types.h" |
| 34 | #include "frv-desc.h" |
| 35 | #include "frv-opc.h" |
| 36 | #include "arch.h" |
| 37 | |
| 38 | #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \ |
| 39 | frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA)) |
| 40 | |
| 41 | #define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0 |
| 42 | |
| 43 | #include "sim-base.h" |
| 44 | #include "cgen-sim.h" |
| 45 | #include "frv-sim.h" |
| 46 | #include "cache.h" |
| 47 | #include "registers.h" |
| 48 | #include "profile.h" |
| 49 | |
| 50 | void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia); |
| 51 | |
| 52 | extern void frv_sim_close (SIM_DESC sd, int quitting); |
| 53 | #define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__) |
| 54 | \f |
| 55 | /* The _sim_cpu struct. */ |
| 56 | |
| 57 | struct _sim_cpu { |
| 58 | /* sim/common cpu base. */ |
| 59 | sim_cpu_base base; |
| 60 | |
| 61 | /* Static parts of cgen. */ |
| 62 | CGEN_CPU cgen_cpu; |
| 63 | |
| 64 | /* CPU specific parts go here. |
| 65 | Note that in files that don't need to access these pieces WANT_CPU_FOO |
| 66 | won't be defined and thus these parts won't appear. This is ok in the |
| 67 | sense that things work. It is a source of bugs though. |
| 68 | One has to of course be careful to not take the size of this |
| 69 | struct and no structure members accessed in non-cpu specific files can |
| 70 | go after here. Oh for a better language. */ |
| 71 | #if defined (WANT_CPU_FRVBF) |
| 72 | FRVBF_CPU_DATA cpu_data; |
| 73 | |
| 74 | /* Control information for registers */ |
| 75 | FRV_REGISTER_CONTROL register_control; |
| 76 | #define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control) |
| 77 | |
| 78 | FRV_VLIW vliw; |
| 79 | #define CPU_VLIW(cpu) (& (cpu)->vliw) |
| 80 | |
| 81 | FRV_CACHE insn_cache; |
| 82 | #define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache) |
| 83 | |
| 84 | FRV_CACHE data_cache; |
| 85 | #define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache) |
| 86 | |
| 87 | FRV_PROFILE_STATE profile_state; |
| 88 | #define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state) |
| 89 | |
| 90 | int debug_state; |
| 91 | #define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state) |
| 92 | |
| 93 | SI load_address; |
| 94 | #define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address) |
| 95 | |
| 96 | SI load_length; |
| 97 | #define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length) |
| 98 | |
| 99 | SI load_flag; |
| 100 | #define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag) |
| 101 | #define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag) |
| 102 | |
| 103 | SI store_flag; |
| 104 | #define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag) |
| 105 | |
| 106 | unsigned long elf_flags; |
| 107 | #define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags) |
| 108 | #endif /* defined (WANT_CPU_FRVBF) */ |
| 109 | }; |
| 110 | \f |
| 111 | /* The sim_state struct. */ |
| 112 | |
| 113 | struct sim_state { |
| 114 | sim_cpu *cpu[MAX_NR_PROCESSORS]; |
| 115 | |
| 116 | CGEN_STATE cgen_state; |
| 117 | |
| 118 | sim_state_base base; |
| 119 | }; |
| 120 | \f |
| 121 | /* Misc. */ |
| 122 | |
| 123 | /* Catch address exceptions. */ |
| 124 | extern SIM_CORE_SIGNAL_FN frv_core_signal; |
| 125 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ |
| 126 | frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \ |
| 127 | (TRANSFER), (ERROR)) |
| 128 | |
| 129 | /* Default memory size. */ |
| 130 | #define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */ |