| 1 | /* Simulator for the FT32 processor |
| 2 | |
| 3 | Copyright (C) 2008-2017 Free Software Foundation, Inc. |
| 4 | Contributed by FTDI <support@ftdichip.com> |
| 5 | |
| 6 | This file is part of simulators. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | #include "config.h" |
| 22 | #include <fcntl.h> |
| 23 | #include <signal.h> |
| 24 | #include <stdlib.h> |
| 25 | #include <stdint.h> |
| 26 | |
| 27 | #include "bfd.h" |
| 28 | #include "gdb/callback.h" |
| 29 | #include "libiberty.h" |
| 30 | #include "gdb/remote-sim.h" |
| 31 | |
| 32 | #include "sim-main.h" |
| 33 | #include "sim-options.h" |
| 34 | |
| 35 | #include "opcode/ft32.h" |
| 36 | |
| 37 | /* |
| 38 | * FT32 is a Harvard architecture: RAM and code occupy |
| 39 | * different address spaces. |
| 40 | * |
| 41 | * sim and gdb model FT32 memory by adding 0x800000 to RAM |
| 42 | * addresses. This means that sim/gdb can treat all addresses |
| 43 | * similarly. |
| 44 | * |
| 45 | * The address space looks like: |
| 46 | * |
| 47 | * 00000 start of code memory |
| 48 | * 3ffff end of code memory |
| 49 | * 800000 start of RAM |
| 50 | * 80ffff end of RAM |
| 51 | */ |
| 52 | |
| 53 | #define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */ |
| 54 | |
| 55 | static unsigned long |
| 56 | ft32_extract_unsigned_integer (unsigned char *addr, int len) |
| 57 | { |
| 58 | unsigned long retval; |
| 59 | unsigned char *p; |
| 60 | unsigned char *startaddr = (unsigned char *) addr; |
| 61 | unsigned char *endaddr = startaddr + len; |
| 62 | |
| 63 | /* Start at the most significant end of the integer, and work towards |
| 64 | the least significant. */ |
| 65 | retval = 0; |
| 66 | |
| 67 | for (p = endaddr; p > startaddr;) |
| 68 | retval = (retval << 8) | * -- p; |
| 69 | |
| 70 | return retval; |
| 71 | } |
| 72 | |
| 73 | static void |
| 74 | ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) |
| 75 | { |
| 76 | unsigned char *p; |
| 77 | unsigned char *startaddr = (unsigned char *)addr; |
| 78 | unsigned char *endaddr = startaddr + len; |
| 79 | |
| 80 | for (p = startaddr; p < endaddr; p++) |
| 81 | { |
| 82 | *p = val & 0xff; |
| 83 | val >>= 8; |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | /* |
| 88 | * Align EA according to its size DW. |
| 89 | * The FT32 ignores the low bit of a 16-bit addresss, |
| 90 | * and the low two bits of a 32-bit address. |
| 91 | */ |
| 92 | static uint32_t ft32_align (uint32_t dw, uint32_t ea) |
| 93 | { |
| 94 | switch (dw) |
| 95 | { |
| 96 | case 1: |
| 97 | ea &= ~1; |
| 98 | break; |
| 99 | case 2: |
| 100 | ea &= ~3; |
| 101 | break; |
| 102 | default: |
| 103 | break; |
| 104 | } |
| 105 | return ea; |
| 106 | } |
| 107 | |
| 108 | /* Read an item from memory address EA, sized DW. */ |
| 109 | static uint32_t |
| 110 | ft32_read_item (SIM_DESC sd, int dw, uint32_t ea) |
| 111 | { |
| 112 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 113 | address_word cia = CPU_PC_GET (cpu); |
| 114 | uint8_t byte[4]; |
| 115 | uint32_t r; |
| 116 | |
| 117 | ea = ft32_align (dw, ea); |
| 118 | |
| 119 | switch (dw) { |
| 120 | case 0: |
| 121 | return sim_core_read_aligned_1 (cpu, cia, read_map, ea); |
| 122 | case 1: |
| 123 | return sim_core_read_aligned_2 (cpu, cia, read_map, ea); |
| 124 | case 2: |
| 125 | return sim_core_read_aligned_4 (cpu, cia, read_map, ea); |
| 126 | default: |
| 127 | abort (); |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | /* Write item V to memory address EA, sized DW. */ |
| 132 | static void |
| 133 | ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v) |
| 134 | { |
| 135 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 136 | address_word cia = CPU_PC_GET (cpu); |
| 137 | uint8_t byte[4]; |
| 138 | |
| 139 | ea = ft32_align (dw, ea); |
| 140 | |
| 141 | switch (dw) { |
| 142 | case 0: |
| 143 | sim_core_write_aligned_1 (cpu, cia, write_map, ea, v); |
| 144 | break; |
| 145 | case 1: |
| 146 | sim_core_write_aligned_2 (cpu, cia, write_map, ea, v); |
| 147 | break; |
| 148 | case 2: |
| 149 | sim_core_write_aligned_4 (cpu, cia, write_map, ea, v); |
| 150 | break; |
| 151 | default: |
| 152 | abort (); |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | #define ILLEGAL() \ |
| 157 | sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL) |
| 158 | |
| 159 | static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea) |
| 160 | { |
| 161 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 162 | uint32_t insnpc = cpu->state.pc; |
| 163 | uint32_t r; |
| 164 | uint8_t byte[4]; |
| 165 | |
| 166 | ea &= 0x1ffff; |
| 167 | if (ea & ~0xffff) |
| 168 | { |
| 169 | /* Simulate some IO devices */ |
| 170 | switch (ea) |
| 171 | { |
| 172 | case 0x10000: |
| 173 | return getchar (); |
| 174 | case 0x1fff4: |
| 175 | /* Read the simulator cycle timer. */ |
| 176 | return cpu->state.cycles / 100; |
| 177 | default: |
| 178 | sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n", |
| 179 | ea, insnpc); |
| 180 | ILLEGAL (); |
| 181 | } |
| 182 | } |
| 183 | return ft32_read_item (sd, dw, RAM_BIAS + ea); |
| 184 | } |
| 185 | |
| 186 | static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d) |
| 187 | { |
| 188 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 189 | ea &= 0x1ffff; |
| 190 | if (ea & 0x10000) |
| 191 | { |
| 192 | /* Simulate some IO devices */ |
| 193 | switch (ea) |
| 194 | { |
| 195 | case 0x10000: |
| 196 | /* Console output */ |
| 197 | putchar (d & 0xff); |
| 198 | break; |
| 199 | case 0x1fc80: |
| 200 | /* Unlock the PM write port */ |
| 201 | cpu->state.pm_unlock = (d == 0x1337f7d1); |
| 202 | break; |
| 203 | case 0x1fc84: |
| 204 | /* Set the PM write address register */ |
| 205 | cpu->state.pm_addr = d; |
| 206 | break; |
| 207 | case 0x1fc88: |
| 208 | if (cpu->state.pm_unlock) |
| 209 | { |
| 210 | /* Write to PM. */ |
| 211 | ft32_write_item (sd, dw, cpu->state.pm_addr, d); |
| 212 | cpu->state.pm_addr += 4; |
| 213 | } |
| 214 | break; |
| 215 | case 0x1fffc: |
| 216 | /* Normal exit. */ |
| 217 | sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]); |
| 218 | break; |
| 219 | case 0x1fff8: |
| 220 | sim_io_printf (sd, "Debug write %08x\n", d); |
| 221 | break; |
| 222 | default: |
| 223 | sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea); |
| 224 | } |
| 225 | } |
| 226 | else |
| 227 | ft32_write_item (sd, dw, RAM_BIAS + ea, d); |
| 228 | } |
| 229 | |
| 230 | #define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea)) |
| 231 | #define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d)) |
| 232 | |
| 233 | /* LSBS (n) is a mask of the least significant N bits. */ |
| 234 | #define LSBS(n) ((1U << (n)) - 1) |
| 235 | |
| 236 | static void ft32_push (SIM_DESC sd, uint32_t v) |
| 237 | { |
| 238 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 239 | cpu->state.regs[FT32_HARD_SP] -= 4; |
| 240 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; |
| 241 | cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v); |
| 242 | } |
| 243 | |
| 244 | static uint32_t ft32_pop (SIM_DESC sd) |
| 245 | { |
| 246 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 247 | uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]); |
| 248 | cpu->state.regs[FT32_HARD_SP] += 4; |
| 249 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; |
| 250 | return r; |
| 251 | } |
| 252 | |
| 253 | /* Extract the low SIZ bits of N as an unsigned number. */ |
| 254 | static int nunsigned (int siz, int n) |
| 255 | { |
| 256 | return n & LSBS (siz); |
| 257 | } |
| 258 | |
| 259 | /* Extract the low SIZ bits of N as a signed number. */ |
| 260 | static int nsigned (int siz, int n) |
| 261 | { |
| 262 | int shift = (sizeof (int) * 8) - siz; |
| 263 | return (n << shift) >> shift; |
| 264 | } |
| 265 | |
| 266 | /* Signed division N / D, matching hw behavior for (MIN_INT, -1). */ |
| 267 | static uint32_t ft32sdiv (uint32_t n, uint32_t d) |
| 268 | { |
| 269 | if (n == 0x80000000UL && d == 0xffffffffUL) |
| 270 | return 0x80000000UL; |
| 271 | else |
| 272 | return (uint32_t)((int)n / (int)d); |
| 273 | } |
| 274 | |
| 275 | /* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */ |
| 276 | static uint32_t ft32smod (uint32_t n, uint32_t d) |
| 277 | { |
| 278 | if (n == 0x80000000UL && d == 0xffffffffUL) |
| 279 | return 0; |
| 280 | else |
| 281 | return (uint32_t)((int)n % (int)d); |
| 282 | } |
| 283 | |
| 284 | /* Circular rotate right N by B bits. */ |
| 285 | static uint32_t ror (uint32_t n, uint32_t b) |
| 286 | { |
| 287 | b &= 31; |
| 288 | return (n >> b) | (n << (32 - b)); |
| 289 | } |
| 290 | |
| 291 | /* Implement the BINS machine instruction. |
| 292 | See FT32 Programmer's Reference for details. */ |
| 293 | static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos) |
| 294 | { |
| 295 | uint32_t bitmask = LSBS (len) << pos; |
| 296 | return (d & ~bitmask) | ((f << pos) & bitmask); |
| 297 | } |
| 298 | |
| 299 | /* Implement the FLIP machine instruction. |
| 300 | See FT32 Programmer's Reference for details. */ |
| 301 | static uint32_t flip (uint32_t x, uint32_t b) |
| 302 | { |
| 303 | if (b & 1) |
| 304 | x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1; |
| 305 | if (b & 2) |
| 306 | x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2; |
| 307 | if (b & 4) |
| 308 | x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4; |
| 309 | if (b & 8) |
| 310 | x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8; |
| 311 | if (b & 16) |
| 312 | x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16; |
| 313 | return x; |
| 314 | } |
| 315 | |
| 316 | static void |
| 317 | step_once (SIM_DESC sd) |
| 318 | { |
| 319 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 320 | address_word cia = CPU_PC_GET (cpu); |
| 321 | uint32_t inst; |
| 322 | uint32_t dw; |
| 323 | uint32_t cb; |
| 324 | uint32_t r_d; |
| 325 | uint32_t cr; |
| 326 | uint32_t cv; |
| 327 | uint32_t bt; |
| 328 | uint32_t r_1; |
| 329 | uint32_t rimm; |
| 330 | uint32_t r_2; |
| 331 | uint32_t k20; |
| 332 | uint32_t pa; |
| 333 | uint32_t aa; |
| 334 | uint32_t k16; |
| 335 | uint32_t k15; |
| 336 | uint32_t al; |
| 337 | uint32_t r_1v; |
| 338 | uint32_t rimmv; |
| 339 | uint32_t bit_pos; |
| 340 | uint32_t bit_len; |
| 341 | uint32_t upper; |
| 342 | uint32_t insnpc; |
| 343 | |
| 344 | if (cpu->state.cycles >= cpu->state.next_tick_cycle) |
| 345 | { |
| 346 | cpu->state.next_tick_cycle += 100000; |
| 347 | ft32_push (sd, cpu->state.pc); |
| 348 | cpu->state.pc = 12; /* interrupt 1. */ |
| 349 | } |
| 350 | inst = ft32_read_item (sd, 2, cpu->state.pc); |
| 351 | cpu->state.cycles += 1; |
| 352 | |
| 353 | /* Handle "call 8" (which is FT32's "break" equivalent) here. */ |
| 354 | if (inst == 0x00340002) |
| 355 | { |
| 356 | sim_engine_halt (sd, cpu, NULL, |
| 357 | cpu->state.pc, |
| 358 | sim_stopped, SIM_SIGTRAP); |
| 359 | goto escape; |
| 360 | } |
| 361 | |
| 362 | dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ); |
| 363 | cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ); |
| 364 | r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ); |
| 365 | cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ); |
| 366 | cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ); |
| 367 | bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ); |
| 368 | r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ); |
| 369 | rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ); |
| 370 | r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ); |
| 371 | k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ)); |
| 372 | pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ); |
| 373 | aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ); |
| 374 | k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ); |
| 375 | k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ); |
| 376 | if (k15 & 0x80) |
| 377 | k15 ^= 0x7f00; |
| 378 | if (k15 & 0x4000) |
| 379 | k15 -= 0x8000; |
| 380 | al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ); |
| 381 | |
| 382 | r_1v = cpu->state.regs[r_1]; |
| 383 | rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f]; |
| 384 | |
| 385 | bit_pos = rimmv & 31; |
| 386 | bit_len = 0xf & (rimmv >> 5); |
| 387 | if (bit_len == 0) |
| 388 | bit_len = 16; |
| 389 | |
| 390 | upper = (inst >> 27); |
| 391 | |
| 392 | insnpc = cpu->state.pc; |
| 393 | cpu->state.pc += 4; |
| 394 | switch (upper) |
| 395 | { |
| 396 | case FT32_PAT_TOC: |
| 397 | case FT32_PAT_TOCI: |
| 398 | { |
| 399 | int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv); |
| 400 | if (take) |
| 401 | { |
| 402 | cpu->state.cycles += 1; |
| 403 | if (bt) |
| 404 | ft32_push (sd, cpu->state.pc); /* this is a call. */ |
| 405 | if (upper == FT32_PAT_TOC) |
| 406 | cpu->state.pc = pa << 2; |
| 407 | else |
| 408 | cpu->state.pc = cpu->state.regs[r_2]; |
| 409 | if (cpu->state.pc == 0x8) |
| 410 | goto escape; |
| 411 | } |
| 412 | } |
| 413 | break; |
| 414 | |
| 415 | case FT32_PAT_ALUOP: |
| 416 | case FT32_PAT_CMPOP: |
| 417 | { |
| 418 | uint32_t result; |
| 419 | switch (al) |
| 420 | { |
| 421 | case 0x0: result = r_1v + rimmv; break; |
| 422 | case 0x1: result = ror (r_1v, rimmv); break; |
| 423 | case 0x2: result = r_1v - rimmv; break; |
| 424 | case 0x3: result = (r_1v << 10) | (1023 & rimmv); break; |
| 425 | case 0x4: result = r_1v & rimmv; break; |
| 426 | case 0x5: result = r_1v | rimmv; break; |
| 427 | case 0x6: result = r_1v ^ rimmv; break; |
| 428 | case 0x7: result = ~(r_1v ^ rimmv); break; |
| 429 | case 0x8: result = r_1v << rimmv; break; |
| 430 | case 0x9: result = r_1v >> rimmv; break; |
| 431 | case 0xa: result = (int32_t)r_1v >> rimmv; break; |
| 432 | case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break; |
| 433 | case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break; |
| 434 | case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break; |
| 435 | case 0xe: result = flip (r_1v, rimmv); break; |
| 436 | default: |
| 437 | sim_io_eprintf (sd, "Unhandled alu %#x\n", al); |
| 438 | ILLEGAL (); |
| 439 | } |
| 440 | if (upper == FT32_PAT_ALUOP) |
| 441 | cpu->state.regs[r_d] = result; |
| 442 | else |
| 443 | { |
| 444 | uint32_t dwmask = 0; |
| 445 | int dwsiz = 0; |
| 446 | int zero; |
| 447 | int sign; |
| 448 | int ahi; |
| 449 | int bhi; |
| 450 | int overflow; |
| 451 | int carry; |
| 452 | int bit; |
| 453 | uint64_t ra; |
| 454 | uint64_t rb; |
| 455 | int above; |
| 456 | int greater; |
| 457 | int greatereq; |
| 458 | |
| 459 | switch (dw) |
| 460 | { |
| 461 | case 0: dwsiz = 7; dwmask = 0xffU; break; |
| 462 | case 1: dwsiz = 15; dwmask = 0xffffU; break; |
| 463 | case 2: dwsiz = 31; dwmask = 0xffffffffU; break; |
| 464 | } |
| 465 | |
| 466 | zero = (0 == (result & dwmask)); |
| 467 | sign = 1 & (result >> dwsiz); |
| 468 | ahi = 1 & (r_1v >> dwsiz); |
| 469 | bhi = 1 & (rimmv >> dwsiz); |
| 470 | overflow = (sign != ahi) & (ahi == !bhi); |
| 471 | bit = (dwsiz + 1); |
| 472 | ra = r_1v & dwmask; |
| 473 | rb = rimmv & dwmask; |
| 474 | switch (al) |
| 475 | { |
| 476 | case 0x0: carry = 1 & ((ra + rb) >> bit); break; |
| 477 | case 0x2: carry = 1 & ((ra - rb) >> bit); break; |
| 478 | default: carry = 0; break; |
| 479 | } |
| 480 | above = (!carry & !zero); |
| 481 | greater = (sign == overflow) & !zero; |
| 482 | greatereq = (sign == overflow); |
| 483 | |
| 484 | cpu->state.regs[r_d] = ( |
| 485 | (above << 6) | |
| 486 | (greater << 5) | |
| 487 | (greatereq << 4) | |
| 488 | (sign << 3) | |
| 489 | (overflow << 2) | |
| 490 | (carry << 1) | |
| 491 | (zero << 0)); |
| 492 | } |
| 493 | } |
| 494 | break; |
| 495 | |
| 496 | case FT32_PAT_LDK: |
| 497 | cpu->state.regs[r_d] = k20; |
| 498 | break; |
| 499 | |
| 500 | case FT32_PAT_LPM: |
| 501 | cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2); |
| 502 | cpu->state.cycles += 1; |
| 503 | break; |
| 504 | |
| 505 | case FT32_PAT_LPMI: |
| 506 | cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15); |
| 507 | cpu->state.cycles += 1; |
| 508 | break; |
| 509 | |
| 510 | case FT32_PAT_STA: |
| 511 | cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); |
| 512 | break; |
| 513 | |
| 514 | case FT32_PAT_STI: |
| 515 | cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]); |
| 516 | break; |
| 517 | |
| 518 | case FT32_PAT_LDA: |
| 519 | cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa); |
| 520 | cpu->state.cycles += 1; |
| 521 | break; |
| 522 | |
| 523 | case FT32_PAT_LDI: |
| 524 | cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); |
| 525 | cpu->state.cycles += 1; |
| 526 | break; |
| 527 | |
| 528 | case FT32_PAT_EXA: |
| 529 | { |
| 530 | uint32_t tmp; |
| 531 | tmp = cpu_mem_read (sd, dw, aa); |
| 532 | cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); |
| 533 | cpu->state.regs[r_d] = tmp; |
| 534 | cpu->state.cycles += 1; |
| 535 | } |
| 536 | break; |
| 537 | |
| 538 | case FT32_PAT_EXI: |
| 539 | { |
| 540 | uint32_t tmp; |
| 541 | tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); |
| 542 | cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]); |
| 543 | cpu->state.regs[r_d] = tmp; |
| 544 | cpu->state.cycles += 1; |
| 545 | } |
| 546 | break; |
| 547 | |
| 548 | case FT32_PAT_PUSH: |
| 549 | ft32_push (sd, r_1v); |
| 550 | break; |
| 551 | |
| 552 | case FT32_PAT_LINK: |
| 553 | ft32_push (sd, cpu->state.regs[r_d]); |
| 554 | cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP]; |
| 555 | cpu->state.regs[FT32_HARD_SP] -= k16; |
| 556 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; |
| 557 | break; |
| 558 | |
| 559 | case FT32_PAT_UNLINK: |
| 560 | cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d]; |
| 561 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; |
| 562 | cpu->state.regs[r_d] = ft32_pop (sd); |
| 563 | break; |
| 564 | |
| 565 | case FT32_PAT_POP: |
| 566 | cpu->state.cycles += 1; |
| 567 | cpu->state.regs[r_d] = ft32_pop (sd); |
| 568 | break; |
| 569 | |
| 570 | case FT32_PAT_RETURN: |
| 571 | cpu->state.pc = ft32_pop (sd); |
| 572 | break; |
| 573 | |
| 574 | case FT32_PAT_FFUOP: |
| 575 | switch (al) |
| 576 | { |
| 577 | case 0x0: |
| 578 | cpu->state.regs[r_d] = r_1v / rimmv; |
| 579 | break; |
| 580 | case 0x1: |
| 581 | cpu->state.regs[r_d] = r_1v % rimmv; |
| 582 | break; |
| 583 | case 0x2: |
| 584 | cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv); |
| 585 | break; |
| 586 | case 0x3: |
| 587 | cpu->state.regs[r_d] = ft32smod (r_1v, rimmv); |
| 588 | break; |
| 589 | |
| 590 | case 0x4: |
| 591 | { |
| 592 | /* strcmp instruction. */ |
| 593 | uint32_t a = r_1v; |
| 594 | uint32_t b = rimmv; |
| 595 | uint32_t i = 0; |
| 596 | while ((GET_BYTE (a + i) != 0) && |
| 597 | (GET_BYTE (a + i) == GET_BYTE (b + i))) |
| 598 | i++; |
| 599 | cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i); |
| 600 | } |
| 601 | break; |
| 602 | |
| 603 | case 0x5: |
| 604 | { |
| 605 | /* memcpy instruction. */ |
| 606 | uint32_t src = r_1v; |
| 607 | uint32_t dst = cpu->state.regs[r_d]; |
| 608 | uint32_t i; |
| 609 | for (i = 0; i < (rimmv & 0x7fff); i++) |
| 610 | PUT_BYTE (dst + i, GET_BYTE (src + i)); |
| 611 | } |
| 612 | break; |
| 613 | case 0x6: |
| 614 | { |
| 615 | /* strlen instruction. */ |
| 616 | uint32_t src = r_1v; |
| 617 | uint32_t i; |
| 618 | for (i = 0; GET_BYTE (src + i) != 0; i++) |
| 619 | ; |
| 620 | cpu->state.regs[r_d] = i; |
| 621 | } |
| 622 | break; |
| 623 | case 0x7: |
| 624 | { |
| 625 | /* memset instruction. */ |
| 626 | uint32_t dst = cpu->state.regs[r_d]; |
| 627 | uint32_t i; |
| 628 | for (i = 0; i < (rimmv & 0x7fff); i++) |
| 629 | PUT_BYTE (dst + i, r_1v); |
| 630 | } |
| 631 | break; |
| 632 | case 0x8: |
| 633 | cpu->state.regs[r_d] = r_1v * rimmv; |
| 634 | break; |
| 635 | case 0x9: |
| 636 | cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32; |
| 637 | break; |
| 638 | case 0xa: |
| 639 | { |
| 640 | /* stpcpy instruction. */ |
| 641 | uint32_t src = r_1v; |
| 642 | uint32_t dst = cpu->state.regs[r_d]; |
| 643 | uint32_t i; |
| 644 | for (i = 0; GET_BYTE (src + i) != 0; i++) |
| 645 | PUT_BYTE (dst + i, GET_BYTE (src + i)); |
| 646 | PUT_BYTE (dst + i, 0); |
| 647 | cpu->state.regs[r_d] = dst + i; |
| 648 | } |
| 649 | break; |
| 650 | case 0xe: |
| 651 | { |
| 652 | /* streamout instruction. */ |
| 653 | uint32_t i; |
| 654 | uint32_t src = cpu->state.regs[r_1]; |
| 655 | for (i = 0; i < rimmv; i += (1 << dw)) |
| 656 | { |
| 657 | cpu_mem_write (sd, |
| 658 | dw, |
| 659 | cpu->state.regs[r_d], |
| 660 | cpu_mem_read (sd, dw, src)); |
| 661 | src += (1 << dw); |
| 662 | } |
| 663 | } |
| 664 | break; |
| 665 | default: |
| 666 | sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc); |
| 667 | ILLEGAL (); |
| 668 | } |
| 669 | break; |
| 670 | |
| 671 | default: |
| 672 | sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc); |
| 673 | ILLEGAL (); |
| 674 | } |
| 675 | cpu->state.num_i++; |
| 676 | |
| 677 | escape: |
| 678 | ; |
| 679 | } |
| 680 | |
| 681 | void |
| 682 | sim_engine_run (SIM_DESC sd, |
| 683 | int next_cpu_nr, /* ignore */ |
| 684 | int nr_cpus, /* ignore */ |
| 685 | int siggnal) /* ignore */ |
| 686 | { |
| 687 | sim_cpu *cpu; |
| 688 | |
| 689 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
| 690 | |
| 691 | cpu = STATE_CPU (sd, 0); |
| 692 | |
| 693 | while (1) |
| 694 | { |
| 695 | step_once (sd); |
| 696 | if (sim_events_tick (sd)) |
| 697 | sim_events_process (sd); |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | static uint32_t * |
| 702 | ft32_lookup_register (SIM_CPU *cpu, int nr) |
| 703 | { |
| 704 | /* Handle the register number translation here. |
| 705 | * Sim registers are 0-31. |
| 706 | * Other tools (gcc, gdb) use: |
| 707 | * 0 - fp |
| 708 | * 1 - sp |
| 709 | * 2 - r0 |
| 710 | * 31 - cc |
| 711 | */ |
| 712 | |
| 713 | if ((nr < 0) || (nr > 32)) |
| 714 | { |
| 715 | sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr); |
| 716 | abort (); |
| 717 | } |
| 718 | |
| 719 | switch (nr) |
| 720 | { |
| 721 | case FT32_FP_REGNUM: |
| 722 | return &cpu->state.regs[FT32_HARD_FP]; |
| 723 | case FT32_SP_REGNUM: |
| 724 | return &cpu->state.regs[FT32_HARD_SP]; |
| 725 | case FT32_CC_REGNUM: |
| 726 | return &cpu->state.regs[FT32_HARD_CC]; |
| 727 | case FT32_PC_REGNUM: |
| 728 | return &cpu->state.pc; |
| 729 | default: |
| 730 | return &cpu->state.regs[nr - 2]; |
| 731 | } |
| 732 | } |
| 733 | |
| 734 | static int |
| 735 | ft32_reg_store (SIM_CPU *cpu, |
| 736 | int rn, |
| 737 | unsigned char *memory, |
| 738 | int length) |
| 739 | { |
| 740 | if (0 <= rn && rn <= 32) |
| 741 | { |
| 742 | if (length == 4) |
| 743 | *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4); |
| 744 | |
| 745 | return 4; |
| 746 | } |
| 747 | else |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | static int |
| 752 | ft32_reg_fetch (SIM_CPU *cpu, |
| 753 | int rn, |
| 754 | unsigned char *memory, |
| 755 | int length) |
| 756 | { |
| 757 | if (0 <= rn && rn <= 32) |
| 758 | { |
| 759 | if (length == 4) |
| 760 | ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn)); |
| 761 | |
| 762 | return 4; |
| 763 | } |
| 764 | else |
| 765 | return 0; |
| 766 | } |
| 767 | |
| 768 | static sim_cia |
| 769 | ft32_pc_get (SIM_CPU *cpu) |
| 770 | { |
| 771 | return cpu->state.pc; |
| 772 | } |
| 773 | |
| 774 | static void |
| 775 | ft32_pc_set (SIM_CPU *cpu, sim_cia newpc) |
| 776 | { |
| 777 | cpu->state.pc = newpc; |
| 778 | } |
| 779 | |
| 780 | /* Cover function of sim_state_free to free the cpu buffers as well. */ |
| 781 | |
| 782 | static void |
| 783 | free_state (SIM_DESC sd) |
| 784 | { |
| 785 | if (STATE_MODULES (sd) != NULL) |
| 786 | sim_module_uninstall (sd); |
| 787 | sim_cpu_free_all (sd); |
| 788 | sim_state_free (sd); |
| 789 | } |
| 790 | |
| 791 | SIM_DESC |
| 792 | sim_open (SIM_OPEN_KIND kind, |
| 793 | host_callback *cb, |
| 794 | struct bfd *abfd, |
| 795 | char * const *argv) |
| 796 | { |
| 797 | char c; |
| 798 | size_t i; |
| 799 | SIM_DESC sd = sim_state_alloc (kind, cb); |
| 800 | |
| 801 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
| 802 | if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) |
| 803 | { |
| 804 | free_state (sd); |
| 805 | return 0; |
| 806 | } |
| 807 | |
| 808 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
| 809 | { |
| 810 | free_state (sd); |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | /* The parser will print an error message for us, so we silently return. */ |
| 815 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
| 816 | { |
| 817 | free_state (sd); |
| 818 | return 0; |
| 819 | } |
| 820 | |
| 821 | /* Allocate external memory if none specified by user. |
| 822 | Use address 4 here in case the user wanted address 0 unmapped. */ |
| 823 | if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) |
| 824 | { |
| 825 | sim_do_command (sd, "memory region 0x00000000,0x40000"); |
| 826 | sim_do_command (sd, "memory region 0x800000,0x10000"); |
| 827 | } |
| 828 | |
| 829 | /* Check for/establish the reference program image. */ |
| 830 | if (sim_analyze_program (sd, |
| 831 | (STATE_PROG_ARGV (sd) != NULL |
| 832 | ? *STATE_PROG_ARGV (sd) |
| 833 | : NULL), abfd) != SIM_RC_OK) |
| 834 | { |
| 835 | free_state (sd); |
| 836 | return 0; |
| 837 | } |
| 838 | |
| 839 | /* Configure/verify the target byte order and other runtime |
| 840 | configuration options. */ |
| 841 | if (sim_config (sd) != SIM_RC_OK) |
| 842 | { |
| 843 | free_state (sd); |
| 844 | return 0; |
| 845 | } |
| 846 | |
| 847 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
| 848 | { |
| 849 | free_state (sd); |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | /* CPU specific initialization. */ |
| 854 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) |
| 855 | { |
| 856 | SIM_CPU *cpu = STATE_CPU (sd, i); |
| 857 | |
| 858 | CPU_REG_FETCH (cpu) = ft32_reg_fetch; |
| 859 | CPU_REG_STORE (cpu) = ft32_reg_store; |
| 860 | CPU_PC_FETCH (cpu) = ft32_pc_get; |
| 861 | CPU_PC_STORE (cpu) = ft32_pc_set; |
| 862 | } |
| 863 | |
| 864 | return sd; |
| 865 | } |
| 866 | |
| 867 | SIM_RC |
| 868 | sim_create_inferior (SIM_DESC sd, |
| 869 | struct bfd *abfd, |
| 870 | char * const *argv, |
| 871 | char * const *env) |
| 872 | { |
| 873 | uint32_t addr; |
| 874 | sim_cpu *cpu = STATE_CPU (sd, 0); |
| 875 | |
| 876 | /* Set the PC. */ |
| 877 | if (abfd != NULL) |
| 878 | addr = bfd_get_start_address (abfd); |
| 879 | else |
| 880 | addr = 0; |
| 881 | |
| 882 | /* Standalone mode (i.e. `run`) will take care of the argv for us in |
| 883 | sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim' |
| 884 | with `gdb`), we need to handle it because the user can change the |
| 885 | argv on the fly via gdb's 'run'. */ |
| 886 | if (STATE_PROG_ARGV (sd) != argv) |
| 887 | { |
| 888 | freeargv (STATE_PROG_ARGV (sd)); |
| 889 | STATE_PROG_ARGV (sd) = dupargv (argv); |
| 890 | } |
| 891 | cpu->state.regs[FT32_HARD_SP] = addr; |
| 892 | cpu->state.num_i = 0; |
| 893 | cpu->state.cycles = 0; |
| 894 | cpu->state.next_tick_cycle = 100000; |
| 895 | |
| 896 | return SIM_RC_OK; |
| 897 | } |