| 1 | // -*- C -*- |
| 2 | // |
| 3 | // In mips.igen, the semantics for many of the instructions were created |
| 4 | // using code generated by gencode. Those semantic segments could be |
| 5 | // greatly simplified. |
| 6 | // |
| 7 | // <insn> ::= |
| 8 | // <insn-word> { "+" <insn-word> } |
| 9 | // ":" <format-name> |
| 10 | // ":" <filter-flags> |
| 11 | // ":" <options> |
| 12 | // ":" <name> |
| 13 | // <nl> |
| 14 | // { <insn-model> } |
| 15 | // { <insn-mnemonic> } |
| 16 | // <code-block> |
| 17 | // |
| 18 | |
| 19 | |
| 20 | // IGEN config - mips16 |
| 21 | // :option:16::insn-bit-size:16 |
| 22 | // :option:16::hi-bit-nr:15 |
| 23 | :option:16::insn-specifying-widths:true |
| 24 | :option:16::gen-delayed-branch:false |
| 25 | |
| 26 | // IGEN config - mips32/64.. |
| 27 | // :option:32::insn-bit-size:32 |
| 28 | // :option:32::hi-bit-nr:31 |
| 29 | :option:32::insn-specifying-widths:true |
| 30 | :option:32::gen-delayed-branch:false |
| 31 | |
| 32 | |
| 33 | // Generate separate simulators for each target |
| 34 | // :option:::multi-sim:true |
| 35 | |
| 36 | |
| 37 | // Models known by this simulator |
| 38 | :model:::mipsI:mips3000: |
| 39 | :model:::mipsII:mips6000: |
| 40 | :model:::mipsIII:mips4000: |
| 41 | :model:::mipsIV:mips8000: |
| 42 | :model:::mips16:mips16: |
| 43 | :model:::r3900:mips3900: |
| 44 | :model:::vr4100:mips4100: |
| 45 | :model:::vr5000:mips5000: |
| 46 | |
| 47 | |
| 48 | |
| 49 | // Pseudo instructions known by IGEN |
| 50 | :internal::::illegal: |
| 51 | { |
| 52 | SignalException (ReservedInstruction, 0); |
| 53 | } |
| 54 | |
| 55 | |
| 56 | // Pseudo instructions known by interp.c |
| 57 | // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK |
| 58 | 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD |
| 59 | "rsvd <OP>" |
| 60 | { |
| 61 | SignalException (ReservedInstruction, instruction_0); |
| 62 | } |
| 63 | |
| 64 | |
| 65 | |
| 66 | // Helper: |
| 67 | // |
| 68 | // Simulate a 32 bit delayslot instruction |
| 69 | // |
| 70 | |
| 71 | :function:::address_word:delayslot32:address_word target |
| 72 | { |
| 73 | instruction_word delay_insn; |
| 74 | sim_events_slip (SD, 1); |
| 75 | DSPC = CIA; |
| 76 | CIA = CIA + 4; /* NOTE not mips16 */ |
| 77 | STATE |= simDELAYSLOT; |
| 78 | delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ |
| 79 | ENGINE_ISSUE_PREFIX_HOOK(); |
| 80 | idecode_issue (CPU_, delay_insn, (CIA)); |
| 81 | STATE &= ~simDELAYSLOT; |
| 82 | return target; |
| 83 | } |
| 84 | |
| 85 | :function:::address_word:nullify_next_insn32: |
| 86 | { |
| 87 | sim_events_slip (SD, 1); |
| 88 | dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); |
| 89 | return CIA + 8; |
| 90 | } |
| 91 | |
| 92 | // Helper: |
| 93 | // |
| 94 | // Check that an access to a HI/LO register meets timing requirements |
| 95 | // |
| 96 | // The following requirements exist: |
| 97 | // |
| 98 | // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read |
| 99 | // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read |
| 100 | // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update |
| 101 | // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}. |
| 102 | // |
| 103 | |
| 104 | :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new |
| 105 | { |
| 106 | if (history->mf.timestamp + 3 > time) |
| 107 | { |
| 108 | sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", |
| 109 | itable[MY_INDEX].name, |
| 110 | new, (long) CIA, |
| 111 | (long) history->mf.cia); |
| 112 | return 0; |
| 113 | } |
| 114 | return 1; |
| 115 | } |
| 116 | |
| 117 | :function:::int:check_mt_hilo:hilo_history *history |
| 118 | *mipsI,mipsII,mipsIII,mipsIV: |
| 119 | *vr4100: |
| 120 | *vr5000: |
| 121 | { |
| 122 | signed64 time = sim_events_time (SD); |
| 123 | int ok = check_mf_cycles (SD_, history, time, "MT"); |
| 124 | history->mt.timestamp = time; |
| 125 | history->mt.cia = CIA; |
| 126 | return ok; |
| 127 | } |
| 128 | |
| 129 | :function:::int:check_mt_hilo:hilo_history *history |
| 130 | *r3900: |
| 131 | { |
| 132 | signed64 time = sim_events_time (SD); |
| 133 | history->mt.timestamp = time; |
| 134 | history->mt.cia = CIA; |
| 135 | return 1; |
| 136 | } |
| 137 | |
| 138 | |
| 139 | :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer |
| 140 | *mipsI,mipsII,mipsIII,mipsIV: |
| 141 | *vr4100: |
| 142 | *vr5000: |
| 143 | *r3900: |
| 144 | { |
| 145 | signed64 time = sim_events_time (SD); |
| 146 | int ok = 1; |
| 147 | if (peer != NULL |
| 148 | && peer->mt.timestamp > history->op.timestamp |
| 149 | && history->mt.timestamp < history->op.timestamp |
| 150 | && ! (history->mf.timestamp > history->op.timestamp |
| 151 | && history->mf.timestamp < peer->mt.timestamp) |
| 152 | && ! (peer->mf.timestamp > history->op.timestamp |
| 153 | && peer->mf.timestamp < peer->mt.timestamp)) |
| 154 | { |
| 155 | /* The peer has been written to since the last OP yet we have |
| 156 | not */ |
| 157 | sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", |
| 158 | itable[MY_INDEX].name, |
| 159 | (long) CIA, |
| 160 | (long) history->op.cia, |
| 161 | (long) peer->mt.cia); |
| 162 | ok = 0; |
| 163 | } |
| 164 | history->mf.timestamp = time; |
| 165 | history->mf.cia = CIA; |
| 166 | return ok; |
| 167 | } |
| 168 | |
| 169 | |
| 170 | |
| 171 | :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo |
| 172 | *mipsI,mipsII,mipsIII,mipsIV: |
| 173 | *vr4100: |
| 174 | *vr5000: |
| 175 | { |
| 176 | signed64 time = sim_events_time (SD); |
| 177 | int ok = (check_mf_cycles (SD_, hi, time, "OP") |
| 178 | && check_mf_cycles (SD_, lo, time, "OP")); |
| 179 | hi->op.timestamp = time; |
| 180 | lo->op.timestamp = time; |
| 181 | hi->op.cia = CIA; |
| 182 | lo->op.cia = CIA; |
| 183 | return ok; |
| 184 | } |
| 185 | |
| 186 | // The r3900 mult and multu insns _can_ be exectuted immediatly after |
| 187 | // a mf{hi,lo} |
| 188 | :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo |
| 189 | *r3900: |
| 190 | { |
| 191 | /* FIXME: could record the fact that a stall occured if we want */ |
| 192 | signed64 time = sim_events_time (SD); |
| 193 | hi->op.timestamp = time; |
| 194 | lo->op.timestamp = time; |
| 195 | hi->op.cia = CIA; |
| 196 | lo->op.cia = CIA; |
| 197 | return 1; |
| 198 | } |
| 199 | |
| 200 | |
| 201 | :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo |
| 202 | *mipsI,mipsII,mipsIII,mipsIV: |
| 203 | *vr4100: |
| 204 | *vr5000: |
| 205 | *r3900: |
| 206 | { |
| 207 | signed64 time = sim_events_time (SD); |
| 208 | int ok = (check_mf_cycles (SD_, hi, time, "OP") |
| 209 | && check_mf_cycles (SD_, lo, time, "OP")); |
| 210 | hi->op.timestamp = time; |
| 211 | lo->op.timestamp = time; |
| 212 | hi->op.cia = CIA; |
| 213 | lo->op.cia = CIA; |
| 214 | return ok; |
| 215 | } |
| 216 | |
| 217 | |
| 218 | |
| 219 | |
| 220 | |
| 221 | // |
| 222 | // Mips Architecture: |
| 223 | // |
| 224 | // CPU Instruction Set (mipsI - mipsIV) |
| 225 | // |
| 226 | |
| 227 | |
| 228 | |
| 229 | 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD |
| 230 | "add r<RD>, r<RS>, r<RT>" |
| 231 | *mipsI,mipsII,mipsIII,mipsIV: |
| 232 | *vr4100: |
| 233 | *vr5000: |
| 234 | *r3900: |
| 235 | { |
| 236 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
| 237 | { |
| 238 | ALU32_BEGIN (GPR[RS]); |
| 239 | ALU32_ADD (GPR[RT]); |
| 240 | ALU32_END (GPR[RD]); |
| 241 | } |
| 242 | TRACE_ALU_RESULT (GPR[RD]); |
| 243 | } |
| 244 | |
| 245 | |
| 246 | |
| 247 | 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI |
| 248 | "addi r<RT>, r<RS>, IMMEDIATE" |
| 249 | *mipsI,mipsII,mipsIII,mipsIV: |
| 250 | *vr4100: |
| 251 | *vr5000: |
| 252 | *r3900: |
| 253 | { |
| 254 | TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); |
| 255 | { |
| 256 | ALU32_BEGIN (GPR[RS]); |
| 257 | ALU32_ADD (EXTEND16 (IMMEDIATE)); |
| 258 | ALU32_END (GPR[RT]); |
| 259 | } |
| 260 | TRACE_ALU_RESULT (GPR[RT]); |
| 261 | } |
| 262 | |
| 263 | |
| 264 | |
| 265 | :function:::void:do_addiu:int rs, int rt, unsigned16 immediate |
| 266 | { |
| 267 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| 268 | GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); |
| 269 | TRACE_ALU_RESULT (GPR[rt]); |
| 270 | } |
| 271 | |
| 272 | 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU |
| 273 | "addiu r<RT>, r<RS>, <IMMEDIATE>" |
| 274 | *mipsI,mipsII,mipsIII,mipsIV: |
| 275 | *vr4100: |
| 276 | *vr5000: |
| 277 | *r3900: |
| 278 | { |
| 279 | do_addiu (SD_, RS, RT, IMMEDIATE); |
| 280 | } |
| 281 | |
| 282 | |
| 283 | |
| 284 | :function:::void:do_addu:int rs, int rt, int rd |
| 285 | { |
| 286 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 287 | GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); |
| 288 | TRACE_ALU_RESULT (GPR[rd]); |
| 289 | } |
| 290 | |
| 291 | 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU |
| 292 | "addu r<RD>, r<RS>, r<RT>" |
| 293 | *mipsI,mipsII,mipsIII,mipsIV: |
| 294 | *vr4100: |
| 295 | *vr5000: |
| 296 | *r3900: |
| 297 | { |
| 298 | do_addu (SD_, RS, RT, RD); |
| 299 | } |
| 300 | |
| 301 | |
| 302 | |
| 303 | :function:::void:do_and:int rs, int rt, int rd |
| 304 | { |
| 305 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 306 | GPR[rd] = GPR[rs] & GPR[rt]; |
| 307 | TRACE_ALU_RESULT (GPR[rd]); |
| 308 | } |
| 309 | |
| 310 | 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND |
| 311 | "and r<RD>, r<RS>, r<RT>" |
| 312 | *mipsI,mipsII,mipsIII,mipsIV: |
| 313 | *vr4100: |
| 314 | *vr5000: |
| 315 | *r3900: |
| 316 | { |
| 317 | do_and (SD_, RS, RT, RD); |
| 318 | } |
| 319 | |
| 320 | |
| 321 | |
| 322 | 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI |
| 323 | "and r<RT>, r<RS>, <IMMEDIATE>" |
| 324 | *mipsI,mipsII,mipsIII,mipsIV: |
| 325 | *vr4100: |
| 326 | *vr5000: |
| 327 | *r3900: |
| 328 | { |
| 329 | TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); |
| 330 | GPR[RT] = GPR[RS] & IMMEDIATE; |
| 331 | TRACE_ALU_RESULT (GPR[RT]); |
| 332 | } |
| 333 | |
| 334 | |
| 335 | |
| 336 | 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ |
| 337 | "beq r<RS>, r<RT>, <OFFSET>" |
| 338 | *mipsI,mipsII,mipsIII,mipsIV: |
| 339 | *vr4100: |
| 340 | *vr5000: |
| 341 | *r3900: |
| 342 | { |
| 343 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 344 | check_branch_bug (); |
| 345 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
| 346 | { |
| 347 | mark_branch_bug (NIA+offset); |
| 348 | DELAY_SLOT (NIA + offset); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | |
| 353 | |
| 354 | 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL |
| 355 | "beql r<RS>, r<RT>, <OFFSET>" |
| 356 | *mipsII: |
| 357 | *mipsIII: |
| 358 | *mipsIV: |
| 359 | *vr4100: |
| 360 | *vr5000: |
| 361 | *r3900: |
| 362 | { |
| 363 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 364 | check_branch_bug (); |
| 365 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
| 366 | { |
| 367 | mark_branch_bug (NIA+offset); |
| 368 | DELAY_SLOT (NIA + offset); |
| 369 | } |
| 370 | else |
| 371 | NULLIFY_NEXT_INSTRUCTION (); |
| 372 | } |
| 373 | |
| 374 | |
| 375 | |
| 376 | 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ |
| 377 | "bgez r<RS>, <OFFSET>" |
| 378 | *mipsI,mipsII,mipsIII,mipsIV: |
| 379 | *vr4100: |
| 380 | *vr5000: |
| 381 | *r3900: |
| 382 | { |
| 383 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 384 | check_branch_bug (); |
| 385 | if ((signed_word) GPR[RS] >= 0) |
| 386 | { |
| 387 | mark_branch_bug (NIA+offset); |
| 388 | DELAY_SLOT (NIA + offset); |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | |
| 393 | |
| 394 | 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL |
| 395 | "bgezal r<RS>, <OFFSET>" |
| 396 | *mipsI,mipsII,mipsIII,mipsIV: |
| 397 | *vr4100: |
| 398 | *vr5000: |
| 399 | *r3900: |
| 400 | { |
| 401 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 402 | check_branch_bug (); |
| 403 | RA = (CIA + 8); |
| 404 | if ((signed_word) GPR[RS] >= 0) |
| 405 | { |
| 406 | mark_branch_bug (NIA+offset); |
| 407 | DELAY_SLOT (NIA + offset); |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | |
| 412 | |
| 413 | 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL |
| 414 | "bgezall r<RS>, <OFFSET>" |
| 415 | *mipsII: |
| 416 | *mipsIII: |
| 417 | *mipsIV: |
| 418 | *vr4100: |
| 419 | *vr5000: |
| 420 | *r3900: |
| 421 | { |
| 422 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 423 | check_branch_bug (); |
| 424 | RA = (CIA + 8); |
| 425 | /* NOTE: The branch occurs AFTER the next instruction has been |
| 426 | executed */ |
| 427 | if ((signed_word) GPR[RS] >= 0) |
| 428 | { |
| 429 | mark_branch_bug (NIA+offset); |
| 430 | DELAY_SLOT (NIA + offset); |
| 431 | } |
| 432 | else |
| 433 | NULLIFY_NEXT_INSTRUCTION (); |
| 434 | } |
| 435 | |
| 436 | |
| 437 | |
| 438 | 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL |
| 439 | "bgezl r<RS>, <OFFSET>" |
| 440 | *mipsII: |
| 441 | *mipsIII: |
| 442 | *mipsIV: |
| 443 | *vr4100: |
| 444 | *vr5000: |
| 445 | *r3900: |
| 446 | { |
| 447 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 448 | check_branch_bug (); |
| 449 | if ((signed_word) GPR[RS] >= 0) |
| 450 | { |
| 451 | mark_branch_bug (NIA+offset); |
| 452 | DELAY_SLOT (NIA + offset); |
| 453 | } |
| 454 | else |
| 455 | NULLIFY_NEXT_INSTRUCTION (); |
| 456 | } |
| 457 | |
| 458 | |
| 459 | |
| 460 | 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ |
| 461 | "bgtz r<RS>, <OFFSET>" |
| 462 | *mipsI,mipsII,mipsIII,mipsIV: |
| 463 | *vr4100: |
| 464 | *vr5000: |
| 465 | *r3900: |
| 466 | { |
| 467 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 468 | check_branch_bug (); |
| 469 | if ((signed_word) GPR[RS] > 0) |
| 470 | { |
| 471 | mark_branch_bug (NIA+offset); |
| 472 | DELAY_SLOT (NIA + offset); |
| 473 | } |
| 474 | } |
| 475 | |
| 476 | |
| 477 | |
| 478 | 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL |
| 479 | "bgtzl r<RS>, <OFFSET>" |
| 480 | *mipsII: |
| 481 | *mipsIII: |
| 482 | *mipsIV: |
| 483 | *vr4100: |
| 484 | *vr5000: |
| 485 | *r3900: |
| 486 | { |
| 487 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 488 | check_branch_bug (); |
| 489 | /* NOTE: The branch occurs AFTER the next instruction has been |
| 490 | executed */ |
| 491 | if ((signed_word) GPR[RS] > 0) |
| 492 | { |
| 493 | mark_branch_bug (NIA+offset); |
| 494 | DELAY_SLOT (NIA + offset); |
| 495 | } |
| 496 | else |
| 497 | NULLIFY_NEXT_INSTRUCTION (); |
| 498 | } |
| 499 | |
| 500 | |
| 501 | |
| 502 | 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ |
| 503 | "blez r<RS>, <OFFSET>" |
| 504 | *mipsI,mipsII,mipsIII,mipsIV: |
| 505 | *vr4100: |
| 506 | *vr5000: |
| 507 | *r3900: |
| 508 | { |
| 509 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 510 | check_branch_bug (); |
| 511 | /* NOTE: The branch occurs AFTER the next instruction has been |
| 512 | executed */ |
| 513 | if ((signed_word) GPR[RS] <= 0) |
| 514 | { |
| 515 | mark_branch_bug (NIA+offset); |
| 516 | DELAY_SLOT (NIA + offset); |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | |
| 521 | |
| 522 | 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL |
| 523 | "bgezl r<RS>, <OFFSET>" |
| 524 | *mipsII: |
| 525 | *mipsIII: |
| 526 | *mipsIV: |
| 527 | *vr4100: |
| 528 | *vr5000: |
| 529 | *r3900: |
| 530 | { |
| 531 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 532 | check_branch_bug (); |
| 533 | if ((signed_word) GPR[RS] <= 0) |
| 534 | { |
| 535 | mark_branch_bug (NIA+offset); |
| 536 | DELAY_SLOT (NIA + offset); |
| 537 | } |
| 538 | else |
| 539 | NULLIFY_NEXT_INSTRUCTION (); |
| 540 | } |
| 541 | |
| 542 | |
| 543 | |
| 544 | 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ |
| 545 | "bltz r<RS>, <OFFSET>" |
| 546 | *mipsI,mipsII,mipsIII,mipsIV: |
| 547 | *vr4100: |
| 548 | *vr5000: |
| 549 | *r3900: |
| 550 | { |
| 551 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 552 | check_branch_bug (); |
| 553 | if ((signed_word) GPR[RS] < 0) |
| 554 | { |
| 555 | mark_branch_bug (NIA+offset); |
| 556 | DELAY_SLOT (NIA + offset); |
| 557 | } |
| 558 | } |
| 559 | |
| 560 | |
| 561 | |
| 562 | 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL |
| 563 | "bltzal r<RS>, <OFFSET>" |
| 564 | *mipsI,mipsII,mipsIII,mipsIV: |
| 565 | *vr4100: |
| 566 | *vr5000: |
| 567 | *r3900: |
| 568 | { |
| 569 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 570 | check_branch_bug (); |
| 571 | RA = (CIA + 8); |
| 572 | /* NOTE: The branch occurs AFTER the next instruction has been |
| 573 | executed */ |
| 574 | if ((signed_word) GPR[RS] < 0) |
| 575 | { |
| 576 | mark_branch_bug (NIA+offset); |
| 577 | DELAY_SLOT (NIA + offset); |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | |
| 582 | |
| 583 | 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL |
| 584 | "bltzall r<RS>, <OFFSET>" |
| 585 | *mipsII: |
| 586 | *mipsIII: |
| 587 | *mipsIV: |
| 588 | *vr4100: |
| 589 | *vr5000: |
| 590 | *r3900: |
| 591 | { |
| 592 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 593 | check_branch_bug (); |
| 594 | RA = (CIA + 8); |
| 595 | if ((signed_word) GPR[RS] < 0) |
| 596 | { |
| 597 | mark_branch_bug (NIA+offset); |
| 598 | DELAY_SLOT (NIA + offset); |
| 599 | } |
| 600 | else |
| 601 | NULLIFY_NEXT_INSTRUCTION (); |
| 602 | } |
| 603 | |
| 604 | |
| 605 | |
| 606 | 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL |
| 607 | "bltzl r<RS>, <OFFSET>" |
| 608 | *mipsII: |
| 609 | *mipsIII: |
| 610 | *mipsIV: |
| 611 | *vr4100: |
| 612 | *vr5000: |
| 613 | *r3900: |
| 614 | { |
| 615 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 616 | check_branch_bug (); |
| 617 | /* NOTE: The branch occurs AFTER the next instruction has been |
| 618 | executed */ |
| 619 | if ((signed_word) GPR[RS] < 0) |
| 620 | { |
| 621 | mark_branch_bug (NIA+offset); |
| 622 | DELAY_SLOT (NIA + offset); |
| 623 | } |
| 624 | else |
| 625 | NULLIFY_NEXT_INSTRUCTION (); |
| 626 | } |
| 627 | |
| 628 | |
| 629 | |
| 630 | 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE |
| 631 | "bne r<RS>, r<RT>, <OFFSET>" |
| 632 | *mipsI,mipsII,mipsIII,mipsIV: |
| 633 | *vr4100: |
| 634 | *vr5000: |
| 635 | *r3900: |
| 636 | { |
| 637 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 638 | check_branch_bug (); |
| 639 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
| 640 | { |
| 641 | mark_branch_bug (NIA+offset); |
| 642 | DELAY_SLOT (NIA + offset); |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | |
| 647 | |
| 648 | 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL |
| 649 | "bnel r<RS>, r<RT>, <OFFSET>" |
| 650 | *mipsII: |
| 651 | *mipsIII: |
| 652 | *mipsIV: |
| 653 | *vr4100: |
| 654 | *vr5000: |
| 655 | *r3900: |
| 656 | { |
| 657 | address_word offset = EXTEND16 (OFFSET) << 2; |
| 658 | check_branch_bug (); |
| 659 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
| 660 | { |
| 661 | mark_branch_bug (NIA+offset); |
| 662 | DELAY_SLOT (NIA + offset); |
| 663 | } |
| 664 | else |
| 665 | NULLIFY_NEXT_INSTRUCTION (); |
| 666 | } |
| 667 | |
| 668 | |
| 669 | |
| 670 | 000000,20.CODE,001101:SPECIAL:32::BREAK |
| 671 | "break" |
| 672 | *mipsI,mipsII,mipsIII,mipsIV: |
| 673 | *vr4100: |
| 674 | *vr5000: |
| 675 | *r3900: |
| 676 | { |
| 677 | /* Check for some break instruction which are reserved for use by the simulator. */ |
| 678 | unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; |
| 679 | if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || |
| 680 | break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) |
| 681 | { |
| 682 | sim_engine_halt (SD, CPU, NULL, cia, |
| 683 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
| 684 | } |
| 685 | else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || |
| 686 | break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) |
| 687 | { |
| 688 | if (STATE & simDELAYSLOT) |
| 689 | PC = cia - 4; /* reference the branch instruction */ |
| 690 | else |
| 691 | PC = cia; |
| 692 | SignalException(BreakPoint, instruction_0); |
| 693 | } |
| 694 | |
| 695 | else |
| 696 | { |
| 697 | /* If we get this far, we're not an instruction reserved by the sim. Raise |
| 698 | the exception. */ |
| 699 | SignalException(BreakPoint, instruction_0); |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | |
| 704 | |
| 705 | 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD |
| 706 | "dadd r<RD>, r<RS>, r<RT>" |
| 707 | *mipsIII: |
| 708 | *mipsIV: |
| 709 | *vr4100: |
| 710 | *vr5000: |
| 711 | { |
| 712 | /* this check's for overflow */ |
| 713 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
| 714 | { |
| 715 | ALU64_BEGIN (GPR[RS]); |
| 716 | ALU64_ADD (GPR[RT]); |
| 717 | ALU64_END (GPR[RD]); |
| 718 | } |
| 719 | TRACE_ALU_RESULT (GPR[RD]); |
| 720 | } |
| 721 | |
| 722 | |
| 723 | |
| 724 | 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI |
| 725 | "daddi r<RT>, r<RS>, <IMMEDIATE>" |
| 726 | *mipsIII: |
| 727 | *mipsIV: |
| 728 | *vr4100: |
| 729 | *vr5000: |
| 730 | { |
| 731 | TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); |
| 732 | { |
| 733 | ALU64_BEGIN (GPR[RS]); |
| 734 | ALU64_ADD (EXTEND16 (IMMEDIATE)); |
| 735 | ALU64_END (GPR[RT]); |
| 736 | } |
| 737 | TRACE_ALU_RESULT (GPR[RT]); |
| 738 | } |
| 739 | |
| 740 | |
| 741 | |
| 742 | :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate |
| 743 | { |
| 744 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| 745 | GPR[rt] = GPR[rs] + EXTEND16 (immediate); |
| 746 | TRACE_ALU_RESULT (GPR[rt]); |
| 747 | } |
| 748 | |
| 749 | 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU |
| 750 | "daddu r<RT>, r<RS>, <IMMEDIATE>" |
| 751 | *mipsIII: |
| 752 | *mipsIV: |
| 753 | *vr4100: |
| 754 | *vr5000: |
| 755 | { |
| 756 | do_daddiu (SD_, RS, RT, IMMEDIATE); |
| 757 | } |
| 758 | |
| 759 | |
| 760 | |
| 761 | :function:::void:do_daddu:int rs, int rt, int rd |
| 762 | { |
| 763 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 764 | GPR[rd] = GPR[rs] + GPR[rt]; |
| 765 | TRACE_ALU_RESULT (GPR[rd]); |
| 766 | } |
| 767 | |
| 768 | 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU |
| 769 | "daddu r<RD>, r<RS>, r<RT>" |
| 770 | *mipsIII: |
| 771 | *mipsIV: |
| 772 | *vr4100: |
| 773 | *vr5000: |
| 774 | { |
| 775 | do_daddu (SD_, RS, RT, RD); |
| 776 | } |
| 777 | |
| 778 | |
| 779 | |
| 780 | :function:::void:do_ddiv:int rs, int rt |
| 781 | { |
| 782 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| 783 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 784 | { |
| 785 | signed64 n = GPR[rs]; |
| 786 | signed64 d = GPR[rt]; |
| 787 | signed64 hi; |
| 788 | signed64 lo; |
| 789 | if (d == 0) |
| 790 | { |
| 791 | lo = SIGNED64 (0x8000000000000000); |
| 792 | hi = 0; |
| 793 | } |
| 794 | else if (d == -1 && n == SIGNED64 (0x8000000000000000)) |
| 795 | { |
| 796 | lo = SIGNED64 (0x8000000000000000); |
| 797 | hi = 0; |
| 798 | } |
| 799 | else |
| 800 | { |
| 801 | lo = (n / d); |
| 802 | hi = (n % d); |
| 803 | } |
| 804 | HI = hi; |
| 805 | LO = lo; |
| 806 | } |
| 807 | TRACE_ALU_RESULT2 (HI, LO); |
| 808 | } |
| 809 | |
| 810 | 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV |
| 811 | "ddiv r<RS>, r<RT>" |
| 812 | *mipsIII: |
| 813 | *mipsIV: |
| 814 | *vr4100: |
| 815 | *vr5000: |
| 816 | { |
| 817 | do_ddiv (SD_, RS, RT); |
| 818 | } |
| 819 | |
| 820 | |
| 821 | |
| 822 | :function:::void:do_ddivu:int rs, int rt |
| 823 | { |
| 824 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| 825 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 826 | { |
| 827 | unsigned64 n = GPR[rs]; |
| 828 | unsigned64 d = GPR[rt]; |
| 829 | unsigned64 hi; |
| 830 | unsigned64 lo; |
| 831 | if (d == 0) |
| 832 | { |
| 833 | lo = SIGNED64 (0x8000000000000000); |
| 834 | hi = 0; |
| 835 | } |
| 836 | else |
| 837 | { |
| 838 | lo = (n / d); |
| 839 | hi = (n % d); |
| 840 | } |
| 841 | HI = hi; |
| 842 | LO = lo; |
| 843 | } |
| 844 | TRACE_ALU_RESULT2 (HI, LO); |
| 845 | } |
| 846 | |
| 847 | 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU |
| 848 | "ddivu r<RS>, r<RT>" |
| 849 | *mipsIII: |
| 850 | *mipsIV: |
| 851 | *vr4100: |
| 852 | *vr5000: |
| 853 | { |
| 854 | do_ddivu (SD_, RS, RT); |
| 855 | } |
| 856 | |
| 857 | |
| 858 | |
| 859 | :function:::void:do_div:int rs, int rt |
| 860 | { |
| 861 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| 862 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 863 | { |
| 864 | signed32 n = GPR[rs]; |
| 865 | signed32 d = GPR[rt]; |
| 866 | if (d == 0) |
| 867 | { |
| 868 | LO = EXTEND32 (0x80000000); |
| 869 | HI = EXTEND32 (0); |
| 870 | } |
| 871 | else if (n == SIGNED32 (0x80000000) && d == -1) |
| 872 | { |
| 873 | LO = EXTEND32 (0x80000000); |
| 874 | HI = EXTEND32 (0); |
| 875 | } |
| 876 | else |
| 877 | { |
| 878 | LO = EXTEND32 (n / d); |
| 879 | HI = EXTEND32 (n % d); |
| 880 | } |
| 881 | } |
| 882 | TRACE_ALU_RESULT2 (HI, LO); |
| 883 | } |
| 884 | |
| 885 | 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV |
| 886 | "div r<RS>, r<RT>" |
| 887 | *mipsI,mipsII,mipsIII,mipsIV: |
| 888 | *vr4100: |
| 889 | *vr5000: |
| 890 | *r3900: |
| 891 | { |
| 892 | do_div (SD_, RS, RT); |
| 893 | } |
| 894 | |
| 895 | |
| 896 | |
| 897 | :function:::void:do_divu:int rs, int rt |
| 898 | { |
| 899 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); |
| 900 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 901 | { |
| 902 | unsigned32 n = GPR[rs]; |
| 903 | unsigned32 d = GPR[rt]; |
| 904 | if (d == 0) |
| 905 | { |
| 906 | LO = EXTEND32 (0x80000000); |
| 907 | HI = EXTEND32 (0); |
| 908 | } |
| 909 | else |
| 910 | { |
| 911 | LO = EXTEND32 (n / d); |
| 912 | HI = EXTEND32 (n % d); |
| 913 | } |
| 914 | } |
| 915 | TRACE_ALU_RESULT2 (HI, LO); |
| 916 | } |
| 917 | |
| 918 | 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU |
| 919 | "divu r<RS>, r<RT>" |
| 920 | *mipsI,mipsII,mipsIII,mipsIV: |
| 921 | *vr4100: |
| 922 | *vr5000: |
| 923 | *r3900: |
| 924 | { |
| 925 | do_divu (SD_, RS, RT); |
| 926 | } |
| 927 | |
| 928 | |
| 929 | |
| 930 | :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p |
| 931 | { |
| 932 | unsigned64 lo; |
| 933 | unsigned64 hi; |
| 934 | unsigned64 m00; |
| 935 | unsigned64 m01; |
| 936 | unsigned64 m10; |
| 937 | unsigned64 m11; |
| 938 | unsigned64 mid; |
| 939 | int sign; |
| 940 | unsigned64 op1 = GPR[rs]; |
| 941 | unsigned64 op2 = GPR[rt]; |
| 942 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| 943 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 944 | /* make signed multiply unsigned */ |
| 945 | sign = 0; |
| 946 | if (signed_p) |
| 947 | { |
| 948 | if (op1 < 0) |
| 949 | { |
| 950 | op1 = - op1; |
| 951 | ++sign; |
| 952 | } |
| 953 | if (op2 < 0) |
| 954 | { |
| 955 | op2 = - op2; |
| 956 | ++sign; |
| 957 | } |
| 958 | } |
| 959 | /* multuply out the 4 sub products */ |
| 960 | m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); |
| 961 | m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); |
| 962 | m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); |
| 963 | m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); |
| 964 | /* add the products */ |
| 965 | mid = ((unsigned64) VH4_8 (m00) |
| 966 | + (unsigned64) VL4_8 (m10) |
| 967 | + (unsigned64) VL4_8 (m01)); |
| 968 | lo = U8_4 (mid, m00); |
| 969 | hi = (m11 |
| 970 | + (unsigned64) VH4_8 (mid) |
| 971 | + (unsigned64) VH4_8 (m01) |
| 972 | + (unsigned64) VH4_8 (m10)); |
| 973 | /* fix the sign */ |
| 974 | if (sign & 1) |
| 975 | { |
| 976 | lo = -lo; |
| 977 | if (lo == 0) |
| 978 | hi = -hi; |
| 979 | else |
| 980 | hi = -hi - 1; |
| 981 | } |
| 982 | /* save the result HI/LO (and a gpr) */ |
| 983 | LO = lo; |
| 984 | HI = hi; |
| 985 | if (rd != 0) |
| 986 | GPR[rd] = lo; |
| 987 | TRACE_ALU_RESULT2 (HI, LO); |
| 988 | } |
| 989 | |
| 990 | :function:::void:do_dmult:int rs, int rt, int rd |
| 991 | { |
| 992 | do_dmultx (SD_, rs, rt, rd, 1); |
| 993 | } |
| 994 | |
| 995 | 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT |
| 996 | "dmult r<RS>, r<RT>" |
| 997 | *mipsIII,mipsIV: |
| 998 | *vr4100: |
| 999 | { |
| 1000 | do_dmult (SD_, RS, RT, 0); |
| 1001 | } |
| 1002 | |
| 1003 | 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT |
| 1004 | "dmult r<RS>, r<RT>":RD == 0 |
| 1005 | "dmult r<RD>, r<RS>, r<RT>" |
| 1006 | *vr5000: |
| 1007 | { |
| 1008 | do_dmult (SD_, RS, RT, RD); |
| 1009 | } |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | :function:::void:do_dmultu:int rs, int rt, int rd |
| 1014 | { |
| 1015 | do_dmultx (SD_, rs, rt, rd, 0); |
| 1016 | } |
| 1017 | |
| 1018 | 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU |
| 1019 | "dmultu r<RS>, r<RT>" |
| 1020 | *mipsIII,mipsIV: |
| 1021 | *vr4100: |
| 1022 | { |
| 1023 | do_dmultu (SD_, RS, RT, 0); |
| 1024 | } |
| 1025 | |
| 1026 | 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU |
| 1027 | "dmultu r<RD>, r<RS>, r<RT>":RD == 0 |
| 1028 | "dmultu r<RS>, r<RT>" |
| 1029 | *vr5000: |
| 1030 | { |
| 1031 | do_dmultu (SD_, RS, RT, RD); |
| 1032 | } |
| 1033 | |
| 1034 | :function:::void:do_dsll:int rt, int rd, int shift |
| 1035 | { |
| 1036 | GPR[rd] = GPR[rt] << shift; |
| 1037 | } |
| 1038 | |
| 1039 | :function:::void:do_dsllv:int rs, int rt, int rd |
| 1040 | { |
| 1041 | int s = MASKED64 (GPR[rs], 5, 0); |
| 1042 | GPR[rd] = GPR[rt] << s; |
| 1043 | } |
| 1044 | |
| 1045 | |
| 1046 | 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL |
| 1047 | "dsll r<RD>, r<RT>, <SHIFT>" |
| 1048 | *mipsIII: |
| 1049 | *mipsIV: |
| 1050 | *vr4100: |
| 1051 | *vr5000: |
| 1052 | { |
| 1053 | do_dsll (SD_, RT, RD, SHIFT); |
| 1054 | } |
| 1055 | |
| 1056 | |
| 1057 | 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 |
| 1058 | "dsll32 r<RD>, r<RT>, <SHIFT>" |
| 1059 | *mipsIII: |
| 1060 | *mipsIV: |
| 1061 | *vr4100: |
| 1062 | *vr5000: |
| 1063 | { |
| 1064 | int s = 32 + SHIFT; |
| 1065 | GPR[RD] = GPR[RT] << s; |
| 1066 | } |
| 1067 | |
| 1068 | 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV |
| 1069 | "dsllv r<RD>, r<RT>, r<RS>" |
| 1070 | *mipsIII: |
| 1071 | *mipsIV: |
| 1072 | *vr4100: |
| 1073 | *vr5000: |
| 1074 | { |
| 1075 | do_dsllv (SD_, RS, RT, RD); |
| 1076 | } |
| 1077 | |
| 1078 | :function:::void:do_dsra:int rt, int rd, int shift |
| 1079 | { |
| 1080 | GPR[rd] = ((signed64) GPR[rt]) >> shift; |
| 1081 | } |
| 1082 | |
| 1083 | |
| 1084 | 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA |
| 1085 | "dsra r<RD>, r<RT>, <SHIFT>" |
| 1086 | *mipsIII: |
| 1087 | *mipsIV: |
| 1088 | *vr4100: |
| 1089 | *vr5000: |
| 1090 | { |
| 1091 | do_dsra (SD_, RT, RD, SHIFT); |
| 1092 | } |
| 1093 | |
| 1094 | |
| 1095 | 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 |
| 1096 | "dsra32 r<RT>, r<RD>, <SHIFT>" |
| 1097 | *mipsIII: |
| 1098 | *mipsIV: |
| 1099 | *vr4100: |
| 1100 | *vr5000: |
| 1101 | { |
| 1102 | int s = 32 + SHIFT; |
| 1103 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
| 1104 | } |
| 1105 | |
| 1106 | |
| 1107 | :function:::void:do_dsrav:int rs, int rt, int rd |
| 1108 | { |
| 1109 | int s = MASKED64 (GPR[rs], 5, 0); |
| 1110 | TRACE_ALU_INPUT2 (GPR[rt], s); |
| 1111 | GPR[rd] = ((signed64) GPR[rt]) >> s; |
| 1112 | TRACE_ALU_RESULT (GPR[rd]); |
| 1113 | } |
| 1114 | |
| 1115 | 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV |
| 1116 | "dsra32 r<RT>, r<RD>, r<RS>" |
| 1117 | *mipsIII: |
| 1118 | *mipsIV: |
| 1119 | *vr4100: |
| 1120 | *vr5000: |
| 1121 | { |
| 1122 | do_dsrav (SD_, RS, RT, RD); |
| 1123 | } |
| 1124 | |
| 1125 | :function:::void:do_dsrl:int rt, int rd, int shift |
| 1126 | { |
| 1127 | GPR[rd] = (unsigned64) GPR[rt] >> shift; |
| 1128 | } |
| 1129 | |
| 1130 | |
| 1131 | 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL |
| 1132 | "dsrl r<RD>, r<RT>, <SHIFT>" |
| 1133 | *mipsIII: |
| 1134 | *mipsIV: |
| 1135 | *vr4100: |
| 1136 | *vr5000: |
| 1137 | { |
| 1138 | do_dsrl (SD_, RT, RD, SHIFT); |
| 1139 | } |
| 1140 | |
| 1141 | |
| 1142 | 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 |
| 1143 | "dsrl32 r<RD>, r<RT>, <SHIFT>" |
| 1144 | *mipsIII: |
| 1145 | *mipsIV: |
| 1146 | *vr4100: |
| 1147 | *vr5000: |
| 1148 | { |
| 1149 | int s = 32 + SHIFT; |
| 1150 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
| 1151 | } |
| 1152 | |
| 1153 | |
| 1154 | :function:::void:do_dsrlv:int rs, int rt, int rd |
| 1155 | { |
| 1156 | int s = MASKED64 (GPR[rs], 5, 0); |
| 1157 | GPR[rd] = (unsigned64) GPR[rt] >> s; |
| 1158 | } |
| 1159 | |
| 1160 | |
| 1161 | |
| 1162 | 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV |
| 1163 | "dsrl32 r<RD>, r<RT>, r<RS>" |
| 1164 | *mipsIII: |
| 1165 | *mipsIV: |
| 1166 | *vr4100: |
| 1167 | *vr5000: |
| 1168 | { |
| 1169 | do_dsrlv (SD_, RS, RT, RD); |
| 1170 | } |
| 1171 | |
| 1172 | |
| 1173 | 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB |
| 1174 | "dsub r<RD>, r<RS>, r<RT>" |
| 1175 | *mipsIII: |
| 1176 | *mipsIV: |
| 1177 | *vr4100: |
| 1178 | *vr5000: |
| 1179 | { |
| 1180 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
| 1181 | { |
| 1182 | ALU64_BEGIN (GPR[RS]); |
| 1183 | ALU64_SUB (GPR[RT]); |
| 1184 | ALU64_END (GPR[RD]); |
| 1185 | } |
| 1186 | TRACE_ALU_RESULT (GPR[RD]); |
| 1187 | } |
| 1188 | |
| 1189 | |
| 1190 | :function:::void:do_dsubu:int rs, int rt, int rd |
| 1191 | { |
| 1192 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 1193 | GPR[rd] = GPR[rs] - GPR[rt]; |
| 1194 | TRACE_ALU_RESULT (GPR[rd]); |
| 1195 | } |
| 1196 | |
| 1197 | 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU |
| 1198 | "dsubu r<RD>, r<RS>, r<RT>" |
| 1199 | *mipsIII: |
| 1200 | *mipsIV: |
| 1201 | *vr4100: |
| 1202 | *vr5000: |
| 1203 | { |
| 1204 | do_dsubu (SD_, RS, RT, RD); |
| 1205 | } |
| 1206 | |
| 1207 | |
| 1208 | 000010,26.INSTR_INDEX:NORMAL:32::J |
| 1209 | "j <INSTR_INDEX>" |
| 1210 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1211 | *vr4100: |
| 1212 | *vr5000: |
| 1213 | *r3900: |
| 1214 | { |
| 1215 | /* NOTE: The region used is that of the delay slot NIA and NOT the |
| 1216 | current instruction */ |
| 1217 | address_word region = (NIA & MASK (63, 28)); |
| 1218 | DELAY_SLOT (region | (INSTR_INDEX << 2)); |
| 1219 | } |
| 1220 | |
| 1221 | |
| 1222 | 000011,26.INSTR_INDEX:NORMAL:32::JAL |
| 1223 | "jal <INSTR_INDEX>" |
| 1224 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1225 | *vr4100: |
| 1226 | *vr5000: |
| 1227 | *r3900: |
| 1228 | { |
| 1229 | /* NOTE: The region used is that of the delay slot and NOT the |
| 1230 | current instruction */ |
| 1231 | address_word region = (NIA & MASK (63, 28)); |
| 1232 | GPR[31] = CIA + 8; |
| 1233 | DELAY_SLOT (region | (INSTR_INDEX << 2)); |
| 1234 | } |
| 1235 | |
| 1236 | 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR |
| 1237 | "jalr r<RS>":RD == 31 |
| 1238 | "jalr r<RD>, r<RS>" |
| 1239 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1240 | *vr4100: |
| 1241 | *vr5000: |
| 1242 | *r3900: |
| 1243 | { |
| 1244 | address_word temp = GPR[RS]; |
| 1245 | GPR[RD] = CIA + 8; |
| 1246 | DELAY_SLOT (temp); |
| 1247 | } |
| 1248 | |
| 1249 | |
| 1250 | 000000,5.RS,000000000000000001000:SPECIAL:32::JR |
| 1251 | "jr r<RS>" |
| 1252 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1253 | *vr4100: |
| 1254 | *vr5000: |
| 1255 | *r3900: |
| 1256 | { |
| 1257 | DELAY_SLOT (GPR[RS]); |
| 1258 | } |
| 1259 | |
| 1260 | |
| 1261 | :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset |
| 1262 | { |
| 1263 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 1264 | address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); |
| 1265 | address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); |
| 1266 | unsigned int byte; |
| 1267 | address_word paddr; |
| 1268 | int uncached; |
| 1269 | unsigned64 memval; |
| 1270 | address_word vaddr; |
| 1271 | |
| 1272 | vaddr = base + offset; |
| 1273 | if ((vaddr & access) != 0) |
| 1274 | { |
| 1275 | SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); |
| 1276 | } |
| 1277 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
| 1278 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); |
| 1279 | LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); |
| 1280 | byte = ((vaddr & mask) ^ bigendiancpu); |
| 1281 | return (memval >> (8 * byte)); |
| 1282 | } |
| 1283 | |
| 1284 | |
| 1285 | 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB |
| 1286 | "lb r<RT>, <OFFSET>(r<BASE>)" |
| 1287 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1288 | *vr4100: |
| 1289 | *vr5000: |
| 1290 | *r3900: |
| 1291 | { |
| 1292 | GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); |
| 1293 | } |
| 1294 | |
| 1295 | |
| 1296 | 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU |
| 1297 | "lbu r<RT>, <OFFSET>(r<BASE>)" |
| 1298 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1299 | *vr4100: |
| 1300 | *vr5000: |
| 1301 | *r3900: |
| 1302 | { |
| 1303 | GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); |
| 1304 | } |
| 1305 | |
| 1306 | |
| 1307 | 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD |
| 1308 | "ld r<RT>, <OFFSET>(r<BASE>)" |
| 1309 | *mipsIII: |
| 1310 | *mipsIV: |
| 1311 | *vr4100: |
| 1312 | *vr5000: |
| 1313 | { |
| 1314 | GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 1315 | } |
| 1316 | |
| 1317 | |
| 1318 | 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz |
| 1319 | "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
| 1320 | *mipsII: |
| 1321 | *mipsIII: |
| 1322 | *mipsIV: |
| 1323 | *vr4100: |
| 1324 | *vr5000: |
| 1325 | *r3900: |
| 1326 | { |
| 1327 | COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 1328 | } |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | |
| 1333 | 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL |
| 1334 | "ldl r<RT>, <OFFSET>(r<BASE>)" |
| 1335 | *mipsIII: |
| 1336 | *mipsIV: |
| 1337 | *vr4100: |
| 1338 | *vr5000: |
| 1339 | { |
| 1340 | GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 1341 | } |
| 1342 | |
| 1343 | |
| 1344 | 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR |
| 1345 | "ldr r<RT>, <OFFSET>(r<BASE>)" |
| 1346 | *mipsIII: |
| 1347 | *mipsIV: |
| 1348 | *vr4100: |
| 1349 | *vr5000: |
| 1350 | { |
| 1351 | GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 1352 | } |
| 1353 | |
| 1354 | |
| 1355 | 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH |
| 1356 | "lh r<RT>, <OFFSET>(r<BASE>)" |
| 1357 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1358 | *vr4100: |
| 1359 | *vr5000: |
| 1360 | *r3900: |
| 1361 | { |
| 1362 | GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 1363 | } |
| 1364 | |
| 1365 | |
| 1366 | 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU |
| 1367 | "lhu r<RT>, <OFFSET>(r<BASE>)" |
| 1368 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1369 | *vr4100: |
| 1370 | *vr5000: |
| 1371 | *r3900: |
| 1372 | { |
| 1373 | GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); |
| 1374 | } |
| 1375 | |
| 1376 | |
| 1377 | 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL |
| 1378 | "ll r<RT>, <OFFSET>(r<BASE>)" |
| 1379 | *mipsII: |
| 1380 | *mipsIII: |
| 1381 | *mipsIV: |
| 1382 | *vr4100: |
| 1383 | *vr5000: |
| 1384 | { |
| 1385 | unsigned32 instruction = instruction_0; |
| 1386 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
| 1387 | int destreg = ((instruction >> 16) & 0x0000001F); |
| 1388 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 1389 | { |
| 1390 | address_word vaddr = ((unsigned64)op1 + offset); |
| 1391 | address_word paddr; |
| 1392 | int uncached; |
| 1393 | if ((vaddr & 3) != 0) |
| 1394 | { |
| 1395 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); |
| 1396 | } |
| 1397 | else |
| 1398 | { |
| 1399 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) |
| 1400 | { |
| 1401 | unsigned64 memval = 0; |
| 1402 | unsigned64 memval1 = 0; |
| 1403 | unsigned64 mask = 0x7; |
| 1404 | unsigned int shift = 2; |
| 1405 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
| 1406 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); |
| 1407 | unsigned int byte; |
| 1408 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
| 1409 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); |
| 1410 | byte = ((vaddr & mask) ^ (bigend << shift)); |
| 1411 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); |
| 1412 | LLBIT = 1; |
| 1413 | } |
| 1414 | } |
| 1415 | } |
| 1416 | } |
| 1417 | |
| 1418 | |
| 1419 | 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD |
| 1420 | "lld r<RT>, <OFFSET>(r<BASE>)" |
| 1421 | *mipsIII: |
| 1422 | *mipsIV: |
| 1423 | *vr4100: |
| 1424 | *vr5000: |
| 1425 | { |
| 1426 | unsigned32 instruction = instruction_0; |
| 1427 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
| 1428 | int destreg = ((instruction >> 16) & 0x0000001F); |
| 1429 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 1430 | { |
| 1431 | address_word vaddr = ((unsigned64)op1 + offset); |
| 1432 | address_word paddr; |
| 1433 | int uncached; |
| 1434 | if ((vaddr & 7) != 0) |
| 1435 | { |
| 1436 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); |
| 1437 | } |
| 1438 | else |
| 1439 | { |
| 1440 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) |
| 1441 | { |
| 1442 | unsigned64 memval = 0; |
| 1443 | unsigned64 memval1 = 0; |
| 1444 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
| 1445 | GPR[destreg] = memval; |
| 1446 | LLBIT = 1; |
| 1447 | } |
| 1448 | } |
| 1449 | } |
| 1450 | } |
| 1451 | |
| 1452 | |
| 1453 | 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI |
| 1454 | "lui r<RT>, <IMMEDIATE>" |
| 1455 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1456 | *vr4100: |
| 1457 | *vr5000: |
| 1458 | *r3900: |
| 1459 | { |
| 1460 | TRACE_ALU_INPUT1 (IMMEDIATE); |
| 1461 | GPR[RT] = EXTEND32 (IMMEDIATE << 16); |
| 1462 | TRACE_ALU_RESULT (GPR[RT]); |
| 1463 | } |
| 1464 | |
| 1465 | |
| 1466 | 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW |
| 1467 | "lw r<RT>, <OFFSET>(r<BASE>)" |
| 1468 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1469 | *vr4100: |
| 1470 | *vr5000: |
| 1471 | *r3900: |
| 1472 | { |
| 1473 | GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 1474 | } |
| 1475 | |
| 1476 | |
| 1477 | 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz |
| 1478 | "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
| 1479 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1480 | *vr4100: |
| 1481 | *vr5000: |
| 1482 | *r3900: |
| 1483 | { |
| 1484 | COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 1485 | } |
| 1486 | |
| 1487 | |
| 1488 | :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt |
| 1489 | { |
| 1490 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 1491 | address_word reverseendian = (ReverseEndian ? -1 : 0); |
| 1492 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); |
| 1493 | unsigned int byte; |
| 1494 | unsigned int word; |
| 1495 | address_word paddr; |
| 1496 | int uncached; |
| 1497 | unsigned64 memval; |
| 1498 | address_word vaddr; |
| 1499 | int nr_lhs_bits; |
| 1500 | int nr_rhs_bits; |
| 1501 | unsigned_word lhs_mask; |
| 1502 | unsigned_word temp; |
| 1503 | |
| 1504 | vaddr = base + offset; |
| 1505 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
| 1506 | paddr = (paddr ^ (reverseendian & mask)); |
| 1507 | if (BigEndianMem == 0) |
| 1508 | paddr = paddr & ~access; |
| 1509 | |
| 1510 | /* compute where within the word/mem we are */ |
| 1511 | byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ |
| 1512 | word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ |
| 1513 | nr_lhs_bits = 8 * byte + 8; |
| 1514 | nr_rhs_bits = 8 * access - 8 * byte; |
| 1515 | /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ |
| 1516 | |
| 1517 | /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", |
| 1518 | (long) ((unsigned64) vaddr >> 32), (long) vaddr, |
| 1519 | (long) ((unsigned64) paddr >> 32), (long) paddr, |
| 1520 | word, byte, nr_lhs_bits, nr_rhs_bits); */ |
| 1521 | |
| 1522 | LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); |
| 1523 | if (word == 0) |
| 1524 | { |
| 1525 | /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ |
| 1526 | temp = (memval << nr_rhs_bits); |
| 1527 | } |
| 1528 | else |
| 1529 | { |
| 1530 | /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ |
| 1531 | temp = (memval >> nr_lhs_bits); |
| 1532 | } |
| 1533 | lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); |
| 1534 | rt = (rt & ~lhs_mask) | (temp & lhs_mask); |
| 1535 | |
| 1536 | /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", |
| 1537 | (long) ((unsigned64) memval >> 32), (long) memval, |
| 1538 | (long) ((unsigned64) temp >> 32), (long) temp, |
| 1539 | (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, |
| 1540 | (long) (rt >> 32), (long) rt); */ |
| 1541 | return rt; |
| 1542 | } |
| 1543 | |
| 1544 | |
| 1545 | 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL |
| 1546 | "lwl r<RT>, <OFFSET>(r<BASE>)" |
| 1547 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1548 | *vr4100: |
| 1549 | *vr5000: |
| 1550 | *r3900: |
| 1551 | { |
| 1552 | GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); |
| 1553 | } |
| 1554 | |
| 1555 | |
| 1556 | :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt |
| 1557 | { |
| 1558 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 1559 | address_word reverseendian = (ReverseEndian ? -1 : 0); |
| 1560 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); |
| 1561 | unsigned int byte; |
| 1562 | address_word paddr; |
| 1563 | int uncached; |
| 1564 | unsigned64 memval; |
| 1565 | address_word vaddr; |
| 1566 | |
| 1567 | vaddr = base + offset; |
| 1568 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
| 1569 | /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ |
| 1570 | paddr = (paddr ^ (reverseendian & mask)); |
| 1571 | if (BigEndianMem != 0) |
| 1572 | paddr = paddr & ~access; |
| 1573 | byte = ((vaddr & mask) ^ (bigendiancpu & mask)); |
| 1574 | /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ |
| 1575 | LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); |
| 1576 | /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", |
| 1577 | (long) paddr, byte, (long) paddr, (long) memval); */ |
| 1578 | { |
| 1579 | unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); |
| 1580 | rt &= ~screen; |
| 1581 | rt |= (memval >> (8 * byte)) & screen; |
| 1582 | } |
| 1583 | return rt; |
| 1584 | } |
| 1585 | |
| 1586 | |
| 1587 | 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR |
| 1588 | "lwr r<RT>, <OFFSET>(r<BASE>)" |
| 1589 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1590 | *vr4100: |
| 1591 | *vr5000: |
| 1592 | *r3900: |
| 1593 | { |
| 1594 | GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); |
| 1595 | } |
| 1596 | |
| 1597 | |
| 1598 | 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU |
| 1599 | "lwu r<RT>, <OFFSET>(r<BASE>)" |
| 1600 | *mipsIII: |
| 1601 | *mipsIV: |
| 1602 | *vr4100: |
| 1603 | *vr5000: |
| 1604 | { |
| 1605 | GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); |
| 1606 | } |
| 1607 | |
| 1608 | |
| 1609 | :function:::void:do_mfhi:int rd |
| 1610 | { |
| 1611 | check_mf_hilo (SD_, HIHISTORY, LOHISTORY); |
| 1612 | TRACE_ALU_INPUT1 (HI); |
| 1613 | GPR[rd] = HI; |
| 1614 | TRACE_ALU_RESULT (GPR[rd]); |
| 1615 | } |
| 1616 | |
| 1617 | 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI |
| 1618 | "mfhi r<RD>" |
| 1619 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1620 | *vr4100: |
| 1621 | *vr5000: |
| 1622 | *r3900: |
| 1623 | { |
| 1624 | do_mfhi (SD_, RD); |
| 1625 | } |
| 1626 | |
| 1627 | |
| 1628 | |
| 1629 | :function:::void:do_mflo:int rd |
| 1630 | { |
| 1631 | check_mf_hilo (SD_, LOHISTORY, HIHISTORY); |
| 1632 | TRACE_ALU_INPUT1 (LO); |
| 1633 | GPR[rd] = LO; |
| 1634 | TRACE_ALU_RESULT (GPR[rd]); |
| 1635 | } |
| 1636 | |
| 1637 | 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO |
| 1638 | "mflo r<RD>" |
| 1639 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1640 | *vr4100: |
| 1641 | *vr5000: |
| 1642 | *r3900: |
| 1643 | { |
| 1644 | do_mflo (SD_, RD); |
| 1645 | } |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN |
| 1650 | "movn r<RD>, r<RS>, r<RT>" |
| 1651 | *mipsIV: |
| 1652 | *vr5000: |
| 1653 | { |
| 1654 | if (GPR[RT] != 0) |
| 1655 | GPR[RD] = GPR[RS]; |
| 1656 | } |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ |
| 1661 | "movz r<RD>, r<RS>, r<RT>" |
| 1662 | *mipsIV: |
| 1663 | *vr5000: |
| 1664 | { |
| 1665 | if (GPR[RT] == 0) |
| 1666 | GPR[RD] = GPR[RS]; |
| 1667 | } |
| 1668 | |
| 1669 | |
| 1670 | |
| 1671 | 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI |
| 1672 | "mthi r<RS>" |
| 1673 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1674 | *vr4100: |
| 1675 | *vr5000: |
| 1676 | *r3900: |
| 1677 | { |
| 1678 | check_mt_hilo (SD_, HIHISTORY); |
| 1679 | HI = GPR[RS]; |
| 1680 | } |
| 1681 | |
| 1682 | |
| 1683 | |
| 1684 | 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO |
| 1685 | "mtlo r<RS>" |
| 1686 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1687 | *vr4100: |
| 1688 | *vr5000: |
| 1689 | *r3900: |
| 1690 | { |
| 1691 | check_mt_hilo (SD_, LOHISTORY); |
| 1692 | LO = GPR[RS]; |
| 1693 | } |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | :function:::void:do_mult:int rs, int rt, int rd |
| 1698 | { |
| 1699 | signed64 prod; |
| 1700 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| 1701 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 1702 | prod = (((signed64)(signed32) GPR[rs]) |
| 1703 | * ((signed64)(signed32) GPR[rt])); |
| 1704 | LO = EXTEND32 (VL4_8 (prod)); |
| 1705 | HI = EXTEND32 (VH4_8 (prod)); |
| 1706 | if (rd != 0) |
| 1707 | GPR[rd] = LO; |
| 1708 | TRACE_ALU_RESULT2 (HI, LO); |
| 1709 | } |
| 1710 | |
| 1711 | 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT |
| 1712 | "mult r<RS>, r<RT>" |
| 1713 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1714 | *vr4100: |
| 1715 | { |
| 1716 | do_mult (SD_, RS, RT, 0); |
| 1717 | } |
| 1718 | |
| 1719 | |
| 1720 | 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT |
| 1721 | "mult r<RS>, r<RT>":RD == 0 |
| 1722 | "mult r<RD>, r<RS>, r<RT>" |
| 1723 | *vr5000: |
| 1724 | *r3900: |
| 1725 | { |
| 1726 | do_mult (SD_, RS, RT, RD); |
| 1727 | } |
| 1728 | |
| 1729 | |
| 1730 | :function:::void:do_multu:int rs, int rt, int rd |
| 1731 | { |
| 1732 | unsigned64 prod; |
| 1733 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); |
| 1734 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 1735 | prod = (((unsigned64)(unsigned32) GPR[rs]) |
| 1736 | * ((unsigned64)(unsigned32) GPR[rt])); |
| 1737 | LO = EXTEND32 (VL4_8 (prod)); |
| 1738 | HI = EXTEND32 (VH4_8 (prod)); |
| 1739 | if (rd != 0) |
| 1740 | GPR[rd] = LO; |
| 1741 | TRACE_ALU_RESULT2 (HI, LO); |
| 1742 | } |
| 1743 | |
| 1744 | 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU |
| 1745 | "multu r<RS>, r<RT>" |
| 1746 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1747 | *vr4100: |
| 1748 | { |
| 1749 | do_multu (SD_, RS, RT, 0); |
| 1750 | } |
| 1751 | |
| 1752 | 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU |
| 1753 | "multu r<RS>, r<RT>":RD == 0 |
| 1754 | "multu r<RD>, r<RS>, r<RT>" |
| 1755 | *vr5000: |
| 1756 | *r3900: |
| 1757 | { |
| 1758 | do_multu (SD_, RS, RT, RD); |
| 1759 | } |
| 1760 | |
| 1761 | |
| 1762 | :function:::void:do_nor:int rs, int rt, int rd |
| 1763 | { |
| 1764 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 1765 | GPR[rd] = ~ (GPR[rs] | GPR[rt]); |
| 1766 | TRACE_ALU_RESULT (GPR[rd]); |
| 1767 | } |
| 1768 | |
| 1769 | 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR |
| 1770 | "nor r<RD>, r<RS>, r<RT>" |
| 1771 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1772 | *vr4100: |
| 1773 | *vr5000: |
| 1774 | *r3900: |
| 1775 | { |
| 1776 | do_nor (SD_, RS, RT, RD); |
| 1777 | } |
| 1778 | |
| 1779 | |
| 1780 | :function:::void:do_or:int rs, int rt, int rd |
| 1781 | { |
| 1782 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 1783 | GPR[rd] = (GPR[rs] | GPR[rt]); |
| 1784 | TRACE_ALU_RESULT (GPR[rd]); |
| 1785 | } |
| 1786 | |
| 1787 | 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR |
| 1788 | "or r<RD>, r<RS>, r<RT>" |
| 1789 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1790 | *vr4100: |
| 1791 | *vr5000: |
| 1792 | *r3900: |
| 1793 | { |
| 1794 | do_or (SD_, RS, RT, RD); |
| 1795 | } |
| 1796 | |
| 1797 | |
| 1798 | |
| 1799 | :function:::void:do_ori:int rs, int rt, unsigned immediate |
| 1800 | { |
| 1801 | TRACE_ALU_INPUT2 (GPR[rs], immediate); |
| 1802 | GPR[rt] = (GPR[rs] | immediate); |
| 1803 | TRACE_ALU_RESULT (GPR[rt]); |
| 1804 | } |
| 1805 | |
| 1806 | 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI |
| 1807 | "ori r<RT>, r<RS>, <IMMEDIATE>" |
| 1808 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1809 | *vr4100: |
| 1810 | *vr5000: |
| 1811 | *r3900: |
| 1812 | { |
| 1813 | do_ori (SD_, RS, RT, IMMEDIATE); |
| 1814 | } |
| 1815 | |
| 1816 | |
| 1817 | 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF |
| 1818 | *mipsIV: |
| 1819 | *vr5000: |
| 1820 | { |
| 1821 | unsigned32 instruction = instruction_0; |
| 1822 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
| 1823 | int hint = ((instruction >> 16) & 0x0000001F); |
| 1824 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 1825 | { |
| 1826 | address_word vaddr = ((unsigned64)op1 + offset); |
| 1827 | address_word paddr; |
| 1828 | int uncached; |
| 1829 | { |
| 1830 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) |
| 1831 | Prefetch(uncached,paddr,vaddr,isDATA,hint); |
| 1832 | } |
| 1833 | } |
| 1834 | } |
| 1835 | |
| 1836 | :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word |
| 1837 | { |
| 1838 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 1839 | address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); |
| 1840 | address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); |
| 1841 | unsigned int byte; |
| 1842 | address_word paddr; |
| 1843 | int uncached; |
| 1844 | unsigned64 memval; |
| 1845 | address_word vaddr; |
| 1846 | |
| 1847 | vaddr = base + offset; |
| 1848 | if ((vaddr & access) != 0) |
| 1849 | { |
| 1850 | SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); |
| 1851 | } |
| 1852 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
| 1853 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); |
| 1854 | byte = ((vaddr & mask) ^ bigendiancpu); |
| 1855 | memval = (word << (8 * byte)); |
| 1856 | StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); |
| 1857 | } |
| 1858 | |
| 1859 | |
| 1860 | 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB |
| 1861 | "sb r<RT>, <OFFSET>(r<BASE>)" |
| 1862 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1863 | *vr4100: |
| 1864 | *vr5000: |
| 1865 | *r3900: |
| 1866 | { |
| 1867 | do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 1868 | } |
| 1869 | |
| 1870 | |
| 1871 | 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC |
| 1872 | "sc r<RT>, <OFFSET>(r<BASE>)" |
| 1873 | *mipsII: |
| 1874 | *mipsIII: |
| 1875 | *mipsIV: |
| 1876 | *vr4100: |
| 1877 | *vr5000: |
| 1878 | { |
| 1879 | unsigned32 instruction = instruction_0; |
| 1880 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
| 1881 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
| 1882 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 1883 | { |
| 1884 | address_word vaddr = ((unsigned64)op1 + offset); |
| 1885 | address_word paddr; |
| 1886 | int uncached; |
| 1887 | if ((vaddr & 3) != 0) |
| 1888 | { |
| 1889 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); |
| 1890 | } |
| 1891 | else |
| 1892 | { |
| 1893 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) |
| 1894 | { |
| 1895 | unsigned64 memval = 0; |
| 1896 | unsigned64 memval1 = 0; |
| 1897 | unsigned64 mask = 0x7; |
| 1898 | unsigned int byte; |
| 1899 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); |
| 1900 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); |
| 1901 | memval = ((unsigned64) op2 << (8 * byte)); |
| 1902 | if (LLBIT) |
| 1903 | { |
| 1904 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); |
| 1905 | } |
| 1906 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; |
| 1907 | } |
| 1908 | } |
| 1909 | } |
| 1910 | } |
| 1911 | |
| 1912 | |
| 1913 | 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD |
| 1914 | "scd r<RT>, <OFFSET>(r<BASE>)" |
| 1915 | *mipsIII: |
| 1916 | *mipsIV: |
| 1917 | *vr4100: |
| 1918 | *vr5000: |
| 1919 | { |
| 1920 | unsigned32 instruction = instruction_0; |
| 1921 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
| 1922 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
| 1923 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 1924 | { |
| 1925 | address_word vaddr = ((unsigned64)op1 + offset); |
| 1926 | address_word paddr; |
| 1927 | int uncached; |
| 1928 | if ((vaddr & 7) != 0) |
| 1929 | { |
| 1930 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); |
| 1931 | } |
| 1932 | else |
| 1933 | { |
| 1934 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) |
| 1935 | { |
| 1936 | unsigned64 memval = 0; |
| 1937 | unsigned64 memval1 = 0; |
| 1938 | memval = op2; |
| 1939 | if (LLBIT) |
| 1940 | { |
| 1941 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); |
| 1942 | } |
| 1943 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; |
| 1944 | } |
| 1945 | } |
| 1946 | } |
| 1947 | } |
| 1948 | |
| 1949 | |
| 1950 | 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD |
| 1951 | "sd r<RT>, <OFFSET>(r<BASE>)" |
| 1952 | *mipsIII: |
| 1953 | *mipsIV: |
| 1954 | *vr4100: |
| 1955 | *vr5000: |
| 1956 | { |
| 1957 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 1958 | } |
| 1959 | |
| 1960 | |
| 1961 | 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz |
| 1962 | "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
| 1963 | *mipsII: |
| 1964 | *mipsIII: |
| 1965 | *mipsIV: |
| 1966 | *vr4100: |
| 1967 | *vr5000: |
| 1968 | { |
| 1969 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); |
| 1970 | } |
| 1971 | |
| 1972 | |
| 1973 | 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL |
| 1974 | "sdl r<RT>, <OFFSET>(r<BASE>)" |
| 1975 | *mipsIII: |
| 1976 | *mipsIV: |
| 1977 | *vr4100: |
| 1978 | *vr5000: |
| 1979 | { |
| 1980 | do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 1981 | } |
| 1982 | |
| 1983 | |
| 1984 | 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR |
| 1985 | "sdr r<RT>, <OFFSET>(r<BASE>)" |
| 1986 | *mipsIII: |
| 1987 | *mipsIV: |
| 1988 | *vr4100: |
| 1989 | *vr5000: |
| 1990 | { |
| 1991 | do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 1992 | } |
| 1993 | |
| 1994 | |
| 1995 | 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH |
| 1996 | "sh r<RT>, <OFFSET>(r<BASE>)" |
| 1997 | *mipsI,mipsII,mipsIII,mipsIV: |
| 1998 | *vr4100: |
| 1999 | *vr5000: |
| 2000 | *r3900: |
| 2001 | { |
| 2002 | do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 2003 | } |
| 2004 | |
| 2005 | |
| 2006 | :function:::void:do_sll:int rt, int rd, int shift |
| 2007 | { |
| 2008 | unsigned32 temp = (GPR[rt] << shift); |
| 2009 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
| 2010 | GPR[rd] = EXTEND32 (temp); |
| 2011 | TRACE_ALU_RESULT (GPR[rd]); |
| 2012 | } |
| 2013 | |
| 2014 | 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL |
| 2015 | "sll r<RD>, r<RT>, <SHIFT>" |
| 2016 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2017 | *vr4100: |
| 2018 | *vr5000: |
| 2019 | *r3900: |
| 2020 | { |
| 2021 | do_sll (SD_, RT, RD, SHIFT); |
| 2022 | } |
| 2023 | |
| 2024 | |
| 2025 | :function:::void:do_sllv:int rs, int rt, int rd |
| 2026 | { |
| 2027 | int s = MASKED (GPR[rs], 4, 0); |
| 2028 | unsigned32 temp = (GPR[rt] << s); |
| 2029 | TRACE_ALU_INPUT2 (GPR[rt], s); |
| 2030 | GPR[rd] = EXTEND32 (temp); |
| 2031 | TRACE_ALU_RESULT (GPR[rd]); |
| 2032 | } |
| 2033 | |
| 2034 | 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV |
| 2035 | "sllv r<RD>, r<RT>, r<RS>" |
| 2036 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2037 | *vr4100: |
| 2038 | *vr5000: |
| 2039 | *r3900: |
| 2040 | { |
| 2041 | do_sllv (SD_, RS, RT, RD); |
| 2042 | } |
| 2043 | |
| 2044 | |
| 2045 | :function:::void:do_slt:int rs, int rt, int rd |
| 2046 | { |
| 2047 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 2048 | GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); |
| 2049 | TRACE_ALU_RESULT (GPR[rd]); |
| 2050 | } |
| 2051 | |
| 2052 | 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT |
| 2053 | "slt r<RD>, r<RS>, r<RT>" |
| 2054 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2055 | *vr4100: |
| 2056 | *vr5000: |
| 2057 | *r3900: |
| 2058 | { |
| 2059 | do_slt (SD_, RS, RT, RD); |
| 2060 | } |
| 2061 | |
| 2062 | |
| 2063 | :function:::void:do_slti:int rs, int rt, unsigned16 immediate |
| 2064 | { |
| 2065 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| 2066 | GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); |
| 2067 | TRACE_ALU_RESULT (GPR[rt]); |
| 2068 | } |
| 2069 | |
| 2070 | 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI |
| 2071 | "slti r<RT>, r<RS>, <IMMEDIATE>" |
| 2072 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2073 | *vr4100: |
| 2074 | *vr5000: |
| 2075 | *r3900: |
| 2076 | { |
| 2077 | do_slti (SD_, RS, RT, IMMEDIATE); |
| 2078 | } |
| 2079 | |
| 2080 | |
| 2081 | :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate |
| 2082 | { |
| 2083 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
| 2084 | GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); |
| 2085 | TRACE_ALU_RESULT (GPR[rt]); |
| 2086 | } |
| 2087 | |
| 2088 | 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU |
| 2089 | "sltiu r<RT>, r<RS>, <IMMEDIATE>" |
| 2090 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2091 | *vr4100: |
| 2092 | *vr5000: |
| 2093 | *r3900: |
| 2094 | { |
| 2095 | do_sltiu (SD_, RS, RT, IMMEDIATE); |
| 2096 | } |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | :function:::void:do_sltu:int rs, int rt, int rd |
| 2101 | { |
| 2102 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 2103 | GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); |
| 2104 | TRACE_ALU_RESULT (GPR[rd]); |
| 2105 | } |
| 2106 | |
| 2107 | 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU |
| 2108 | "sltu r<RD>, r<RS>, r<RT>" |
| 2109 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2110 | *vr4100: |
| 2111 | *vr5000: |
| 2112 | *r3900: |
| 2113 | { |
| 2114 | do_sltu (SD_, RS, RT, RD); |
| 2115 | } |
| 2116 | |
| 2117 | |
| 2118 | :function:::void:do_sra:int rt, int rd, int shift |
| 2119 | { |
| 2120 | signed32 temp = (signed32) GPR[rt] >> shift; |
| 2121 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
| 2122 | GPR[rd] = EXTEND32 (temp); |
| 2123 | TRACE_ALU_RESULT (GPR[rd]); |
| 2124 | } |
| 2125 | |
| 2126 | 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA |
| 2127 | "sra r<RD>, r<RT>, <SHIFT>" |
| 2128 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2129 | *vr4100: |
| 2130 | *vr5000: |
| 2131 | *r3900: |
| 2132 | { |
| 2133 | do_sra (SD_, RT, RD, SHIFT); |
| 2134 | } |
| 2135 | |
| 2136 | |
| 2137 | |
| 2138 | :function:::void:do_srav:int rs, int rt, int rd |
| 2139 | { |
| 2140 | int s = MASKED (GPR[rs], 4, 0); |
| 2141 | signed32 temp = (signed32) GPR[rt] >> s; |
| 2142 | TRACE_ALU_INPUT2 (GPR[rt], s); |
| 2143 | GPR[rd] = EXTEND32 (temp); |
| 2144 | TRACE_ALU_RESULT (GPR[rd]); |
| 2145 | } |
| 2146 | |
| 2147 | 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV |
| 2148 | "srav r<RD>, r<RT>, r<RS>" |
| 2149 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2150 | *vr4100: |
| 2151 | *vr5000: |
| 2152 | *r3900: |
| 2153 | { |
| 2154 | do_srav (SD_, RS, RT, RD); |
| 2155 | } |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | :function:::void:do_srl:int rt, int rd, int shift |
| 2160 | { |
| 2161 | unsigned32 temp = (unsigned32) GPR[rt] >> shift; |
| 2162 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
| 2163 | GPR[rd] = EXTEND32 (temp); |
| 2164 | TRACE_ALU_RESULT (GPR[rd]); |
| 2165 | } |
| 2166 | |
| 2167 | 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL |
| 2168 | "srl r<RD>, r<RT>, <SHIFT>" |
| 2169 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2170 | *vr4100: |
| 2171 | *vr5000: |
| 2172 | *r3900: |
| 2173 | { |
| 2174 | do_srl (SD_, RT, RD, SHIFT); |
| 2175 | } |
| 2176 | |
| 2177 | |
| 2178 | :function:::void:do_srlv:int rs, int rt, int rd |
| 2179 | { |
| 2180 | int s = MASKED (GPR[rs], 4, 0); |
| 2181 | unsigned32 temp = (unsigned32) GPR[rt] >> s; |
| 2182 | TRACE_ALU_INPUT2 (GPR[rt], s); |
| 2183 | GPR[rd] = EXTEND32 (temp); |
| 2184 | TRACE_ALU_RESULT (GPR[rd]); |
| 2185 | } |
| 2186 | |
| 2187 | 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV |
| 2188 | "srlv r<RD>, r<RT>, r<RS>" |
| 2189 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2190 | *vr4100: |
| 2191 | *vr5000: |
| 2192 | *r3900: |
| 2193 | { |
| 2194 | do_srlv (SD_, RS, RT, RD); |
| 2195 | } |
| 2196 | |
| 2197 | |
| 2198 | 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB |
| 2199 | "sub r<RD>, r<RS>, r<RT>" |
| 2200 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2201 | *vr4100: |
| 2202 | *vr5000: |
| 2203 | *r3900: |
| 2204 | { |
| 2205 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
| 2206 | { |
| 2207 | ALU32_BEGIN (GPR[RS]); |
| 2208 | ALU32_SUB (GPR[RT]); |
| 2209 | ALU32_END (GPR[RD]); |
| 2210 | } |
| 2211 | TRACE_ALU_RESULT (GPR[RD]); |
| 2212 | } |
| 2213 | |
| 2214 | |
| 2215 | :function:::void:do_subu:int rs, int rt, int rd |
| 2216 | { |
| 2217 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 2218 | GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); |
| 2219 | TRACE_ALU_RESULT (GPR[rd]); |
| 2220 | } |
| 2221 | |
| 2222 | 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU |
| 2223 | "subu r<RD>, r<RS>, r<RT>" |
| 2224 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2225 | *vr4100: |
| 2226 | *vr5000: |
| 2227 | *r3900: |
| 2228 | { |
| 2229 | do_subu (SD_, RS, RT, RD); |
| 2230 | } |
| 2231 | |
| 2232 | |
| 2233 | 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW |
| 2234 | "sw r<RT>, <OFFSET>(r<BASE>)" |
| 2235 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2236 | *vr4100: |
| 2237 | *r3900: |
| 2238 | *vr5000: |
| 2239 | { |
| 2240 | do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 2241 | } |
| 2242 | |
| 2243 | |
| 2244 | 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz |
| 2245 | "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
| 2246 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2247 | *vr4100: |
| 2248 | *vr5000: |
| 2249 | *r3900: |
| 2250 | { |
| 2251 | do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); |
| 2252 | } |
| 2253 | |
| 2254 | |
| 2255 | |
| 2256 | :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt |
| 2257 | { |
| 2258 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 2259 | address_word reverseendian = (ReverseEndian ? -1 : 0); |
| 2260 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); |
| 2261 | unsigned int byte; |
| 2262 | unsigned int word; |
| 2263 | address_word paddr; |
| 2264 | int uncached; |
| 2265 | unsigned64 memval; |
| 2266 | address_word vaddr; |
| 2267 | int nr_lhs_bits; |
| 2268 | int nr_rhs_bits; |
| 2269 | |
| 2270 | vaddr = base + offset; |
| 2271 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
| 2272 | paddr = (paddr ^ (reverseendian & mask)); |
| 2273 | if (BigEndianMem == 0) |
| 2274 | paddr = paddr & ~access; |
| 2275 | |
| 2276 | /* compute where within the word/mem we are */ |
| 2277 | byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ |
| 2278 | word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ |
| 2279 | nr_lhs_bits = 8 * byte + 8; |
| 2280 | nr_rhs_bits = 8 * access - 8 * byte; |
| 2281 | /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ |
| 2282 | /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", |
| 2283 | (long) ((unsigned64) vaddr >> 32), (long) vaddr, |
| 2284 | (long) ((unsigned64) paddr >> 32), (long) paddr, |
| 2285 | word, byte, nr_lhs_bits, nr_rhs_bits); */ |
| 2286 | |
| 2287 | if (word == 0) |
| 2288 | { |
| 2289 | memval = (rt >> nr_rhs_bits); |
| 2290 | } |
| 2291 | else |
| 2292 | { |
| 2293 | memval = (rt << nr_lhs_bits); |
| 2294 | } |
| 2295 | /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", |
| 2296 | (long) ((unsigned64) rt >> 32), (long) rt, |
| 2297 | (long) ((unsigned64) memval >> 32), (long) memval); */ |
| 2298 | StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); |
| 2299 | } |
| 2300 | |
| 2301 | |
| 2302 | 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL |
| 2303 | "swl r<RT>, <OFFSET>(r<BASE>)" |
| 2304 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2305 | *vr4100: |
| 2306 | *vr5000: |
| 2307 | *r3900: |
| 2308 | { |
| 2309 | do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 2310 | } |
| 2311 | |
| 2312 | |
| 2313 | :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt |
| 2314 | { |
| 2315 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 2316 | address_word reverseendian = (ReverseEndian ? -1 : 0); |
| 2317 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); |
| 2318 | unsigned int byte; |
| 2319 | address_word paddr; |
| 2320 | int uncached; |
| 2321 | unsigned64 memval; |
| 2322 | address_word vaddr; |
| 2323 | |
| 2324 | vaddr = base + offset; |
| 2325 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
| 2326 | paddr = (paddr ^ (reverseendian & mask)); |
| 2327 | if (BigEndianMem != 0) |
| 2328 | paddr &= ~access; |
| 2329 | byte = ((vaddr & mask) ^ (bigendiancpu & mask)); |
| 2330 | memval = (rt << (byte * 8)); |
| 2331 | StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); |
| 2332 | } |
| 2333 | |
| 2334 | 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR |
| 2335 | "swr r<RT>, <OFFSET>(r<BASE>)" |
| 2336 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2337 | *vr4100: |
| 2338 | *vr5000: |
| 2339 | *r3900: |
| 2340 | { |
| 2341 | do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
| 2342 | } |
| 2343 | |
| 2344 | |
| 2345 | 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC |
| 2346 | "sync":STYPE == 0 |
| 2347 | "sync <STYPE>" |
| 2348 | *mipsII: |
| 2349 | *mipsIII: |
| 2350 | *mipsIV: |
| 2351 | *vr4100: |
| 2352 | *vr5000: |
| 2353 | *r3900: |
| 2354 | { |
| 2355 | SyncOperation (STYPE); |
| 2356 | } |
| 2357 | |
| 2358 | |
| 2359 | 000000,20.CODE,001100:SPECIAL:32::SYSCALL |
| 2360 | "syscall <CODE>" |
| 2361 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2362 | *vr4100: |
| 2363 | *vr5000: |
| 2364 | *r3900: |
| 2365 | { |
| 2366 | SignalException(SystemCall, instruction_0); |
| 2367 | } |
| 2368 | |
| 2369 | |
| 2370 | 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ |
| 2371 | "teq r<RS>, r<RT>" |
| 2372 | *mipsII: |
| 2373 | *mipsIII: |
| 2374 | *mipsIV: |
| 2375 | *vr4100: |
| 2376 | *vr5000: |
| 2377 | { |
| 2378 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
| 2379 | SignalException(Trap, instruction_0); |
| 2380 | } |
| 2381 | |
| 2382 | |
| 2383 | 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI |
| 2384 | "teqi r<RS>, <IMMEDIATE>" |
| 2385 | *mipsII: |
| 2386 | *mipsIII: |
| 2387 | *mipsIV: |
| 2388 | *vr4100: |
| 2389 | *vr5000: |
| 2390 | { |
| 2391 | if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) |
| 2392 | SignalException(Trap, instruction_0); |
| 2393 | } |
| 2394 | |
| 2395 | |
| 2396 | 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE |
| 2397 | "tge r<RS>, r<RT>" |
| 2398 | *mipsII: |
| 2399 | *mipsIII: |
| 2400 | *mipsIV: |
| 2401 | *vr4100: |
| 2402 | *vr5000: |
| 2403 | { |
| 2404 | if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) |
| 2405 | SignalException(Trap, instruction_0); |
| 2406 | } |
| 2407 | |
| 2408 | |
| 2409 | 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI |
| 2410 | "tgei r<RS>, <IMMEDIATE>" |
| 2411 | *mipsII: |
| 2412 | *mipsIII: |
| 2413 | *mipsIV: |
| 2414 | *vr4100: |
| 2415 | *vr5000: |
| 2416 | { |
| 2417 | if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) |
| 2418 | SignalException(Trap, instruction_0); |
| 2419 | } |
| 2420 | |
| 2421 | |
| 2422 | 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU |
| 2423 | "tgeiu r<RS>, <IMMEDIATE>" |
| 2424 | *mipsII: |
| 2425 | *mipsIII: |
| 2426 | *mipsIV: |
| 2427 | *vr4100: |
| 2428 | *vr5000: |
| 2429 | { |
| 2430 | if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) |
| 2431 | SignalException(Trap, instruction_0); |
| 2432 | } |
| 2433 | |
| 2434 | |
| 2435 | 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU |
| 2436 | "tgeu r<RS>, r<RT>" |
| 2437 | *mipsII: |
| 2438 | *mipsIII: |
| 2439 | *mipsIV: |
| 2440 | *vr4100: |
| 2441 | *vr5000: |
| 2442 | { |
| 2443 | if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) |
| 2444 | SignalException(Trap, instruction_0); |
| 2445 | } |
| 2446 | |
| 2447 | |
| 2448 | 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT |
| 2449 | "tlt r<RS>, r<RT>" |
| 2450 | *mipsII: |
| 2451 | *mipsIII: |
| 2452 | *mipsIV: |
| 2453 | *vr4100: |
| 2454 | *vr5000: |
| 2455 | { |
| 2456 | if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) |
| 2457 | SignalException(Trap, instruction_0); |
| 2458 | } |
| 2459 | |
| 2460 | |
| 2461 | 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI |
| 2462 | "tlti r<RS>, <IMMEDIATE>" |
| 2463 | *mipsII: |
| 2464 | *mipsIII: |
| 2465 | *mipsIV: |
| 2466 | *vr4100: |
| 2467 | *vr5000: |
| 2468 | { |
| 2469 | if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) |
| 2470 | SignalException(Trap, instruction_0); |
| 2471 | } |
| 2472 | |
| 2473 | |
| 2474 | 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU |
| 2475 | "tltiu r<RS>, <IMMEDIATE>" |
| 2476 | *mipsII: |
| 2477 | *mipsIII: |
| 2478 | *mipsIV: |
| 2479 | *vr4100: |
| 2480 | *vr5000: |
| 2481 | { |
| 2482 | if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) |
| 2483 | SignalException(Trap, instruction_0); |
| 2484 | } |
| 2485 | |
| 2486 | |
| 2487 | 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU |
| 2488 | "tltu r<RS>, r<RT>" |
| 2489 | *mipsII: |
| 2490 | *mipsIII: |
| 2491 | *mipsIV: |
| 2492 | *vr4100: |
| 2493 | *vr5000: |
| 2494 | { |
| 2495 | if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) |
| 2496 | SignalException(Trap, instruction_0); |
| 2497 | } |
| 2498 | |
| 2499 | |
| 2500 | 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE |
| 2501 | "tne r<RS>, r<RT>" |
| 2502 | *mipsII: |
| 2503 | *mipsIII: |
| 2504 | *mipsIV: |
| 2505 | *vr4100: |
| 2506 | *vr5000: |
| 2507 | { |
| 2508 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
| 2509 | SignalException(Trap, instruction_0); |
| 2510 | } |
| 2511 | |
| 2512 | |
| 2513 | 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI |
| 2514 | "tne r<RS>, <IMMEDIATE>" |
| 2515 | *mipsII: |
| 2516 | *mipsIII: |
| 2517 | *mipsIV: |
| 2518 | *vr4100: |
| 2519 | *vr5000: |
| 2520 | { |
| 2521 | if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) |
| 2522 | SignalException(Trap, instruction_0); |
| 2523 | } |
| 2524 | |
| 2525 | |
| 2526 | :function:::void:do_xor:int rs, int rt, int rd |
| 2527 | { |
| 2528 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
| 2529 | GPR[rd] = GPR[rs] ^ GPR[rt]; |
| 2530 | TRACE_ALU_RESULT (GPR[rd]); |
| 2531 | } |
| 2532 | |
| 2533 | 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR |
| 2534 | "xor r<RD>, r<RS>, r<RT>" |
| 2535 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2536 | *vr4100: |
| 2537 | *vr5000: |
| 2538 | *r3900: |
| 2539 | { |
| 2540 | do_xor (SD_, RS, RT, RD); |
| 2541 | } |
| 2542 | |
| 2543 | |
| 2544 | :function:::void:do_xori:int rs, int rt, unsigned16 immediate |
| 2545 | { |
| 2546 | TRACE_ALU_INPUT2 (GPR[rs], immediate); |
| 2547 | GPR[rt] = GPR[rs] ^ immediate; |
| 2548 | TRACE_ALU_RESULT (GPR[rt]); |
| 2549 | } |
| 2550 | |
| 2551 | 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI |
| 2552 | "xori r<RT>, r<RS>, <IMMEDIATE>" |
| 2553 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2554 | *vr4100: |
| 2555 | *vr5000: |
| 2556 | *r3900: |
| 2557 | { |
| 2558 | do_xori (SD_, RS, RT, IMMEDIATE); |
| 2559 | } |
| 2560 | |
| 2561 | \f |
| 2562 | // |
| 2563 | // MIPS Architecture: |
| 2564 | // |
| 2565 | // FPU Instruction Set (COP1 & COP1X) |
| 2566 | // |
| 2567 | |
| 2568 | |
| 2569 | :%s::::FMT:int fmt |
| 2570 | { |
| 2571 | switch (fmt) |
| 2572 | { |
| 2573 | case fmt_single: return "s"; |
| 2574 | case fmt_double: return "d"; |
| 2575 | case fmt_word: return "w"; |
| 2576 | case fmt_long: return "l"; |
| 2577 | default: return "?"; |
| 2578 | } |
| 2579 | } |
| 2580 | |
| 2581 | :%s::::X:int x |
| 2582 | { |
| 2583 | switch (x) |
| 2584 | { |
| 2585 | case 0: return "f"; |
| 2586 | case 1: return "t"; |
| 2587 | default: return "?"; |
| 2588 | } |
| 2589 | } |
| 2590 | |
| 2591 | :%s::::TF:int tf |
| 2592 | { |
| 2593 | if (tf) |
| 2594 | return "t"; |
| 2595 | else |
| 2596 | return "f"; |
| 2597 | } |
| 2598 | |
| 2599 | :%s::::ND:int nd |
| 2600 | { |
| 2601 | if (nd) |
| 2602 | return "l"; |
| 2603 | else |
| 2604 | return ""; |
| 2605 | } |
| 2606 | |
| 2607 | :%s::::COND:int cond |
| 2608 | { |
| 2609 | switch (cond) |
| 2610 | { |
| 2611 | case 00: return "f"; |
| 2612 | case 01: return "un"; |
| 2613 | case 02: return "eq"; |
| 2614 | case 03: return "ueq"; |
| 2615 | case 04: return "olt"; |
| 2616 | case 05: return "ult"; |
| 2617 | case 06: return "ole"; |
| 2618 | case 07: return "ule"; |
| 2619 | case 010: return "sf"; |
| 2620 | case 011: return "ngle"; |
| 2621 | case 012: return "seq"; |
| 2622 | case 013: return "ngl"; |
| 2623 | case 014: return "lt"; |
| 2624 | case 015: return "nge"; |
| 2625 | case 016: return "le"; |
| 2626 | case 017: return "ngt"; |
| 2627 | default: return "?"; |
| 2628 | } |
| 2629 | } |
| 2630 | |
| 2631 | |
| 2632 | 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt |
| 2633 | "abs.%s<FMT> f<FD>, f<FS>" |
| 2634 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2635 | *vr4100: |
| 2636 | *vr5000: |
| 2637 | *r3900: |
| 2638 | { |
| 2639 | unsigned32 instruction = instruction_0; |
| 2640 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2641 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2642 | int format = ((instruction >> 21) & 0x00000007); |
| 2643 | { |
| 2644 | if ((format != fmt_single) && (format != fmt_double)) |
| 2645 | SignalException(ReservedInstruction,instruction); |
| 2646 | else |
| 2647 | StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format)); |
| 2648 | } |
| 2649 | } |
| 2650 | |
| 2651 | |
| 2652 | |
| 2653 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt |
| 2654 | "add.%s<FMT> f<FD>, f<FS>, f<FT>" |
| 2655 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2656 | *vr4100: |
| 2657 | *vr5000: |
| 2658 | *r3900: |
| 2659 | { |
| 2660 | unsigned32 instruction = instruction_0; |
| 2661 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2662 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2663 | int ft = ((instruction >> 16) & 0x0000001F); |
| 2664 | int format = ((instruction >> 21) & 0x00000007); |
| 2665 | { |
| 2666 | if ((format != fmt_single) && (format != fmt_double)) |
| 2667 | SignalException(ReservedInstruction, instruction); |
| 2668 | else |
| 2669 | StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format)); |
| 2670 | } |
| 2671 | } |
| 2672 | |
| 2673 | |
| 2674 | |
| 2675 | // BC1F |
| 2676 | // BC1FL |
| 2677 | // BC1T |
| 2678 | // BC1TL |
| 2679 | |
| 2680 | 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a |
| 2681 | "bc1%s<TF>%s<ND> <OFFSET>" |
| 2682 | *mipsI,mipsII,mipsIII: |
| 2683 | { |
| 2684 | check_branch_bug (); |
| 2685 | TRACE_BRANCH_INPUT (PREVCOC1()); |
| 2686 | if (PREVCOC1() == TF) |
| 2687 | { |
| 2688 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); |
| 2689 | TRACE_BRANCH_RESULT (dest); |
| 2690 | mark_branch_bug (dest); |
| 2691 | DELAY_SLOT (dest); |
| 2692 | } |
| 2693 | else if (ND) |
| 2694 | { |
| 2695 | TRACE_BRANCH_RESULT (0); |
| 2696 | NULLIFY_NEXT_INSTRUCTION (); |
| 2697 | } |
| 2698 | else |
| 2699 | { |
| 2700 | TRACE_BRANCH_RESULT (NIA); |
| 2701 | } |
| 2702 | } |
| 2703 | |
| 2704 | 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b |
| 2705 | "bc1%s<TF>%s<ND> <OFFSET>":CC == 0 |
| 2706 | "bc1%s<TF>%s<ND> <CC>, <OFFSET>" |
| 2707 | *mipsIV: |
| 2708 | *vr5000: |
| 2709 | #*vr4100: |
| 2710 | *r3900: |
| 2711 | { |
| 2712 | check_branch_bug (); |
| 2713 | if (GETFCC(CC) == TF) |
| 2714 | { |
| 2715 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); |
| 2716 | mark_branch_bug (dest); |
| 2717 | DELAY_SLOT (dest); |
| 2718 | } |
| 2719 | else if (ND) |
| 2720 | { |
| 2721 | NULLIFY_NEXT_INSTRUCTION (); |
| 2722 | } |
| 2723 | } |
| 2724 | |
| 2725 | |
| 2726 | |
| 2727 | |
| 2728 | |
| 2729 | |
| 2730 | // C.EQ.S |
| 2731 | // C.EQ.D |
| 2732 | // ... |
| 2733 | |
| 2734 | :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn |
| 2735 | { |
| 2736 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
| 2737 | SignalException (ReservedInstruction, insn); |
| 2738 | else |
| 2739 | { |
| 2740 | int less; |
| 2741 | int equal; |
| 2742 | int unordered; |
| 2743 | int condition; |
| 2744 | unsigned64 ofs = ValueFPR (fs, fmt); |
| 2745 | unsigned64 oft = ValueFPR (ft, fmt); |
| 2746 | if (NaN (ofs, fmt) || NaN (oft, fmt)) |
| 2747 | { |
| 2748 | if (FCSR & FP_ENABLE (IO)) |
| 2749 | { |
| 2750 | FCSR |= FP_CAUSE (IO); |
| 2751 | SignalExceptionFPE (); |
| 2752 | } |
| 2753 | less = 0; |
| 2754 | equal = 0; |
| 2755 | unordered = 1; |
| 2756 | } |
| 2757 | else |
| 2758 | { |
| 2759 | less = Less (ofs, oft, fmt); |
| 2760 | equal = Equal (ofs, oft, fmt); |
| 2761 | unordered = 0; |
| 2762 | } |
| 2763 | condition = (((cond & (1 << 2)) && less) |
| 2764 | || ((cond & (1 << 1)) && equal) |
| 2765 | || ((cond & (1 << 0)) && unordered)); |
| 2766 | SETFCC (cc, condition); |
| 2767 | } |
| 2768 | } |
| 2769 | |
| 2770 | 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta |
| 2771 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>" |
| 2772 | *mipsI,mipsII,mipsIII: |
| 2773 | { |
| 2774 | do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0); |
| 2775 | } |
| 2776 | |
| 2777 | 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb |
| 2778 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 |
| 2779 | "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" |
| 2780 | *mipsIV: |
| 2781 | *vr4100: |
| 2782 | *vr5000: |
| 2783 | *r3900: |
| 2784 | { |
| 2785 | do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0); |
| 2786 | } |
| 2787 | |
| 2788 | |
| 2789 | 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt |
| 2790 | "ceil.l.%s<FMT> f<FD>, f<FS>" |
| 2791 | *mipsIII: |
| 2792 | *mipsIV: |
| 2793 | *vr4100: |
| 2794 | *vr5000: |
| 2795 | *r3900: |
| 2796 | { |
| 2797 | unsigned32 instruction = instruction_0; |
| 2798 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2799 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2800 | int format = ((instruction >> 21) & 0x00000007); |
| 2801 | { |
| 2802 | if ((format != fmt_single) && (format != fmt_double)) |
| 2803 | SignalException(ReservedInstruction,instruction); |
| 2804 | else |
| 2805 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long)); |
| 2806 | } |
| 2807 | } |
| 2808 | |
| 2809 | |
| 2810 | 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W |
| 2811 | *mipsII: |
| 2812 | *mipsIII: |
| 2813 | *mipsIV: |
| 2814 | *vr4100: |
| 2815 | *vr5000: |
| 2816 | *r3900: |
| 2817 | { |
| 2818 | unsigned32 instruction = instruction_0; |
| 2819 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2820 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2821 | int format = ((instruction >> 21) & 0x00000007); |
| 2822 | { |
| 2823 | if ((format != fmt_single) && (format != fmt_double)) |
| 2824 | SignalException(ReservedInstruction,instruction); |
| 2825 | else |
| 2826 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word)); |
| 2827 | } |
| 2828 | } |
| 2829 | |
| 2830 | |
| 2831 | // CFC1 |
| 2832 | // CTC1 |
| 2833 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1 |
| 2834 | "c%s<X>c1 r<RT>, f<FS>" |
| 2835 | *mipsI: |
| 2836 | *mipsII: |
| 2837 | *mipsIII: |
| 2838 | { |
| 2839 | if (X) |
| 2840 | { |
| 2841 | if (FS == 0) |
| 2842 | PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT])); |
| 2843 | else if (FS == 31) |
| 2844 | PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT])); |
| 2845 | /* else NOP */ |
| 2846 | PENDING_FILL(COCIDX,0); /* special case */ |
| 2847 | } |
| 2848 | else |
| 2849 | { /* control from */ |
| 2850 | if (FS == 0) |
| 2851 | PENDING_FILL(RT,SIGNEXTEND(FCR0,32)); |
| 2852 | else if (FS == 31) |
| 2853 | PENDING_FILL(RT,SIGNEXTEND(FCR31,32)); |
| 2854 | /* else NOP */ |
| 2855 | } |
| 2856 | } |
| 2857 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1 |
| 2858 | "c%s<X>c1 r<RT>, f<FS>" |
| 2859 | *mipsIV: |
| 2860 | *vr4100: |
| 2861 | *vr5000: |
| 2862 | *r3900: |
| 2863 | { |
| 2864 | if (X) |
| 2865 | { |
| 2866 | /* control to */ |
| 2867 | TRACE_ALU_INPUT1 (GPR[RT]); |
| 2868 | if (FS == 0) |
| 2869 | { |
| 2870 | FCR0 = VL4_8(GPR[RT]); |
| 2871 | TRACE_ALU_RESULT (FCR0); |
| 2872 | } |
| 2873 | else if (FS == 31) |
| 2874 | { |
| 2875 | FCR31 = VL4_8(GPR[RT]); |
| 2876 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); |
| 2877 | TRACE_ALU_RESULT (FCR31); |
| 2878 | } |
| 2879 | else |
| 2880 | { |
| 2881 | TRACE_ALU_RESULT0 (); |
| 2882 | } |
| 2883 | /* else NOP */ |
| 2884 | } |
| 2885 | else |
| 2886 | { /* control from */ |
| 2887 | if (FS == 0) |
| 2888 | { |
| 2889 | TRACE_ALU_INPUT1 (FCR0); |
| 2890 | GPR[RT] = SIGNEXTEND (FCR0, 32); |
| 2891 | } |
| 2892 | else if (FS == 31) |
| 2893 | { |
| 2894 | TRACE_ALU_INPUT1 (FCR31); |
| 2895 | GPR[RT] = SIGNEXTEND (FCR31, 32); |
| 2896 | } |
| 2897 | TRACE_ALU_RESULT (GPR[RT]); |
| 2898 | /* else NOP */ |
| 2899 | } |
| 2900 | } |
| 2901 | |
| 2902 | |
| 2903 | // |
| 2904 | // FIXME: Does not correctly differentiate between mips* |
| 2905 | // |
| 2906 | 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt |
| 2907 | "cvt.d.%s<FMT> f<FD>, f<FS>" |
| 2908 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2909 | *vr4100: |
| 2910 | *vr5000: |
| 2911 | *r3900: |
| 2912 | { |
| 2913 | unsigned32 instruction = instruction_0; |
| 2914 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2915 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2916 | int format = ((instruction >> 21) & 0x00000007); |
| 2917 | { |
| 2918 | if ((format == fmt_double) | 0) |
| 2919 | SignalException(ReservedInstruction,instruction); |
| 2920 | else |
| 2921 | StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double)); |
| 2922 | } |
| 2923 | } |
| 2924 | |
| 2925 | |
| 2926 | 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt |
| 2927 | "cvt.l.%s<FMT> f<FD>, f<FS>" |
| 2928 | *mipsIII: |
| 2929 | *mipsIV: |
| 2930 | *vr4100: |
| 2931 | *vr5000: |
| 2932 | *r3900: |
| 2933 | { |
| 2934 | unsigned32 instruction = instruction_0; |
| 2935 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2936 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2937 | int format = ((instruction >> 21) & 0x00000007); |
| 2938 | { |
| 2939 | if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word))) |
| 2940 | SignalException(ReservedInstruction,instruction); |
| 2941 | else |
| 2942 | StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long)); |
| 2943 | } |
| 2944 | } |
| 2945 | |
| 2946 | |
| 2947 | // |
| 2948 | // FIXME: Does not correctly differentiate between mips* |
| 2949 | // |
| 2950 | 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt |
| 2951 | "cvt.s.%s<FMT> f<FD>, f<FS>" |
| 2952 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2953 | *vr4100: |
| 2954 | *vr5000: |
| 2955 | *r3900: |
| 2956 | { |
| 2957 | unsigned32 instruction = instruction_0; |
| 2958 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2959 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2960 | int format = ((instruction >> 21) & 0x00000007); |
| 2961 | { |
| 2962 | if ((format == fmt_single) | 0) |
| 2963 | SignalException(ReservedInstruction,instruction); |
| 2964 | else |
| 2965 | StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single)); |
| 2966 | } |
| 2967 | } |
| 2968 | |
| 2969 | |
| 2970 | 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt |
| 2971 | "cvt.w.%s<FMT> f<FD>, f<FS>" |
| 2972 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2973 | *vr4100: |
| 2974 | *vr5000: |
| 2975 | *r3900: |
| 2976 | { |
| 2977 | unsigned32 instruction = instruction_0; |
| 2978 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2979 | int fs = ((instruction >> 11) & 0x0000001F); |
| 2980 | int format = ((instruction >> 21) & 0x00000007); |
| 2981 | { |
| 2982 | if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word))) |
| 2983 | SignalException(ReservedInstruction,instruction); |
| 2984 | else |
| 2985 | StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word)); |
| 2986 | } |
| 2987 | } |
| 2988 | |
| 2989 | |
| 2990 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt |
| 2991 | "div.%s<FMT> f<FD>, f<FS>, f<FT>" |
| 2992 | *mipsI,mipsII,mipsIII,mipsIV: |
| 2993 | *vr4100: |
| 2994 | *vr5000: |
| 2995 | *r3900: |
| 2996 | { |
| 2997 | unsigned32 instruction = instruction_0; |
| 2998 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 2999 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3000 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3001 | int format = ((instruction >> 21) & 0x00000007); |
| 3002 | { |
| 3003 | if ((format != fmt_single) && (format != fmt_double)) |
| 3004 | SignalException(ReservedInstruction,instruction); |
| 3005 | else |
| 3006 | StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format)); |
| 3007 | } |
| 3008 | } |
| 3009 | |
| 3010 | |
| 3011 | // DMFC1 |
| 3012 | // DMTC1 |
| 3013 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1 |
| 3014 | "dm%s<X>c1 r<RT>, f<FS>" |
| 3015 | *mipsIII: |
| 3016 | { |
| 3017 | if (X) |
| 3018 | { |
| 3019 | if (SizeFGR() == 64) |
| 3020 | PENDING_FILL((FS + FGRIDX),GPR[RT]); |
| 3021 | else if ((FS & 0x1) == 0) |
| 3022 | { |
| 3023 | PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT])); |
| 3024 | PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT])); |
| 3025 | } |
| 3026 | } |
| 3027 | else |
| 3028 | { |
| 3029 | if (SizeFGR() == 64) |
| 3030 | PENDING_FILL(RT,FGR[FS]); |
| 3031 | else if ((FS & 0x1) == 0) |
| 3032 | PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS])); |
| 3033 | else |
| 3034 | { |
| 3035 | if (STATE_VERBOSE_P(SD)) |
| 3036 | sim_io_eprintf (SD, |
| 3037 | "Warning: PC 0x%x: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n", |
| 3038 | CIA); |
| 3039 | PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); |
| 3040 | } |
| 3041 | } |
| 3042 | } |
| 3043 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1 |
| 3044 | "dm%s<X>c1 r<RT>, f<FS>" |
| 3045 | *mipsIV: |
| 3046 | *vr4100: |
| 3047 | *vr5000: |
| 3048 | *r3900: |
| 3049 | { |
| 3050 | if (X) |
| 3051 | { |
| 3052 | if (SizeFGR() == 64) |
| 3053 | StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); |
| 3054 | else if ((FS & 0x1) == 0) |
| 3055 | StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]); |
| 3056 | } |
| 3057 | else |
| 3058 | { |
| 3059 | if (SizeFGR() == 64) |
| 3060 | GPR[RT] = FGR[FS]; |
| 3061 | else if ((FS & 0x1) == 0) |
| 3062 | GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; |
| 3063 | else |
| 3064 | { |
| 3065 | if (STATE_VERBOSE_P(SD)) |
| 3066 | sim_io_eprintf (SD, |
| 3067 | "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n", |
| 3068 | (long) CIA); |
| 3069 | GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; |
| 3070 | } |
| 3071 | } |
| 3072 | } |
| 3073 | |
| 3074 | |
| 3075 | 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt |
| 3076 | "floor.l.%s<FMT> f<FD>, f<FS>" |
| 3077 | *mipsIII: |
| 3078 | *mipsIV: |
| 3079 | *vr4100: |
| 3080 | *vr5000: |
| 3081 | *r3900: |
| 3082 | { |
| 3083 | unsigned32 instruction = instruction_0; |
| 3084 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3085 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3086 | int format = ((instruction >> 21) & 0x00000007); |
| 3087 | { |
| 3088 | if ((format != fmt_single) && (format != fmt_double)) |
| 3089 | SignalException(ReservedInstruction,instruction); |
| 3090 | else |
| 3091 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long)); |
| 3092 | } |
| 3093 | } |
| 3094 | |
| 3095 | |
| 3096 | 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt |
| 3097 | "floor.w.%s<FMT> f<FD>, f<FS>" |
| 3098 | *mipsII: |
| 3099 | *mipsIII: |
| 3100 | *mipsIV: |
| 3101 | *vr4100: |
| 3102 | *vr5000: |
| 3103 | *r3900: |
| 3104 | { |
| 3105 | unsigned32 instruction = instruction_0; |
| 3106 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3107 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3108 | int format = ((instruction >> 21) & 0x00000007); |
| 3109 | { |
| 3110 | if ((format != fmt_single) && (format != fmt_double)) |
| 3111 | SignalException(ReservedInstruction,instruction); |
| 3112 | else |
| 3113 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word)); |
| 3114 | } |
| 3115 | } |
| 3116 | |
| 3117 | |
| 3118 | 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1 |
| 3119 | "ldc1 f<FT>, <OFFSET>(r<BASE>)" |
| 3120 | *mipsI: |
| 3121 | *mipsII: |
| 3122 | *mipsIII: |
| 3123 | *mipsIV: |
| 3124 | *vr4100: |
| 3125 | *vr5000: |
| 3126 | *r3900: |
| 3127 | { |
| 3128 | COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 3129 | } |
| 3130 | |
| 3131 | |
| 3132 | 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1 |
| 3133 | "ldxc1 f<FD>, r<INDEX>(r<BASE>)" |
| 3134 | *mipsIV: |
| 3135 | *vr5000: |
| 3136 | { |
| 3137 | COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); |
| 3138 | } |
| 3139 | |
| 3140 | |
| 3141 | |
| 3142 | 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 |
| 3143 | "lwc1 f<FT>, <OFFSET>(r<BASE>)" |
| 3144 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3145 | *vr4100: |
| 3146 | *vr5000: |
| 3147 | *r3900: |
| 3148 | { |
| 3149 | COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); |
| 3150 | } |
| 3151 | |
| 3152 | |
| 3153 | 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1 |
| 3154 | "lwxc1 f<FD>, r<INDEX>(r<BASE>)" |
| 3155 | *mipsIV: |
| 3156 | *vr5000: |
| 3157 | { |
| 3158 | COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); |
| 3159 | } |
| 3160 | |
| 3161 | |
| 3162 | |
| 3163 | // |
| 3164 | // FIXME: Not correct for mips* |
| 3165 | // |
| 3166 | 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D |
| 3167 | "madd.d f<FD>, f<FR>, f<FS>, f<FT>" |
| 3168 | *mipsIV: |
| 3169 | *vr5000: |
| 3170 | { |
| 3171 | unsigned32 instruction = instruction_0; |
| 3172 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3173 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3174 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3175 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3176 | { |
| 3177 | StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); |
| 3178 | } |
| 3179 | } |
| 3180 | |
| 3181 | |
| 3182 | 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S |
| 3183 | "madd.s f<FD>, f<FR>, f<FS>, f<FT>" |
| 3184 | *mipsIV: |
| 3185 | *vr5000: |
| 3186 | { |
| 3187 | unsigned32 instruction = instruction_0; |
| 3188 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3189 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3190 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3191 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3192 | { |
| 3193 | StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); |
| 3194 | } |
| 3195 | } |
| 3196 | |
| 3197 | |
| 3198 | // MFC1 |
| 3199 | // MTC1 |
| 3200 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1 |
| 3201 | "m%s<X>c1 r<RT>, f<FS>" |
| 3202 | *mipsI: |
| 3203 | *mipsII: |
| 3204 | *mipsIII: |
| 3205 | { |
| 3206 | if (X) |
| 3207 | { /*MTC1*/ |
| 3208 | if (SizeFGR() == 64) |
| 3209 | { |
| 3210 | if (STATE_VERBOSE_P(SD)) |
| 3211 | sim_io_eprintf (SD, |
| 3212 | "Warning: PC 0x%x: MTC1 not DMTC1 with 64 bit regs\n", CIA); |
| 3213 | PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); |
| 3214 | } |
| 3215 | else |
| 3216 | PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); |
| 3217 | } |
| 3218 | else /*MFC1*/ |
| 3219 | PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32)); |
| 3220 | } |
| 3221 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1 |
| 3222 | "m%s<X>c1 r<RT>, f<FS>" |
| 3223 | *mipsIV: |
| 3224 | *vr4100: |
| 3225 | *vr5000: |
| 3226 | *r3900: |
| 3227 | { |
| 3228 | int fs = FS; |
| 3229 | if (X) |
| 3230 | /*MTC1*/ |
| 3231 | StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); |
| 3232 | else /*MFC1*/ |
| 3233 | GPR[RT] = SIGNEXTEND(FGR[FS],32); |
| 3234 | } |
| 3235 | |
| 3236 | |
| 3237 | 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt |
| 3238 | "mov.%s<FMT> f<FD>, f<FS>" |
| 3239 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3240 | *vr4100: |
| 3241 | *vr5000: |
| 3242 | *r3900: |
| 3243 | { |
| 3244 | unsigned32 instruction = instruction_0; |
| 3245 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3246 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3247 | int format = ((instruction >> 21) & 0x00000007); |
| 3248 | { |
| 3249 | StoreFPR(destreg,format,ValueFPR(fs,format)); |
| 3250 | } |
| 3251 | } |
| 3252 | |
| 3253 | |
| 3254 | // MOVF |
| 3255 | // MOVT |
| 3256 | 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf |
| 3257 | "mov%s<TF> r<RD>, r<RS>, <CC>" |
| 3258 | *mipsIV: |
| 3259 | *vr5000: |
| 3260 | { |
| 3261 | if (GETFCC(CC) == TF) |
| 3262 | GPR[RD] = GPR[RS]; |
| 3263 | } |
| 3264 | |
| 3265 | |
| 3266 | // MOVF.fmt |
| 3267 | // MOVT.fmt |
| 3268 | 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt |
| 3269 | "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" |
| 3270 | *mipsIV: |
| 3271 | *vr5000: |
| 3272 | { |
| 3273 | unsigned32 instruction = instruction_0; |
| 3274 | int format = ((instruction >> 21) & 0x00000007); |
| 3275 | { |
| 3276 | if (GETFCC(CC) == TF) |
| 3277 | StoreFPR (FD, format, ValueFPR (FS, format)); |
| 3278 | else |
| 3279 | StoreFPR (FD, format, ValueFPR (FD, format)); |
| 3280 | } |
| 3281 | } |
| 3282 | |
| 3283 | |
| 3284 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt |
| 3285 | *mipsIV: |
| 3286 | *vr5000: |
| 3287 | { |
| 3288 | unsigned32 instruction = instruction_0; |
| 3289 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3290 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3291 | int format = ((instruction >> 21) & 0x00000007); |
| 3292 | { |
| 3293 | StoreFPR(destreg,format,ValueFPR(fs,format)); |
| 3294 | } |
| 3295 | } |
| 3296 | |
| 3297 | |
| 3298 | // MOVT see MOVtf |
| 3299 | |
| 3300 | |
| 3301 | // MOVT.fmt see MOVtf.fmt |
| 3302 | |
| 3303 | |
| 3304 | |
| 3305 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt |
| 3306 | "movz.%s<FMT> f<FD>, f<FS>, r<RT>" |
| 3307 | *mipsIV: |
| 3308 | *vr5000: |
| 3309 | { |
| 3310 | unsigned32 instruction = instruction_0; |
| 3311 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3312 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3313 | int format = ((instruction >> 21) & 0x00000007); |
| 3314 | { |
| 3315 | StoreFPR(destreg,format,ValueFPR(fs,format)); |
| 3316 | } |
| 3317 | } |
| 3318 | |
| 3319 | |
| 3320 | // MSUB.fmt |
| 3321 | 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D |
| 3322 | "msub.d f<FD>, f<FR>, f<FS>, f<FT>" |
| 3323 | *mipsIV: |
| 3324 | *vr5000: |
| 3325 | { |
| 3326 | unsigned32 instruction = instruction_0; |
| 3327 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3328 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3329 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3330 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3331 | { |
| 3332 | StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); |
| 3333 | } |
| 3334 | } |
| 3335 | |
| 3336 | |
| 3337 | // MSUB.fmt |
| 3338 | 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S |
| 3339 | "msub.s f<FD>, f<FR>, f<FS>, f<FT>" |
| 3340 | *mipsIV: |
| 3341 | *vr5000: |
| 3342 | { |
| 3343 | unsigned32 instruction = instruction_0; |
| 3344 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3345 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3346 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3347 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3348 | { |
| 3349 | StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); |
| 3350 | } |
| 3351 | } |
| 3352 | |
| 3353 | |
| 3354 | // MTC1 see MxC1 |
| 3355 | |
| 3356 | |
| 3357 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt |
| 3358 | "mul.%s<FMT> f<FD>, f<FS>, f<FT>" |
| 3359 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3360 | *vr4100: |
| 3361 | *vr5000: |
| 3362 | *r3900: |
| 3363 | { |
| 3364 | unsigned32 instruction = instruction_0; |
| 3365 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3366 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3367 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3368 | int format = ((instruction >> 21) & 0x00000007); |
| 3369 | { |
| 3370 | if ((format != fmt_single) && (format != fmt_double)) |
| 3371 | SignalException(ReservedInstruction,instruction); |
| 3372 | else |
| 3373 | StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format)); |
| 3374 | } |
| 3375 | } |
| 3376 | |
| 3377 | |
| 3378 | 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt |
| 3379 | "neg.%s<FMT> f<FD>, f<FS>" |
| 3380 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3381 | *vr4100: |
| 3382 | *vr5000: |
| 3383 | *r3900: |
| 3384 | { |
| 3385 | unsigned32 instruction = instruction_0; |
| 3386 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3387 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3388 | int format = ((instruction >> 21) & 0x00000007); |
| 3389 | { |
| 3390 | if ((format != fmt_single) && (format != fmt_double)) |
| 3391 | SignalException(ReservedInstruction,instruction); |
| 3392 | else |
| 3393 | StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format)); |
| 3394 | } |
| 3395 | } |
| 3396 | |
| 3397 | |
| 3398 | // NMADD.fmt |
| 3399 | 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D |
| 3400 | "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>" |
| 3401 | *mipsIV: |
| 3402 | *vr5000: |
| 3403 | { |
| 3404 | unsigned32 instruction = instruction_0; |
| 3405 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3406 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3407 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3408 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3409 | { |
| 3410 | StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); |
| 3411 | } |
| 3412 | } |
| 3413 | |
| 3414 | |
| 3415 | // NMADD.fmt |
| 3416 | 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S |
| 3417 | "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>" |
| 3418 | *mipsIV: |
| 3419 | *vr5000: |
| 3420 | { |
| 3421 | unsigned32 instruction = instruction_0; |
| 3422 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3423 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3424 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3425 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3426 | { |
| 3427 | StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); |
| 3428 | } |
| 3429 | } |
| 3430 | |
| 3431 | |
| 3432 | // NMSUB.fmt |
| 3433 | 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D |
| 3434 | "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>" |
| 3435 | *mipsIV: |
| 3436 | *vr5000: |
| 3437 | { |
| 3438 | unsigned32 instruction = instruction_0; |
| 3439 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3440 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3441 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3442 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3443 | { |
| 3444 | StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); |
| 3445 | } |
| 3446 | } |
| 3447 | |
| 3448 | |
| 3449 | // NMSUB.fmt |
| 3450 | 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S |
| 3451 | "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>" |
| 3452 | *mipsIV: |
| 3453 | *vr5000: |
| 3454 | { |
| 3455 | unsigned32 instruction = instruction_0; |
| 3456 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3457 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3458 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3459 | int fr = ((instruction >> 21) & 0x0000001F); |
| 3460 | { |
| 3461 | StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); |
| 3462 | } |
| 3463 | } |
| 3464 | |
| 3465 | |
| 3466 | 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX |
| 3467 | "prefx <HINT>, r<INDEX>(r<BASE>)" |
| 3468 | *mipsIV: |
| 3469 | *vr5000: |
| 3470 | { |
| 3471 | unsigned32 instruction = instruction_0; |
| 3472 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3473 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
| 3474 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 3475 | { |
| 3476 | address_word vaddr = ((unsigned64)op1 + (unsigned64)op2); |
| 3477 | address_word paddr; |
| 3478 | int uncached; |
| 3479 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) |
| 3480 | Prefetch(uncached,paddr,vaddr,isDATA,fs); |
| 3481 | } |
| 3482 | } |
| 3483 | |
| 3484 | 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt |
| 3485 | "recip.%s<FMT> f<FD>, f<FS>" |
| 3486 | *mipsIV: |
| 3487 | *vr5000: |
| 3488 | { |
| 3489 | unsigned32 instruction = instruction_0; |
| 3490 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3491 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3492 | int format = ((instruction >> 21) & 0x00000007); |
| 3493 | { |
| 3494 | if ((format != fmt_single) && (format != fmt_double)) |
| 3495 | SignalException(ReservedInstruction,instruction); |
| 3496 | else |
| 3497 | StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format)); |
| 3498 | } |
| 3499 | } |
| 3500 | |
| 3501 | |
| 3502 | 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt |
| 3503 | "round.l.%s<FMT> f<FD>, f<FS>" |
| 3504 | *mipsIII: |
| 3505 | *mipsIV: |
| 3506 | *vr4100: |
| 3507 | *vr5000: |
| 3508 | *r3900: |
| 3509 | { |
| 3510 | unsigned32 instruction = instruction_0; |
| 3511 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3512 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3513 | int format = ((instruction >> 21) & 0x00000007); |
| 3514 | { |
| 3515 | if ((format != fmt_single) && (format != fmt_double)) |
| 3516 | SignalException(ReservedInstruction,instruction); |
| 3517 | else |
| 3518 | StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long)); |
| 3519 | } |
| 3520 | } |
| 3521 | |
| 3522 | |
| 3523 | 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt |
| 3524 | "round.w.%s<FMT> f<FD>, f<FS>" |
| 3525 | *mipsII: |
| 3526 | *mipsIII: |
| 3527 | *mipsIV: |
| 3528 | *vr4100: |
| 3529 | *vr5000: |
| 3530 | *r3900: |
| 3531 | { |
| 3532 | unsigned32 instruction = instruction_0; |
| 3533 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3534 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3535 | int format = ((instruction >> 21) & 0x00000007); |
| 3536 | { |
| 3537 | if ((format != fmt_single) && (format != fmt_double)) |
| 3538 | SignalException(ReservedInstruction,instruction); |
| 3539 | else |
| 3540 | StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word)); |
| 3541 | } |
| 3542 | } |
| 3543 | |
| 3544 | |
| 3545 | 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt |
| 3546 | *mipsIV: |
| 3547 | "rsqrt.%s<FMT> f<FD>, f<FS>" |
| 3548 | *vr5000: |
| 3549 | { |
| 3550 | unsigned32 instruction = instruction_0; |
| 3551 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3552 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3553 | int format = ((instruction >> 21) & 0x00000007); |
| 3554 | { |
| 3555 | if ((format != fmt_single) && (format != fmt_double)) |
| 3556 | SignalException(ReservedInstruction,instruction); |
| 3557 | else |
| 3558 | StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format)); |
| 3559 | } |
| 3560 | } |
| 3561 | |
| 3562 | |
| 3563 | 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1 |
| 3564 | "sdc1 f<FT>, <OFFSET>(r<BASE>)" |
| 3565 | *mipsI: |
| 3566 | *mipsII: |
| 3567 | *mipsIII: |
| 3568 | *mipsIV: |
| 3569 | *vr4100: |
| 3570 | *vr5000: |
| 3571 | *r3900: |
| 3572 | { |
| 3573 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); |
| 3574 | } |
| 3575 | |
| 3576 | |
| 3577 | 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1 |
| 3578 | "ldxc1 f<FS>, r<INDEX>(r<BASE>)" |
| 3579 | *mipsIV: |
| 3580 | *vr5000: |
| 3581 | { |
| 3582 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); |
| 3583 | } |
| 3584 | |
| 3585 | |
| 3586 | 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt |
| 3587 | "sqrt.%s<FMT> f<FD>, f<FS>" |
| 3588 | *mipsII: |
| 3589 | *mipsIII: |
| 3590 | *mipsIV: |
| 3591 | *vr4100: |
| 3592 | *vr5000: |
| 3593 | *r3900: |
| 3594 | { |
| 3595 | unsigned32 instruction = instruction_0; |
| 3596 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3597 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3598 | int format = ((instruction >> 21) & 0x00000007); |
| 3599 | { |
| 3600 | if ((format != fmt_single) && (format != fmt_double)) |
| 3601 | SignalException(ReservedInstruction,instruction); |
| 3602 | else |
| 3603 | StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format))); |
| 3604 | } |
| 3605 | } |
| 3606 | |
| 3607 | |
| 3608 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt |
| 3609 | "sub.%s<FMT> f<FD>, f<FS>, f<FT>" |
| 3610 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3611 | *vr4100: |
| 3612 | *vr5000: |
| 3613 | *r3900: |
| 3614 | { |
| 3615 | unsigned32 instruction = instruction_0; |
| 3616 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3617 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3618 | int ft = ((instruction >> 16) & 0x0000001F); |
| 3619 | int format = ((instruction >> 21) & 0x00000007); |
| 3620 | { |
| 3621 | if ((format != fmt_single) && (format != fmt_double)) |
| 3622 | SignalException(ReservedInstruction,instruction); |
| 3623 | else |
| 3624 | StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format)); |
| 3625 | } |
| 3626 | } |
| 3627 | |
| 3628 | |
| 3629 | |
| 3630 | 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1 |
| 3631 | "swc1 f<FT>, <OFFSET>(r<BASE>)" |
| 3632 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3633 | *vr4100: |
| 3634 | *vr5000: |
| 3635 | *r3900: |
| 3636 | { |
| 3637 | unsigned32 instruction = instruction_0; |
| 3638 | signed_word offset = EXTEND16 (OFFSET); |
| 3639 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); |
| 3640 | signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; |
| 3641 | { |
| 3642 | address_word vaddr = ((uword64)op1 + offset); |
| 3643 | address_word paddr; |
| 3644 | int uncached; |
| 3645 | if ((vaddr & 3) != 0) |
| 3646 | { |
| 3647 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); |
| 3648 | } |
| 3649 | else |
| 3650 | { |
| 3651 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) |
| 3652 | { |
| 3653 | uword64 memval = 0; |
| 3654 | uword64 memval1 = 0; |
| 3655 | uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); |
| 3656 | address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); |
| 3657 | address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); |
| 3658 | unsigned int byte; |
| 3659 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); |
| 3660 | byte = ((vaddr & mask) ^ bigendiancpu); |
| 3661 | memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte)); |
| 3662 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); |
| 3663 | } |
| 3664 | } |
| 3665 | } |
| 3666 | } |
| 3667 | |
| 3668 | |
| 3669 | 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1 |
| 3670 | "swxc1 f<FS>, r<INDEX>(r<BASE>)" |
| 3671 | *mipsIV: |
| 3672 | *vr5000: |
| 3673 | { |
| 3674 | unsigned32 instruction = instruction_0; |
| 3675 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3676 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
| 3677 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 3678 | { |
| 3679 | address_word vaddr = ((unsigned64)op1 + op2); |
| 3680 | address_word paddr; |
| 3681 | int uncached; |
| 3682 | if ((vaddr & 3) != 0) |
| 3683 | { |
| 3684 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); |
| 3685 | } |
| 3686 | else |
| 3687 | { |
| 3688 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) |
| 3689 | { |
| 3690 | unsigned64 memval = 0; |
| 3691 | unsigned64 memval1 = 0; |
| 3692 | unsigned64 mask = 0x7; |
| 3693 | unsigned int byte; |
| 3694 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); |
| 3695 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); |
| 3696 | memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); |
| 3697 | { |
| 3698 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); |
| 3699 | } |
| 3700 | } |
| 3701 | } |
| 3702 | } |
| 3703 | } |
| 3704 | |
| 3705 | |
| 3706 | 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt |
| 3707 | "trunc.l.%s<FMT> f<FD>, f<FS>" |
| 3708 | *mipsIII: |
| 3709 | *mipsIV: |
| 3710 | *vr4100: |
| 3711 | *vr5000: |
| 3712 | *r3900: |
| 3713 | { |
| 3714 | unsigned32 instruction = instruction_0; |
| 3715 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3716 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3717 | int format = ((instruction >> 21) & 0x00000007); |
| 3718 | { |
| 3719 | if ((format != fmt_single) && (format != fmt_double)) |
| 3720 | SignalException(ReservedInstruction,instruction); |
| 3721 | else |
| 3722 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long)); |
| 3723 | } |
| 3724 | } |
| 3725 | |
| 3726 | |
| 3727 | 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W |
| 3728 | "trunc.w.%s<FMT> f<FD>, f<FS>" |
| 3729 | *mipsII: |
| 3730 | *mipsIII: |
| 3731 | *mipsIV: |
| 3732 | *vr4100: |
| 3733 | *vr5000: |
| 3734 | *r3900: |
| 3735 | { |
| 3736 | unsigned32 instruction = instruction_0; |
| 3737 | int destreg = ((instruction >> 6) & 0x0000001F); |
| 3738 | int fs = ((instruction >> 11) & 0x0000001F); |
| 3739 | int format = ((instruction >> 21) & 0x00000007); |
| 3740 | { |
| 3741 | if ((format != fmt_single) && (format != fmt_double)) |
| 3742 | SignalException(ReservedInstruction,instruction); |
| 3743 | else |
| 3744 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word)); |
| 3745 | } |
| 3746 | } |
| 3747 | |
| 3748 | \f |
| 3749 | // |
| 3750 | // MIPS Architecture: |
| 3751 | // |
| 3752 | // System Control Instruction Set (COP0) |
| 3753 | // |
| 3754 | |
| 3755 | |
| 3756 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F |
| 3757 | "bc0f <OFFSET>" |
| 3758 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3759 | *vr4100: |
| 3760 | *vr5000: |
| 3761 | |
| 3762 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F |
| 3763 | "bc0f <OFFSET>" |
| 3764 | // stub needed for eCos as tx39 hardware bug workaround |
| 3765 | *r3900: |
| 3766 | { |
| 3767 | /* do nothing */ |
| 3768 | } |
| 3769 | |
| 3770 | |
| 3771 | 010000,01000,00010,16.OFFSET:COP0:32::BC0FL |
| 3772 | "bc0fl <OFFSET>" |
| 3773 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3774 | *vr4100: |
| 3775 | *vr5000: |
| 3776 | |
| 3777 | |
| 3778 | 010000,01000,00001,16.OFFSET:COP0:32::BC0T |
| 3779 | "bc0t <OFFSET>" |
| 3780 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3781 | *vr4100: |
| 3782 | |
| 3783 | |
| 3784 | 010000,01000,00011,16.OFFSET:COP0:32::BC0TL |
| 3785 | "bc0tl <OFFSET>" |
| 3786 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3787 | *vr4100: |
| 3788 | *vr5000: |
| 3789 | |
| 3790 | |
| 3791 | 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE |
| 3792 | *mipsIII: |
| 3793 | *mipsIV: |
| 3794 | *vr4100: |
| 3795 | *vr5000: |
| 3796 | *r3900: |
| 3797 | { |
| 3798 | unsigned32 instruction = instruction_0; |
| 3799 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
| 3800 | int hint = ((instruction >> 16) & 0x0000001F); |
| 3801 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; |
| 3802 | { |
| 3803 | address_word vaddr = (op1 + offset); |
| 3804 | address_word paddr; |
| 3805 | int uncached; |
| 3806 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) |
| 3807 | CacheOp(hint,vaddr,paddr,instruction); |
| 3808 | } |
| 3809 | } |
| 3810 | |
| 3811 | |
| 3812 | 010000,10000,000000000000000,111001:COP0:32::DI |
| 3813 | "di" |
| 3814 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3815 | *vr4100: |
| 3816 | *vr5000: |
| 3817 | |
| 3818 | |
| 3819 | 010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0 |
| 3820 | "dmfc0 r<RT>, r<RD>" |
| 3821 | *mipsIII,mipsIV: |
| 3822 | { |
| 3823 | DecodeCoproc (instruction_0); |
| 3824 | } |
| 3825 | |
| 3826 | |
| 3827 | 010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0 |
| 3828 | "dmtc0 r<RT>, r<RD>" |
| 3829 | *mipsIII,mipsIV: |
| 3830 | { |
| 3831 | DecodeCoproc (instruction_0); |
| 3832 | } |
| 3833 | |
| 3834 | |
| 3835 | 010000,10000,000000000000000,111000:COP0:32::EI |
| 3836 | "ei" |
| 3837 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3838 | *vr4100: |
| 3839 | *vr5000: |
| 3840 | |
| 3841 | |
| 3842 | 010000,10000,000000000000000,011000:COP0:32::ERET |
| 3843 | "eret" |
| 3844 | *mipsIII: |
| 3845 | *mipsIV: |
| 3846 | *vr4100: |
| 3847 | *vr5000: |
| 3848 | { |
| 3849 | if (SR & status_ERL) |
| 3850 | { |
| 3851 | /* Oops, not yet available */ |
| 3852 | sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); |
| 3853 | NIA = EPC; |
| 3854 | SR &= ~status_ERL; |
| 3855 | } |
| 3856 | else |
| 3857 | { |
| 3858 | NIA = EPC; |
| 3859 | SR &= ~status_EXL; |
| 3860 | } |
| 3861 | } |
| 3862 | |
| 3863 | |
| 3864 | 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 |
| 3865 | "mfc0 r<RT>, r<RD> # <REGX>" |
| 3866 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3867 | *r3900: |
| 3868 | *vr4100: |
| 3869 | *vr5000: |
| 3870 | { |
| 3871 | TRACE_ALU_INPUT0 (); |
| 3872 | DecodeCoproc (instruction_0); |
| 3873 | TRACE_ALU_RESULT (GPR[RT]); |
| 3874 | } |
| 3875 | |
| 3876 | 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 |
| 3877 | "mtc0 r<RT>, r<RD> # <REGX>" |
| 3878 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3879 | *r3900: |
| 3880 | *vr4100: |
| 3881 | *vr5000: |
| 3882 | { |
| 3883 | DecodeCoproc (instruction_0); |
| 3884 | } |
| 3885 | |
| 3886 | |
| 3887 | 010000,10000,000000000000000,010000:COP0:32::RFE |
| 3888 | "rfe" |
| 3889 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3890 | *r3900: |
| 3891 | *vr4100: |
| 3892 | *vr5000: |
| 3893 | { |
| 3894 | DecodeCoproc (instruction_0); |
| 3895 | } |
| 3896 | |
| 3897 | |
| 3898 | 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz |
| 3899 | "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>" |
| 3900 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3901 | *vr4100: |
| 3902 | *r3900: |
| 3903 | { |
| 3904 | DecodeCoproc (instruction_0); |
| 3905 | } |
| 3906 | |
| 3907 | |
| 3908 | |
| 3909 | 010000,10000,000000000000000,001000:COP0:32::TLBP |
| 3910 | "tlbp" |
| 3911 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3912 | *vr4100: |
| 3913 | *vr5000: |
| 3914 | |
| 3915 | |
| 3916 | 010000,10000,000000000000000,000001:COP0:32::TLBR |
| 3917 | "tlbr" |
| 3918 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3919 | *vr4100: |
| 3920 | *vr5000: |
| 3921 | |
| 3922 | |
| 3923 | 010000,10000,000000000000000,000010:COP0:32::TLBWI |
| 3924 | "tlbwi" |
| 3925 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3926 | *vr4100: |
| 3927 | *vr5000: |
| 3928 | |
| 3929 | |
| 3930 | 010000,10000,000000000000000,000110:COP0:32::TLBWR |
| 3931 | "tlbwr" |
| 3932 | *mipsI,mipsII,mipsIII,mipsIV: |
| 3933 | *vr4100: |
| 3934 | *vr5000: |
| 3935 | |
| 3936 | \f |
| 3937 | :include:::m16.igen |
| 3938 | :include:::tx.igen |
| 3939 | :include:::vr.igen |
| 3940 | \f |