| 1 | /* Copyright (C) 1998, Cygnus Solutions */ |
| 2 | |
| 3 | #ifndef H_PKE_H |
| 4 | #define H_PKE_H |
| 5 | |
| 6 | #include "sim-main.h" |
| 7 | #include "sky-device.h" |
| 8 | |
| 9 | |
| 10 | |
| 11 | /* External functions */ |
| 12 | |
| 13 | void pke0_attach(SIM_DESC sd); |
| 14 | void pke0_issue(SIM_DESC sd); |
| 15 | void pke1_attach(SIM_DESC sd); |
| 16 | void pke1_issue(SIM_DESC sd); |
| 17 | |
| 18 | |
| 19 | /* structs declared below */ |
| 20 | struct pke_fifo; |
| 21 | struct fifo_quadword; |
| 22 | |
| 23 | |
| 24 | /* Quadword data type */ |
| 25 | |
| 26 | typedef unsigned_4 quadword[4]; |
| 27 | |
| 28 | /* truncate address to quadword */ |
| 29 | #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f) |
| 30 | /* extract offset in quadword */ |
| 31 | #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f) |
| 32 | |
| 33 | |
| 34 | /* SCEI memory mapping information */ |
| 35 | |
| 36 | #define PKE0_REGISTER_WINDOW_START 0x10003800 |
| 37 | #define PKE1_REGISTER_WINDOW_START 0x10003C00 |
| 38 | #define PKE0_FIFO_ADDR 0x10004000 |
| 39 | #define PKE1_FIFO_ADDR 0x10005000 |
| 40 | |
| 41 | |
| 42 | /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */ |
| 43 | #define VU0_MEM0_SRCADDR_START 0x21000000 |
| 44 | #define VU0_MEM1_SRCADDR_START 0x21004000 |
| 45 | #define VU1_MEM0_SRCADDR_START 0x21008000 |
| 46 | #define VU1_MEM1_SRCADDR_START 0x2100C000 |
| 47 | |
| 48 | /* GPUIF STAT register */ |
| 49 | #define GPUIF_REG_STAT_APATH_E 11 |
| 50 | #define GPUIF_REG_STAT_APATH_B 10 |
| 51 | |
| 52 | /* COP2 STAT register */ |
| 53 | #define COP2_REG_STAT_ADDR VPU_STAT |
| 54 | #define COP2_REG_STAT_VBS1_E 8 |
| 55 | #define COP2_REG_STAT_VBS1_B 8 |
| 56 | #define COP2_REG_STAT_VBS0_E 0 |
| 57 | #define COP2_REG_STAT_VBS0_B 0 |
| 58 | |
| 59 | |
| 60 | /* Quadword indices of PKE registers. Actual registers sit at bottom |
| 61 | 32 bits of each quadword. */ |
| 62 | #define PKE_REG_STAT 0x00 |
| 63 | #define PKE_REG_FBRST 0x01 |
| 64 | #define PKE_REG_ERR 0x02 |
| 65 | #define PKE_REG_MARK 0x03 |
| 66 | #define PKE_REG_CYCLE 0x04 |
| 67 | #define PKE_REG_MODE 0x05 |
| 68 | #define PKE_REG_NUM 0x06 |
| 69 | #define PKE_REG_MASK 0x07 |
| 70 | #define PKE_REG_CODE 0x08 |
| 71 | #define PKE_REG_ITOPS 0x09 |
| 72 | #define PKE_REG_BASE 0x0a /* pke1 only */ |
| 73 | #define PKE_REG_OFST 0x0b /* pke1 only */ |
| 74 | #define PKE_REG_TOPS 0x0c /* pke1 only */ |
| 75 | #define PKE_REG_ITOP 0x0d |
| 76 | #define PKE_REG_TOP 0x0e /* pke1 only */ |
| 77 | #define PKE_REG_DBF 0x0f /* pke1 only */ |
| 78 | #define PKE_REG_R0 0x10 /* R0 .. R3 must be contiguous */ |
| 79 | #define PKE_REG_R1 0x11 |
| 80 | #define PKE_REG_R2 0x12 |
| 81 | #define PKE_REG_R3 0x13 |
| 82 | #define PKE_REG_C0 0x14 /* C0 .. C3 must be contiguous */ |
| 83 | #define PKE_REG_C1 0x15 |
| 84 | #define PKE_REG_C2 0x16 |
| 85 | #define PKE_REG_C3 0x17 |
| 86 | /* one plus last index */ |
| 87 | #define PKE_NUM_REGS 0x18 |
| 88 | |
| 89 | #define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS) |
| 90 | |
| 91 | |
| 92 | |
| 93 | /* PKE commands */ |
| 94 | |
| 95 | #define PKE_CMD_PKENOP_MASK 0x7F |
| 96 | #define PKE_CMD_PKENOP_BITS 0x00 |
| 97 | #define PKE_CMD_STCYCL_MASK 0x7F |
| 98 | #define PKE_CMD_STCYCL_BITS 0x01 |
| 99 | #define PKE_CMD_OFFSET_MASK 0x7F |
| 100 | #define PKE_CMD_OFFSET_BITS 0x02 |
| 101 | #define PKE_CMD_BASE_MASK 0x7F |
| 102 | #define PKE_CMD_BASE_BITS 0x03 |
| 103 | #define PKE_CMD_ITOP_MASK 0x7F |
| 104 | #define PKE_CMD_ITOP_BITS 0x04 |
| 105 | #define PKE_CMD_STMOD_MASK 0x7F |
| 106 | #define PKE_CMD_STMOD_BITS 0x05 |
| 107 | #define PKE_CMD_MSKPATH3_MASK 0x7F |
| 108 | #define PKE_CMD_MSKPATH3_BITS 0x06 |
| 109 | #define PKE_CMD_PKEMARK_MASK 0x7F |
| 110 | #define PKE_CMD_PKEMARK_BITS 0x07 |
| 111 | #define PKE_CMD_FLUSHE_MASK 0x7F |
| 112 | #define PKE_CMD_FLUSHE_BITS 0x10 |
| 113 | #define PKE_CMD_FLUSH_MASK 0x7F |
| 114 | #define PKE_CMD_FLUSH_BITS 0x11 |
| 115 | #define PKE_CMD_FLUSHA_MASK 0x7F |
| 116 | #define PKE_CMD_FLUSHA_BITS 0x13 |
| 117 | #define PKE_CMD_PKEMSCAL_MASK 0x7F /* CAL == "call" */ |
| 118 | #define PKE_CMD_PKEMSCAL_BITS 0x14 |
| 119 | #define PKE_CMD_PKEMSCNT_MASK 0x7F /* CNT == "continue" */ |
| 120 | #define PKE_CMD_PKEMSCNT_BITS 0x17 |
| 121 | #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */ |
| 122 | #define PKE_CMD_PKEMSCALF_BITS 0x15 |
| 123 | #define PKE_CMD_STMASK_MASK 0x7F |
| 124 | #define PKE_CMD_STMASK_BITS 0x20 |
| 125 | #define PKE_CMD_STROW_MASK 0x7F |
| 126 | #define PKE_CMD_STROW_BITS 0x30 |
| 127 | #define PKE_CMD_STCOL_MASK 0x7F |
| 128 | #define PKE_CMD_STCOL_BITS 0x31 |
| 129 | #define PKE_CMD_MPG_MASK 0x7F |
| 130 | #define PKE_CMD_MPG_BITS 0x4A |
| 131 | #define PKE_CMD_DIRECT_MASK 0x7F |
| 132 | #define PKE_CMD_DIRECT_BITS 0x50 |
| 133 | #define PKE_CMD_DIRECTHL_MASK 0x7F |
| 134 | #define PKE_CMD_DIRECTHL_BITS 0x51 |
| 135 | #define PKE_CMD_UNPACK_MASK 0x60 |
| 136 | #define PKE_CMD_UNPACK_BITS 0x60 |
| 137 | |
| 138 | /* test given word for particular PKE command bit pattern */ |
| 139 | #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS) |
| 140 | |
| 141 | |
| 142 | /* register bitmasks: bit numbers for end and beginning of fields */ |
| 143 | |
| 144 | /* PKE opcode */ |
| 145 | #define PKE_OPCODE_I_E 31 |
| 146 | #define PKE_OPCODE_I_B 31 |
| 147 | #define PKE_OPCODE_CMD_E 30 |
| 148 | #define PKE_OPCODE_CMD_B 24 |
| 149 | #define PKE_OPCODE_NUM_E 23 |
| 150 | #define PKE_OPCODE_NUM_B 16 |
| 151 | #define PKE_OPCODE_IMM_E 15 |
| 152 | #define PKE_OPCODE_IMM_B 0 |
| 153 | |
| 154 | /* STAT register */ |
| 155 | #define PKE_REG_STAT_FQC_E 28 |
| 156 | #define PKE_REG_STAT_FQC_B 24 |
| 157 | #define PKE_REG_STAT_FDR_E 23 |
| 158 | #define PKE_REG_STAT_FDR_B 23 |
| 159 | #define PKE_REG_STAT_ER1_E 13 |
| 160 | #define PKE_REG_STAT_ER1_B 13 |
| 161 | #define PKE_REG_STAT_ER0_E 12 |
| 162 | #define PKE_REG_STAT_ER0_B 12 |
| 163 | #define PKE_REG_STAT_INT_E 11 |
| 164 | #define PKE_REG_STAT_INT_B 11 |
| 165 | #define PKE_REG_STAT_PIS_E 10 |
| 166 | #define PKE_REG_STAT_PIS_B 10 |
| 167 | #define PKE_REG_STAT_PFS_E 9 |
| 168 | #define PKE_REG_STAT_PFS_B 9 |
| 169 | #define PKE_REG_STAT_PSS_E 8 |
| 170 | #define PKE_REG_STAT_PSS_B 8 |
| 171 | #define PKE_REG_STAT_DBF_E 7 |
| 172 | #define PKE_REG_STAT_DBF_B 7 |
| 173 | #define PKE_REG_STAT_MRK_E 6 |
| 174 | #define PKE_REG_STAT_MRK_B 6 |
| 175 | #define PKE_REG_STAT_PGW_E 3 |
| 176 | #define PKE_REG_STAT_PGW_B 3 |
| 177 | #define PKE_REG_STAT_PEW_E 2 |
| 178 | #define PKE_REG_STAT_PEW_B 2 |
| 179 | #define PKE_REG_STAT_PPS_E 1 |
| 180 | #define PKE_REG_STAT_PPS_B 0 |
| 181 | |
| 182 | #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */ |
| 183 | #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */ |
| 184 | #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */ |
| 185 | #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */ |
| 186 | #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */ |
| 187 | |
| 188 | /* DBF register */ |
| 189 | #define PKE_REG_DBF_DF_E 0 |
| 190 | #define PKE_REG_DBF_DF_B 0 |
| 191 | |
| 192 | /* OFST register */ |
| 193 | #define PKE_REG_OFST_OFFSET_E 9 |
| 194 | #define PKE_REG_OFST_OFFSET_B 0 |
| 195 | |
| 196 | /* OFST register */ |
| 197 | #define PKE_REG_TOPS_TOPS_E 9 |
| 198 | #define PKE_REG_TOPS_TOPS_B 0 |
| 199 | |
| 200 | /* BASE register */ |
| 201 | #define PKE_REG_BASE_BASE_E 9 |
| 202 | #define PKE_REG_BASE_BASE_B 0 |
| 203 | |
| 204 | /* ITOPS register */ |
| 205 | #define PKE_REG_ITOPS_ITOPS_E 9 |
| 206 | #define PKE_REG_ITOPS_ITOPS_B 0 |
| 207 | |
| 208 | /* MODE register */ |
| 209 | #define PKE_REG_MODE_MDE_E 1 |
| 210 | #define PKE_REG_MODE_MDE_B 0 |
| 211 | |
| 212 | /* NUM register */ |
| 213 | #define PKE_REG_NUM_NUM_E 9 |
| 214 | #define PKE_REG_NUM_NUM_B 0 |
| 215 | |
| 216 | /* MARK register */ |
| 217 | #define PKE_REG_MARK_MARK_E 15 |
| 218 | #define PKE_REG_MARK_MARK_B 0 |
| 219 | |
| 220 | /* ITOP register */ |
| 221 | #define PKE_REG_ITOP_ITOP_E 9 |
| 222 | #define PKE_REG_ITOP_ITOP_B 0 |
| 223 | |
| 224 | /* TOP register */ |
| 225 | #define PKE_REG_TOP_TOP_E 9 |
| 226 | #define PKE_REG_TOP_TOP_B 0 |
| 227 | |
| 228 | /* MASK register */ |
| 229 | #define PKE_REG_MASK_MASK_E 31 |
| 230 | #define PKE_REG_MASK_MASK_B 0 |
| 231 | |
| 232 | /* CYCLE register */ |
| 233 | #define PKE_REG_CYCLE_WL_E 15 |
| 234 | #define PKE_REG_CYCLE_WL_B 8 |
| 235 | #define PKE_REG_CYCLE_CL_E 7 |
| 236 | #define PKE_REG_CYCLE_CL_B 0 |
| 237 | |
| 238 | /* ERR register */ |
| 239 | #define PKE_REG_ERR_ME1_E 2 |
| 240 | #define PKE_REG_ERR_ME1_B 2 |
| 241 | #define PKE_REG_ERR_ME0_E 1 |
| 242 | #define PKE_REG_ERR_ME0_B 1 |
| 243 | #define PKE_REG_ERR_MII_E 0 |
| 244 | #define PKE_REG_ERR_MII_B 0 |
| 245 | |
| 246 | /* FBRST command bitfields */ |
| 247 | #define PKE_REG_FBRST_STC_E 3 |
| 248 | #define PKE_REG_FBRST_STC_B 3 |
| 249 | #define PKE_REG_FBRST_STP_E 2 |
| 250 | #define PKE_REG_FBRST_STP_B 2 |
| 251 | #define PKE_REG_FBRST_FBK_E 1 |
| 252 | #define PKE_REG_FBRST_FBK_B 1 |
| 253 | #define PKE_REG_FBRST_RST_E 0 |
| 254 | #define PKE_REG_FBRST_RST_B 0 |
| 255 | |
| 256 | /* MSKPATH3 command bitfields */ |
| 257 | #define PKE_REG_MSKPATH3_E 15 |
| 258 | #define PKE_REG_MSKPATH3_B 15 |
| 259 | |
| 260 | |
| 261 | /* UNPACK opcodes */ |
| 262 | #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl)) |
| 263 | #define PKE_UNPACK_S_32 PKE_UNPACK(0, 0) |
| 264 | #define PKE_UNPACK_S_16 PKE_UNPACK(0, 1) |
| 265 | #define PKE_UNPACK_S_8 PKE_UNPACK(0, 2) |
| 266 | #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0) |
| 267 | #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1) |
| 268 | #define PKE_UNPACK_V2_8 PKE_UNPACK(1, 2) |
| 269 | #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0) |
| 270 | #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1) |
| 271 | #define PKE_UNPACK_V3_8 PKE_UNPACK(2, 2) |
| 272 | #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0) |
| 273 | #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1) |
| 274 | #define PKE_UNPACK_V4_8 PKE_UNPACK(3, 2) |
| 275 | #define PKE_UNPACK_V4_5 PKE_UNPACK(3, 3) |
| 276 | |
| 277 | |
| 278 | /* MASK register sub-field definitions */ |
| 279 | #define PKE_MASKREG_INPUT 0 |
| 280 | #define PKE_MASKREG_ROW 1 |
| 281 | #define PKE_MASKREG_COLUMN 2 |
| 282 | #define PKE_MASKREG_NOTHING 3 |
| 283 | |
| 284 | |
| 285 | /* STMOD register field definitions */ |
| 286 | #define PKE_MODE_INPUT 0 |
| 287 | #define PKE_MODE_ADDROW 1 |
| 288 | #define PKE_MODE_ACCROW 2 |
| 289 | |
| 290 | |
| 291 | /* extract a MASK register sub-field for row [0..3] and column [0..3] */ |
| 292 | /* MASK register is laid out of 2-bit values in this r-c order */ |
| 293 | /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */ |
| 294 | #define PKE_MASKREG_GET(me,row,col) \ |
| 295 | ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03) |
| 296 | |
| 297 | |
| 298 | /* operations - replace with those in sim-bits.h when convenient */ |
| 299 | |
| 300 | /* unsigned 32-bit mask of given width */ |
| 301 | #define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1) |
| 302 | /* e.g.: BIT_MASK(4) = 00011111 */ |
| 303 | |
| 304 | /* mask between given given bits numbers (MSB) */ |
| 305 | #define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1)))) |
| 306 | /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */ |
| 307 | |
| 308 | /* set bitfield value */ |
| 309 | #define BIT_MASK_SET(lvalue,begin,end,value) \ |
| 310 | do { \ |
| 311 | ASSERT((begin) <= (end)); \ |
| 312 | (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \ |
| 313 | (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \ |
| 314 | } while(0) |
| 315 | |
| 316 | /* get bitfield value */ |
| 317 | #define BIT_MASK_GET(rvalue,begin,end) \ |
| 318 | (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin)) |
| 319 | /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */ |
| 320 | |
| 321 | /* These ugly macro hacks allow succinct bitfield accesses */ |
| 322 | /* set a bitfield in a register by "name" */ |
| 323 | #define PKE_REG_MASK_SET(me,reg,flag,value) \ |
| 324 | do { \ |
| 325 | unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \ |
| 326 | PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \ |
| 327 | BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \ |
| 328 | PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \ |
| 329 | (value)); \ |
| 330 | if((me)->fifo_trace_file != NULL) \ |
| 331 | { \ |
| 332 | if(old != (value)) \ |
| 333 | fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \ |
| 334 | } \ |
| 335 | } while(0) |
| 336 | |
| 337 | /* get a bitfield from a register by "name" */ |
| 338 | #define PKE_REG_MASK_GET(me,reg,flag) \ |
| 339 | BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \ |
| 340 | PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E) |
| 341 | |
| 342 | |
| 343 | #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value)) |
| 344 | |
| 345 | |
| 346 | /* Classify words in a FIFO quadword */ |
| 347 | enum wordclass |
| 348 | { |
| 349 | wc_dma = 'D', |
| 350 | wc_pkecode = 'P', |
| 351 | wc_unknown = '?', |
| 352 | wc_pkedata = '.', |
| 353 | wc_gpuiftag = 'g' |
| 354 | }; |
| 355 | |
| 356 | |
| 357 | /* One row in the FIFO */ |
| 358 | struct fifo_quadword |
| 359 | { |
| 360 | /* 128 bits of data */ |
| 361 | quadword data; |
| 362 | /* source main memory address (or 0: unknown) */ |
| 363 | unsigned_4 source_address; |
| 364 | /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */ |
| 365 | enum wordclass word_class[4]; |
| 366 | }; |
| 367 | |
| 368 | |
| 369 | /* quadword FIFO structure for PKE */ |
| 370 | typedef struct pke_fifo |
| 371 | { |
| 372 | struct fifo_quadword** quadwords; /* pointer to fifo quadwords */ |
| 373 | unsigned_4 origin; /* quadword serial number of quadwords[0] */ |
| 374 | unsigned_4 length; /* length of quadword pointer array: 0..N */ |
| 375 | unsigned_4 next; /* relative index of first unfilled quadword: 0..length-1 */ |
| 376 | } pke_fifo; |
| 377 | |
| 378 | #define PKE_FIFO_GROW_SIZE 1000 /* number of quadword pointers to allocate */ |
| 379 | #define PKE_FIFO_ARCHEOLOGY 1000 /* number of old quadwords to keep as history */ |
| 380 | |
| 381 | |
| 382 | /* PKE internal state: FIFOs, registers, handle to VU friend */ |
| 383 | struct pke_device |
| 384 | { |
| 385 | /* common device info */ |
| 386 | device dev; |
| 387 | |
| 388 | /* identity: 0=PKE0, 1=PKE1 */ |
| 389 | int pke_number; |
| 390 | int flags; |
| 391 | |
| 392 | /* quadword registers: data in [0] word only */ |
| 393 | quadword regs[PKE_NUM_REGS]; |
| 394 | |
| 395 | /* write buffer for FIFO address */ |
| 396 | quadword fifo_qw_in_progress; |
| 397 | int fifo_qw_done; /* bitfield */ |
| 398 | |
| 399 | /* FIFO - private: use only pke_fifo_* routines to access */ |
| 400 | struct pke_fifo fifo; /* array of FIFO quadword pointers */ |
| 401 | FILE* fifo_trace_file; /* stdio stream open in append mode, or 0 for no trace */ |
| 402 | |
| 403 | /* FIFO cache -- curry last search pke_pcrel_fifo results */ |
| 404 | unsigned_4 last_fifo_pc; |
| 405 | unsigned_4 last_qw_pc; |
| 406 | unsigned_4 last_num; |
| 407 | unsigned_4 last_new_fifo_pc; |
| 408 | unsigned_4 last_new_qw_pc; |
| 409 | |
| 410 | /* PC */ |
| 411 | int fifo_pc; /* 0 .. (fifo_num_elements-1): quadword index of next instruction */ |
| 412 | int qw_pc; /* 0 .. 3: word index of next instruction */ |
| 413 | }; |
| 414 | |
| 415 | |
| 416 | /* Flags for PKE.flags */ |
| 417 | |
| 418 | #define PKE_FLAG_NONE 0x00 |
| 419 | #define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */ |
| 420 | #define PKE_FLAG_INT_NOLOOP 0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */ |
| 421 | |
| 422 | |
| 423 | /* Kludge alert */ |
| 424 | |
| 425 | #define PKE_MEM_READ(me,addr,data,size) \ |
| 426 | do { \ |
| 427 | sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \ |
| 428 | unsigned_##size value = \ |
| 429 | sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \ |
| 430 | (SIM_ADDR)(addr)); \ |
| 431 | memcpy((unsigned_##size*) (data), (void*) & value, size); \ |
| 432 | } while(0) |
| 433 | |
| 434 | #define PKE_MEM_WRITE(me,addr,data,size) \ |
| 435 | do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \ |
| 436 | unsigned_##size value; \ |
| 437 | memcpy((void*) & value, (unsigned_##size*)(data), size); \ |
| 438 | sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \ |
| 439 | (SIM_ADDR)(addr), value); \ |
| 440 | if((me)->fifo_trace_file != NULL) \ |
| 441 | { \ |
| 442 | int i; \ |
| 443 | unsigned_##size value_te; \ |
| 444 | value_te = H2T_##size(value); \ |
| 445 | fprintf((me)->fifo_trace_file, "# Write %2d bytes to ", size); \ |
| 446 | fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \ |
| 447 | for(i=0; i<size; i++) \ |
| 448 | fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value_te))[i]); \ |
| 449 | fprintf((me)->fifo_trace_file, "\n"); \ |
| 450 | } \ |
| 451 | } while(0) |
| 452 | |
| 453 | |
| 454 | |
| 455 | #endif /* H_PKE_H */ |